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| author | SergeyDegtyar <sndegtyar@gmail.com> | 2019-09-03 11:53:37 +0300 |
|---|---|---|
| committer | SergeyDegtyar <sndegtyar@gmail.com> | 2019-09-03 11:53:37 +0300 |
| commit | 11f330ed223f524cbbdbe2433599990a69b8f380 (patch) | |
| tree | 627373ced7ca850efe284caf31c7866cddaa934b /tests/ecp5/counter.v | |
| parent | 7e8f7f4c59c96897159d32771d0c7179c5474281 (diff) | |
| download | yosys-11f330ed223f524cbbdbe2433599990a69b8f380.tar.gz yosys-11f330ed223f524cbbdbe2433599990a69b8f380.tar.bz2 yosys-11f330ed223f524cbbdbe2433599990a69b8f380.zip | |
Add tests for ECP5 architecture
Diffstat (limited to 'tests/ecp5/counter.v')
| -rw-r--r-- | tests/ecp5/counter.v | 17 |
1 files changed, 17 insertions, 0 deletions
diff --git a/tests/ecp5/counter.v b/tests/ecp5/counter.v new file mode 100644 index 000000000..52852f8ac --- /dev/null +++ b/tests/ecp5/counter.v @@ -0,0 +1,17 @@ +module top (
+out,
+clk,
+reset
+);
+ output [7:0] out;
+ input clk, reset;
+ reg [7:0] out;
+
+ always @(posedge clk, posedge reset)
+ if (reset) begin
+ out <= 8'b0 ;
+ end else
+ out <= out + 1;
+
+
+endmodule
|