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| author | Eddie Hung <eddie@fpgeh.com> | 2019-09-03 10:49:21 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-09-03 10:49:21 -0700 |
| commit | d6a84a78a7ca70e567bc1b0665751daf0e44f4ae (patch) | |
| tree | 131ecdaa9713cdcf31f5e5fe11aa86e877ac5103 /tests/ice40/mux.ys | |
| parent | 67587bad7fb1adf14ca9598bb1a01d0ffda6a018 (diff) | |
| parent | 58af64b63a3a253ab08b1410422677deac5c6618 (diff) | |
| download | yosys-d6a84a78a7ca70e567bc1b0665751daf0e44f4ae.tar.gz yosys-d6a84a78a7ca70e567bc1b0665751daf0e44f4ae.tar.bz2 yosys-d6a84a78a7ca70e567bc1b0665751daf0e44f4ae.zip | |
Merge remote-tracking branch 'origin/master' into eddie/deferred_top
Diffstat (limited to 'tests/ice40/mux.ys')
| -rw-r--r-- | tests/ice40/mux.ys | 8 |
1 files changed, 8 insertions, 0 deletions
diff --git a/tests/ice40/mux.ys b/tests/ice40/mux.ys new file mode 100644 index 000000000..182b49499 --- /dev/null +++ b/tests/ice40/mux.ys @@ -0,0 +1,8 @@ +read_verilog mux.v +proc +flatten +equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd top # Constrain all select calls below inside the top module +select -assert-count 19 t:SB_LUT4 +select -assert-none t:SB_LUT4 %% t:* %D |