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-rw-r--r--CHANGELOG3
-rw-r--r--Makefile2
-rw-r--r--frontends/ast/simplify.cc13
-rw-r--r--frontends/verilog/verilog_parser.y22
-rw-r--r--tests/verilog/net_types.sv34
-rw-r--r--tests/verilog/net_types.ys5
-rw-r--r--tests/verilog/prefix.sv95
-rw-r--r--tests/verilog/prefix.ys5
8 files changed, 164 insertions, 15 deletions
diff --git a/CHANGELOG b/CHANGELOG
index dade2f0e9..ab41d689d 100644
--- a/CHANGELOG
+++ b/CHANGELOG
@@ -56,7 +56,7 @@ Yosys 0.9 .. Yosys 0.9-dev
- Added "portlist" command
- Added "check -mapped"
- Added "check -allow-tbuf"
- - Added "autoname" pass
+ - Added "autoname" pass
- Added "write_verilog -extmem"
- Added "opt_mem" pass
- Added "scratchpad" pass
@@ -94,6 +94,7 @@ Yosys 0.9 .. Yosys 0.9-dev
- Added support for parsing the 'bind' construct
- support declaration in procedural for initialization
- support declaration in generate for initialization
+ - Support wand and wor of data types
* Verific support
- Added "verific -L"
diff --git a/Makefile b/Makefile
index 7ef98d393..60ab2ccc2 100644
--- a/Makefile
+++ b/Makefile
@@ -127,7 +127,7 @@ LDFLAGS += -rdynamic
LDLIBS += -lrt
endif
-YOSYS_VER := 0.9+4306
+YOSYS_VER := 0.9+4309
GIT_REV := $(shell git -C $(YOSYS_SRC) rev-parse --short HEAD 2> /dev/null || echo UNKNOWN)
OBJS = kernel/version_$(GIT_REV).o
diff --git a/frontends/ast/simplify.cc b/frontends/ast/simplify.cc
index f713cf8e1..607ca9a8b 100644
--- a/frontends/ast/simplify.cc
+++ b/frontends/ast/simplify.cc
@@ -4045,7 +4045,7 @@ AstNode *AstNode::readmem(bool is_readmemh, std::string mem_filename, AstNode *m
// prefix is carried forward, but resolution of their children is deferred
void AstNode::expand_genblock(const std::string &prefix)
{
- if (type == AST_IDENTIFIER || type == AST_FCALL || type == AST_TCALL || type == AST_WIRETYPE) {
+ if (type == AST_IDENTIFIER || type == AST_FCALL || type == AST_TCALL || type == AST_WIRETYPE || type == AST_PREFIX) {
log_assert(!str.empty());
// search starting in the innermost scope and then stepping outward
@@ -4131,10 +4131,15 @@ void AstNode::expand_genblock(const std::string &prefix)
for (size_t i = 0; i < children.size(); i++) {
AstNode *child = children[i];
- // AST_PREFIX member names should not be prefixed; a nested AST_PREFIX
- // still needs to recursed-into
- if (type == AST_PREFIX && i == 1 && child->type == AST_IDENTIFIER)
+ // AST_PREFIX member names should not be prefixed; we recurse into them
+ // as normal to ensure indices and ranges are properly resolved, and
+ // then restore the previous string
+ if (type == AST_PREFIX && i == 1) {
+ std::string backup_scope_name = child->str;
+ child->expand_genblock(prefix);
+ child->str = backup_scope_name;
continue;
+ }
// functions/tasks may reference wires, constants, etc. in this scope
if (child->type == AST_FUNCTION || child->type == AST_TASK)
continue;
diff --git a/frontends/verilog/verilog_parser.y b/frontends/verilog/verilog_parser.y
index acb8b996c..5eb1115ce 100644
--- a/frontends/verilog/verilog_parser.y
+++ b/frontends/verilog/verilog_parser.y
@@ -832,16 +832,10 @@ opt_wire_type_token:
wire_type_token | %empty;
wire_type_token:
- TOK_WOR {
- astbuf3->is_wor = true;
+ // nets
+ net_type {
} |
- TOK_WAND {
- astbuf3->is_wand = true;
- } |
- // wires
- TOK_WIRE {
- } |
- TOK_WIRE logic_type {
+ net_type logic_type {
} |
// regs
TOK_REG {
@@ -868,6 +862,15 @@ wire_type_token:
astbuf3->range_right = 0;
};
+net_type:
+ TOK_WOR {
+ astbuf3->is_wor = true;
+ } |
+ TOK_WAND {
+ astbuf3->is_wand = true;
+ } |
+ TOK_WIRE;
+
logic_type:
TOK_LOGIC {
} |
@@ -2974,6 +2977,7 @@ rvalue:
hierarchical_id '[' expr ']' '.' rvalue {
$$ = new AstNode(AST_PREFIX, $3, $6);
$$->str = *$1;
+ SET_AST_NODE_LOC($$, @1, @6);
delete $1;
} |
hierarchical_id range {
diff --git a/tests/verilog/net_types.sv b/tests/verilog/net_types.sv
new file mode 100644
index 000000000..7226a7ee5
--- /dev/null
+++ b/tests/verilog/net_types.sv
@@ -0,0 +1,34 @@
+module top;
+ wire logic wire_logic_0; assign wire_logic_0 = 0;
+ wire logic wire_logic_1; assign wire_logic_1 = 1;
+ wand logic wand_logic_0; assign wand_logic_0 = 0; assign wand_logic_0 = 1;
+ wand logic wand_logic_1; assign wand_logic_1 = 1; assign wand_logic_1 = 1;
+ wor logic wor_logic_0; assign wor_logic_0 = 0; assign wor_logic_0 = 0;
+ wor logic wor_logic_1; assign wor_logic_1 = 1; assign wor_logic_1 = 0;
+
+ wire integer wire_integer; assign wire_integer = 4'b1001;
+ wand integer wand_integer; assign wand_integer = 4'b1001; assign wand_integer = 4'b1010;
+ wor integer wor_integer; assign wor_integer = 4'b1001; assign wor_integer = 4'b1010;
+
+ typedef logic [3:0] typename;
+ wire typename wire_typename; assign wire_typename = 4'b1001;
+ wand typename wand_typename; assign wand_typename = 4'b1001; assign wand_typename = 4'b1010;
+ wor typename wor_typename; assign wor_typename = 4'b1001; assign wor_typename = 4'b1010;
+
+ always @* begin
+ assert (wire_logic_0 == 0);
+ assert (wire_logic_1 == 1);
+ assert (wand_logic_0 == 0);
+ assert (wand_logic_1 == 1);
+ assert (wor_logic_0 == 0);
+ assert (wor_logic_1 == 1);
+
+ assert (wire_integer == 4'b1001);
+ assert (wand_integer == 4'b1000);
+ assert (wor_integer == 4'b1011);
+
+ assert (wire_typename == 4'b1001);
+ assert (wand_typename == 4'b1000);
+ assert (wor_typename == 4'b1011);
+ end
+endmodule
diff --git a/tests/verilog/net_types.ys b/tests/verilog/net_types.ys
new file mode 100644
index 000000000..9f75812ea
--- /dev/null
+++ b/tests/verilog/net_types.ys
@@ -0,0 +1,5 @@
+read_verilog -sv net_types.sv
+hierarchy
+proc
+opt -full
+sat -verify -prove-asserts -show-all
diff --git a/tests/verilog/prefix.sv b/tests/verilog/prefix.sv
new file mode 100644
index 000000000..2d7fbb134
--- /dev/null
+++ b/tests/verilog/prefix.sv
@@ -0,0 +1,95 @@
+module top;
+ genvar i, j;
+ if (1) begin : blk1
+ integer a = 1;
+ for (i = 0; i < 2; i = i + 1) begin : blk2
+ integer b = i;
+ for (j = 0; j < 2; j = j + 1) begin : blk3
+ integer c = j;
+ localparam x = i;
+ localparam y = j;
+ always @* begin
+ assert (1 == a);
+ assert (1 == blk1.a);
+ assert (1 == top.blk1.a);
+ assert (i == b);
+ assert (i == blk2[i].b);
+ assert (i == blk1.blk2[i].b);
+ assert (i == top.blk1.blk2[i].b);
+ assert (i == blk2[x].b);
+ assert (i == blk1.blk2[x].b);
+ assert (i == top.blk1.blk2[x].b);
+ assert (j == c);
+ assert (j == blk3[j].c);
+ assert (j == blk2[x].blk3[j].c);
+ assert (j == blk1.blk2[x].blk3[j].c);
+ assert (j == top.blk1.blk2[x].blk3[j].c);
+ assert (j == c);
+ assert (j == blk3[y].c);
+ assert (j == blk2[x].blk3[y].c);
+ assert (j == blk1.blk2[x].blk3[y].c);
+ assert (j == top.blk1.blk2[x].blk3[y].c);
+ assert (j == top.blk1.blk2[x].blk3[y].c[0]);
+ assert (0 == top.blk1.blk2[x].blk3[y].c[1]);
+ assert (0 == top.blk1.blk2[x].blk3[y].c[j]);
+ end
+ end
+ always @* begin
+ assert (1 == a);
+ assert (1 == blk1.a);
+ assert (1 == top.blk1.a);
+ assert (i == b);
+ assert (i == blk2[i].b);
+ assert (i == blk1.blk2[i].b);
+ assert (i == top.blk1.blk2[i].b);
+ assert (0 == blk3[0].c);
+ assert (0 == blk2[i].blk3[0].c);
+ assert (0 == blk1.blk2[i].blk3[0].c);
+ assert (0 == top.blk1.blk2[i].blk3[0].c);
+ assert (1 == blk3[1].c);
+ assert (1 == blk2[i].blk3[1].c);
+ assert (1 == blk1.blk2[i].blk3[1].c);
+ assert (1 == top.blk1.blk2[i].blk3[1].c);
+ end
+ end
+ always @* begin
+ assert (1 == a);
+ assert (1 == blk1.a);
+ assert (1 == top.blk1.a);
+ assert (0 == blk2[0].b);
+ assert (0 == blk1.blk2[0].b);
+ assert (0 == top.blk1.blk2[0].b);
+ assert (1 == blk2[1].b);
+ assert (1 == blk1.blk2[1].b);
+ assert (1 == top.blk1.blk2[1].b);
+ assert (0 == blk2[0].blk3[0].c);
+ assert (0 == blk1.blk2[0].blk3[0].c);
+ assert (0 == top.blk1.blk2[0].blk3[0].c);
+ assert (1 == blk2[0].blk3[1].c);
+ assert (1 == blk1.blk2[0].blk3[1].c);
+ assert (1 == top.blk1.blk2[0].blk3[1].c);
+ assert (0 == blk2[1].blk3[0].c);
+ assert (0 == blk1.blk2[1].blk3[0].c);
+ assert (0 == top.blk1.blk2[1].blk3[0].c);
+ assert (1 == blk2[1].blk3[1].c);
+ assert (1 == blk1.blk2[1].blk3[1].c);
+ assert (1 == top.blk1.blk2[1].blk3[1].c);
+ end
+ end
+ always @* begin
+ assert (1 == blk1.a);
+ assert (1 == top.blk1.a);
+ assert (0 == blk1.blk2[0].b);
+ assert (0 == top.blk1.blk2[0].b);
+ assert (1 == blk1.blk2[1].b);
+ assert (1 == top.blk1.blk2[1].b);
+ assert (0 == blk1.blk2[0].blk3[0].c);
+ assert (0 == top.blk1.blk2[0].blk3[0].c);
+ assert (1 == blk1.blk2[0].blk3[1].c);
+ assert (1 == top.blk1.blk2[0].blk3[1].c);
+ assert (0 == blk1.blk2[1].blk3[0].c);
+ assert (0 == top.blk1.blk2[1].blk3[0].c);
+ assert (1 == blk1.blk2[1].blk3[1].c);
+ assert (1 == top.blk1.blk2[1].blk3[1].c);
+ end
+endmodule
diff --git a/tests/verilog/prefix.ys b/tests/verilog/prefix.ys
new file mode 100644
index 000000000..ed3b3a111
--- /dev/null
+++ b/tests/verilog/prefix.ys
@@ -0,0 +1,5 @@
+read_verilog -sv prefix.sv
+hierarchy
+proc
+select -module top
+sat -verify -seq 1 -prove-asserts -show-all
generated by cgit v1.2.3 (git 2.25.1) at 2025-05-30 21:44:49 +0000