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-rw-r--r--passes/techmap/abc.cc2
-rwxr-xr-xtechlibs/achronix/synth_achronix.cc4
-rw-r--r--techlibs/anlogic/synth_anlogic.cc2
-rw-r--r--techlibs/coolrunner2/synth_coolrunner2.cc2
-rw-r--r--techlibs/easic/synth_easic.cc2
-rw-r--r--techlibs/ecp5/synth_ecp5.cc2
-rw-r--r--techlibs/gowin/synth_gowin.cc2
-rw-r--r--techlibs/greenpak4/synth_greenpak4.cc2
-rw-r--r--techlibs/ice40/synth_ice40.cc2
-rw-r--r--techlibs/intel/synth_intel.cc6
-rw-r--r--techlibs/sf2/synth_sf2.cc2
-rw-r--r--techlibs/xilinx/ff_map.v8
-rw-r--r--techlibs/xilinx/synth_xilinx.cc16
-rw-r--r--tests/simple/retime.v6
14 files changed, 33 insertions, 25 deletions
diff --git a/passes/techmap/abc.cc b/passes/techmap/abc.cc
index 21b70f492..3adbe0a04 100644
--- a/passes/techmap/abc.cc
+++ b/passes/techmap/abc.cc
@@ -1726,7 +1726,7 @@ struct AbcPass : public Pass {
signal_init[initsig[i]] = State::S0;
break;
case State::S1:
- signal_init[initsig[i]] = State::S0;
+ signal_init[initsig[i]] = State::S1;
break;
default:
break;
diff --git a/techlibs/achronix/synth_achronix.cc b/techlibs/achronix/synth_achronix.cc
index 626860d9c..3dbf20911 100755
--- a/techlibs/achronix/synth_achronix.cc
+++ b/techlibs/achronix/synth_achronix.cc
@@ -152,12 +152,12 @@ struct SynthAchronixPass : public ScriptPass {
run("clean -purge");
run("setundef -undriven -zero");
if (retime || help_mode)
- run("abc -markgroups -dff", "(only if -retime)");
+ run("abc -markgroups -dff -D 1", "(only if -retime)");
}
if (check_label("map_luts"))
{
- run("abc -lut 4" + string(retime ? " -dff" : ""));
+ run("abc -lut 4" + string(retime ? " -dff -D 1" : ""));
run("clean");
}
diff --git a/techlibs/anlogic/synth_anlogic.cc b/techlibs/anlogic/synth_anlogic.cc
index 620bf3965..258e3d722 100644
--- a/techlibs/anlogic/synth_anlogic.cc
+++ b/techlibs/anlogic/synth_anlogic.cc
@@ -164,7 +164,7 @@ struct SynthAnlogicPass : public ScriptPass
run("opt -undriven -fine");
run("techmap -map +/techmap.v -map +/anlogic/arith_map.v");
if (retime || help_mode)
- run("abc -dff", "(only if -retime)");
+ run("abc -dff -D 1", "(only if -retime)");
}
if (check_label("map_ffs"))
diff --git a/techlibs/coolrunner2/synth_coolrunner2.cc b/techlibs/coolrunner2/synth_coolrunner2.cc
index 21bbcaef4..fa4fe0f5b 100644
--- a/techlibs/coolrunner2/synth_coolrunner2.cc
+++ b/techlibs/coolrunner2/synth_coolrunner2.cc
@@ -161,7 +161,7 @@ struct SynthCoolrunner2Pass : public ScriptPass
if (check_label("map_pla"))
{
- run("abc -sop -I 40 -P 56");
+ run("abc -sop -I 40 -P 56" + string(retime ? " -dff -D 1" : ""));
run("clean");
}
diff --git a/techlibs/easic/synth_easic.cc b/techlibs/easic/synth_easic.cc
index dd9e3dab7..7bacc7890 100644
--- a/techlibs/easic/synth_easic.cc
+++ b/techlibs/easic/synth_easic.cc
@@ -158,7 +158,7 @@ struct SynthEasicPass : public ScriptPass
run("techmap");
run("opt -fast");
if (retime || help_mode) {
- run("abc -dff", " (only if -retime)");
+ run("abc -dff -D 1", " (only if -retime)");
run("opt_clean", "(only if -retime)");
}
}
diff --git a/techlibs/ecp5/synth_ecp5.cc b/techlibs/ecp5/synth_ecp5.cc
index 4b889d672..45f101451 100644
--- a/techlibs/ecp5/synth_ecp5.cc
+++ b/techlibs/ecp5/synth_ecp5.cc
@@ -242,7 +242,7 @@ struct SynthEcp5Pass : public ScriptPass
else
run("techmap -map +/techmap.v -map +/ecp5/arith_map.v");
if (retime || help_mode)
- run("abc -dff", "(only if -retime)");
+ run("abc -dff -D 1", "(only if -retime)");
}
if (check_label("map_ffs"))
diff --git a/techlibs/gowin/synth_gowin.cc b/techlibs/gowin/synth_gowin.cc
index 9a3fcdbb6..0ebd77d63 100644
--- a/techlibs/gowin/synth_gowin.cc
+++ b/techlibs/gowin/synth_gowin.cc
@@ -163,7 +163,7 @@ struct SynthGowinPass : public ScriptPass
run("splitnets -ports");
run("setundef -undriven -zero");
if (retime || help_mode)
- run("abc -dff", "(only if -retime)");
+ run("abc -dff -D 1", "(only if -retime)");
}
if (check_label("map_luts"))
diff --git a/techlibs/greenpak4/synth_greenpak4.cc b/techlibs/greenpak4/synth_greenpak4.cc
index eeb001b46..3222be2e3 100644
--- a/techlibs/greenpak4/synth_greenpak4.cc
+++ b/techlibs/greenpak4/synth_greenpak4.cc
@@ -165,7 +165,7 @@ struct SynthGreenPAK4Pass : public ScriptPass
run("dfflibmap -prepare -liberty +/greenpak4/gp_dff.lib");
run("opt -fast");
if (retime || help_mode)
- run("abc -dff", "(only if -retime)");
+ run("abc -dff -D 1", "(only if -retime)");
}
if (check_label("map_luts"))
diff --git a/techlibs/ice40/synth_ice40.cc b/techlibs/ice40/synth_ice40.cc
index 8899bfcc4..d114b6269 100644
--- a/techlibs/ice40/synth_ice40.cc
+++ b/techlibs/ice40/synth_ice40.cc
@@ -274,7 +274,7 @@ struct SynthIce40Pass : public ScriptPass
else
run("techmap -map +/techmap.v -map +/ice40/arith_map.v");
if (retime || help_mode)
- run("abc -dff", "(only if -retime)");
+ run("abc -dff -D 1", "(only if -retime)");
run("ice40_opt");
}
diff --git a/techlibs/intel/synth_intel.cc b/techlibs/intel/synth_intel.cc
index 0f1d7a7b5..290282bd9 100644
--- a/techlibs/intel/synth_intel.cc
+++ b/techlibs/intel/synth_intel.cc
@@ -210,15 +210,15 @@ struct SynthIntelPass : public ScriptPass {
run("clean -purge");
run("setundef -undriven -zero");
if (retime || help_mode)
- run("abc -markgroups -dff", "(only if -retime)");
+ run("abc -markgroups -dff -D 1", "(only if -retime)");
}
if (check_label("map_luts"))
{
if(family_opt=="a10gx" || family_opt=="cyclonev")
- run("abc -luts 2:2,3,6:5" + string(retime ? " -dff" : ""));
+ run("abc -luts 2:2,3,6:5" + string(retime ? " -dff -D 1" : ""));
else
- run("abc -lut 4" + string(retime ? " -dff" : ""));
+ run("abc -lut 4" + string(retime ? " -dff -D 1" : ""));
run("clean");
}
diff --git a/techlibs/sf2/synth_sf2.cc b/techlibs/sf2/synth_sf2.cc
index 0924df7a6..3c5a58b4c 100644
--- a/techlibs/sf2/synth_sf2.cc
+++ b/techlibs/sf2/synth_sf2.cc
@@ -181,7 +181,7 @@ struct SynthSf2Pass : public ScriptPass
run("opt -undriven -fine");
run("techmap -map +/techmap.v -map +/sf2/arith_map.v");
if (retime || help_mode)
- run("abc -dff", "(only if -retime)");
+ run("abc -dff -D 1", "(only if -retime)");
}
if (check_label("map_ffs"))
diff --git a/techlibs/xilinx/ff_map.v b/techlibs/xilinx/ff_map.v
index 13beaa6ae..3d5f78770 100644
--- a/techlibs/xilinx/ff_map.v
+++ b/techlibs/xilinx/ff_map.v
@@ -28,14 +28,14 @@ module \$_DFF_P_ (input D, C, output Q); FDRE #(.INIT(|0)) _TECHMAP_REPL
module \$_DFFE_NP_ (input D, C, E, output Q); FDRE_1 #(.INIT(|0)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(E), .R(1'b0)); endmodule
module \$_DFFE_PP_ (input D, C, E, output Q); FDRE #(.INIT(|0)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(E), .R(1'b0)); endmodule
-module \$_DFF_NN0_ (input D, C, R, output Q); FDCE_1 #(.INIT(|0)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(1'b1), .CLR(!R)); endmodule
+module \$_DFF_NN0_ (input D, C, R, output Q); \$_DFF_NP0_ _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .R(~R)); endmodule
module \$_DFF_NP0_ (input D, C, R, output Q); FDCE_1 #(.INIT(|0)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(1'b1), .CLR( R)); endmodule
-module \$_DFF_PN0_ (input D, C, R, output Q); FDCE #(.INIT(|0)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(1'b1), .CLR(!R)); endmodule
+module \$_DFF_PN0_ (input D, C, R, output Q); \$_DFF_PP0_ _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .R(~R)); endmodule
module \$_DFF_PP0_ (input D, C, R, output Q); FDCE #(.INIT(|0)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(1'b1), .CLR( R)); endmodule
-module \$_DFF_NN1_ (input D, C, R, output Q); FDPE_1 #(.INIT(|0)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(1'b1), .PRE(!R)); endmodule
+module \$_DFF_NN1_ (input D, C, R, output Q); \$_DFF_NP1 _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .R(~R)); endmodule
module \$_DFF_NP1_ (input D, C, R, output Q); FDPE_1 #(.INIT(|0)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(1'b1), .PRE( R)); endmodule
-module \$_DFF_PN1_ (input D, C, R, output Q); FDPE #(.INIT(|0)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(1'b1), .PRE(!R)); endmodule
+module \$_DFF_PN1_ (input D, C, R, output Q); \$_DFF_PP1 _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .R(~R)); endmodule
module \$_DFF_PP1_ (input D, C, R, output Q); FDPE #(.INIT(|0)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(1'b1), .PRE( R)); endmodule
`endif
diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc
index 805ae8e6e..a462b9052 100644
--- a/techlibs/xilinx/synth_xilinx.cc
+++ b/techlibs/xilinx/synth_xilinx.cc
@@ -110,13 +110,14 @@ struct SynthXilinxPass : public Pass
log(" dffsr2dff\n");
log(" dff2dffe\n");
log(" opt -full\n");
- log(" techmap -map +/techmap.v -map +/xilinx/arith_map.v -map +/xilinx/ff_map.v\n");
+ log(" techmap -map +/techmap.v -map +/xilinx/arith_map.v\n");
log(" opt -fast\n");
log("\n");
log(" map_luts:\n");
- log(" abc -luts 2:2,3,6:5,10,20 [-dff] (without '-vpr' only!)\n");
- log(" abc -lut 5 [-dff] (with '-vpr' only!)\n");
+ log(" techmap -map +/techmap.v -map +/xilinx/ff_map.v t:$_DFF_?N?\n");
+ log(" abc -luts 2:2,3,6:5,10,20 [-dff -D 1]\n");
log(" clean\n");
+ log(" techmap -map +/xilinx/lut_map.v -map +/xilinx/ff_map.v");
log("\n");
log(" map_cells:\n");
log(" techmap -map +/xilinx/cells_map.v\n");
@@ -256,9 +257,9 @@ struct SynthXilinxPass : public Pass
Pass::call(design, "opt -full");
if (vpr) {
- Pass::call(design, "techmap -map +/techmap.v -map +/xilinx/arith_map.v -map +/xilinx/ff_map.v -D _EXPLICIT_CARRY");
+ Pass::call(design, "techmap -map +/techmap.v -map +/xilinx/arith_map.v -D _EXPLICIT_CARRY");
} else {
- Pass::call(design, "techmap -map +/techmap.v -map +/xilinx/arith_map.v -map +/xilinx/ff_map.v");
+ Pass::call(design, "techmap -map +/techmap.v -map +/xilinx/arith_map.v");
}
Pass::call(design, "hierarchy -check");
@@ -267,9 +268,10 @@ struct SynthXilinxPass : public Pass
if (check_label(active, run_from, run_to, "map_luts"))
{
- Pass::call(design, "abc -luts 2:2,3,6:5,10,20" + string(retime ? " -dff" : ""));
+ Pass::call(design, "techmap -map +/techmap.v -map +/xilinx/ff_map.v t:$_DFF_?N?");
+ Pass::call(design, "abc -luts 2:2,3,6:5,10,20" + string(retime ? " -dff -D 1" : ""));
Pass::call(design, "clean");
- Pass::call(design, "techmap -map +/xilinx/lut_map.v");
+ Pass::call(design, "techmap -map +/xilinx/lut_map.v -map +/xilinx/ff_map.v");
}
if (check_label(active, run_from, run_to, "map_cells"))
diff --git a/tests/simple/retime.v b/tests/simple/retime.v
new file mode 100644
index 000000000..30b6087dc
--- /dev/null
+++ b/tests/simple/retime.v
@@ -0,0 +1,6 @@
+module retime_test(input clk, input [7:0] a, output z);
+ reg [7:0] ff = 8'hF5;
+ always @(posedge clk)
+ ff <= {ff[6:0], ^a};
+ assign z = ff[7];
+endmodule
generated by cgit v1.2.3 (git 2.25.1) at 2025-04-05 19:38:30 +0000