Module *module;

SigMap sigmap;

pool<SigBit> input_bits, output_bits;

dict<SigBit, SigBit> not_map, alias_map;

dict<SigBit, pair<SigBit, SigBit>> and_map;

vector<std::tuple<SigBit,RTLIL::Cell*,RTLIL::IdString,int>> ci_bits;

vector<std::tuple<SigBit,RTLIL::Cell*,RTLIL::IdString,int,int>> co_bits;

dict<SigBit, float> arrival_times;

vector<pair<int, int>> aig_gates;

for (auto wire : module->wires())

{

bool keep = wire->attributes.count("\\keep");

for (int i = 0; i < GetSize(wire); i++)

dict<SigBit, pool<IdString>> bit_drivers, bit_users;

TopoSort<IdString, RTLIL::sort_by_id_str> toposort;

bool abc9_box_seen = false;

for (auto cell : module->selected_cells()) {

if (cell->type == "$_NOT_")

log_assert(!holes_mode);

RTLIL::Module* inst_module = module->design->module(cell->type);

if (inst_module && inst_module->attributes.count("\\abc9_box_id")) {

abc9_box_seen = true;

}

}

}

}

}

}

}

}

}

}

if (abc9_box_seen) {

for (auto &it : bit_users)

if (bit_drivers.count(it.first))

for (auto driver_cell : bit_drivers.at(it.first))

}

}

}

box_list.emplace_back(cell);

}

undriven_bits.erase(bit);

if (!undriven_bits.empty() && !holes_mode) {

undriven_bits.sort();

for (auto bit : undriven_bits) {

input_bits.insert(bit);

}

}

if (holes_mode) {

aig_map[bit] = 2*aig_m;

}

for (auto &c : ci_bits) {

RTLIL::SigBit bit = std::get<0>(c);

aig_m++, aig_i++;

}

for (auto &c : co_bits) {

aig_outputs.push_back(bit2aig(bit));

}

}

void write_aiger(std::ostream &f, bool ascii_mode)

std::stringstream h_buffer;

auto write_h_buffer = std::bind(write_buffer, std::ref(h_buffer), std::placeholders::_1);

write_h_buffer(1);

log_debug("boxNum = %d\n", GetSize(box_list));

write_h_buffer(box_list.size());

//for (auto bit : output_bits)

// write_o_buffer(0);

RTLIL::Module *holes_module = module->design->addModule("$__holes__");

log_assert(holes_module);

int port_id = 1;

int box_count = 0;

for (auto cell : box_list) {

RTLIL::Module* box_module = module->design->module(cell->type);

int box_inputs = 0, box_outputs = 0;

holes_cell = holes_module->addCell(cell->name, cell->type);

holes_cell->parameters = cell->parameters;

}

// NB: Assume box_module->ports are sorted alphabetically

RTLIL::Wire *w = box_module->wire(port_name);

log_assert(w);

RTLIL::Wire *holes_wire;

for (int i = 0; i < GetSize(w); i++) {

box_inputs++;

holes_wire = holes_module->wire(stringf("\\i%d", box_inputs));

holes_module->ports.push_back(holes_wire->name);

}

if (holes_cell)

}

if (w->port_output) {

box_outputs += GetSize(w);

for (int i = 0; i < GetSize(w); i++) {

if (GetSize(w) == 1)

else

holes_wire->port_output = true;

holes_wire->port_id = port_id++;

holes_module->ports.push_back(holes_wire->name);

if (holes_cell)

else

holes_module->connect(holes_wire, State::S0);

}

}

}

write_h_buffer(box_inputs);

std::stringstream r_buffer;

auto write_r_buffer = std::bind(write_buffer, std::ref(r_buffer), std::placeholders::_1);

f << "r";

std::string buffer_str = r_buffer.str();

int32_t buffer_size_be = to_big_endian(buffer_str.size());

f.write(reinterpret_cast<const char*>(&buffer_size_be), sizeof(buffer_size_be));

f.write(buffer_str.data(), buffer_str.size());

if (holes_module) {

log_push();

//holes_module->fixup_ports();

holes_module->check();

// TODO: Should techmap/aigmap/check all lib_whitebox-es just once,

// instead of per write_xaiger call

log_error("Whitebox contents cannot be represented as AIG. Please verify whiteboxes are synthesisable.\n");

// Move into a new (temporary) design so that "clean" will only

// operate (and run checks on) this one module

RTLIL::Design *holes_design = new RTLIL::Design;

holes_design->add(holes_module);

Pass::call(holes_design, "clean -purge");

std::stringstream a_buffer;

XAigerWriter writer(holes_module, true /* holes_mode */);

writer.write_aiger(a_buffer, false /*ascii_mode*/);

delete holes_design;

f << "a";

void write_map(std::ostream &f, bool verbose_map)

{

dict<int, string> input_lines;

dict<int, string> output_lines;

dict<int, string> wire_lines;

if (output_bits.count(b)) {

int o = ordered_outputs.at(b);

continue;

}

f << it.second;

log_assert(input_lines.size() == input_bits.size());

int box_count = 0;

for (auto cell : box_list)

f << stringf("box %d %d %s\n", box_count++, 0, log_id(cell->name));

for (auto &it : output_lines)

f << it.second;

log_assert(output_lines.size() == output_bits.size());

wire_lines.sort();

for (auto &it : wire_lines)

log(" write ASCII version of AIGER format\n");

log("\n");

log(" -map <filename>\n");

log("\n");

log(" -vmap <filename>\n");

log(" like -map, but more verbose\n");

void AigerReader::post_process()

{

pool<IdString> seen_boxes;

for (auto cell : boxes) {

RTLIL::Module* box_module = design->module(cell->type);

log_assert(box_module);

if (seen_boxes.insert(cell->type).second) {

auto it = box_module->attributes.find("\\abc9_carry");

if (it != box_module->attributes.end()) {

RTLIL::Wire *carry_in = nullptr, *carry_out = nullptr;

carry_out->port_id = ports.size();

}

}

// NB: Assume box_module->ports are sorted alphabetically

// (as RTLIL::Module::fixup_ports() would do)

}

rhs.append(wire);

}

cell->setPort(port_name, rhs);

}

}

dict<RTLIL::IdString, int> wideports_cache;

}

}

log_debug(" -> %s\n", log_id(wire));

}

else if (type == "box") {

RTLIL::Cell* cell = module->cell(stringf("$__box%d__", variable));

bool markgroups;

int map_autoidx;

inline std::string remap_name(RTLIL::IdString abc9_name)

{

return stringf("$abc$%d$%s", map_autoidx, abc9_name.c_str()+1);

}

{

// For every unique SCC found, (arbitrarily) find the first

// cell in the component, and select (and mark) all its output

}

};

bool /*keepff*/, std::string delay_target, std::string /*lutin_shared*/, bool fast_mode,

bool show_tempdir, std::string box_file, std::string lut_file,

std::string wire_delay, const dict<int,IdString> &box_lookup, bool nomfs

)

{

map_autoidx = autoidx++;

std::string tempdir_name = "/tmp/yosys-abc-XXXXXX";

if (!cleanup)

tempdir_name[0] = tempdir_name[4] = '_';

fprintf(f, "%s\n", abc9_script.c_str());

fclose(f);

bool count_output = false;

for (auto port_name : module->ports) {

RTLIL::Wire *port_wire = module->wire(port_name);

if (count_output)

{

//log("Extracted %d gates and %d wires to a netlist network with %d inputs and %d outputs.\n",

// count_gates, GetSize(signal_list), count_input, count_output);

design->remove(design->module(ID($__abc9__)));

#endif

// Now 'unexpose' those wires by undoing

// the expose operation -- remove them from PO/PI

// and re-connecting them back together

dict<IdString, bool> abc9_box;

vector<RTLIL::Cell*> boxes;

module->remove(cell);

continue;

}

dict<SigBit, std::vector<RTLIL::Cell*>> bit2sinks;

std::map<IdString, int> cell_stats;

{

RTLIL::Cell *cell = nullptr;

if (!a_bit.wire) {

RTLIL::Wire *wire = module->wire(remap_name(y_bit.wire->name));

log_assert(wire);

module->connect(RTLIL::SigBit(wire, y_bit.offset), State::S1);

if (!driver_lut) {

// If a driver couldn't be found (could be from PI or box CI)

// then implement using a LUT

RTLIL::SigBit(module->wires_.at(remap_name(a_bit.wire->name)), a_bit.offset),

RTLIL::SigBit(module->wires_.at(remap_name(y_bit.wire->name)), y_bit.offset),

RTLIL::Const::from_string("01"));

cell_stats[ID($lut)]++;

}

else

continue;

}

else

if (cell && markgroups) cell->attributes[ID(abcgroup)] = map_autoidx;

continue;

}

RTLIL::Cell *existing_cell = nullptr;

module->connect(my_y, my_a);

log_abort();

continue;

}

}

else {

log_assert(existing_cell);

}

if (markgroups) cell->attributes[ID(abcgroup)] = map_autoidx;

cell->attributes = existing_cell->attributes;

}

else {

}

RTLIL::SigSpec newsig;

for (auto c : conn.second.chunks()) {

if (c.width == 0)

}

cell->setPort(conn.first, newsig);

}

}

}

log("internally. This is not going to \"run ABC on your design\". It will instead run\n");

log("ABC on logic snippets extracted from your design. You will not get any useful\n");

log("output when passing an ABC script that writes a file. Instead write your full\n");

log("\n");

log("[1] http://www.eecs.berkeley.edu/~alanmi/abc/\n");

log("\n");

log_header(design, "Executing ABC9 pass (technology mapping using ABC9).\n");

log_push();

#ifdef ABCEXTERNAL

std::string exe_file = ABCEXTERNAL;

#else

#endif

std::string script_file, clk_str, box_file, lut_file;

std::string delay_target, lutin_shared = "-S 1", wire_delay;

bool show_tempdir = false;

bool nomfs = false;

vector<int> lut_costs;

}

}

{

continue;

continue;

}

CellTypes ct(design);

std::set<RTLIL::Cell*> unassigned_cells(all_cells.begin(), all_cells.end());

std::set<RTLIL::Cell*> expand_queue, next_expand_queue;

std::set<RTLIL::Cell*> expand_queue_up, next_expand_queue_up;

std::set<RTLIL::Cell*> expand_queue_down, next_expand_queue_down;

std::map<RTLIL::Cell*, std::set<RTLIL::SigBit>> cell_to_bit, cell_to_bit_up, cell_to_bit_down;

std::map<RTLIL::SigBit, std::set<RTLIL::Cell*>> bit_to_cell, bit_to_cell_up, bit_to_cell_down;

for (auto &conn : cell->connections())

if (bit.wire != nullptr) {

cell_to_bit[cell].insert(bit);

bit_to_cell[bit].insert(cell);

bit_to_cell_up[bit].insert(cell);

}

}

continue;

unassigned_cells.erase(cell);

expand_queue.insert(cell);

expand_queue_up.insert(cell);

expand_queue_down.insert(cell);

}

while (!expand_queue_up.empty() || !expand_queue_down.empty())

if (!expand_queue_up.empty())

{

RTLIL::Cell *cell = *expand_queue_up.begin();

expand_queue_up.erase(cell);

for (auto bit : cell_to_bit_up[cell])

if (unassigned_cells.count(c)) {

unassigned_cells.erase(c);

next_expand_queue_up.insert(c);

assigned_cells_reverse[c] = key;

expand_queue.insert(c);

}

if (!expand_queue_down.empty())

{

RTLIL::Cell *cell = *expand_queue_down.begin();

expand_queue_down.erase(cell);

for (auto bit : cell_to_bit_down[cell])

if (unassigned_cells.count(c)) {

unassigned_cells.erase(c);

next_expand_queue_up.insert(c);

assigned_cells_reverse[c] = key;

expand_queue.insert(c);

}

while (!expand_queue.empty())

{

RTLIL::Cell *cell = *expand_queue.begin();

expand_queue.erase(cell);

for (auto bit : cell_to_bit.at(cell)) {

if (unassigned_cells.count(c)) {

unassigned_cells.erase(c);

next_expand_queue.insert(c);

assigned_cells_reverse[c] = key;

}

bit_to_cell[bit].clear();

expand_queue.swap(next_expand_queue);

}

for (auto cell : unassigned_cells) {

assigned_cells_reverse[cell] = key;

}

log_header(design, "Summary of detected clock domains:\n");

for (auto &it : assigned_cells)

for (auto &it : assigned_cells) {

box_file, lut_file, wire_delay, box_lookup, nomfs);

}

}

log_pop();

}

} Abc9Pass;

*

*/

module RAM32X1D (

output DPO, SPO,

: (S0 ? I1 : I0);

endmodule

// Box to emulate comb/seq behaviour of RAMD{32,64} and SRL{16,32}

// Necessary since RAMD* and SRL* have both combinatorial (i.e.

// same-cycle read operation) and sequential (write operation

// ============================================================================

module \$__ABC9_LUT6 (input A, input [5:0] S, output Y);

assign Y = A;

endmodule

592 540 520 356 - 512 548 292 - 228

580 526 507 398 385 508 528 378 380 114

# SLICEM/A6LUT

# Box to emulate comb/seq behaviour of RAMD{32,64} and SRL{16,32}

# Necessary since RAMD* and SRL* have both combinatorial (i.e.

// Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLL_L.sdf#L238-L250

module FDRE (

(* abc9_arrival=303 *)

output reg Q,

endcase endgenerate

endmodule

(* abc9_arrival=303 *)

output reg Q,

(* clkbuf_sink *)

input C,

);

initial Q <= INIT;

endmodule

module FDCE (

(* abc9_arrival=303 *)

output reg Q,

endcase endgenerate

endmodule

module FDPE (

(* abc9_arrival=303 *)

output reg Q,

parameter [0:0] IS_PRE_INVERTED = 1'b0;

initial Q <= INIT;

generate case ({|IS_C_INVERTED, |IS_PRE_INVERTED})

endcase endgenerate

endmodule

(* abc9_arrival=303 *)

output reg Q,

(* clkbuf_sink *)

input C,

);

parameter [0:0] INIT = 1'b1;

initial Q <= INIT;

endmodule

(* abc9_arrival=303 *)

output reg Q,

(* clkbuf_sink *)

input C,

);

initial Q <= INIT;

endmodule

(* abc9_arrival=303 *)

output reg Q,

(* clkbuf_sink *)

input C,

);

parameter [0:0] INIT = 1'b1;

initial Q <= INIT;

endmodule

module LDCE (

ff_map_file = "+/xilinx/xc7_ff_map.v";

if (check_label("begin")) {

if (vpr)

run("read_verilog -lib +/xilinx/cells_xtra.v");