aboutsummaryrefslogtreecommitdiffstats
diff options
context:
space:
mode:
Diffstat
-rw-r--r--backends/edif/edif.cc43
-rw-r--r--techlibs/anlogic/synth_anlogic.cc1
-rw-r--r--techlibs/common/techmap.v3
-rw-r--r--techlibs/coolrunner2/synth_coolrunner2.cc4
-rw-r--r--techlibs/ecp5/synth_ecp5.cc1
-rw-r--r--techlibs/efinix/synth_efinix.cc1
-rw-r--r--techlibs/gowin/synth_gowin.cc2
-rw-r--r--techlibs/greenpak4/synth_greenpak4.cc3
-rw-r--r--techlibs/ice40/synth_ice40.cc1
-rw-r--r--techlibs/sf2/synth_sf2.cc1
-rwxr-xr-xtests/techmap/run-test.sh2
-rw-r--r--tests/techmap/shiftx2mux.ys11
12 files changed, 50 insertions, 23 deletions
diff --git a/backends/edif/edif.cc b/backends/edif/edif.cc
index 616b754ce..199560ad0 100644
--- a/backends/edif/edif.cc
+++ b/backends/edif/edif.cc
@@ -246,19 +246,25 @@ struct EdifBackend : public Backend {
else if (!ct.cell_input(cell_it.first, port_it.first))
dir = "OUTPUT";
}
- if (port_it.second == 1)
+ int width = port_it.second;
+ int start = 0;
+ bool upto = false;
+ auto m = design->module(cell_it.first);
+ if (m) {
+ auto w = m->wire(port_it.first);
+ if (w) {
+ width = GetSize(w);
+ start = w->start_offset;
+ upto = w->upto;
+ }
+ }
+ if (width == 1)
*f << stringf(" (port %s (direction %s))\n", EDIF_DEF(port_it.first), dir);
else {
- int b[2] = {port_it.second-1, 0};
- auto m = design->module(cell_it.first);
- if (m) {
- auto w = m->wire(port_it.first);
- if (w) {
- b[w->upto ? 0 : 1] = w->start_offset;
- b[w->upto ? 1 : 0] = w->start_offset+GetSize(w)-1;
- }
- }
- *f << stringf(" (port (array %s %d) (direction %s))\n", EDIF_DEFR(port_it.first, port_rename, b[0], b[1]), port_it.second, dir);
+ int b[2];
+ b[upto ? 0 : 1] = start;
+ b[upto ? 1 : 0] = start+width-1;
+ *f << stringf(" (port (array %s %d) (direction %s))\n", EDIF_DEFR(port_it.first, port_rename, b[0], b[1]), width, dir);
}
}
*f << stringf(" )\n");
@@ -390,18 +396,23 @@ struct EdifBackend : public Backend {
if (sig[i].wire == NULL && sig[i] != RTLIL::State::S0 && sig[i] != RTLIL::State::S1)
log_warning("Bit %d of cell port %s.%s.%s driven by %s will be left unconnected in EDIF output.\n",
i, log_id(module), log_id(cell), log_id(p.first), log_signal(sig[i]));
- else if (sig.size() == 1)
- net_join_db[sig[i]].insert(make_pair(stringf("(portRef %s (instanceRef %s))", EDIF_REF(p.first), EDIF_REF(cell->name)), cell->output(p.first)));
else {
int member_idx = GetSize(sig)-i-1;
auto m = design->module(cell->type);
+ int width = sig.size();
if (m) {
auto w = m->wire(p.first);
- if (w)
+ if (w) {
member_idx = GetSize(w)-i-1;
+ width = GetSize(w);
+ }
+ }
+ if (width == 1)
+ net_join_db[sig[i]].insert(make_pair(stringf("(portRef %s (instanceRef %s))", EDIF_REF(p.first), EDIF_REF(cell->name)), cell->output(p.first)));
+ else {
+ net_join_db[sig[i]].insert(make_pair(stringf("(portRef (member %s %d) (instanceRef %s))",
+ EDIF_REF(p.first), member_idx, EDIF_REF(cell->name)), cell->output(p.first)));
}
- net_join_db[sig[i]].insert(make_pair(stringf("(portRef (member %s %d) (instanceRef %s))",
- EDIF_REF(p.first), member_idx, EDIF_REF(cell->name)), cell->output(p.first)));
}
}
}
diff --git a/techlibs/anlogic/synth_anlogic.cc b/techlibs/anlogic/synth_anlogic.cc
index aaa6bda4a..96a231286 100644
--- a/techlibs/anlogic/synth_anlogic.cc
+++ b/techlibs/anlogic/synth_anlogic.cc
@@ -175,6 +175,7 @@ struct SynthAnlogicPass : public ScriptPass
if (check_label("map_gates"))
{
run("techmap -map +/techmap.v -map +/anlogic/arith_map.v");
+ run("opt -fast");
if (retime || help_mode)
run("abc -dff -D 1", "(only if -retime)");
}
diff --git a/techlibs/common/techmap.v b/techlibs/common/techmap.v
index 75a51e55e..be6530eb4 100644
--- a/techlibs/common/techmap.v
+++ b/techlibs/common/techmap.v
@@ -152,10 +152,11 @@ module _90_shift_shiftx (A, B, Y);
localparam len = 2**(B_WIDTH-1);
localparam Y_WIDTH2 = 2**CLOG2_Y_WIDTH;
wire [len-1:0] T, F, AA;
+ wire [(A_WIDTH+Y_WIDTH2*2):0] Apad = {{Y_WIDTH2*2{extbit}}, A};
genvar i;
for (i = 0; i < A_WIDTH; i=i+Y_WIDTH2*2) begin
assign F[i/2 +: Y_WIDTH2] = A[i +: Y_WIDTH2];
- assign T[i/2 +: Y_WIDTH2] = (i + Y_WIDTH2 < A_WIDTH) ? A[i+Y_WIDTH2 +: Y_WIDTH2] : {Y_WIDTH2{extbit}};
+ assign T[i/2 +: Y_WIDTH2] = Apad[i+Y_WIDTH2 +: Y_WIDTH2];
assign AA[i/2 +: Y_WIDTH2] = B[CLOG2_Y_WIDTH] ? T[i/2 +: Y_WIDTH2] : F[i/2 +: Y_WIDTH2];
end
wire [B_WIDTH-2:0] BB = {B[B_WIDTH-1:CLOG2_Y_WIDTH+1], {CLOG2_Y_WIDTH{1'b0}}};
diff --git a/techlibs/coolrunner2/synth_coolrunner2.cc b/techlibs/coolrunner2/synth_coolrunner2.cc
index 388e2b792..3bac8623d 100644
--- a/techlibs/coolrunner2/synth_coolrunner2.cc
+++ b/techlibs/coolrunner2/synth_coolrunner2.cc
@@ -144,8 +144,8 @@ struct SynthCoolrunner2Pass : public ScriptPass
if (check_label("fine"))
{
run("opt -fast -full");
- run("techmap");
- run("techmap -map +/coolrunner2/cells_latch.v");
+ run("techmap -map +/techmap.v -map +/coolrunner2/cells_latch.v");
+ run("opt -fast");
run("dfflibmap -prepare -liberty +/coolrunner2/xc2_dff.lib");
}
diff --git a/techlibs/ecp5/synth_ecp5.cc b/techlibs/ecp5/synth_ecp5.cc
index bce20f604..d47b2bed4 100644
--- a/techlibs/ecp5/synth_ecp5.cc
+++ b/techlibs/ecp5/synth_ecp5.cc
@@ -289,6 +289,7 @@ struct SynthEcp5Pass : public ScriptPass
run("techmap");
else
run("techmap -map +/techmap.v -map +/ecp5/arith_map.v");
+ run("opt -fast");
if (retime || help_mode)
run("abc -dff -D 1", "(only if -retime)");
}
diff --git a/techlibs/efinix/synth_efinix.cc b/techlibs/efinix/synth_efinix.cc
index 0efd91708..637d7c00d 100644
--- a/techlibs/efinix/synth_efinix.cc
+++ b/techlibs/efinix/synth_efinix.cc
@@ -175,6 +175,7 @@ struct SynthEfinixPass : public ScriptPass
if (check_label("map_gates"))
{
run("techmap -map +/techmap.v -map +/efinix/arith_map.v");
+ run("opt -fast");
if (retime || help_mode)
run("abc -dff -D 1", "(only if -retime)");
}
diff --git a/techlibs/gowin/synth_gowin.cc b/techlibs/gowin/synth_gowin.cc
index 99dd3834b..d8d8397b6 100644
--- a/techlibs/gowin/synth_gowin.cc
+++ b/techlibs/gowin/synth_gowin.cc
@@ -211,7 +211,7 @@ struct SynthGowinPass : public ScriptPass
if (check_label("map_gates"))
{
run("techmap -map +/techmap.v -map +/gowin/arith_map.v");
- run("techmap -map +/techmap.v");
+ run("opt -fast");
if (retime || help_mode)
run("abc -dff -D 1", "(only if -retime)");
run("splitnets");
diff --git a/techlibs/greenpak4/synth_greenpak4.cc b/techlibs/greenpak4/synth_greenpak4.cc
index e1fbe6b69..bfbb56d15 100644
--- a/techlibs/greenpak4/synth_greenpak4.cc
+++ b/techlibs/greenpak4/synth_greenpak4.cc
@@ -160,8 +160,7 @@ struct SynthGreenPAK4Pass : public ScriptPass
run("opt -fast -mux_undef -undriven -fine");
run("memory_map");
run("opt -undriven -fine");
- run("techmap");
- run("techmap -map +/greenpak4/cells_latch.v");
+ run("techmap -map +/techmap.v -map +/greenpak4/cells_latch.v");
run("dfflibmap -prepare -liberty +/greenpak4/gp_dff.lib");
run("opt -fast");
if (retime || help_mode)
diff --git a/techlibs/ice40/synth_ice40.cc b/techlibs/ice40/synth_ice40.cc
index d92e40726..fdb203dcb 100644
--- a/techlibs/ice40/synth_ice40.cc
+++ b/techlibs/ice40/synth_ice40.cc
@@ -316,6 +316,7 @@ struct SynthIce40Pass : public ScriptPass
run("ice40_wrapcarry");
run("techmap -map +/techmap.v -map +/ice40/arith_map.v");
}
+ run("opt -fast");
if (retime || help_mode)
run("abc -dff -D 1", "(only if -retime)");
run("ice40_opt");
diff --git a/techlibs/sf2/synth_sf2.cc b/techlibs/sf2/synth_sf2.cc
index 543dfdb9e..5efa005c8 100644
--- a/techlibs/sf2/synth_sf2.cc
+++ b/techlibs/sf2/synth_sf2.cc
@@ -180,6 +180,7 @@ struct SynthSf2Pass : public ScriptPass
run("memory_map");
run("opt -undriven -fine");
run("techmap -map +/techmap.v -map +/sf2/arith_map.v");
+ run("opt -fast");
if (retime || help_mode)
run("abc -dff -D 1", "(only if -retime)");
}
diff --git a/tests/techmap/run-test.sh b/tests/techmap/run-test.sh
index 96489ff15..c16f204d9 100755
--- a/tests/techmap/run-test.sh
+++ b/tests/techmap/run-test.sh
@@ -6,7 +6,7 @@ for x in *.ys; do
echo "all:: run-$x"
echo "run-$x:"
echo " @echo 'Running $x..'"
- echo " @../../yosys -ql ${x%.ys}.log $x"
+ echo " @../../yosys -ql ${x%.ys}.log -e 'select out of bounds' $x"
done
for s in *.sh; do
if [ "$s" != "run-test.sh" ]; then
diff --git a/tests/techmap/shiftx2mux.ys b/tests/techmap/shiftx2mux.ys
index c13b5f600..eb29680f6 100644
--- a/tests/techmap/shiftx2mux.ys
+++ b/tests/techmap/shiftx2mux.ys
@@ -108,3 +108,14 @@ design -import gate -as gate
miter -equiv -flatten -make_assert -make_outputs gold gate miter
sat -verify -prove-asserts -show-ports miter
+
+design -reset
+read_verilog <<EOT
+module top(input [6:0] A, input [1:0] B, output [1:0] Y);
+wire [7:0] AA = {1'bx, A};
+assign Y = AA[B*2 +: 2];
+endmodule
+EOT
+opt
+wreduce
+equiv_opt techmap
generated by cgit v1.2.3 (git 2.25.1) at 2025-04-07 13:34:04 +0000