diff options
32 files changed, 718 insertions, 68 deletions
diff --git a/.travis.yml b/.travis.yml index 1c08c21a8..fbb4018af 100644 --- a/.travis.yml +++ b/.travis.yml @@ -1,36 +1,153 @@ sudo: false -script: make && make test language: cpp -addons: - apt: - sources: - - ubuntu-toolchain-r-test - packages: - - gperf - - build-essential - - clang - - bison - - flex - - libreadline-dev - - gawk - - tcl-dev - - libffi-dev - - git - - mercurial - - graphviz - - xdot - - pkg-config - - python - - g++-4.8 + +cache: + ccache: true + directories: + - ~/.local-bin + + +env: + global: + - MAKEFLAGS="-j 2" + +matrix: + include: + # Latest gcc-4.8, earliest version supported by Travis + - os: linux + addons: + apt: + packages: + - g++-4.8 + - gperf + - build-essential + - bison + - flex + - libreadline-dev + - gawk + - tcl-dev + - libffi-dev + - git + - mercurial + - graphviz + - xdot + - pkg-config + - python + env: + - MATRIX_EVAL="CONFIG=gcc && CC=gcc-4.8 && CXX=g++-4.8" + + # Latest gcc-6 on Travis Linux + - os: linux + addons: + apt: + sources: + - ubuntu-toolchain-r-test + packages: + - g++-6 + - gperf + - build-essential + - bison + - flex + - libreadline-dev + - gawk + - tcl-dev + - libffi-dev + - git + - mercurial + - graphviz + - xdot + - pkg-config + - python + env: + - MATRIX_EVAL="CONFIG=gcc && CC=gcc-6 && CXX=g++-6" + + # Latest gcc supported on Travis Linux + - os: linux + addons: + apt: + sources: + - ubuntu-toolchain-r-test + packages: + - g++-7 + - gperf + - build-essential + - bison + - flex + - libreadline-dev + - gawk + - tcl-dev + - libffi-dev + - git + - mercurial + - graphviz + - xdot + - pkg-config + - python + env: + - MATRIX_EVAL="CONFIG=gcc && CC=gcc-7 && CXX=g++-7" + + # Clang which ships on Trusty Linux + - os: linux + addons: + apt: + sources: + - ubuntu-toolchain-r-test + - llvm-toolchain-precise-3.8 + packages: + - clang-3.8 + - gperf + - build-essential + - bison + - flex + - libreadline-dev + - gawk + - tcl-dev + - libffi-dev + - git + - mercurial + - graphviz + - xdot + - pkg-config + - python + env: + - MATRIX_EVAL="CONFIG=clang && CC=clang-3.8 && CXX=clang++-3.8" + + # Latest clang supported by Travis Linux + - os: linux + addons: + apt: + sources: + - llvm-toolchain-trusty-5.0 + packages: + - clang-5.0 + - gperf + - build-essential + - bison + - flex + - libreadline-dev + - gawk + - tcl-dev + - libffi-dev + - git + - mercurial + - graphviz + - xdot + - pkg-config + - python + env: + - MATRIX_EVAL="CONFIG=clang && CC=clang-5.0 && CXX=clang++-5.0" + + # Latest clang on Mac OS X + - os: osx + osx_image: xcode8 + env: + - MATRIX_EVAL="CONFIG=gcc && CC=gcc-7 && CXX=g++-7" + before_install: - - if [ "$CXX" = "g++" ]; then export CXX="g++-4.8" CC="gcc-4.8"; fi - - if [[ "$TRAVIS_OS_NAME" == "osx" ]]; then brew tap Homebrew/bundle && brew bundle; fi - - git clone git://github.com/steveicarus/iverilog.git - - (cd iverilog && autoconf && ./configure --prefix=$HOME/iverilog && make && make install) - - export PATH=$PATH:$HOME/iverilog/bin -compiler: -# - clang - - gcc -os: - - linux -# - osx + - ./.travis/setup.sh + +script: + - ./.travis/build-and-test.sh + +after_success: + - ./.travis/deploy-after-success.sh diff --git a/.travis/build-and-test.sh b/.travis/build-and-test.sh new file mode 100755 index 000000000..096dde64f --- /dev/null +++ b/.travis/build-and-test.sh @@ -0,0 +1,49 @@ +#! /bin/bash + +set -e + +source .travis/common.sh + +########################################################################## + +echo +echo 'Configuring...' && echo -en 'travis_fold:start:script.configure\\r' +echo + +if [ "$CONFIG" = "gcc" ]; then + echo "Configuring for gcc." + make config-gcc +elif [ "$CONFIG" = "clang" ]; then + echo "Configuring for clang." + make config-clang +fi + +echo +echo -en 'travis_fold:end:script.configure\\r' +echo + +########################################################################## + +echo +echo 'Building...' && echo -en 'travis_fold:start:script.build\\r' +echo + +make + +echo +echo -en 'travis_fold:end:script.build\\r' +echo + +########################################################################## + +echo +echo 'Testing...' && echo -en 'travis_fold:start:script.test\\r' +echo + +make test + +echo +echo -en 'travis_fold:end:script.test\\r' +echo + +########################################################################## diff --git a/.travis/common.sh b/.travis/common.sh new file mode 100644 index 000000000..8eecc4c09 --- /dev/null +++ b/.travis/common.sh @@ -0,0 +1,15 @@ +#! /bin/bash + +# Setup the CC / CXX from the matrix config +eval "${MATRIX_EVAL}" + +# Look for location binaries first +export PATH="$HOME/.local-bin/bin:$PATH" + +# OS X specific common setup +if [[ "$TRAVIS_OS_NAME" == "osx" ]]; then + export PATH="/usr/local/opt/ccache/libexec:$PATH" +fi + +# Parallel builds! +MAKEFLAGS="-j 2" diff --git a/.travis/deploy-after-success.sh b/.travis/deploy-after-success.sh new file mode 100755 index 000000000..d64e95244 --- /dev/null +++ b/.travis/deploy-after-success.sh @@ -0,0 +1,6 @@ +#! /bin/bash + +set -x +set -e + +# FIXME: Upload the build results somewhere... diff --git a/.travis/setup.sh b/.travis/setup.sh new file mode 100755 index 000000000..81ff37742 --- /dev/null +++ b/.travis/setup.sh @@ -0,0 +1,97 @@ +#! /bin/bash + +set -e + +source .travis/common.sh + +########################################################################## + +# Fixing Travis's git clone +echo +echo 'Fixing git setup...' && echo -en 'travis_fold:start:before_install.git\\r' +echo +git fetch --unshallow && git fetch --tags + +# For pull requests, we get more info about the git source. +if [ z"$TRAVIS_PULL_REQUEST_SLUG" != z ]; then + echo "- Fetching from pull request source" + git remote add source https://github.com/$TRAVIS_PULL_REQUEST_SLUG.git + git fetch source && git fetch --tags + + echo "- Fetching the actual pull request" + git fetch origin pull/$TRAVIS_PULL_REQUEST/head:pull-$TRAVIS_PULL_REQUEST-head + git fetch origin pull/$TRAVIS_PULL_REQUEST/merge:pull-$TRAVIS_PULL_REQUEST-merge + + git log -n 5 --graph pull-$TRAVIS_PULL_REQUEST-merge +fi + +# For building branches we need to fix the "detached head" state. +if [ z"$TRAVIS_BRANCH" != z ]; then + TRAVIS_COMMIT_ACTUAL=$(git log --pretty=format:'%H' -n 1) + echo "- Fixing detached head (current $TRAVIS_COMMIT_ACTUAL -> $TRAVIS_COMMIT)" + git remote -v + git branch -v + if [ x"$(git show-ref -s HEAD)" = x"$TRAVIS_COMMIT" ]; then + echo "Checked out at $TRAVIS_COMMIT" + else + if [ z"$TRAVIS_PULL_REQUEST_SLUG" != z ]; then + git fetch source $TRAVIS_COMMIT || echo "Unable to fetch $TRAVIS_COMMIT from source" + fi + git fetch origin $TRAVIS_COMMIT || echo "Unable to fetch $TRAVIS_COMMIT from origin" + fi + git branch -D $TRAVIS_BRANCH || true + git checkout $TRAVIS_COMMIT -b $TRAVIS_BRANCH + git branch -v +fi + +# Output status information. +git status +git describe --tags +git log -n 5 --graph +echo +echo -en 'travis_fold:end:before_install.git\\r' +echo + +########################################################################## + +# Mac OS X specific setup. +if [[ "$TRAVIS_OS_NAME" == "osx" ]]; then + ( + echo + echo 'Setting up brew...' && echo -en 'travis_fold:start:before_install.brew\\r' + echo + brew update + brew tap Homebrew/bundle + brew bundle + brew install ccache + brew install gcc + echo + echo -en 'travis_fold:end:before_install.brew\\r' + echo + ) +fi + +########################################################################## + +# Install iverilog +( + if [ ! -e ~/.local-bin/bin/iverilog ]; then + echo + echo 'Building iverilog...' && echo -en 'travis_fold:start:before_install.iverilog\\r' + echo + mkdir -p ~/.local-src + mkdir -p ~/.local-bin + cd ~/.local-src + git clone git://github.com/steveicarus/iverilog.git + cd iverilog + autoconf + ./configure --prefix=$HOME/.local-bin + make + make install + echo + echo -en 'travis_fold:end:before_install.iverilog\\r' + echo + fi +) + +########################################################################## diff --git a/backends/smt2/smtbmc.py b/backends/smt2/smtbmc.py index d9b79e26e..560e39d86 100644 --- a/backends/smt2/smtbmc.py +++ b/backends/smt2/smtbmc.py @@ -1279,7 +1279,7 @@ else: # not tempind, covermode step += step_size - if gentrace: + if gentrace and retstatus: print_anyconsts(0) write_trace(0, num_steps, '%') diff --git a/examples/intel/DE2i-150/run_cycloneiv b/examples/intel/DE2i-150/run_cycloneiv index 321ed2778..518807b57 100644 --- a/examples/intel/DE2i-150/run_cycloneiv +++ b/examples/intel/DE2i-150/run_cycloneiv @@ -1,2 +1,2 @@ #/bin/env bash -yosys -p "synth_intel -family cycloneiv -top top -vout top.vqm" top.v sevenseg.v +yosys -p "synth_intel -family cycloneiv -top top -vqm top.vqm" top.v sevenseg.v diff --git a/examples/intel/MAX10/run_max10 b/examples/intel/MAX10/run_max10 index ef7649afb..0378e4fa7 100644 --- a/examples/intel/MAX10/run_max10 +++ b/examples/intel/MAX10/run_max10 @@ -1 +1 @@ -yosys -p "synth_intel -family max10 -top top -vout top.vqm" top.v sevenseg.v +yosys -p "synth_intel -family max10 -top top -vqm top.vqm" top.v sevenseg.v diff --git a/examples/intel/asicworld_lfsr/run_cycloneiv b/examples/intel/asicworld_lfsr/run_cycloneiv index cb7f5c9b1..c7498bded 100755 --- a/examples/intel/asicworld_lfsr/run_cycloneiv +++ b/examples/intel/asicworld_lfsr/run_cycloneiv @@ -1,2 +1,2 @@ #!/bin/env bash -yosys -p "synth_intel -family cycloneiv -top lfsr_updown -vout top.vqm" lfsr_updown.v +yosys -p "synth_intel -family cycloneiv -top lfsr_updown -vqm top.vqm" lfsr_updown.v diff --git a/examples/intel/asicworld_lfsr/run_max10 b/examples/intel/asicworld_lfsr/run_max10 index 6bb812c16..b75d552bb 100755 --- a/examples/intel/asicworld_lfsr/run_max10 +++ b/examples/intel/asicworld_lfsr/run_max10 @@ -1,2 +1,2 @@ #!/bin/env bash -yosys -p "synth_intel -family max10 -top lfsr_updown -vout top.vqm" lfsr_updown.v +yosys -p "synth_intel -family max10 -top lfsr_updown -vqm top.vqm" lfsr_updown.v diff --git a/frontends/verilog/preproc.cc b/frontends/verilog/preproc.cc index ee742d485..00bdcee43 100644 --- a/frontends/verilog/preproc.cc +++ b/frontends/verilog/preproc.cc @@ -366,14 +366,31 @@ std::string frontend_verilog_preproc(std::istream &f, std::string filename, cons ff.clear(); std::string fixed_fn = fn; ff.open(fixed_fn.c_str()); - if (ff.fail() && fn.size() > 0 && fn[0] != '/' && filename.find('/') != std::string::npos) { + + bool filename_path_sep_found; + bool fn_relative; +#ifdef _WIN32 + // Both forward and backslash are acceptable separators on Windows. + filename_path_sep_found = (filename.find_first_of("/\\") != std::string::npos); + // Easier just to invert the check for an absolute path (e.g. C:\ or C:/) + fn_relative = !(fn[1] == ':' && (fn[2] == '/' || fn[2] == '\\')); +#else + filename_path_sep_found = (filename.find('/') != std::string::npos); + fn_relative = (fn[0] != '/'); +#endif + + if (ff.fail() && fn.size() > 0 && fn_relative && filename_path_sep_found) { // if the include file was not found, it is not given with an absolute path, and the // currently read file is given with a path, then try again relative to its directory ff.clear(); +#ifdef _WIN32 + fixed_fn = filename.substr(0, filename.find_last_of("/\\")+1) + fn; +#else fixed_fn = filename.substr(0, filename.rfind('/')+1) + fn; +#endif ff.open(fixed_fn); } - if (ff.fail() && fn.size() > 0 && fn[0] != '/') { + if (ff.fail() && fn.size() > 0 && fn_relative) { // if the include file was not found and it is not given with an absolute path, then // search it in the include path for (auto incdir : include_dirs) { @@ -505,7 +522,7 @@ std::string frontend_verilog_preproc(std::istream &f, std::string filename, cons if (try_expand_macro(defines_with_args, defines_map, tok)) continue; - + output_code.push_back(tok); } @@ -521,4 +538,3 @@ std::string frontend_verilog_preproc(std::istream &f, std::string filename, cons } YOSYS_NAMESPACE_END - diff --git a/frontends/verilog/verilog_lexer.l b/frontends/verilog/verilog_lexer.l index 07d85bed8..d6d00c371 100644 --- a/frontends/verilog/verilog_lexer.l +++ b/frontends/verilog/verilog_lexer.l @@ -170,6 +170,7 @@ YOSYS_NAMESPACE_END "endgenerate" { return TOK_ENDGENERATE; } "while" { return TOK_WHILE; } "repeat" { return TOK_REPEAT; } +"automatic" { return TOK_AUTOMATIC; } "unique" { SV_KEYWORD(TOK_UNIQUE); } "unique0" { SV_KEYWORD(TOK_UNIQUE); } diff --git a/frontends/verilog/verilog_parser.y b/frontends/verilog/verilog_parser.y index ec92f6628..9aa01c9f0 100644 --- a/frontends/verilog/verilog_parser.y +++ b/frontends/verilog/verilog_parser.y @@ -108,7 +108,7 @@ static void free_attr(std::map<std::string, AstNode*> *al) %token TOK_INPUT TOK_OUTPUT TOK_INOUT TOK_WIRE TOK_REG %token TOK_INTEGER TOK_SIGNED TOK_ASSIGN TOK_ALWAYS TOK_INITIAL %token TOK_BEGIN TOK_END TOK_IF TOK_ELSE TOK_FOR TOK_WHILE TOK_REPEAT -%token TOK_DPI_FUNCTION TOK_POSEDGE TOK_NEGEDGE TOK_OR +%token TOK_DPI_FUNCTION TOK_POSEDGE TOK_NEGEDGE TOK_OR TOK_AUTOMATIC %token TOK_CASE TOK_CASEX TOK_CASEZ TOK_ENDCASE TOK_DEFAULT %token TOK_FUNCTION TOK_ENDFUNCTION TOK_TASK TOK_ENDTASK %token TOK_GENERATE TOK_ENDGENERATE TOK_GENVAR TOK_REAL @@ -359,6 +359,7 @@ package_body_stmt: non_opt_delay: '#' TOK_ID { delete $2; } | '#' TOK_CONSTVAL { delete $2; } | + '#' TOK_REALVAL { delete $2; } | '#' '(' expr ')' { delete $3; } | '#' '(' expr ':' expr ':' expr ')' { delete $3; delete $5; delete $7; }; @@ -523,35 +524,35 @@ task_func_decl: } opt_dpi_function_args ';' { current_function_or_task = NULL; } | - attr TOK_TASK TOK_ID { + attr TOK_TASK opt_automatic TOK_ID { current_function_or_task = new AstNode(AST_TASK); - current_function_or_task->str = *$3; + current_function_or_task->str = *$4; append_attr(current_function_or_task, $1); ast_stack.back()->children.push_back(current_function_or_task); ast_stack.push_back(current_function_or_task); current_function_or_task_port_id = 1; - delete $3; + delete $4; } task_func_args_opt ';' task_func_body TOK_ENDTASK { current_function_or_task = NULL; ast_stack.pop_back(); } | - attr TOK_FUNCTION opt_signed range_or_signed_int TOK_ID { + attr TOK_FUNCTION opt_automatic opt_signed range_or_signed_int TOK_ID { current_function_or_task = new AstNode(AST_FUNCTION); - current_function_or_task->str = *$5; + current_function_or_task->str = *$6; append_attr(current_function_or_task, $1); ast_stack.back()->children.push_back(current_function_or_task); ast_stack.push_back(current_function_or_task); AstNode *outreg = new AstNode(AST_WIRE); - outreg->str = *$5; - outreg->is_signed = $3; - if ($4 != NULL) { - outreg->children.push_back($4); - outreg->is_signed = $3 || $4->is_signed; - $4->is_signed = false; + outreg->str = *$6; + outreg->is_signed = $4; + if ($5 != NULL) { + outreg->children.push_back($5); + outreg->is_signed = $4 || $5->is_signed; + $5->is_signed = false; } current_function_or_task->children.push_back(outreg); current_function_or_task_port_id = 1; - delete $5; + delete $6; } task_func_args_opt ';' task_func_body TOK_ENDFUNCTION { current_function_or_task = NULL; ast_stack.pop_back(); @@ -578,6 +579,10 @@ dpi_function_args: dpi_function_arg | /* empty */; +opt_automatic: + TOK_AUTOMATIC | + /* empty */; + opt_signed: TOK_SIGNED { $$ = true; diff --git a/libs/ezsat/ezminisat.cc b/libs/ezsat/ezminisat.cc index e0ee6292d..4be5fd493 100644 --- a/libs/ezsat/ezminisat.cc +++ b/libs/ezsat/ezminisat.cc @@ -18,8 +18,12 @@ */ // needed for MiniSAT headers (see Minisat Makefile) -#define __STDC_LIMIT_MACROS +#ifndef __STDC_FORMAT_MACROS #define __STDC_FORMAT_MACROS +#endif +#ifndef __STDC_LIMIT_MACROS +#define __STDC_LIMIT_MACROS +#endif #include "ezminisat.h" diff --git a/libs/minisat/00_PATCH_remove_zlib.patch b/libs/minisat/00_PATCH_remove_zlib.patch index 61a36f7e5..068356b73 100644 --- a/libs/minisat/00_PATCH_remove_zlib.patch +++ b/libs/minisat/00_PATCH_remove_zlib.patch @@ -36,3 +36,20 @@ int operator * () const { return (pos >= size) ? EOF : buf[pos]; } void operator ++ () { pos++; assureLookahead(); } +--- Dimacs.h ++++ Dimacs.h +@@ -76,10 +76,10 @@ static void parse_DIMACS_main(B& in, Solver& S, bool strictp = false) { + + // Inserts problem into solver. + // +-template<class Solver> +-static void parse_DIMACS(gzFile input_stream, Solver& S, bool strictp = false) { +- StreamBuffer in(input_stream); +- parse_DIMACS_main(in, S, strictp); } ++//template<class Solver> ++//static void parse_DIMACS(gzFile input_stream, Solver& S, bool strictp = false) { ++// StreamBuffer in(input_stream); ++// parse_DIMACS_main(in, S, strictp); } + + //================================================================================================= + } diff --git a/libs/minisat/00_UPDATE.sh b/libs/minisat/00_UPDATE.sh index 2ffc11553..ea26215ab 100644..100755 --- a/libs/minisat/00_UPDATE.sh +++ b/libs/minisat/00_UPDATE.sh @@ -9,8 +9,8 @@ rm -rf minisat_upstream sed -i -e 's,^#include *"minisat/[^/]\+/\?,#include ",' *.cc *.h sed -i -e 's/Minisat::memUsedPeak()/Minisat::memUsedPeak(bool)/' System.cc sed -i -e 's/PRI[iu]64/ & /' Options.h Solver.cc -sed -i -e '1 i #define __STDC_LIMIT_MACROS' *.cc -sed -i -e '1 i #define __STDC_FORMAT_MACROS' *.cc +sed -i -e '1 i #ifndef __STDC_LIMIT_MACROS\n#define __STDC_LIMIT_MACROS\n#endif' *.cc +sed -i -e '1 i #ifndef __STDC_FORMAT_MACROS\n#define __STDC_FORMAT_MACROS\n#endif' *.cc patch -p0 < 00_PATCH_mkLit_default_arg.patch patch -p0 < 00_PATCH_remove_zlib.patch diff --git a/libs/minisat/Dimacs.h b/libs/minisat/Dimacs.h index ccfa1c013..61b9d3ca0 100644 --- a/libs/minisat/Dimacs.h +++ b/libs/minisat/Dimacs.h @@ -76,10 +76,10 @@ static void parse_DIMACS_main(B& in, Solver& S, bool strictp = false) { // Inserts problem into solver. // -template<class Solver> -static void parse_DIMACS(gzFile input_stream, Solver& S, bool strictp = false) { - StreamBuffer in(input_stream); - parse_DIMACS_main(in, S, strictp); } +//template<class Solver> +//static void parse_DIMACS(gzFile input_stream, Solver& S, bool strictp = false) { +// StreamBuffer in(input_stream); +// parse_DIMACS_main(in, S, strictp); } //================================================================================================= } diff --git a/libs/minisat/Options.cc b/libs/minisat/Options.cc index 1aff3fab2..5c45dd6ac 100644 --- a/libs/minisat/Options.cc +++ b/libs/minisat/Options.cc @@ -1,5 +1,9 @@ +#ifndef __STDC_FORMAT_MACROS #define __STDC_FORMAT_MACROS +#endif +#ifndef __STDC_LIMIT_MACROS #define __STDC_LIMIT_MACROS +#endif /**************************************************************************************[Options.cc] Copyright (c) 2008-2010, Niklas Sorensson diff --git a/libs/minisat/SimpSolver.cc b/libs/minisat/SimpSolver.cc index fd5774e0e..7348a905d 100644 --- a/libs/minisat/SimpSolver.cc +++ b/libs/minisat/SimpSolver.cc @@ -1,5 +1,9 @@ +#ifndef __STDC_FORMAT_MACROS #define __STDC_FORMAT_MACROS +#endif +#ifndef __STDC_LIMIT_MACROS #define __STDC_LIMIT_MACROS +#endif /***********************************************************************************[SimpSolver.cc] Copyright (c) 2006, Niklas Een, Niklas Sorensson Copyright (c) 2007-2010, Niklas Sorensson diff --git a/libs/minisat/Solver.cc b/libs/minisat/Solver.cc index ab476853a..f6d4fb5ae 100644 --- a/libs/minisat/Solver.cc +++ b/libs/minisat/Solver.cc @@ -1,5 +1,9 @@ +#ifndef __STDC_FORMAT_MACROS #define __STDC_FORMAT_MACROS +#endif +#ifndef __STDC_LIMIT_MACROS #define __STDC_LIMIT_MACROS +#endif /***************************************************************************************[Solver.cc] Copyright (c) 2003-2006, Niklas Een, Niklas Sorensson Copyright (c) 2007-2010, Niklas Sorensson diff --git a/libs/minisat/System.cc b/libs/minisat/System.cc index ceef4292b..1921a1d71 100644 --- a/libs/minisat/System.cc +++ b/libs/minisat/System.cc @@ -1,5 +1,9 @@ +#ifndef __STDC_FORMAT_MACROS #define __STDC_FORMAT_MACROS +#endif +#ifndef __STDC_LIMIT_MACROS #define __STDC_LIMIT_MACROS +#endif /***************************************************************************************[System.cc] Copyright (c) 2003-2006, Niklas Een, Niklas Sorensson Copyright (c) 2007-2010, Niklas Sorensson diff --git a/libs/subcircuit/subcircuit.h b/libs/subcircuit/subcircuit.h index 5291c6421..8368efab1 100644 --- a/libs/subcircuit/subcircuit.h +++ b/libs/subcircuit/subcircuit.h @@ -131,7 +131,7 @@ namespace SubCircuit public: Solver(); - ~Solver(); + virtual ~Solver(); void setVerbose(); void addGraph(std::string graphId, const Graph &graph); diff --git a/techlibs/achronix/Makefile.inc b/techlibs/achronix/Makefile.inc index 4dfa59856..affe0334a 100755 --- a/techlibs/achronix/Makefile.inc +++ b/techlibs/achronix/Makefile.inc @@ -1,6 +1,6 @@ OBJS += techlibs/achronix/synth_speedster.o -$(eval $(call add_share_file,share/achronix/speedster22i/,techlibs/achronix/speedster22i/cells_comb_speedster.v)) -$(eval $(call add_share_file,share/achronix/speedster22i/,techlibs/achronix/speedster22i/cells_map_speedster.v)) +$(eval $(call add_share_file,share/achronix/speedster22i/,techlibs/achronix/speedster22i/cells_sim.v)) +$(eval $(call add_share_file,share/achronix/speedster22i/,techlibs/achronix/speedster22i/cells_map.v)) diff --git a/techlibs/achronix/speedster22i/cells_arith_speedster.v b/techlibs/achronix/speedster22i/cells_arith.v index 9ef073f7c..9ef073f7c 100755 --- a/techlibs/achronix/speedster22i/cells_arith_speedster.v +++ b/techlibs/achronix/speedster22i/cells_arith.v diff --git a/techlibs/achronix/speedster22i/cells_map_speedster.v b/techlibs/achronix/speedster22i/cells_map.v index fb26eabf0..fb26eabf0 100755 --- a/techlibs/achronix/speedster22i/cells_map_speedster.v +++ b/techlibs/achronix/speedster22i/cells_map.v diff --git a/techlibs/achronix/speedster22i/cells_comb_speedster.v b/techlibs/achronix/speedster22i/cells_sim.v index 24c57c41a..24c57c41a 100755 --- a/techlibs/achronix/speedster22i/cells_comb_speedster.v +++ b/techlibs/achronix/speedster22i/cells_sim.v diff --git a/techlibs/achronix/synth_speedster.cc b/techlibs/achronix/synth_speedster.cc index 8158c56fd..3808af6f1 100755 --- a/techlibs/achronix/synth_speedster.cc +++ b/techlibs/achronix/synth_speedster.cc @@ -122,7 +122,7 @@ struct SynthIntelPass : public ScriptPass { { if (check_label("begin")) { - run("read_verilog -sv -lib +/achronix/speedster22i/cells_comb_speedster.v"); + run("read_verilog -sv -lib +/achronix/speedster22i/cells_sim.v"); run(stringf("hierarchy -check %s", help_mode ? "-top <top>" : top_opt.c_str())); } @@ -164,7 +164,7 @@ struct SynthIntelPass : public ScriptPass { if (check_label("map_cells")) { run("iopadmap -bits -outpad $__outpad I:O -inpad $__inpad O:I"); - run("techmap -map +/achronix/speedster22i/cells_map_speedster.v"); + run("techmap -map +/achronix/speedster22i/cells_map.v"); run("dffinit -ff dffeas Q INIT"); run("clean -purge"); } diff --git a/techlibs/intel/Makefile.inc b/techlibs/intel/Makefile.inc index 429d23677..ec7cea379 100644 --- a/techlibs/intel/Makefile.inc +++ b/techlibs/intel/Makefile.inc @@ -8,11 +8,13 @@ $(eval $(call add_share_file,share/intel/common,techlibs/intel/common/brams_map. $(eval $(call add_share_file,share/intel/max10,techlibs/intel/max10/cells_sim.v)) $(eval $(call add_share_file,share/intel/a10gx,techlibs/intel/a10gx/cells_sim.v)) $(eval $(call add_share_file,share/intel/cyclonev,techlibs/intel/cyclonev/cells_sim.v)) +$(eval $(call add_share_file,share/intel/cyclone10,techlibs/intel/cyclone10/cells_sim.v)) $(eval $(call add_share_file,share/intel/cycloneiv,techlibs/intel/cycloneiv/cells_sim.v)) $(eval $(call add_share_file,share/intel/cycloneive,techlibs/intel/cycloneive/cells_sim.v)) $(eval $(call add_share_file,share/intel/max10,techlibs/intel/max10/cells_map.v)) $(eval $(call add_share_file,share/intel/a10gx,techlibs/intel/a10gx/cells_map.v)) $(eval $(call add_share_file,share/intel/cyclonev,techlibs/intel/cyclonev/cells_map.v)) +$(eval $(call add_share_file,share/intel/cyclone10,techlibs/intel/cyclone10/cells_map.v)) $(eval $(call add_share_file,share/intel/cycloneiv,techlibs/intel/cycloneiv/cells_map.v)) $(eval $(call add_share_file,share/intel/cycloneive,techlibs/intel/cycloneive/cells_map.v)) #$(eval $(call add_share_file,share/intel/max10,techlibs/intel/max10/arith_map.v)) diff --git a/techlibs/intel/cyclone10/cells_arith.v b/techlibs/intel/cyclone10/cells_arith.v new file mode 100644 index 000000000..5ae8d6cea --- /dev/null +++ b/techlibs/intel/cyclone10/cells_arith.v @@ -0,0 +1,65 @@ +/* + * yosys -- Yosys Open SYnthesis Suite + * + * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at> + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + * + */ + +// NOTE: This is still WIP. +(* techmap_celltype = "$alu" *) +module _80_altera_a10gx_alu (A, B, CI, BI, X, Y, CO); + parameter A_SIGNED = 0; + parameter B_SIGNED = 0; + parameter A_WIDTH = 1; + parameter B_WIDTH = 1; + parameter Y_WIDTH = 1; + + input [A_WIDTH-1:0] A; + input [B_WIDTH-1:0] B; + output [Y_WIDTH-1:0] X, Y; + + input CI, BI; + //output [Y_WIDTH-1:0] CO; + output CO; + + wire _TECHMAP_FAIL_ = Y_WIDTH <= 4; + + wire [Y_WIDTH-1:0] A_buf, B_buf; + \$pos #(.A_SIGNED(A_SIGNED), .A_WIDTH(A_WIDTH), .Y_WIDTH(Y_WIDTH)) A_conv (.A(A), .Y(A_buf)); + \$pos #(.A_SIGNED(B_SIGNED), .A_WIDTH(B_WIDTH), .Y_WIDTH(Y_WIDTH)) B_conv (.A(B), .Y(B_buf)); + + wire [Y_WIDTH-1:0] AA = A_buf; + wire [Y_WIDTH-1:0] BB = BI ? ~B_buf : B_buf; + //wire [Y_WIDTH:0] C = {CO, CI}; + wire [Y_WIDTH+1:0] COx; + wire [Y_WIDTH+1:0] C = {COx, CI}; + + /* Start implementation */ + (* keep *) cyclone10lp_lcell_comb #(.lut_mask(16'b0000_0000_1010_1010), .sum_lutc_input("cin")) carry_start (.cout(COx[0]), .dataa(C[0]), .datab(1'b1), .datac(1'b1), .datad(1'b1)); + + genvar i; + generate for (i = 0; i < Y_WIDTH; i = i + 1) begin: slice + if(i==Y_WIDTH-1) begin + (* keep *) cyclone10lp_lcell_comb #(.lut_mask(16'b1111_0000_1110_0000), .sum_lutc_input("cin")) carry_end (.combout(COx[Y_WIDTH]), .dataa(1'b1), .datab(1'b1), .datac(1'b1), .datad(1'b1), .cin(C[Y_WIDTH])); + assign CO = COx[Y_WIDTH]; + end + else + cyclone10lp_lcell_comb #(.lut_mask(16'b1001_0110_1110_1000), .sum_lutc_input("cin")) arith_cell (.combout(Y[i]), .cout(COx[i+1]), .dataa(AA[i]), .datab(BB[i]), .datac(1'b1), .datad(1'b1), .cin(C[i+1])); + end: slice + endgenerate + /* End implementation */ + assign X = AA ^ BB; + +endmodule diff --git a/techlibs/intel/cyclone10/cells_map.v b/techlibs/intel/cyclone10/cells_map.v new file mode 100644 index 000000000..8ac5a55ec --- /dev/null +++ b/techlibs/intel/cyclone10/cells_map.v @@ -0,0 +1,99 @@ +/* + * yosys -- Yosys Open SYnthesis Suite + * + * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at> + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + * + */ +// Normal mode DFF negedge clk, negedge reset +module \$_DFF_N_ (input D, C, output Q); + parameter WYSIWYG="TRUE"; + dffeas #(.is_wysiwyg(WYSIWYG)) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(C), .clrn(1'b1), .prn(1'b1), .ena(1'b1), .asdata(1'b0), .aload(1'b0), .sclr(1'b0), .sload(1'b0)); +endmodule +// Normal mode DFF +module \$_DFF_P_ (input D, C, output Q); + parameter WYSIWYG="TRUE"; + dffeas #(.is_wysiwyg(WYSIWYG)) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(C), .clrn(1'b1), .prn(1'b1), .ena(1'b1), .asdata(1'b0), .aload(1'b0), .sclr(1'b0), .sload(1'b0)); +endmodule + +// Async Active Low Reset DFF +module \$_DFF_PN0_ (input D, C, R, output Q); + parameter WYSIWYG="TRUE"; + dffeas #(.is_wysiwyg(WYSIWYG)) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(C), .clrn(R), .prn(1'b1), .ena(1'b1), .asdata(1'b0), .aload(1'b0), .sclr(1'b0), .sload(1'b0)); +endmodule +// Async Active High Reset DFF +module \$_DFF_PP0_ (input D, C, R, output Q); + parameter WYSIWYG="TRUE"; + wire R_i = ~ R; + dffeas #(.is_wysiwyg(WYSIWYG)) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(C), .clrn(R_i), .prn(1'b1), .ena(1'b1), .asdata(1'b0), .aload(1'b0), .sclr(1'b0), .sload(1'b0)); +endmodule + +module \$__DFFE_PP0 (input D, C, E, R, output Q); + parameter WYSIWYG="TRUE"; + wire E_i = ~ E; + dffeas #(.is_wysiwyg(WYSIWYG)) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(C), .clrn(R), .prn(1'b1), .ena(1'b1), .asdata(1'b0), .aload(1'b0), .sclr(E_i), .sload(1'b0)); +endmodule + +// Input buffer map +module \$__inpad (input I, output O); + cyclone10lp_io_ibuf _TECHMAP_REPLACE_ (.o(O), .i(I), .ibar(1'b0)); +endmodule + +// Output buffer map +module \$__outpad (input I, output O); + cyclone10lp_io_obuf _TECHMAP_REPLACE_ (.o(O), .i(I), .oe(1'b1)); +endmodule + +// LUT Map +/* 0 -> datac + 1 -> cin */ +module \$lut (A, Y); + parameter WIDTH = 0; + parameter LUT = 0; + input [WIDTH-1:0] A; + output Y; + generate + if (WIDTH == 1) begin + assign Y = ~A[0]; // Not need to spend 1 logic cell for such an easy function + end else + if (WIDTH == 2) begin + cyclone10lp_lcell_comb #(.lut_mask({4{LUT}}), + .sum_lutc_input("datac")) _TECHMAP_REPLACE_ (.combout(Y), + .dataa(A[0]), + .datab(A[1]), + .datac(1'b1), + .datad(1'b1)); + end else + if(WIDTH == 3) begin + cyclone10lp_lcell_comb #(.lut_mask({2{LUT}}), + .sum_lutc_input("datac")) _TECHMAP_REPLACE_ (.combout(Y), + .dataa(A[0]), + .datab(A[1]), + .datac(A[2]), + .datad(1'b1)); + end else + if(WIDTH == 4) begin + cyclone10lp_lcell_comb #(.lut_mask(LUT), + .sum_lutc_input("datac")) _TECHMAP_REPLACE_ (.combout(Y), + .dataa(A[0]), + .datab(A[1]), + .datac(A[2]), + .datad(A[3])); + end else + wire _TECHMAP_FAIL_ = 1; + endgenerate + +endmodule + + diff --git a/techlibs/intel/cyclone10/cells_sim.v b/techlibs/intel/cyclone10/cells_sim.v new file mode 100644 index 000000000..f5a8aee2b --- /dev/null +++ b/techlibs/intel/cyclone10/cells_sim.v @@ -0,0 +1,137 @@ +/* + * yosys -- Yosys Open SYnthesis Suite + * + * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at> + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + * + */ +module VCC (output V); + assign V = 1'b1; +endmodule // VCC + +module GND (output G); + assign G = 1'b0; +endmodule // GND + +/* Altera Cyclone 10 LP devices Input Buffer Primitive */ +module cyclone10lp_io_ibuf + (output o, input i, input ibar); + assign ibar = ibar; + assign o = i; +endmodule // cyclone10lp_io_ibuf + +/* Altera Cyclone 10 LP devices Output Buffer Primitive */ +module cyclone10lp_io_obuf + (output o, input i, input oe); + assign o = i; + assign oe = oe; +endmodule // cyclone10lp_io_obuf + +/* Altera Cyclone IV (E) 4-input non-fracturable LUT Primitive */ +module cyclone10lp_lcell_comb + (output combout, cout, + input dataa, datab, datac, datad, cin); + + /* Internal parameters which define the behaviour + of the LUT primitive. + lut_mask define the lut function, can be expressed in 16-digit bin or hex. + sum_lutc_input define the type of LUT (combinational | arithmetic). + dont_touch for retiming || carry options. + lpm_type for WYSIWYG */ + + parameter lut_mask = 16'hFFFF; + parameter dont_touch = "off"; + parameter lpm_type = "cyclone10lp_lcell_comb"; + parameter sum_lutc_input = "datac"; + + reg [1:0] lut_type; + reg cout_rt; + reg combout_rt; + wire dataa_w; + wire datab_w; + wire datac_w; + wire datad_w; + wire cin_w; + + assign dataa_w = dataa; + assign datab_w = datab; + assign datac_w = datac; + assign datad_w = datad; + + function lut_data; + input [15:0] mask; + input dataa, datab, datac, datad; + reg [7:0] s3; + reg [3:0] s2; + reg [1:0] s1; + begin + s3 = datad ? mask[15:8] : mask[7:0]; + s2 = datac ? s3[7:4] : s3[3:0]; + s1 = datab ? s2[3:2] : s2[1:0]; + lut_data = dataa ? s1[1] : s1[0]; + end + + endfunction + + initial begin + if (sum_lutc_input == "datac") lut_type = 0; + else + if (sum_lutc_input == "cin") lut_type = 1; + else begin + $error("Error in sum_lutc_input. Parameter %s is not a valid value.\n", sum_lutc_input); + $finish(); + end + end + + always @(dataa_w or datab_w or datac_w or datad_w or cin_w) begin + if (lut_type == 0) begin // logic function + combout_rt = lut_data(lut_mask, dataa_w, datab_w, + datac_w, datad_w); + end + else if (lut_type == 1) begin // arithmetic function + combout_rt = lut_data(lut_mask, dataa_w, datab_w, + cin_w, datad_w); + end + cout_rt = lut_data(lut_mask, dataa_w, datab_w, cin_w, 'b0); + end + + assign combout = combout_rt & 1'b1; + assign cout = cout_rt & 1'b1; + +endmodule // cyclone10lp_lcell_comb + +/* Altera D Flip-Flop Primitive */ +module dffeas + (output q, + input d, clk, clrn, prn, ena, + input asdata, aload, sclr, sload); + + // Timing simulation is not covered + parameter power_up="dontcare"; + parameter is_wysiwyg="false"; + + reg q_tmp; + wire reset; + reg [7:0] debug_net; + + assign reset = (prn && sclr && ~clrn && ena); + assign q = q_tmp & 1'b1; + + always @(posedge clk, posedge aload) begin + if(reset) q_tmp <= 0; + else q_tmp <= d; + end + assign q = q_tmp; + +endmodule // dffeas diff --git a/techlibs/intel/synth_intel.cc b/techlibs/intel/synth_intel.cc index 9e4b33601..9b3e92b14 100644 --- a/techlibs/intel/synth_intel.cc +++ b/techlibs/intel/synth_intel.cc @@ -127,7 +127,7 @@ struct SynthIntelPass : public ScriptPass { if (!design->full_selection()) log_cmd_error("This command only operates on fully selected designs!\n"); - if (family_opt != "max10" && family_opt !="a10gx" && family_opt != "cyclonev" && family_opt !="cycloneiv" && family_opt !="cycloneive") + if (family_opt != "max10" && family_opt !="a10gx" && family_opt != "cyclonev" && family_opt !="cycloneiv" && family_opt !="cycloneive" && family_opt != "cyclone10") log_cmd_error("Invalid or not family specified: '%s'\n", family_opt.c_str()); log_header(design, "Executing SYNTH_INTEL pass.\n"); @@ -148,6 +148,8 @@ struct SynthIntelPass : public ScriptPass { run("read_verilog -sv -lib +/intel/a10gx/cells_sim.v"); else if(check_label("family") && family_opt=="cyclonev") run("read_verilog -sv -lib +/intel/cyclonev/cells_sim.v"); + else if(check_label("family") && family_opt=="cyclone10") + run("read_verilog -sv -lib +/intel/cyclone10/cells_sim.v"); else if(check_label("family") && family_opt=="cycloneiv") run("read_verilog -sv -lib +/intel/cycloneiv/cells_sim.v"); else @@ -211,6 +213,8 @@ struct SynthIntelPass : public ScriptPass { run("techmap -map +/intel/a10gx/cells_map.v"); else if(family_opt=="cyclonev") run("techmap -map +/intel/cyclonev/cells_map.v"); + else if(family_opt=="cyclone10") + run("techmap -map +/intel/cyclone10/cells_map.v"); else if(family_opt=="cycloneiv") run("techmap -map +/intel/cycloneiv/cells_map.v"); else |