diff options
| -rw-r--r-- | manual/PRESENTATION_ExAdv.tex | 37 | ||||
| -rw-r--r-- | manual/PRESENTATION_ExAdv/Makefile | 5 | ||||
| -rw-r--r-- | manual/PRESENTATION_ExAdv/addshift_map.v | 20 | ||||
| -rw-r--r-- | manual/PRESENTATION_ExAdv/addshift_test.v | 5 | ||||
| -rw-r--r-- | manual/PRESENTATION_ExAdv/addshift_test.ys | 6 | ||||
| -rw-r--r-- | manual/PRESENTATION_Intro.tex | 2 | ||||
| -rw-r--r-- | passes/techmap/techmap.cc | 39 |
7 files changed, 111 insertions, 3 deletions
diff --git a/manual/PRESENTATION_ExAdv.tex b/manual/PRESENTATION_ExAdv.tex index 80210b96d..e42a535f4 100644 --- a/manual/PRESENTATION_ExAdv.tex +++ b/manual/PRESENTATION_ExAdv.tex @@ -406,7 +406,42 @@ input values to cells. \subsubsection{Handling shorted inputs} \begin{frame}{\subsubsecname} -TBD +\begin{itemize} +\item The special parameters {\tt \_TECHMAP\_BITS\_CONNMAP\_} and +{\tt \_TECHMAP\_CONNMAP\_\it <port-name>\tt \_} can be used to handle shorted inputs. +\medskip +\item Each bit of the port correlates to an {\tt \_TECHMAP\_BITS\_CONNMAP\_} bits wide +number in {\tt \_TECHMAP\_CONNMAP\_\it <port-name>\tt \_}. +\medskip +\item Each unique signal bit is assigned its own number. Identical fields in the {\tt +\_TECHMAP\_CONNMAP\_\it <port-name>\tt \_} parameters mean shorted signal bits. +\medskip +\item The numbers 0-3 are reserved for {\tt 0}, {\tt 1}, {\tt x}, and {\tt z} respectively. +\medskip +\item Example use-cases: +\begin{itemize} +\item Detecting shared clock or control signals in memory interfaces. +\item In some cases this can be used for for optimization. +\end{itemize} +\end{itemize} +\end{frame} + +\begin{frame}[t]{\subsubsecname{} -- Example} +\vbox to 0cm{ +\vskip4.5cm +\hskip6.5cm\includegraphics[width=5cm,trim=0 0cm 0 0cm]{PRESENTATION_ExAdv/addshift.pdf} +\vss +} +\vskip-0.6cm +\begin{columns} +\column[t]{6cm} +\vskip-0.4cm +\lstinputlisting[basicstyle=\ttfamily\fontsize{7pt}{8pt}\selectfont, language=verilog]{PRESENTATION_ExAdv/addshift_map.v} +\column[t]{4.2cm} +\vskip-0.6cm +\lstinputlisting[basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, frame=single, language=verilog]{PRESENTATION_ExAdv/addshift_test.v} +\lstinputlisting[basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, frame=single, language=ys, lastline=5]{PRESENTATION_ExAdv/addshift_test.ys} +\end{columns} \end{frame} \subsubsection{Notes on using techmap} diff --git a/manual/PRESENTATION_ExAdv/Makefile b/manual/PRESENTATION_ExAdv/Makefile index 3bbc239a4..2a2858e5f 100644 --- a/manual/PRESENTATION_ExAdv/Makefile +++ b/manual/PRESENTATION_ExAdv/Makefile @@ -1,5 +1,5 @@ -all: select_01.pdf red_or3x1.pdf sym_mul.pdf mymul.pdf mulshift.pdf +all: select_01.pdf red_or3x1.pdf sym_mul.pdf mymul.pdf mulshift.pdf addshift.pdf select_01.pdf: select_01.v select_01.ys ../../yosys select_01.ys @@ -16,3 +16,6 @@ mymul.pdf: mymul_* mulshift.pdf: mulshift_* ../../yosys mulshift_test.ys +addshift.pdf: addshift_* + ../../yosys addshift_test.ys + diff --git a/manual/PRESENTATION_ExAdv/addshift_map.v b/manual/PRESENTATION_ExAdv/addshift_map.v new file mode 100644 index 000000000..b6d91b01b --- /dev/null +++ b/manual/PRESENTATION_ExAdv/addshift_map.v @@ -0,0 +1,20 @@ +module \$add (A, B, Y); + parameter A_SIGNED = 0; + parameter B_SIGNED = 0; + parameter A_WIDTH = 1; + parameter B_WIDTH = 1; + parameter Y_WIDTH = 1; + + input [A_WIDTH-1:0] A; + input [B_WIDTH-1:0] B; + output [Y_WIDTH-1:0] Y; + + parameter _TECHMAP_BITS_CONNMAP_ = 0; + parameter _TECHMAP_CONNMAP_A_ = 0; + parameter _TECHMAP_CONNMAP_B_ = 0; + + wire _TECHMAP_FAIL_ = A_WIDTH != B_WIDTH || B_WIDTH < Y_WIDTH || + _TECHMAP_CONNMAP_A_ != _TECHMAP_CONNMAP_B_; + + assign Y = A << 1; +endmodule diff --git a/manual/PRESENTATION_ExAdv/addshift_test.v b/manual/PRESENTATION_ExAdv/addshift_test.v new file mode 100644 index 000000000..b53271faa --- /dev/null +++ b/manual/PRESENTATION_ExAdv/addshift_test.v @@ -0,0 +1,5 @@ +module test (A, B, X, Y); +input [7:0] A, B; +output [7:0] X = A + B; +output [7:0] Y = A + A; +endmodule diff --git a/manual/PRESENTATION_ExAdv/addshift_test.ys b/manual/PRESENTATION_ExAdv/addshift_test.ys new file mode 100644 index 000000000..c08f1106a --- /dev/null +++ b/manual/PRESENTATION_ExAdv/addshift_test.ys @@ -0,0 +1,6 @@ +read_verilog addshift_test.v +hierarchy -check -top test + +techmap -map addshift_map.v;; + +show -prefix addshift -format pdf -notitle diff --git a/manual/PRESENTATION_Intro.tex b/manual/PRESENTATION_Intro.tex index 275766474..1c07928b0 100644 --- a/manual/PRESENTATION_Intro.tex +++ b/manual/PRESENTATION_Intro.tex @@ -359,7 +359,7 @@ as Qflow\footnote[frame]{\url{http://opencircuitdesign.com/qflow/}} for ASIC des Map registers to available hardware flip-flops. }% \only<12>{ - Map logix to available hardware gates. + Map logic to available hardware gates. }% \only<13>{ Clean up the design (just the last step of {\tt opt}). diff --git a/passes/techmap/techmap.cc b/passes/techmap/techmap.cc index 53164b58a..74621d3e5 100644 --- a/passes/techmap/techmap.cc +++ b/passes/techmap/techmap.cc @@ -271,6 +271,37 @@ struct TechmapWorker parameters[stringf("\\_TECHMAP_CONSTVAL_%s_", RTLIL::id2cstr(conn.first))] = RTLIL::SigSpec(v).as_const(); } } + + int unique_bit_id_counter = 0; + std::map<RTLIL::SigBit, int> unique_bit_id; + unique_bit_id[RTLIL::State::S0] = unique_bit_id_counter++; + unique_bit_id[RTLIL::State::S1] = unique_bit_id_counter++; + unique_bit_id[RTLIL::State::Sx] = unique_bit_id_counter++; + unique_bit_id[RTLIL::State::Sz] = unique_bit_id_counter++; + + for (auto conn : cell->connections) + if (tpl->avail_parameters.count(stringf("\\_TECHMAP_CONNMAP_%s_", RTLIL::id2cstr(conn.first))) != 0) { + for (auto &bit : sigmap(conn.second).to_sigbit_vector()) + if (unique_bit_id.count(bit) == 0) + unique_bit_id[bit] = unique_bit_id_counter++; + } + + int bits = 0; + for (int i = 0; i < 32; i++) + if (((unique_bit_id_counter-1) & (1 << i)) != 0) + bits = i; + if (tpl->avail_parameters.count("\\_TECHMAP_BITS_CONNMAP_")) + parameters["\\_TECHMAP_BITS_CONNMAP_"] = bits; + + for (auto conn : cell->connections) + if (tpl->avail_parameters.count(stringf("\\_TECHMAP_CONNMAP_%s_", RTLIL::id2cstr(conn.first))) != 0) { + RTLIL::Const value; + for (auto &bit : sigmap(conn.second).to_sigbit_vector()) { + RTLIL::Const chunk(unique_bit_id.at(bit), bits); + value.bits.insert(value.bits.end(), chunk.bits.begin(), chunk.bits.end()); + } + parameters[stringf("\\_TECHMAP_CONNMAP_%s_", RTLIL::id2cstr(conn.first))] = value; + } } std::pair<RTLIL::IdString, std::map<RTLIL::IdString, RTLIL::Const>> key(tpl_name, parameters); @@ -468,6 +499,14 @@ struct TechmapPass : public Pass { log(" former has a 1-bit for each constant input bit and the latter has the\n"); log(" value for this bit. The unused bits of the latter are set to undef (x).\n"); log("\n"); + log(" _TECHMAP_BITS_CONNMAP_\n"); + log(" _TECHMAP_CONNMAP_<port-name>_\n"); + log(" For an N-bit port, the _TECHMAP_CONNMAP_<port-name>_ parameter, if it\n"); + log(" exists, will be set to an N*_TECHMAP_BITS_CONNMAP_ bit vector containing\n"); + log(" N words (of _TECHMAP_BITS_CONNMAP_ bits each) that assign each single\n"); + log(" bit driver a unique id. The values 0-3 are reserved for 0, 1, x, and z.\n"); + log(" This can be used to detect shorted inputs.\n"); + log("\n"); log("When a module in the map file has a parameter where the according cell in the\n"); log("design has a port, the module from the map file is only used if the port in\n"); log("the design is connected to a constant value. The parameter is then set to the\n"); |