diff options
| -rw-r--r-- | passes/techmap/shregmap.cc | 582 | ||||
| -rw-r--r-- | techlibs/xilinx/cells_map.v | 110 | ||||
| -rw-r--r-- | techlibs/xilinx/cells_sim.v | 39 | ||||
| -rw-r--r-- | techlibs/xilinx/cells_xtra.sh | 4 | ||||
| -rw-r--r-- | techlibs/xilinx/cells_xtra.v | 16 | ||||
| -rw-r--r-- | techlibs/xilinx/synth_xilinx.cc | 8 |
6 files changed, 512 insertions, 247 deletions
diff --git a/passes/techmap/shregmap.cc b/passes/techmap/shregmap.cc index f20863ba0..3b3170e04 100644 --- a/passes/techmap/shregmap.cc +++ b/passes/techmap/shregmap.cc @@ -26,7 +26,9 @@ PRIVATE_NAMESPACE_BEGIN struct ShregmapTech { virtual ~ShregmapTech() { } - virtual bool analyze(vector<int> &taps) = 0; + virtual void init(const Module * /*module*/, const SigMap &/*sigmap*/) {} + virtual void non_chain_user(const SigBit &/*bit*/, const Cell* /*cell*/, IdString /*port*/) {} + virtual bool analyze(vector<int> &taps, const vector<SigBit> &qbits) = 0; virtual bool fixup(Cell *cell, dict<int, SigBit> &taps) = 0; }; @@ -54,7 +56,7 @@ struct ShregmapOptions struct ShregmapTechGreenpak4 : ShregmapTech { - bool analyze(vector<int> &taps) + bool analyze(vector<int> &taps, const vector<SigBit> &/*qbits*/) { if (GetSize(taps) > 2 && taps[0] == 0 && taps[2] < 17) { taps.clear(); @@ -91,302 +93,424 @@ struct ShregmapTechGreenpak4 : ShregmapTech } }; -struct ShregmapWorker +struct ShregmapTechXilinx7 : ShregmapTech { - Module *module; - SigMap sigmap; - + dict<SigBit, std::pair<Cell*,int>> sigbit_to_shiftx_offset; const ShregmapOptions &opts; - int dff_count, shreg_count; - pool<Cell*> remove_cells; - pool<SigBit> remove_init; + ShregmapTechXilinx7(const ShregmapOptions &opts) : opts(opts) {} - dict<SigBit, bool> sigbit_init; - dict<SigBit, Cell*> sigbit_chain_next; - dict<SigBit, Cell*> sigbit_chain_prev; - pool<SigBit> sigbit_with_non_chain_users; - pool<Cell*> chain_start_cells; + virtual void init(const Module* module, const SigMap &sigmap) override + { + for (auto i : module->cells_) { + auto cell = i.second; + if (cell->type != "$shiftx") continue; + if (cell->getParam("\\Y_WIDTH") != 1) continue; + int j = 0; + for (auto bit : sigmap(cell->getPort("\\A"))) + sigbit_to_shiftx_offset[bit] = std::make_pair(cell, j++); + log_assert(j == cell->getParam("\\A_WIDTH").as_int()); + } + } - void make_sigbit_chain_next_prev() + virtual void non_chain_user(const SigBit &bit, const Cell *cell, IdString port) override { - for (auto wire : module->wires()) - { - if (wire->port_output || wire->get_bool_attribute("\\keep")) { - for (auto bit : sigmap(wire)) - sigbit_with_non_chain_users.insert(bit); - } + auto it = sigbit_to_shiftx_offset.find(bit); + if (it == sigbit_to_shiftx_offset.end()) + return; + if (cell && cell->type == "$shiftx" && port == "\\A") + return; + sigbit_to_shiftx_offset.erase(it); + } - if (wire->attributes.count("\\init")) { - SigSpec initsig = sigmap(wire); - Const initval = wire->attributes.at("\\init"); - for (int i = 0; i < GetSize(initsig) && i < GetSize(initval); i++) - if (initval[i] == State::S0 && !opts.zinit) - sigbit_init[initsig[i]] = false; - else if (initval[i] == State::S1) - sigbit_init[initsig[i]] = true; - } - } + virtual bool analyze(vector<int> &taps, const vector<SigBit> &qbits) override + { + if (GetSize(taps) == 1) + return taps[0] >= opts.minlen-1; - for (auto cell : module->cells()) - { - if (opts.ffcells.count(cell->type) && !cell->get_bool_attribute("\\keep")) - { - IdString d_port = opts.ffcells.at(cell->type).first; - IdString q_port = opts.ffcells.at(cell->type).second; - - SigBit d_bit = sigmap(cell->getPort(d_port).as_bit()); - SigBit q_bit = sigmap(cell->getPort(q_port).as_bit()); - - if (opts.init || sigbit_init.count(q_bit) == 0) - { - if (sigbit_chain_next.count(d_bit)) { - sigbit_with_non_chain_users.insert(d_bit); - } else - sigbit_chain_next[d_bit] = cell; - - sigbit_chain_prev[q_bit] = cell; - continue; + if (taps.back() < opts.minlen-1) + return false; + + Cell *shiftx = nullptr; + for (int i = 0; i < GetSize(taps); ++i) { + // Check taps are sequential + if (i != taps[i]) + return false; + // Check taps are not connected to a shift register, + // or sequential to the same shift register + auto it = sigbit_to_shiftx_offset.find(qbits[i]); + if (i == 0) { + if (it == sigbit_to_shiftx_offset.end()) { + return false; + } + else { + shiftx = it->second.first; + int offset = it->second.second; + if (offset != i) + return false; + } + } + else { + if (it == sigbit_to_shiftx_offset.end()) { + return false; + } + else { + if (shiftx != it->second.first) + return false; + int offset = it->second.second; + if (offset != i) + return false; } } - - for (auto conn : cell->connections()) - if (cell->input(conn.first)) - for (auto bit : sigmap(conn.second)) - sigbit_with_non_chain_users.insert(bit); } + log_assert(shiftx); + + // Cannot implement variable-length shift registers + // greater than 128 since Q31 cannot be output onto + // fabric + if (GetSize(taps) > 128) + return false; + + // Only map if $shiftx exclusively covers the shift register + if (GetSize(taps) != shiftx->getParam("\\A_WIDTH").as_int()) + return false; + + return true; } - void find_chain_start_cells() + virtual bool fixup(Cell *cell, dict<int, SigBit> &taps) override { - for (auto it : sigbit_chain_next) - { - if (opts.tech == nullptr && sigbit_with_non_chain_users.count(it.first)) - goto start_cell; + const auto &tap = *taps.begin(); + auto bit = tap.second; + auto it = sigbit_to_shiftx_offset.find(bit); + // If fixed-length, no fixup necessary + if (it == sigbit_to_shiftx_offset.end()) + return true; - if (sigbit_chain_prev.count(it.first) != 0) - { - Cell *c1 = sigbit_chain_prev.at(it.first); - Cell *c2 = it.second; + auto cell_q = cell->getPort("\\Q"); + log_assert(cell_q.is_bit()); - if (c1->type != c2->type) - goto start_cell; + Cell* shiftx = it->second.first; + // FIXME: Hack to ensure that $shiftx gets optimised away + // Without this, Yosys will refuse to optimise away a $shiftx + // where \\A 's width is not perfectly \\B_WIDTH ** 2 + // See YosysHQ/yosys#878 + auto shiftx_bwidth = shiftx->getParam("\\B_WIDTH").as_int(); + shiftx->setPort("\\A", cell_q.repeat(1 << shiftx_bwidth)); + shiftx->setParam("\\A_WIDTH", 1 << shiftx_bwidth); - if (c1->parameters != c2->parameters) - goto start_cell; + cell->setPort("\\L", shiftx->getPort("\\B")); - IdString d_port = opts.ffcells.at(c1->type).first; - IdString q_port = opts.ffcells.at(c1->type).second; + return true; + } +}; - auto c1_conn = c1->connections(); - auto c2_conn = c1->connections(); - c1_conn.erase(d_port); - c1_conn.erase(q_port); +struct ShregmapWorker +{ + Module *module; + SigMap sigmap; - c2_conn.erase(d_port); - c2_conn.erase(q_port); + const ShregmapOptions &opts; + int dff_count, shreg_count; - if (c1_conn != c2_conn) - goto start_cell; + pool<Cell*> remove_cells; + pool<SigBit> remove_init; - continue; - } + dict<SigBit, bool> sigbit_init; + dict<SigBit, Cell*> sigbit_chain_next; + dict<SigBit, Cell*> sigbit_chain_prev; + pool<SigBit> sigbit_with_non_chain_users; + pool<Cell*> chain_start_cells; - start_cell: - chain_start_cells.insert(it.second); + void make_sigbit_chain_next_prev() + { + for (auto wire : module->wires()) + { + if (wire->port_output || wire->get_bool_attribute("\\keep")) { + for (auto bit : sigmap(wire)) { + sigbit_with_non_chain_users.insert(bit); + if (opts.tech) opts.tech->non_chain_user(bit, nullptr, {}); } + } + + if (wire->attributes.count("\\init")) { + SigSpec initsig = sigmap(wire); + Const initval = wire->attributes.at("\\init"); + for (int i = 0; i < GetSize(initsig) && i < GetSize(initval); i++) + if (initval[i] == State::S0 && !opts.zinit) + sigbit_init[initsig[i]] = false; + else if (initval[i] == State::S1) + sigbit_init[initsig[i]] = true; + } } - vector<Cell*> create_chain(Cell *start_cell) + for (auto cell : module->cells()) { - vector<Cell*> chain; - - Cell *c = start_cell; - while (c != nullptr) - { - chain.push_back(c); + if (opts.ffcells.count(cell->type) && !cell->get_bool_attribute("\\keep")) + { + IdString d_port = opts.ffcells.at(cell->type).first; + IdString q_port = opts.ffcells.at(cell->type).second; - IdString q_port = opts.ffcells.at(c->type).second; - SigBit q_bit = sigmap(c->getPort(q_port).as_bit()); + SigBit d_bit = sigmap(cell->getPort(d_port).as_bit()); + SigBit q_bit = sigmap(cell->getPort(q_port).as_bit()); - if (sigbit_chain_next.count(q_bit) == 0) - break; + if (opts.init || sigbit_init.count(q_bit) == 0) + { + if (sigbit_chain_next.count(d_bit)) { + sigbit_with_non_chain_users.insert(d_bit); + } else + sigbit_chain_next[d_bit] = cell; - c = sigbit_chain_next.at(q_bit); - if (chain_start_cells.count(c) != 0) - break; + sigbit_chain_prev[q_bit] = cell; + continue; } - - return chain; + } + + for (auto conn : cell->connections()) + if (cell->input(conn.first)) + for (auto bit : sigmap(conn.second)) { + sigbit_with_non_chain_users.insert(bit); + if (opts.tech) opts.tech->non_chain_user(bit, cell, conn.first); + } } + } - void process_chain(vector<Cell*> &chain) + void find_chain_start_cells() + { + for (auto it : sigbit_chain_next) { - if (GetSize(chain) < opts.keep_before + opts.minlen + opts.keep_after) - return; + if (opts.tech == nullptr && sigbit_with_non_chain_users.count(it.first)) + goto start_cell; - int cursor = opts.keep_before; - while (cursor < GetSize(chain) - opts.keep_after) - { - int depth = GetSize(chain) - opts.keep_after - cursor; + if (sigbit_chain_prev.count(it.first) != 0) + { + Cell *c1 = sigbit_chain_prev.at(it.first); + Cell *c2 = it.second; - if (opts.maxlen > 0) - depth = std::min(opts.maxlen, depth); + if (c1->type != c2->type) + goto start_cell; - Cell *first_cell = chain[cursor]; - IdString q_port = opts.ffcells.at(first_cell->type).second; - dict<int, SigBit> taps_dict; + if (c1->parameters != c2->parameters) + goto start_cell; - if (opts.tech) - { - vector<SigBit> qbits; - vector<int> taps; + IdString d_port = opts.ffcells.at(c1->type).first; + IdString q_port = opts.ffcells.at(c1->type).second; - for (int i = 0; i < depth; i++) - { - Cell *cell = chain[cursor+i]; - auto qbit = sigmap(cell->getPort(q_port)); - qbits.push_back(qbit); + auto c1_conn = c1->connections(); + auto c2_conn = c1->connections(); - if (sigbit_with_non_chain_users.count(qbit)) - taps.push_back(i); - } + c1_conn.erase(d_port); + c1_conn.erase(q_port); - while (depth > 0) - { - if (taps.empty() || taps.back() < depth-1) - taps.push_back(depth-1); + c2_conn.erase(d_port); + c2_conn.erase(q_port); - if (opts.tech->analyze(taps)) - break; + if (c1_conn != c2_conn) + goto start_cell; - taps.pop_back(); - depth--; - } - - depth = 0; - for (auto tap : taps) { - taps_dict[tap] = qbits.at(tap); - log_assert(depth < tap+1); - depth = tap+1; - } - } + continue; + } - if (depth < 2) { - cursor++; - continue; - } +start_cell: + chain_start_cells.insert(it.second); + } + } - Cell *last_cell = chain[cursor+depth-1]; + vector<Cell*> create_chain(Cell *start_cell) + { + vector<Cell*> chain; - log("Converting %s.%s ... %s.%s to a shift register with depth %d.\n", - log_id(module), log_id(first_cell), log_id(module), log_id(last_cell), depth); + Cell *c = start_cell; + while (c != nullptr) + { + chain.push_back(c); - dff_count += depth; - shreg_count += 1; + IdString q_port = opts.ffcells.at(c->type).second; + SigBit q_bit = sigmap(c->getPort(q_port).as_bit()); - string shreg_cell_type_str = "$__SHREG"; - if (opts.params) { - shreg_cell_type_str += "_"; - } else { - if (first_cell->type[1] != '_') - shreg_cell_type_str += "_"; - shreg_cell_type_str += first_cell->type.substr(1); - } + if (sigbit_chain_next.count(q_bit) == 0) + break; - if (opts.init) { - vector<State> initval; - for (int i = depth-1; i >= 0; i--) { - SigBit bit = sigmap(chain[cursor+i]->getPort(q_port).as_bit()); - if (sigbit_init.count(bit) == 0) - initval.push_back(State::Sx); - else if (sigbit_init.at(bit)) - initval.push_back(State::S1); - else - initval.push_back(State::S0); - remove_init.insert(bit); - } - first_cell->setParam("\\INIT", initval); - } + c = sigbit_chain_next.at(q_bit); + if (chain_start_cells.count(c) != 0) + break; + } - if (opts.zinit) - for (int i = depth-1; i >= 0; i--) { - SigBit bit = sigmap(chain[cursor+i]->getPort(q_port).as_bit()); - remove_init.insert(bit); - } + return chain; + } - if (opts.params) - { - int param_clkpol = -1; - int param_enpol = 2; + void process_chain(vector<Cell*> &chain) + { + if (GetSize(chain) < opts.keep_before + opts.minlen + opts.keep_after) + return; - if (first_cell->type == "$_DFF_N_") param_clkpol = 0; - if (first_cell->type == "$_DFF_P_") param_clkpol = 1; + int cursor = opts.keep_before; + while (cursor < GetSize(chain) - opts.keep_after) + { + int depth = GetSize(chain) - opts.keep_after - cursor; - if (first_cell->type == "$_DFFE_NN_") param_clkpol = 0, param_enpol = 0; - if (first_cell->type == "$_DFFE_NP_") param_clkpol = 0, param_enpol = 1; - if (first_cell->type == "$_DFFE_PN_") param_clkpol = 1, param_enpol = 0; - if (first_cell->type == "$_DFFE_PP_") param_clkpol = 1, param_enpol = 1; + if (opts.maxlen > 0) + depth = std::min(opts.maxlen, depth); - log_assert(param_clkpol >= 0); - first_cell->setParam("\\CLKPOL", param_clkpol); - if (opts.ffe) first_cell->setParam("\\ENPOL", param_enpol); - } + Cell *first_cell = chain[cursor]; + IdString q_port = opts.ffcells.at(first_cell->type).second; + dict<int, SigBit> taps_dict; - first_cell->type = shreg_cell_type_str; - first_cell->setPort(q_port, last_cell->getPort(q_port)); - first_cell->setParam("\\DEPTH", depth); + if (opts.tech) + { + vector<SigBit> qbits; + vector<int> taps; - if (opts.tech != nullptr && !opts.tech->fixup(first_cell, taps_dict)) - remove_cells.insert(first_cell); + for (int i = 0; i < depth; i++) + { + Cell *cell = chain[cursor+i]; + auto qbit = sigmap(cell->getPort(q_port)); + qbits.push_back(qbit); - for (int i = 1; i < depth; i++) - remove_cells.insert(chain[cursor+i]); - cursor += depth; + if (sigbit_with_non_chain_users.count(qbit)) + taps.push_back(i); } - } - - void cleanup() - { - for (auto cell : remove_cells) - module->remove(cell); - for (auto wire : module->wires()) + while (depth > 0) { - if (wire->attributes.count("\\init") == 0) - continue; + if (taps.empty() || taps.back() < depth-1) + taps.push_back(depth-1); - SigSpec initsig = sigmap(wire); - Const &initval = wire->attributes.at("\\init"); + if (opts.tech->analyze(taps, qbits)) + break; - for (int i = 0; i < GetSize(initsig) && i < GetSize(initval); i++) - if (remove_init.count(initsig[i])) - initval[i] = State::Sx; + taps.pop_back(); + depth--; + } + + depth = 0; + for (auto tap : taps) { + taps_dict[tap] = qbits.at(tap); + log_assert(depth < tap+1); + depth = tap+1; + } + } + + if (depth < 2) { + cursor++; + continue; + } + + Cell *last_cell = chain[cursor+depth-1]; + + log("Converting %s.%s ... %s.%s to a shift register with depth %d.\n", + log_id(module), log_id(first_cell), log_id(module), log_id(last_cell), depth); + + dff_count += depth; + shreg_count += 1; + + string shreg_cell_type_str = "$__SHREG"; + if (opts.params) { + shreg_cell_type_str += "_"; + } else { + if (first_cell->type[1] != '_') + shreg_cell_type_str += "_"; + shreg_cell_type_str += first_cell->type.substr(1); + } + + if (opts.init) { + vector<State> initval; + for (int i = depth-1; i >= 0; i--) { + SigBit bit = sigmap(chain[cursor+i]->getPort(q_port).as_bit()); + if (sigbit_init.count(bit) == 0) + initval.push_back(State::Sx); + else if (sigbit_init.at(bit)) + initval.push_back(State::S1); + else + initval.push_back(State::S0); + remove_init.insert(bit); + } + first_cell->setParam("\\INIT", initval); + } - if (SigSpec(initval).is_fully_undef()) - wire->attributes.erase("\\init"); + if (opts.zinit) + for (int i = depth-1; i >= 0; i--) { + SigBit bit = sigmap(chain[cursor+i]->getPort(q_port).as_bit()); + remove_init.insert(bit); } - remove_cells.clear(); - sigbit_chain_next.clear(); - sigbit_chain_prev.clear(); - chain_start_cells.clear(); + if (opts.params) + { + int param_clkpol = -1; + int param_enpol = 2; + + if (first_cell->type == "$_DFF_N_") param_clkpol = 0; + if (first_cell->type == "$_DFF_P_") param_clkpol = 1; + + if (first_cell->type == "$_DFFE_NN_") param_clkpol = 0, param_enpol = 0; + if (first_cell->type == "$_DFFE_NP_") param_clkpol = 0, param_enpol = 1; + if (first_cell->type == "$_DFFE_PN_") param_clkpol = 1, param_enpol = 0; + if (first_cell->type == "$_DFFE_PP_") param_clkpol = 1, param_enpol = 1; + + log_assert(param_clkpol >= 0); + first_cell->setParam("\\CLKPOL", param_clkpol); + if (opts.ffe) first_cell->setParam("\\ENPOL", param_enpol); + } + + first_cell->type = shreg_cell_type_str; + first_cell->setPort(q_port, last_cell->getPort(q_port)); + if (!first_cell->hasPort("\\L")) + first_cell->setPort("\\L", depth-1); + first_cell->setParam("\\DEPTH", depth); + + if (opts.tech != nullptr && !opts.tech->fixup(first_cell, taps_dict)) + remove_cells.insert(first_cell); + + for (int i = 1; i < depth; i++) + remove_cells.insert(chain[cursor+i]); + cursor += depth; } + } - ShregmapWorker(Module *module, const ShregmapOptions &opts) : - module(module), sigmap(module), opts(opts), dff_count(0), shreg_count(0) + void cleanup() + { + for (auto cell : remove_cells) + module->remove(cell); + + for (auto wire : module->wires()) { - make_sigbit_chain_next_prev(); - find_chain_start_cells(); + if (wire->attributes.count("\\init") == 0) + continue; - for (auto c : chain_start_cells) { - vector<Cell*> chain = create_chain(c); - process_chain(chain); - } + SigSpec initsig = sigmap(wire); + Const &initval = wire->attributes.at("\\init"); + + for (int i = 0; i < GetSize(initsig) && i < GetSize(initval); i++) + if (remove_init.count(initsig[i])) + initval[i] = State::Sx; + + if (SigSpec(initval).is_fully_undef()) + wire->attributes.erase("\\init"); + } - cleanup(); + remove_cells.clear(); + sigbit_chain_next.clear(); + sigbit_chain_prev.clear(); + chain_start_cells.clear(); + } + + ShregmapWorker(Module *module, const ShregmapOptions &opts) : + module(module), sigmap(module), opts(opts), dff_count(0), shreg_count(0) + { + if (opts.tech) + opts.tech->init(module, sigmap); + + make_sigbit_chain_next_prev(); + find_chain_start_cells(); + + for (auto c : chain_start_cells) { + vector<Cell*> chain = create_chain(c); + process_chain(chain); } + + cleanup(); + } }; struct ShregmapPass : public Pass { @@ -501,6 +625,12 @@ struct ShregmapPass : public Pass { clkpol = "pos"; opts.zinit = true; opts.tech = new ShregmapTechGreenpak4; + } + else if (tech == "xilinx") { + opts.init = true; + opts.params = true; + enpol = "any_or_none"; + opts.tech = new ShregmapTechXilinx7(opts); } else { argidx--; break; diff --git a/techlibs/xilinx/cells_map.v b/techlibs/xilinx/cells_map.v index d5801c0fc..1d538e262 100644 --- a/techlibs/xilinx/cells_map.v +++ b/techlibs/xilinx/cells_map.v @@ -17,4 +17,112 @@ * */ -// Empty for now +module \$__SHREG_ (input C, input D, input [31:0] L, input E, output Q); + parameter DEPTH = 0; + parameter [DEPTH-1:0] INIT = 0; + parameter CLKPOL = 1; + parameter ENPOL = 2; + wire CE; + + // shregmap's INIT parameter shifts out LSB first; + // however Xilinx expects MSB first + function [DEPTH-1:0] brev; + input [DEPTH-1:0] din; + integer i; + begin + for (i = 0; i < DEPTH; i=i+1) + brev[i] = din[DEPTH-1-i]; + end + endfunction + localparam [DEPTH-1:0] INIT_R = brev(INIT); + + parameter _TECHMAP_CONSTMSK_L_ = 0; + parameter _TECHMAP_CONSTVAL_L_ = 0; + + generate + if (ENPOL == 0) + assign CE = ~E; + else if (ENPOL == 1) + assign CE = E; + else + assign CE = 1'b1; + if (DEPTH == 1) begin + wire _TECHMAP_FAIL_ = ~&_TECHMAP_CONSTMSK_L_ || _TECHMAP_CONSTVAL_L_ != 0; + if (CLKPOL) + FDRE #(.INIT(INIT_R)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(CE), .R(1'b0)); + else + FDRE_1 #(.INIT(INIT_R)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(CE), .R(1'b0)); + end else + if (DEPTH <= 16) begin + SRL16E #(.INIT(INIT_R), .IS_CLK_INVERTED(~CLKPOL[0])) _TECHMAP_REPLACE_ (.A0(L[0]), .A1(L[1]), .A2(L[2]), .A3(L[3]), .CE(CE), .CLK(C), .D(D), .Q(Q)); + end else + if (DEPTH > 17 && DEPTH <= 32) begin + SRLC32E #(.INIT(INIT_R), .IS_CLK_INVERTED(~CLKPOL[0])) _TECHMAP_REPLACE_ (.A(L[4:0]), .CE(CE), .CLK(C), .D(D), .Q(Q)); + end else + if (DEPTH > 33 && DEPTH <= 64) begin + wire T0, T1, T2; + SRLC32E #(.INIT(INIT_R[32-1:0]), .IS_CLK_INVERTED(~CLKPOL[0])) fpga_srl_0 (.A(L[4:0]), .CE(CE), .CLK(C), .D(D), .Q(T0), .Q31(T1)); + \$__SHREG_ #(.DEPTH(DEPTH-32), .INIT(INIT[DEPTH-32-1:0]), .CLKPOL(CLKPOL), .ENPOL(ENPOL)) fpga_srl_1 (.C(C), .D(T1), .L(L), .E(E), .Q(T2)); + if (&_TECHMAP_CONSTMSK_L_) + assign Q = T2; + else + MUXF7 fpga_mux_0 (.O(Q), .I0(T0), .I1(T2), .S(L[5])); + end else + if (DEPTH > 65 && DEPTH <= 96) begin + wire T0, T1, T2, T3, T4, T5, T6; + SRLC32E #(.INIT(INIT_R[32-1:0]), .IS_CLK_INVERTED(~CLKPOL[0])) fpga_srl_0 (.A(L[4:0]), .CE(CE), .CLK(C), .D(D), .Q(T0), .Q31(T1)); + SRLC32E #(.INIT(INIT_R[64-1:32]), .IS_CLK_INVERTED(~CLKPOL[0])) fpga_srl_1 (.A(L[4:0]), .CE(CE), .CLK(C), .D(T1), .Q(T2), .Q31(T3)); + \$__SHREG_ #(.DEPTH(DEPTH-64), .INIT(INIT[DEPTH-64-1:0]), .CLKPOL(CLKPOL), .ENPOL(ENPOL)) fpga_srl_2 (.C(C), .D(T3), .L(L[4:0]), .E(E), .Q(T4)); + if (&_TECHMAP_CONSTMSK_L_) + assign Q = T4; + else begin + MUXF7 fpga_mux_0 (.O(T5), .I0(T0), .I1(T2), .S(L[5])); + MUXF7 fpga_mux_1 (.O(T6), .I0(T4), .I1(1'b0 /* unused */), .S(L[5])); + MUXF8 fpga_mux_2 (.O(Q), .I0(T5), .I1(T6), .S(L[6])); + end + end else + if (DEPTH > 97 && DEPTH <= 128) begin + wire T0, T1, T2, T3, T4, T5, T6, T7, T8; + SRLC32E #(.INIT(INIT_R[32-1:0]), .IS_CLK_INVERTED(~CLKPOL[0])) fpga_srl_0 (.A(L[4:0]), .CE(CE), .CLK(C), .D(D), .Q(T0), .Q31(T1)); + SRLC32E #(.INIT(INIT_R[64-1:32]), .IS_CLK_INVERTED(~CLKPOL[0])) fpga_srl_1 (.A(L[4:0]), .CE(CE), .CLK(C), .D(T1), .Q(T2), .Q31(T3)); + SRLC32E #(.INIT(INIT_R[96-1:64]), .IS_CLK_INVERTED(~CLKPOL[0])) fpga_srl_2 (.A(L[4:0]), .CE(CE), .CLK(C), .D(T3), .Q(T4), .Q31(T5)); + \$__SHREG_ #(.DEPTH(DEPTH-96), .INIT(INIT[DEPTH-96-1:0]), .CLKPOL(CLKPOL), .ENPOL(ENPOL)) fpga_srl_3 (.C(C), .D(T5), .L(L[4:0]), .E(E), .Q(T6)); + if (&_TECHMAP_CONSTMSK_L_) + assign Q = T6; + else begin + MUXF7 fpga_mux_0 (.O(T7), .I0(T0), .I1(T2), .S(L[5])); + MUXF7 fpga_mux_1 (.O(T8), .I0(T4), .I1(T6), .S(L[5])); + MUXF8 fpga_mux_2 (.O(Q), .I0(T7), .I1(T8), .S(L[6])); + end + end + else if (DEPTH <= 128 || (DEPTH == 129 && &_TECHMAP_CONSTMSK_L_)) begin + // Handle cases where depth is just 1 over a convenient value, + if (&_TECHMAP_CONSTMSK_L_) begin + // For constant length, use the flop + wire T0; + \$__SHREG_ #(.DEPTH(DEPTH-1), .INIT(INIT[DEPTH-1:1]), .CLKPOL(CLKPOL), .ENPOL(ENPOL)) fpga_srl_0 (.C(C), .D(D), .L(DEPTH-1-1), .E(E), .Q(T0)); + \$__SHREG_ #(.DEPTH(1), .INIT(INIT[0]), .CLKPOL(CLKPOL), .ENPOL(ENPOL)) fpga_srl_1 (.C(C), .D(T0), .L(0), .E(E), .Q(Q)); + end + else begin + // For variable length, bump up to the next length + // because we can't access Q31 + \$__SHREG_ #(.DEPTH(DEPTH+1), .INIT(INIT), .CLKPOL(CLKPOL), .ENPOL(ENPOL)) _TECHMAP_REPLACE_ (.C(C), .D(D), .L(L), .E(E), .Q(Q)); + end + end + else begin + if (&_TECHMAP_CONSTMSK_L_) begin + // UG474 (v1.8, p34) states that: + // "There are no direct connections between slices to form longer shift + // registers, nor is the MC31 output at LUT B/C/D available." + wire T0; + \$__SHREG_ #(.DEPTH(128), .INIT(INIT[DEPTH-1:DEPTH-128]), .CLKPOL(CLKPOL), .ENPOL(ENPOL)) fpga_srl_0 (.C(C), .D(D), .L(127), .E(E), .Q(T0)); + \$__SHREG_ #(.DEPTH(DEPTH-128), .INIT(INIT[DEPTH-128-1:0]), .CLKPOL(CLKPOL), .ENPOL(ENPOL)) fpga_srl_1 (.C(C), .D(T0), .L(DEPTH-1-128), .E(E), .Q(Q)); + end + else begin + // No way to create variable length shift registers >128 bits as Q31 + // cannot be output to the fabric... + wire _TECHMAP_FAIL_ = 1; + end + end + endgenerate +endmodule diff --git a/techlibs/xilinx/cells_sim.v b/techlibs/xilinx/cells_sim.v index ff5ff0726..c756115f6 100644 --- a/techlibs/xilinx/cells_sim.v +++ b/techlibs/xilinx/cells_sim.v @@ -251,3 +251,42 @@ module RAM128X1D ( wire clk = WCLK ^ IS_WCLK_INVERTED; always @(posedge clk) if (WE) mem[A] <= D; endmodule + +module SRL16E ( + output Q, + input A0, A1, A2, A3, CE, CLK, D +); + parameter [15:0] INIT = 16'h0000; + parameter [0:0] IS_CLK_INVERTED = 1'b0; + + reg [15:0] r = INIT; + assign Q = r[{A3,A2,A1,A0}]; + generate + if (IS_CLK_INVERTED) begin + always @(negedge CLK) if (CE) r <= { r[14:0], D }; + end + else + always @(posedge CLK) if (CE) r <= { r[14:0], D }; + endgenerate +endmodule + +module SRLC32E ( + output Q, + output Q31, + input [4:0] A, + input CE, CLK, D +); + parameter [31:0] INIT = 32'h00000000; + parameter [0:0] IS_CLK_INVERTED = 1'b0; + + reg [31:0] r = INIT; + assign Q31 = r[31]; + assign Q = r[A]; + generate + if (IS_CLK_INVERTED) begin + always @(negedge CLK) if (CE) r <= { r[30:0], D }; + end + else + always @(posedge CLK) if (CE) r <= { r[30:0], D }; + endgenerate +endmodule diff --git a/techlibs/xilinx/cells_xtra.sh b/techlibs/xilinx/cells_xtra.sh index 37c3e5480..46ababdea 100644 --- a/techlibs/xilinx/cells_xtra.sh +++ b/techlibs/xilinx/cells_xtra.sh @@ -134,8 +134,8 @@ function xtract_cell_decl() xtract_cell_decl ROM256X1 xtract_cell_decl ROM32X1 xtract_cell_decl ROM64X1 - xtract_cell_decl SRL16E - xtract_cell_decl SRLC32E + #xtract_cell_decl SRL16E + #xtract_cell_decl SRLC32E xtract_cell_decl STARTUPE2 xtract_cell_decl USR_ACCESSE2 xtract_cell_decl XADC diff --git a/techlibs/xilinx/cells_xtra.v b/techlibs/xilinx/cells_xtra.v index 995d62e18..6adad35ae 100644 --- a/techlibs/xilinx/cells_xtra.v +++ b/techlibs/xilinx/cells_xtra.v @@ -3843,22 +3843,6 @@ module ROM64X1 (...); input A0, A1, A2, A3, A4, A5; endmodule -module SRL16E (...); - parameter [15:0] INIT = 16'h0000; - parameter [0:0] IS_CLK_INVERTED = 1'b0; - output Q; - input A0, A1, A2, A3, CE, CLK, D; -endmodule - -module SRLC32E (...); - parameter [31:0] INIT = 32'h00000000; - parameter [0:0] IS_CLK_INVERTED = 1'b0; - output Q; - output Q31; - input [4:0] A; - input CE, CLK, D; -endmodule - module STARTUPE2 (...); parameter PROG_USR = "FALSE"; parameter real SIM_CCLK_FREQ = 0.0; diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc index 805ae8e6e..61895e032 100644 --- a/techlibs/xilinx/synth_xilinx.cc +++ b/techlibs/xilinx/synth_xilinx.cc @@ -110,7 +110,9 @@ struct SynthXilinxPass : public Pass log(" dffsr2dff\n"); log(" dff2dffe\n"); log(" opt -full\n"); - log(" techmap -map +/techmap.v -map +/xilinx/arith_map.v -map +/xilinx/ff_map.v\n"); + log(" simplemap t:$dff*\n"); + log(" shregmap -tech xilinx\n"); + log(" techmap -map +/techmap.v -map +/xilinx/arith_map.v +/xilinx/ff_map.v\n"); log(" opt -fast\n"); log("\n"); log(" map_luts:\n"); @@ -255,13 +257,15 @@ struct SynthXilinxPass : public Pass Pass::call(design, "dff2dffe"); Pass::call(design, "opt -full"); + Pass::call(design, "simplemap t:$dff*"); + Pass::call(design, "shregmap -tech xilinx"); + if (vpr) { Pass::call(design, "techmap -map +/techmap.v -map +/xilinx/arith_map.v -map +/xilinx/ff_map.v -D _EXPLICIT_CARRY"); } else { Pass::call(design, "techmap -map +/techmap.v -map +/xilinx/arith_map.v -map +/xilinx/ff_map.v"); } - Pass::call(design, "hierarchy -check"); Pass::call(design, "opt -fast"); } |