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-rw-r--r--passes/cmds/design.cc10
-rw-r--r--tests/various/design.ys18
-rw-r--r--tests/various/design1.ys9
3 files changed, 30 insertions, 7 deletions
diff --git a/passes/cmds/design.cc b/passes/cmds/design.cc
index cfe97067d..421defe0c 100644
--- a/passes/cmds/design.cc
+++ b/passes/cmds/design.cc
@@ -228,14 +228,20 @@ struct DesignPass : public Pass {
}
if (import_mode) {
+ std::vector<RTLIL::Module*> candidates;
for (auto module : copy_src_modules)
{
if (module->get_bool_attribute(ID::top)) {
- copy_src_modules.clear();
- copy_src_modules.push_back(module);
+ candidates.clear();
+ candidates.push_back(module);
break;
}
+ if (!module->get_blackbox_attribute())
+ candidates.push_back(module);
}
+
+ if (GetSize(candidates) == 1)
+ copy_src_modules = std::move(candidates);
}
}
diff --git a/tests/various/design.ys b/tests/various/design.ys
index f13ad8171..a64430dc7 100644
--- a/tests/various/design.ys
+++ b/tests/various/design.ys
@@ -1,9 +1,17 @@
read_verilog <<EOT
+(* blackbox *)
+module bb(input i, output o);
+endmodule
+
+(* whitebox *)
+module wb(input i, output o);
+assign o = ~i;
+endmodule
+
module top(input i, output o);
-assign o = i;
+assign o = ~i;
endmodule
EOT
-design -stash foo
-design -delete foo
-logger -expect error "No saved design 'foo' found!" 1
-design -delete foo
+
+design -stash gate
+design -import gate -as gate
diff --git a/tests/various/design1.ys b/tests/various/design1.ys
new file mode 100644
index 000000000..f13ad8171
--- /dev/null
+++ b/tests/various/design1.ys
@@ -0,0 +1,9 @@
+read_verilog <<EOT
+module top(input i, output o);
+assign o = i;
+endmodule
+EOT
+design -stash foo
+design -delete foo
+logger -expect error "No saved design 'foo' found!" 1
+design -delete foo