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-rw-r--r--.gitattributes1
-rw-r--r--CHANGELOG3
-rw-r--r--CODEOWNERS38
-rw-r--r--Makefile9
-rw-r--r--README.md6
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-rw-r--r--tests/various/abc9.ys39
-rw-r--r--tests/various/attrib07_func_call.v2
-rw-r--r--tests/various/const_func.v75
-rw-r--r--tests/various/const_func.ys1
-rw-r--r--tests/various/constmsk_testmap.v2
-rw-r--r--tests/various/plugin.cc2
-rw-r--r--tests/various/printattr.ys14
-rw-r--r--tests/various/shregmap.v4
-rw-r--r--tests/various/signed.ys28
-rw-r--r--tests/various/xaiger.ys13
-rw-r--r--tests/verilog/bug2037.ys58
-rw-r--r--tests/verilog/bug2042-sv.ys2
-rw-r--r--tests/verilog/task_attr.ys28
393 files changed, 15910 insertions, 4542 deletions
diff --git a/.gitattributes b/.gitattributes
new file mode 100644
index 000000000..f85ae06c9
--- /dev/null
+++ b/.gitattributes
@@ -0,0 +1 @@
+*.v linguist-language=Verilog
diff --git a/CHANGELOG b/CHANGELOG
index 3b36c3182..12fc88550 100644
--- a/CHANGELOG
+++ b/CHANGELOG
@@ -66,6 +66,9 @@ Yosys 0.9 .. Yosys 0.9-dev
- Added "design -delete"
- Added "select -unset"
- Use YosysHQ/abc instead of upstream berkeley-abc/abc
+ - Added $divfloor and $modfloor cells
+ - Added $adffe, $dffsre, $sdff, $sdffe, $sdffce, $adlatch cells
+ - Added "dfflegalize" pass
Yosys 0.8 .. Yosys 0.9
----------------------
diff --git a/CODEOWNERS b/CODEOWNERS
new file mode 100644
index 000000000..350a62120
--- /dev/null
+++ b/CODEOWNERS
@@ -0,0 +1,38 @@
+## CODE NOTIFICATIONS
+# Register yourself here to be notified about modifications
+# for any files you have an interest in/know your way around.
+
+# Each line is a file pattern followed by one or more users.
+# Both github usernames and email addresses are supported.
+# Order is important; the last matching pattern takes the most
+# precedence. Previous matches will not be applied.
+
+
+# PATH (can use glob) USERNAME(S)
+
+passes/cmds/scratchpad.cc @nakengelhardt
+frontends/rpc/ @whitequark
+backends/cxxrtl/ @whitequark
+passes/cmds/bugpoint.cc @whitequark
+passes/techmap/flowmap.cc @whitequark
+passes/opt/opt_lut.cc @whitequark
+
+
+## External Contributors
+# Only users with write permission to the repository get review
+# requests automatically, but we add information for other
+# contributors here too, so we know who to ask to take a look.
+# These still override previous lines, so be careful not to
+# accidentally disable any of the above rules.
+
+techlibs/intel_alm/ @ZirconiumX
+
+# pyosys
+misc/*.py @btut
+
+backends/firrtl @ucbjrl @azidar
+
+passes/sat/qbfsat.cc @boqwxp
+passes/sat/qbfsat.h @boqwxp
+passes/cmds/exec.cc @boqwxp
+passes/cmds/printattrs.cc @boqwxp
diff --git a/Makefile b/Makefile
index cd6179879..3d3e60359 100644
--- a/Makefile
+++ b/Makefile
@@ -135,7 +135,7 @@ bumpversion:
# is just a symlink to your actual ABC working directory, as 'make mrproper'
# will remove the 'abc' directory and you do not want to accidentally
# delete your work on ABC..
-ABCREV = fd2c9b1
+ABCREV = 341db25
ABCPULL = 1
ABCURL ?= https://github.com/YosysHQ/abc
ABCMKARGS = CC="$(CXX)" CXX="$(CXX)" ABC_USE_LIBSTDCXX=1
@@ -588,6 +588,11 @@ $(eval $(call add_include_file,passes/fsm/fsmdata.h))
$(eval $(call add_include_file,frontends/ast/ast.h))
$(eval $(call add_include_file,backends/ilang/ilang_backend.h))
$(eval $(call add_include_file,backends/cxxrtl/cxxrtl.h))
+$(eval $(call add_include_file,backends/cxxrtl/cxxrtl_vcd.h))
+$(eval $(call add_include_file,backends/cxxrtl/cxxrtl_capi.cc))
+$(eval $(call add_include_file,backends/cxxrtl/cxxrtl_capi.h))
+$(eval $(call add_include_file,backends/cxxrtl/cxxrtl_vcd_capi.cc))
+$(eval $(call add_include_file,backends/cxxrtl/cxxrtl_vcd_capi.h))
OBJS += kernel/driver.o kernel/register.o kernel/rtlil.o kernel/log.o kernel/calc.o kernel/yosys.o
OBJS += kernel/cellaigs.o kernel/celledges.o
@@ -717,7 +722,7 @@ ifneq ($(ABCREV),default)
echo 'REEBE: NOP pbagnvaf ybpny zbqvsvpngvbaf! Frg NOPERI=qrsnhyg va Lbflf Znxrsvyr!' | tr 'A-Za-z' 'N-ZA-Mn-za-m'; false; \
fi
# set a variable so the test fails if git fails to run - when comparing outputs directly, empty string would match empty string
- $(Q) if ! (cd abc && rev="`git rev-parse $(ABCREV)`" && test "`git rev-parse HEAD`" == "$$rev"); then \
+ $(Q) if ! (cd abc 2> /dev/null && rev="`git rev-parse $(ABCREV)`" && test "`git rev-parse HEAD`" == "$$rev"); then \
test $(ABCPULL) -ne 0 || { echo 'REEBE: NOP abg hc gb qngr naq NOPCHYY frg gb 0 va Znxrsvyr!' | tr 'A-Za-z' 'N-ZA-Mn-za-m'; exit 1; }; \
echo "Pulling ABC from $(ABCURL):"; set -x; \
test -d abc || git clone $(ABCURL) abc; \
diff --git a/README.md b/README.md
index c17c0c3b1..203a292d1 100644
--- a/README.md
+++ b/README.md
@@ -309,7 +309,9 @@ Verilog Attributes and non-standard features
that have ports with a width that depends on a parameter.
- The ``hdlname`` attribute is used by some passes to document the original
- (HDL) name of a module when renaming a module.
+ (HDL) name of a module when renaming a module. It should contain a single
+ name, or, when describing a hierarchical name in a flattened design, multiple
+ names separated by a single space character.
- The ``keep`` attribute on cells and wires is used to mark objects that should
never be removed by the optimizer. This is used for example for cells that
@@ -556,6 +558,8 @@ from SystemVerilog:
- enums are supported (including inside packages)
- but are currently not strongly typed
+- packed structs and unions are supported.
+
- SystemVerilog interfaces (SVIs) are supported. Modports for specifying whether
ports are inputs or outputs are supported.
diff --git a/backends/aiger/aiger.cc b/backends/aiger/aiger.cc
index e5a41b5c5..81a3f483b 100644
--- a/backends/aiger/aiger.cc
+++ b/backends/aiger/aiger.cc
@@ -681,7 +681,7 @@ struct AigerWriter
struct AigerBackend : public Backend {
AigerBackend() : Backend("aiger", "write design to AIGER file") { }
- void help() YS_OVERRIDE
+ void help() override
{
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
log("\n");
@@ -719,7 +719,7 @@ struct AigerBackend : public Backend {
log(" AIGER file happy.\n");
log("\n");
}
- void execute(std::ostream *&f, std::string filename, std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
+ void execute(std::ostream *&f, std::string filename, std::vector<std::string> args, RTLIL::Design *design) override
{
bool ascii_mode = false;
bool zinit_mode = false;
diff --git a/backends/aiger/xaiger.cc b/backends/aiger/xaiger.cc
index 1fb7210cb..ef0103c17 100644
--- a/backends/aiger/xaiger.cc
+++ b/backends/aiger/xaiger.cc
@@ -76,14 +76,16 @@ void aiger_encode(std::ostream &f, int x)
struct XAigerWriter
{
+ Design *design;
Module *module;
SigMap sigmap;
+ dict<SigBit, State> init_map;
pool<SigBit> input_bits, output_bits;
dict<SigBit, SigBit> not_map, alias_map;
dict<SigBit, pair<SigBit, SigBit>> and_map;
vector<SigBit> ci_bits, co_bits;
- dict<SigBit, Cell*> ff_bits;
+ vector<Cell*> ff_list;
dict<SigBit, float> arrival_times;
vector<pair<int, int>> aig_gates;
@@ -137,7 +139,7 @@ struct XAigerWriter
return a;
}
- XAigerWriter(Module *module, bool holes_mode=false) : module(module), sigmap(module)
+ XAigerWriter(Module *module, bool dff_mode) : design(module->design), module(module), sigmap(module)
{
pool<SigBit> undriven_bits;
pool<SigBit> unused_bits;
@@ -154,10 +156,11 @@ struct XAigerWriter
// promote keep wires
for (auto wire : module->wires())
- if (wire->get_bool_attribute(ID::keep))
+ if (wire->get_bool_attribute(ID::keep) || wire->get_bool_attribute(ID::abc9_keep))
sigmap.add(wire);
- for (auto wire : module->wires())
+ for (auto wire : module->wires()) {
+ auto it = wire->attributes.find(ID::init);
for (int i = 0; i < GetSize(wire); i++)
{
SigBit wirebit(wire, i);
@@ -174,17 +177,27 @@ struct XAigerWriter
undriven_bits.insert(bit);
unused_bits.insert(bit);
- bool scc = wire->attributes.count(ID::abc9_scc);
- if (wire->port_input || scc)
+ bool keep = wire->get_bool_attribute(ID::abc9_keep);
+ if (wire->port_input || keep)
input_bits.insert(bit);
- bool keep = wire->get_bool_attribute(ID::keep);
- if (wire->port_output || keep || scc) {
+ keep = keep || wire->get_bool_attribute(ID::keep);
+ if (wire->port_output || keep) {
if (bit != wirebit)
alias_map[wirebit] = bit;
output_bits.insert(wirebit);
}
+
+ if (it != wire->attributes.end()) {
+ auto s = it->second[i];
+ if (s != State::Sx) {
+ auto r = init_map.insert(std::make_pair(bit, it->second[i]));
+ if (!r.second && r.first->second != it->second[i])
+ log_error("Bit '%s' has a conflicting (* init *) value.\n", log_signal(bit));
+ }
+ }
}
+ }
TimingInfo timing;
@@ -212,18 +225,14 @@ struct XAigerWriter
continue;
}
- if (cell->type == ID($__ABC9_FF_) &&
- // The presence of an abc9_mergeability attribute indicates
- // that we do want to pass this flop to ABC
- cell->attributes.count(ID::abc9_mergeability))
+ if (dff_mode && cell->type.in(ID($_DFF_N_), ID($_DFF_P_)) && !cell->get_bool_attribute(ID::abc9_keep))
{
SigBit D = sigmap(cell->getPort(ID::D).as_bit());
SigBit Q = sigmap(cell->getPort(ID::Q).as_bit());
unused_bits.erase(D);
undriven_bits.erase(Q);
alias_map[Q] = D;
- auto r YS_ATTRIBUTE(unused) = ff_bits.insert(std::make_pair(D, cell));
- log_assert(r.second);
+ ff_list.emplace_back(cell);
continue;
}
@@ -231,31 +240,29 @@ struct XAigerWriter
continue;
}
- RTLIL::Module* inst_module = module->design->module(cell->type);
- if (inst_module) {
- IdString derived_type = inst_module->derive(module->design, cell->parameters);
- inst_module = module->design->module(derived_type);
- log_assert(inst_module);
-
+ RTLIL::Module* inst_module = design->module(cell->type);
+ if (inst_module && inst_module->get_blackbox_attribute()) {
bool abc9_flop = false;
- if (!cell->has_keep_attr()) {
- auto it = cell->attributes.find(ID::abc9_box_seq);
- if (it != cell->attributes.end()) {
- int abc9_box_seq = it->second.as_int();
- if (GetSize(box_list) <= abc9_box_seq)
- box_list.resize(abc9_box_seq+1);
- box_list[abc9_box_seq] = cell;
- // Only flop boxes may have arrival times
- // (all others are combinatorial)
- abc9_flop = inst_module->get_bool_attribute(ID::abc9_flop);
- if (!abc9_flop)
- continue;
- }
+
+ auto it = cell->attributes.find(ID::abc9_box_seq);
+ if (it != cell->attributes.end()) {
+ log_assert(!cell->has_keep_attr());
+ log_assert(cell->parameters.empty());
+ int abc9_box_seq = it->second.as_int();
+ if (GetSize(box_list) <= abc9_box_seq)
+ box_list.resize(abc9_box_seq+1);
+ box_list[abc9_box_seq] = cell;
+ // Only flop boxes may have arrival times
+ // (all others are combinatorial)
+ log_assert(cell->parameters.empty());
+ abc9_flop = inst_module->get_bool_attribute(ID::abc9_flop);
+ if (!abc9_flop)
+ continue;
}
- if (!timing.count(derived_type))
+ if (!timing.count(inst_module->name))
timing.setup_module(inst_module);
- auto &t = timing.at(derived_type).arrival;
+ auto &t = timing.at(inst_module->name).arrival;
for (const auto &conn : cell->connections()) {
auto port_wire = inst_module->wire(conn.first);
if (!port_wire->port_output)
@@ -269,7 +276,7 @@ struct XAigerWriter
#ifndef NDEBUG
if (ys_debug(1)) {
static std::set<std::tuple<IdString,IdString,int>> seen;
- if (seen.emplace(derived_type, conn.first, i).second) log("%s.%s[%d] abc9_arrival = %d\n",
+ if (seen.emplace(inst_module->name, conn.first, i).second) log("%s.%s[%d] abc9_arrival = %d\n",
log_id(cell->type), log_id(conn.first), i, d);
}
#endif
@@ -280,10 +287,6 @@ struct XAigerWriter
if (abc9_flop)
continue;
}
- else {
- if (cell->type == ID($__ABC9_DELAY))
- log_error("Cell type '%s' not recognised. Check that '+/abc9_model.v' has been read.\n", cell->type.c_str());
- }
bool cell_known = inst_module || cell->known();
for (const auto &c : cell->connections()) {
@@ -317,9 +320,9 @@ struct XAigerWriter
for (auto cell : box_list) {
log_assert(cell);
- RTLIL::Module* box_module = module->design->module(cell->type);
+ RTLIL::Module* box_module = design->module(cell->type);
log_assert(box_module);
- log_assert(box_module->attributes.count(ID::abc9_box_id) || box_module->get_bool_attribute(ID::abc9_flop));
+ log_assert(box_module->has_attribute(ID::abc9_box_id));
auto r = box_ports.insert(cell->type);
if (r.second) {
@@ -383,27 +386,6 @@ struct XAigerWriter
undriven_bits.erase(O);
}
}
-
- // Connect <cell>.abc9_ff.Q (inserted by abc9_map.v) as the last input to the flop box
- if (box_module->get_bool_attribute(ID::abc9_flop)) {
- SigSpec rhs = module->wire(stringf("%s.abc9_ff.Q", cell->name.c_str()));
- if (rhs.empty())
- log_error("'%s.abc9_ff.Q' is not a wire present in module '%s'.\n", log_id(cell), log_id(module));
-
- for (auto b : rhs) {
- SigBit I = sigmap(b);
- if (b == RTLIL::Sx)
- b = State::S0;
- else if (I != b) {
- if (I == RTLIL::Sx)
- alias_map[b] = State::S0;
- else
- alias_map[b] = I;
- }
- co_bits.emplace_back(b);
- unused_bits.erase(I);
- }
- }
}
for (auto bit : input_bits)
@@ -419,16 +401,14 @@ struct XAigerWriter
undriven_bits.erase(bit);
}
- if (holes_mode) {
- struct sort_by_port_id {
- bool operator()(const RTLIL::SigBit& a, const RTLIL::SigBit& b) const {
- return a.wire->port_id < b.wire->port_id ||
- (a.wire->port_id == b.wire->port_id && a.offset < b.offset);
- }
- };
- input_bits.sort(sort_by_port_id());
- output_bits.sort(sort_by_port_id());
- }
+ struct sort_by_port_id {
+ bool operator()(const RTLIL::SigBit& a, const RTLIL::SigBit& b) const {
+ return a.wire->port_id < b.wire->port_id ||
+ (a.wire->port_id == b.wire->port_id && a.offset < b.offset);
+ }
+ };
+ input_bits.sort(sort_by_port_id());
+ output_bits.sort(sort_by_port_id());
aig_map[State::S0] = 0;
aig_map[State::S1] = 1;
@@ -439,8 +419,7 @@ struct XAigerWriter
aig_map[bit] = 2*aig_m;
}
- for (const auto &i : ff_bits) {
- const Cell *cell = i.second;
+ for (auto cell : ff_list) {
const SigBit &q = sigmap(cell->getPort(ID::Q));
aig_m++, aig_i++;
log_assert(!aig_map.count(q));
@@ -487,8 +466,8 @@ struct XAigerWriter
aig_outputs.push_back(aig);
}
- for (auto &i : ff_bits) {
- const SigBit &d = i.first;
+ for (auto cell : ff_list) {
+ const SigBit &d = sigmap(cell->getPort(ID::D));
aig_o++;
aig_outputs.push_back(aig_map.at(d));
}
@@ -560,16 +539,16 @@ struct XAigerWriter
std::stringstream h_buffer;
auto write_h_buffer = std::bind(write_buffer, std::ref(h_buffer), std::placeholders::_1);
write_h_buffer(1);
- log_debug("ciNum = %d\n", GetSize(input_bits) + GetSize(ff_bits) + GetSize(ci_bits));
- write_h_buffer(input_bits.size() + ff_bits.size() + ci_bits.size());
- log_debug("coNum = %d\n", GetSize(output_bits) + GetSize(ff_bits) + GetSize(co_bits));
- write_h_buffer(output_bits.size() + GetSize(ff_bits) + GetSize(co_bits));
- log_debug("piNum = %d\n", GetSize(input_bits) + GetSize(ff_bits));
- write_h_buffer(input_bits.size() + ff_bits.size());
- log_debug("poNum = %d\n", GetSize(output_bits) + GetSize(ff_bits));
- write_h_buffer(output_bits.size() + ff_bits.size());
+ log_debug("ciNum = %d\n", GetSize(input_bits) + GetSize(ff_list) + GetSize(ci_bits));
+ write_h_buffer(GetSize(input_bits) + GetSize(ff_list) + GetSize(ci_bits));
+ log_debug("coNum = %d\n", GetSize(output_bits) + GetSize(ff_list) + GetSize(co_bits));
+ write_h_buffer(GetSize(output_bits) + GetSize(ff_list) + GetSize(co_bits));
+ log_debug("piNum = %d\n", GetSize(input_bits) + GetSize(ff_list));
+ write_h_buffer(GetSize(input_bits) + GetSize(ff_list));
+ log_debug("poNum = %d\n", GetSize(output_bits) + GetSize(ff_list));
+ write_h_buffer(GetSize(output_bits) + GetSize(ff_list));
log_debug("boxNum = %d\n", GetSize(box_list));
- write_h_buffer(box_list.size());
+ write_h_buffer(GetSize(box_list));
auto write_buffer_float = [](std::stringstream &buffer, float f32) {
buffer.write(reinterpret_cast<const char*>(&f32), sizeof(f32));
@@ -583,23 +562,20 @@ struct XAigerWriter
//for (auto bit : output_bits)
// write_o_buffer(0);
- if (!box_list.empty() || !ff_bits.empty()) {
+ if (!box_list.empty() || !ff_list.empty()) {
dict<IdString, std::tuple<int,int,int>> cell_cache;
int box_count = 0;
for (auto cell : box_list) {
log_assert(cell);
+ log_assert(cell->parameters.empty());
- RTLIL::Module* box_module = module->design->module(cell->type);
- log_assert(box_module);
-
- IdString derived_type = box_module->derive(box_module->design, cell->parameters);
- box_module = box_module->design->module(derived_type);
- log_assert(box_module);
-
- auto r = cell_cache.insert(derived_type);
+ auto r = cell_cache.insert(cell->type);
auto &v = r.first->second;
if (r.second) {
+ RTLIL::Module* box_module = design->module(cell->type);
+ log_assert(box_module);
+
int box_inputs = 0, box_outputs = 0;
for (auto port_name : box_module->ports) {
RTLIL::Wire *w = box_module->wire(port_name);
@@ -610,11 +586,6 @@ struct XAigerWriter
box_outputs += GetSize(w);
}
- // For flops only, create an extra 1-bit input that drives a new wire
- // called "<cell>.abc9_ff.Q" that is used below
- if (box_module->get_bool_attribute(ID::abc9_flop))
- box_inputs++;
-
std::get<0>(v) = box_inputs;
std::get<1>(v) = box_outputs;
std::get<2>(v) = box_module->attributes.at(ID::abc9_box_id).as_int();
@@ -628,30 +599,33 @@ struct XAigerWriter
std::stringstream r_buffer;
auto write_r_buffer = std::bind(write_buffer, std::ref(r_buffer), std::placeholders::_1);
- log_debug("flopNum = %d\n", GetSize(ff_bits));
- write_r_buffer(ff_bits.size());
+ log_debug("flopNum = %d\n", GetSize(ff_list));
+ write_r_buffer(ff_list.size());
std::stringstream s_buffer;
auto write_s_buffer = std::bind(write_buffer, std::ref(s_buffer), std::placeholders::_1);
- write_s_buffer(ff_bits.size());
+ write_s_buffer(ff_list.size());
- for (const auto &i : ff_bits) {
- const SigBit &d = i.first;
- const Cell *cell = i.second;
+ dict<SigSpec, int> clk_to_mergeability;
+ for (const auto cell : ff_list) {
+ const SigBit &d = sigmap(cell->getPort(ID::D));
+ const SigBit &q = sigmap(cell->getPort(ID::Q));
- int mergeability = cell->attributes.at(ID::abc9_mergeability).as_int();
+ SigSpec clk_and_pol{sigmap(cell->getPort(ID::C)), cell->type[6] == 'P' ? State::S1 : State::S0};
+ auto r = clk_to_mergeability.insert(std::make_pair(clk_and_pol, clk_to_mergeability.size()+1));
+ int mergeability = r.first->second;
log_assert(mergeability > 0);
write_r_buffer(mergeability);
- Const init = cell->attributes.at(ID::abc9_init, State::Sx);
- log_assert(GetSize(init) == 1);
+ State init = init_map.at(q, State::Sx);
+ log_debug("Cell '%s' (type %s) has (* init *) value '%s'.\n", log_id(cell), log_id(cell->type), log_signal(init));
if (init == State::S1)
write_s_buffer(1);
else if (init == State::S0)
write_s_buffer(0);
else {
log_assert(init == State::Sx);
- write_s_buffer(0);
+ write_s_buffer(2);
}
// Use arrival time from output of flop box
@@ -671,10 +645,16 @@ struct XAigerWriter
f.write(reinterpret_cast<const char*>(&buffer_size_be), sizeof(buffer_size_be));
f.write(buffer_str.data(), buffer_str.size());
- RTLIL::Module *holes_module = module->design->module(stringf("%s$holes", module->name.c_str()));
+ RTLIL::Design *holes_design;
+ auto it = saved_designs.find("$abc9_holes");
+ if (it != saved_designs.end())
+ holes_design = it->second;
+ else
+ holes_design = nullptr;
+ RTLIL::Module *holes_module = holes_design ? holes_design->module(module->name) : nullptr;
if (holes_module) {
std::stringstream a_buffer;
- XAigerWriter writer(holes_module, true /* holes_mode */);
+ XAigerWriter writer(holes_module, false /* dff_mode */);
writer.write_aiger(a_buffer, false /*ascii_mode*/);
f << "a";
@@ -704,10 +684,10 @@ struct XAigerWriter
f << stringf("Generated by %s\n", yosys_version_str);
- module->design->scratchpad_set_int("write_xaiger.num_ands", and_map.size());
- module->design->scratchpad_set_int("write_xaiger.num_wires", aig_map.size());
- module->design->scratchpad_set_int("write_xaiger.num_inputs", input_bits.size());
- module->design->scratchpad_set_int("write_xaiger.num_outputs", output_bits.size());
+ design->scratchpad_set_int("write_xaiger.num_ands", and_map.size());
+ design->scratchpad_set_int("write_xaiger.num_wires", aig_map.size());
+ design->scratchpad_set_int("write_xaiger.num_inputs", input_bits.size());
+ design->scratchpad_set_int("write_xaiger.num_outputs", output_bits.size());
}
void write_map(std::ostream &f)
@@ -717,8 +697,6 @@ struct XAigerWriter
for (auto wire : module->wires())
{
- SigSpec sig = sigmap(wire);
-
for (int i = 0; i < GetSize(wire); i++)
{
RTLIL::SigBit b(wire, i);
@@ -731,7 +709,6 @@ struct XAigerWriter
if (output_bits.count(b)) {
int o = ordered_outputs.at(b);
output_lines[o] += stringf("output %d %d %s\n", o - GetSize(co_bits), wire->start_offset+i, log_id(wire));
- continue;
}
}
}
@@ -754,17 +731,17 @@ struct XAigerWriter
struct XAigerBackend : public Backend {
XAigerBackend() : Backend("xaiger", "write design to XAIGER file") { }
- void help() YS_OVERRIDE
+ void help() override
{
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
log("\n");
log(" write_xaiger [options] [filename]\n");
log("\n");
log("Write the top module (according to the (* top *) attribute or if only one module\n");
- log("is currently selected) to an XAIGER file. Any non $_NOT_, $_AND_, $_ABC9_FF_, or");
- log("non (* abc9_box_id *) cells will be converted into psuedo-inputs and\n");
- log("pseudo-outputs. Whitebox contents will be taken from the '<module-name>$holes'\n");
- log("module, if it exists.\n");
+ log("is currently selected) to an XAIGER file. Any non $_NOT_, $_AND_, (optionally\n");
+ log("$_DFF_N_, $_DFF_P_), or non (* abc9_box *) cells will be converted into psuedo-\n");
+ log("inputs and pseudo-outputs. Whitebox contents will be taken from the equivalent\n");
+ log("module in the '$abc9_holes' design, if it exists.\n");
log("\n");
log(" -ascii\n");
log(" write ASCII version of AIGER format\n");
@@ -772,10 +749,13 @@ struct XAigerBackend : public Backend {
log(" -map <filename>\n");
log(" write an extra file with port and box symbols\n");
log("\n");
+ log(" -dff\n");
+ log(" write $_DFF_[NP]_ cells\n");
+ log("\n");
}
- void execute(std::ostream *&f, std::string filename, std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
+ void execute(std::ostream *&f, std::string filename, std::vector<std::string> args, RTLIL::Design *design) override
{
- bool ascii_mode = false;
+ bool ascii_mode = false, dff_mode = false;
std::string map_filename;
log_header(design, "Executing XAIGER backend.\n");
@@ -791,6 +771,10 @@ struct XAigerBackend : public Backend {
map_filename = args[++argidx];
continue;
}
+ if (args[argidx] == "-dff") {
+ dff_mode = true;
+ continue;
+ }
break;
}
extra_args(f, filename, args, argidx, !ascii_mode);
@@ -808,7 +792,7 @@ struct XAigerBackend : public Backend {
if (!top_module->memories.empty())
log_error("Found unmapped memories in module %s: unmapped memories are not supported in XAIGER backend!\n", log_id(top_module));
- XAigerWriter writer(top_module);
+ XAigerWriter writer(top_module, dff_mode);
writer.write_aiger(*f, ascii_mode);
if (!map_filename.empty()) {
diff --git a/backends/blif/blif.cc b/backends/blif/blif.cc
index b028df848..780a16320 100644
--- a/backends/blif/blif.cc
+++ b/backends/blif/blif.cc
@@ -482,7 +482,7 @@ struct BlifDumper
struct BlifBackend : public Backend {
BlifBackend() : Backend("blif", "write design to BLIF file") { }
- void help() YS_OVERRIDE
+ void help() override
{
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
log("\n");
@@ -552,7 +552,7 @@ struct BlifBackend : public Backend {
log(" do not write definitions for the $true, $false and $undef wires.\n");
log("\n");
}
- void execute(std::ostream *&f, std::string filename, std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
+ void execute(std::ostream *&f, std::string filename, std::vector<std::string> args, RTLIL::Design *design) override
{
std::string top_module_name;
std::string buf_type, buf_in, buf_out;
diff --git a/backends/btor/btor.cc b/backends/btor/btor.cc
index 14c8484e8..e5da6c1e7 100644
--- a/backends/btor/btor.cc
+++ b/backends/btor/btor.cc
@@ -40,6 +40,7 @@ struct BtorWorker
bool verbose;
bool single_bad;
bool cover_mode;
+ bool print_internal_names;
int next_nid = 1;
int initstate_nid = -1;
@@ -78,7 +79,7 @@ struct BtorWorker
vector<string> info_lines;
dict<int, int> info_clocks;
- void btorf(const char *fmt, ...)
+ void btorf(const char *fmt, ...) YS_ATTRIBUTE(format(printf, 2, 3))
{
va_list ap;
va_start(ap, fmt);
@@ -86,7 +87,7 @@ struct BtorWorker
va_end(ap);
}
- void infof(const char *fmt, ...)
+ void infof(const char *fmt, ...) YS_ATTRIBUTE(format(printf, 2, 3))
{
va_list ap;
va_start(ap, fmt);
@@ -98,6 +99,7 @@ struct BtorWorker
string getinfo(T *obj, bool srcsym = false)
{
string infostr = log_id(obj);
+ if (!srcsym && !print_internal_names && infostr[0] == '$') return "";
if (obj->attributes.count(ID::src)) {
string src = obj->attributes.at(ID::src).decode_string().c_str();
if (srcsym && infostr[0] == '$') {
@@ -117,7 +119,7 @@ struct BtorWorker
infostr += " ; " + src;
}
}
- return infostr;
+ return " " + infostr;
}
void btorf_push(const string &id)
@@ -242,7 +244,7 @@ struct BtorWorker
btorf("%d slt %d %d %d\n", nid_b_ltz, sid_bit, nid_b, nid_zero);
nid = next_nid++;
- btorf("%d ite %d %d %d %d %s\n", nid, sid, nid_b_ltz, nid_l, nid_r, getinfo(cell).c_str());
+ btorf("%d ite %d %d %d %d%s\n", nid, sid, nid_b_ltz, nid_l, nid_r, getinfo(cell).c_str());
}
else
{
@@ -250,7 +252,7 @@ struct BtorWorker
int nid_b = get_sig_nid(cell->getPort(ID::B), width, b_signed);
nid = next_nid++;
- btorf("%d %s %d %d %d %s\n", nid, btor_op.c_str(), sid, nid_a, nid_b, getinfo(cell).c_str());
+ btorf("%d %s %d %d %d%s\n", nid, btor_op.c_str(), sid, nid_a, nid_b, getinfo(cell).c_str());
}
SigSpec sig = sigmap(cell->getPort(ID::Y));
@@ -266,26 +268,32 @@ struct BtorWorker
goto okay;
}
- if (cell->type.in(ID($div), ID($mod)))
+ if (cell->type.in(ID($div), ID($mod), ID($modfloor)))
{
+ bool a_signed = cell->hasParam(ID::A_SIGNED) ? cell->getParam(ID::A_SIGNED).as_bool() : false;
+ bool b_signed = cell->hasParam(ID::B_SIGNED) ? cell->getParam(ID::B_SIGNED).as_bool() : false;
+
string btor_op;
if (cell->type == ID($div)) btor_op = "div";
+ // "rem" = truncating modulo
if (cell->type == ID($mod)) btor_op = "rem";
+ // "mod" = flooring modulo
+ if (cell->type == ID($modfloor)) {
+ // "umod" doesn't exist because it's the same as "urem"
+ btor_op = a_signed || b_signed ? "mod" : "rem";
+ }
log_assert(!btor_op.empty());
int width = GetSize(cell->getPort(ID::Y));
width = std::max(width, GetSize(cell->getPort(ID::A)));
width = std::max(width, GetSize(cell->getPort(ID::B)));
- bool a_signed = cell->hasParam(ID::A_SIGNED) ? cell->getParam(ID::A_SIGNED).as_bool() : false;
- bool b_signed = cell->hasParam(ID::B_SIGNED) ? cell->getParam(ID::B_SIGNED).as_bool() : false;
-
int nid_a = get_sig_nid(cell->getPort(ID::A), width, a_signed);
int nid_b = get_sig_nid(cell->getPort(ID::B), width, b_signed);
int sid = get_bv_sid(width);
int nid = next_nid++;
- btorf("%d %c%s %d %d %d %s\n", nid, a_signed || b_signed ? 's' : 'u', btor_op.c_str(), sid, nid_a, nid_b, getinfo(cell).c_str());
+ btorf("%d %c%s %d %d %d%s\n", nid, a_signed || b_signed ? 's' : 'u', btor_op.c_str(), sid, nid_a, nid_b, getinfo(cell).c_str());
SigSpec sig = sigmap(cell->getPort(ID::Y));
@@ -311,12 +319,12 @@ struct BtorWorker
if (cell->type == ID($_ANDNOT_)) {
btorf("%d not %d %d\n", nid1, sid, nid_b);
- btorf("%d and %d %d %d %s\n", nid2, sid, nid_a, nid1, getinfo(cell).c_str());
+ btorf("%d and %d %d %d%s\n", nid2, sid, nid_a, nid1, getinfo(cell).c_str());
}
if (cell->type == ID($_ORNOT_)) {
btorf("%d not %d %d\n", nid1, sid, nid_b);
- btorf("%d or %d %d %d %s\n", nid2, sid, nid_a, nid1, getinfo(cell).c_str());
+ btorf("%d or %d %d %d%s\n", nid2, sid, nid_a, nid1, getinfo(cell).c_str());
}
SigSpec sig = sigmap(cell->getPort(ID::Y));
@@ -338,13 +346,13 @@ struct BtorWorker
if (cell->type == ID($_OAI3_)) {
btorf("%d or %d %d %d\n", nid1, sid, nid_a, nid_b);
btorf("%d and %d %d %d\n", nid2, sid, nid1, nid_c);
- btorf("%d not %d %d %s\n", nid3, sid, nid2, getinfo(cell).c_str());
+ btorf("%d not %d %d%s\n", nid3, sid, nid2, getinfo(cell).c_str());
}
if (cell->type == ID($_AOI3_)) {
btorf("%d and %d %d %d\n", nid1, sid, nid_a, nid_b);
btorf("%d or %d %d %d\n", nid2, sid, nid1, nid_c);
- btorf("%d not %d %d %s\n", nid3, sid, nid2, getinfo(cell).c_str());
+ btorf("%d not %d %d%s\n", nid3, sid, nid2, getinfo(cell).c_str());
}
SigSpec sig = sigmap(cell->getPort(ID::Y));
@@ -369,14 +377,14 @@ struct BtorWorker
btorf("%d or %d %d %d\n", nid1, sid, nid_a, nid_b);
btorf("%d or %d %d %d\n", nid2, sid, nid_c, nid_d);
btorf("%d and %d %d %d\n", nid3, sid, nid1, nid2);
- btorf("%d not %d %d %s\n", nid4, sid, nid3, getinfo(cell).c_str());
+ btorf("%d not %d %d%s\n", nid4, sid, nid3, getinfo(cell).c_str());
}
if (cell->type == ID($_AOI4_)) {
btorf("%d and %d %d %d\n", nid1, sid, nid_a, nid_b);
btorf("%d and %d %d %d\n", nid2, sid, nid_c, nid_d);
btorf("%d or %d %d %d\n", nid3, sid, nid1, nid2);
- btorf("%d not %d %d %s\n", nid4, sid, nid3, getinfo(cell).c_str());
+ btorf("%d not %d %d%s\n", nid4, sid, nid3, getinfo(cell).c_str());
}
SigSpec sig = sigmap(cell->getPort(ID::Y));
@@ -408,9 +416,9 @@ struct BtorWorker
int nid = next_nid++;
if (cell->type.in(ID($lt), ID($le), ID($ge), ID($gt))) {
- btorf("%d %c%s %d %d %d %s\n", nid, a_signed || b_signed ? 's' : 'u', btor_op.c_str(), sid, nid_a, nid_b, getinfo(cell).c_str());
+ btorf("%d %c%s %d %d %d%s\n", nid, a_signed || b_signed ? 's' : 'u', btor_op.c_str(), sid, nid_a, nid_b, getinfo(cell).c_str());
} else {
- btorf("%d %s %d %d %d %s\n", nid, btor_op.c_str(), sid, nid_a, nid_b, getinfo(cell).c_str());
+ btorf("%d %s %d %d %d%s\n", nid, btor_op.c_str(), sid, nid_a, nid_b, getinfo(cell).c_str());
}
SigSpec sig = sigmap(cell->getPort(ID::Y));
@@ -441,7 +449,7 @@ struct BtorWorker
int nid_a = get_sig_nid(cell->getPort(ID::A), width, a_signed);
int nid = next_nid++;
- btorf("%d %s %d %d\n", nid, btor_op.c_str(), sid, nid_a, getinfo(cell).c_str());
+ btorf("%d %s %d %d%s\n", nid, btor_op.c_str(), sid, nid_a, getinfo(cell).c_str());
SigSpec sig = sigmap(cell->getPort(ID::Y));
@@ -482,9 +490,9 @@ struct BtorWorker
int nid = next_nid++;
if (btor_op != "not")
- btorf("%d %s %d %d %d\n", nid, btor_op.c_str(), sid, nid_a, nid_b, getinfo(cell).c_str());
+ btorf("%d %s %d %d %d%s\n", nid, btor_op.c_str(), sid, nid_a, nid_b, getinfo(cell).c_str());
else
- btorf("%d %s %d %d\n", nid, btor_op.c_str(), sid, nid_a, getinfo(cell).c_str());
+ btorf("%d %s %d %d%s\n", nid, btor_op.c_str(), sid, nid_a, getinfo(cell).c_str());
SigSpec sig = sigmap(cell->getPort(ID::Y));
@@ -515,11 +523,11 @@ struct BtorWorker
if (cell->type == ID($reduce_xnor)) {
int nid2 = next_nid++;
- btorf("%d %s %d %d %s\n", nid, btor_op.c_str(), sid, nid_a, getinfo(cell).c_str());
- btorf("%d not %d %d %d\n", nid2, sid, nid);
+ btorf("%d %s %d %d%s\n", nid, btor_op.c_str(), sid, nid_a, getinfo(cell).c_str());
+ btorf("%d not %d %d\n", nid2, sid, nid);
nid = nid2;
} else {
- btorf("%d %s %d %d %s\n", nid, btor_op.c_str(), sid, nid_a, getinfo(cell).c_str());
+ btorf("%d %s %d %d%s\n", nid, btor_op.c_str(), sid, nid_a, getinfo(cell).c_str());
}
SigSpec sig = sigmap(cell->getPort(ID::Y));
@@ -554,9 +562,9 @@ struct BtorWorker
int tmp = nid;
nid = next_nid++;
btorf("%d ite %d %d %d %d\n", tmp, sid, nid_s, nid_b, nid_a);
- btorf("%d not %d %d %s\n", nid, sid, tmp, getinfo(cell).c_str());
+ btorf("%d not %d %d%s\n", nid, sid, tmp, getinfo(cell).c_str());
} else {
- btorf("%d ite %d %d %d %d %s\n", nid, sid, nid_s, nid_b, nid_a, getinfo(cell).c_str());
+ btorf("%d ite %d %d %d %d%s\n", nid, sid, nid_s, nid_b, nid_a, getinfo(cell).c_str());
}
add_nid_sig(nid, sig_y);
@@ -579,7 +587,7 @@ struct BtorWorker
int nid_s = get_sig_nid(sig_s.extract(i));
int nid2 = next_nid++;
if (i == GetSize(sig_s)-1)
- btorf("%d ite %d %d %d %d %s\n", nid2, sid, nid_s, nid_b, nid, getinfo(cell).c_str());
+ btorf("%d ite %d %d %d %d%s\n", nid2, sid, nid_s, nid_b, nid, getinfo(cell).c_str());
else
btorf("%d ite %d %d %d %d\n", nid2, sid, nid_s, nid_b, nid);
nid = nid2;
@@ -634,7 +642,7 @@ struct BtorWorker
int sid = get_bv_sid(GetSize(sig_q));
int nid = next_nid++;
- if (symbol.empty())
+ if (symbol.empty() || (!print_internal_names && symbol[0] == '$'))
btorf("%d state %d\n", nid, sid);
else
btorf("%d state %d %s\n", nid, sid, log_id(symbol));
@@ -1043,8 +1051,8 @@ struct BtorWorker
return nid;
}
- BtorWorker(std::ostream &f, RTLIL::Module *module, bool verbose, bool single_bad, bool cover_mode, string info_filename) :
- f(f), sigmap(module), module(module), verbose(verbose), single_bad(single_bad), cover_mode(cover_mode), info_filename(info_filename)
+ BtorWorker(std::ostream &f, RTLIL::Module *module, bool verbose, bool single_bad, bool cover_mode, bool print_internal_names, string info_filename) :
+ f(f), sigmap(module), module(module), verbose(verbose), single_bad(single_bad), cover_mode(cover_mode), print_internal_names(print_internal_names), info_filename(info_filename)
{
if (!info_filename.empty())
infof("name %s\n", log_id(module));
@@ -1067,7 +1075,7 @@ struct BtorWorker
int sid = get_bv_sid(GetSize(sig));
int nid = next_nid++;
- btorf("%d input %d %s\n", nid, sid, getinfo(wire).c_str());
+ btorf("%d input %d%s\n", nid, sid, getinfo(wire).c_str());
add_nid_sig(nid, sig);
}
@@ -1091,7 +1099,7 @@ struct BtorWorker
btorf_push(stringf("output %s", log_id(wire)));
int nid = get_sig_nid(wire);
- btorf("%d output %d %s\n", next_nid++, nid, getinfo(wire).c_str());
+ btorf("%d output %d%s\n", next_nid++, nid, getinfo(wire).c_str());
btorf_pop(stringf("output %s", log_id(wire)));
}
@@ -1133,10 +1141,10 @@ struct BtorWorker
bad_properties.push_back(nid_en_and_not_a);
} else {
if (cover_mode) {
- infof("bad %d %s\n", nid_en_and_not_a, getinfo(cell, true).c_str());
+ infof("bad %d%s\n", nid_en_and_not_a, getinfo(cell, true).c_str());
} else {
int nid = next_nid++;
- btorf("%d bad %d %s\n", nid, nid_en_and_not_a, getinfo(cell, true).c_str());
+ btorf("%d bad %d%s\n", nid, nid_en_and_not_a, getinfo(cell, true).c_str());
}
}
@@ -1158,7 +1166,7 @@ struct BtorWorker
bad_properties.push_back(nid_en_and_a);
} else {
int nid = next_nid++;
- btorf("%d bad %d %s\n", nid, nid_en_and_a, getinfo(cell, true).c_str());
+ btorf("%d bad %d%s\n", nid, nid_en_and_a, getinfo(cell, true).c_str());
}
btorf_pop(log_id(cell));
@@ -1179,7 +1187,7 @@ struct BtorWorker
continue;
int this_nid = next_nid++;
- btorf("%d uext %d %d %d %s\n", this_nid, sid, nid, 0, getinfo(wire).c_str());
+ btorf("%d uext %d %d %d%s\n", this_nid, sid, nid, 0, getinfo(wire).c_str());
btorf_pop(stringf("wire %s", log_id(wire)));
continue;
@@ -1250,14 +1258,14 @@ struct BtorWorker
}
int nid2 = next_nid++;
- btorf("%d next %d %d %d %s\n", nid2, sid, nid, nid_head, getinfo(cell).c_str());
+ btorf("%d next %d %d %d%s\n", nid2, sid, nid, nid_head, getinfo(cell).c_str());
}
else
{
SigSpec sig = sigmap(cell->getPort(ID::D));
int nid_q = get_sig_nid(sig);
int sid = get_bv_sid(GetSize(sig));
- btorf("%d next %d %d %d %s\n", next_nid++, sid, nid, nid_q, getinfo(cell).c_str());
+ btorf("%d next %d %d %d%s\n", next_nid++, sid, nid, nid_q, getinfo(cell).c_str());
}
btorf_pop(stringf("next %s", log_id(cell)));
@@ -1327,7 +1335,7 @@ struct BtorWorker
struct BtorBackend : public Backend {
BtorBackend() : Backend("btor", "write design to BTOR file") { }
- void help() YS_OVERRIDE
+ void help() override
{
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
log("\n");
@@ -1347,10 +1355,13 @@ struct BtorBackend : public Backend {
log(" -i <filename>\n");
log(" Create additional info file with auxiliary information\n");
log("\n");
+ log(" -x\n");
+ log(" Output symbols for internal netnames (starting with '$')\n");
+ log("\n");
}
- void execute(std::ostream *&f, std::string filename, std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
+ void execute(std::ostream *&f, std::string filename, std::vector<std::string> args, RTLIL::Design *design) override
{
- bool verbose = false, single_bad = false, cover_mode = false;
+ bool verbose = false, single_bad = false, cover_mode = false, print_internal_names = false;
string info_filename;
log_header(design, "Executing BTOR backend.\n");
@@ -1374,6 +1385,10 @@ struct BtorBackend : public Backend {
info_filename = args[++argidx];
continue;
}
+ if (args[argidx] == "-x") {
+ print_internal_names = true;
+ continue;
+ }
break;
}
extra_args(f, filename, args, argidx);
@@ -1386,7 +1401,7 @@ struct BtorBackend : public Backend {
*f << stringf("; BTOR description generated by %s for module %s.\n",
yosys_version_str, log_id(topmod));
- BtorWorker(*f, topmod, verbose, single_bad, cover_mode, info_filename);
+ BtorWorker(*f, topmod, verbose, single_bad, cover_mode, print_internal_names, info_filename);
*f << stringf("; end of yosys output\n");
}
diff --git a/backends/btor/test_cells.sh b/backends/btor/test_cells.sh
index e0f1a0514..3f077201a 100644
--- a/backends/btor/test_cells.sh
+++ b/backends/btor/test_cells.sh
@@ -6,7 +6,7 @@ rm -rf test_cells.tmp
mkdir -p test_cells.tmp
cd test_cells.tmp
-../../../yosys -p 'test_cell -n 5 -w test all /$alu /$fa /$lcu /$lut /$sop /$macc /$mul /$div /$mod'
+../../../yosys -p 'test_cell -n 5 -w test all /$alu /$fa /$lcu /$lut /$sop /$macc /$mul /$div /$mod /$divfloor /$modfloor'
for fn in test_*.il; do
../../../yosys -p "
diff --git a/backends/cxxrtl/Makefile.inc b/backends/cxxrtl/Makefile.inc
index f93e65f85..aaa304502 100644
--- a/backends/cxxrtl/Makefile.inc
+++ b/backends/cxxrtl/Makefile.inc
@@ -1,2 +1,2 @@
-OBJS += backends/cxxrtl/cxxrtl.o
+OBJS += backends/cxxrtl/cxxrtl_backend.o
diff --git a/backends/cxxrtl/cxxrtl.h b/backends/cxxrtl/cxxrtl.h
index 701510b7f..f0d7b9fc7 100644
--- a/backends/cxxrtl/cxxrtl.h
+++ b/backends/cxxrtl/cxxrtl.h
@@ -17,6 +17,11 @@
*/
// This file is included by the designs generated with `write_cxxrtl`. It is not used in Yosys itself.
+//
+// The CXXRTL support library implements compile time specialized arbitrary width arithmetics, as well as provides
+// composite lvalues made out of bit slices and concatenations of lvalues. This allows the `write_cxxrtl` pass
+// to perform a straightforward translation of RTLIL structures to readable C++, relying on the C++ compiler
+// to unwrap the abstraction and generate efficient code.
#ifndef CXXRTL_H
#define CXXRTL_H
@@ -33,13 +38,24 @@
#include <memory>
#include <sstream>
-// The cxxrtl support library implements compile time specialized arbitrary width arithmetics, as well as provides
-// composite lvalues made out of bit slices and concatenations of lvalues. This allows the `write_cxxrtl` pass
-// to perform a straightforward translation of RTLIL structures to readable C++, relying on the C++ compiler
-// to unwrap the abstraction and generate efficient code.
+#include <backends/cxxrtl/cxxrtl_capi.h>
+
+// CXXRTL essentially uses the C++ compiler as a hygienic macro engine that feeds an instruction selector.
+// It generates a lot of specialized template functions with relatively large bodies that, when inlined
+// into the caller and (for those with loops) unrolled, often expose many new optimization opportunities.
+// Because of this, most of the CXXRTL runtime must be always inlined for best performance.
+#ifndef __has_attribute
+# define __has_attribute(x) 0
+#endif
+#if __has_attribute(always_inline)
+#define CXXRTL_ALWAYS_INLINE inline __attribute__((__always_inline__))
+#else
+#define CXXRTL_ALWAYS_INLINE inline
+#endif
+
namespace cxxrtl {
-// All arbitrary-width values in cxxrtl are backed by arrays of unsigned integers called chunks. The chunk size
+// All arbitrary-width values in CXXRTL are backed by arrays of unsigned integers called chunks. The chunk size
// is the same regardless of the value width to simplify manipulating values via FFI interfaces, e.g. driving
// and introspecting the simulation in Python.
//
@@ -49,6 +65,9 @@ namespace cxxrtl {
// invisible to the compiler, (b) we often operate on non-power-of-2 values and have to clear the high bits anyway.
// Therefore, using relatively wide chunks and clearing the high bits explicitly and only when we know they may be
// clobbered results in simpler generated code.
+typedef uint32_t chunk_t;
+typedef uint64_t wide_chunk_t;
+
template<typename T>
struct chunk_traits {
static_assert(std::is_integral<T>::value && std::is_unsigned<T>::value,
@@ -65,7 +84,7 @@ template<size_t Bits>
struct value : public expr_base<value<Bits>> {
static constexpr size_t bits = Bits;
- using chunk = chunk_traits<uint32_t>;
+ using chunk = chunk_traits<chunk_t>;
static constexpr chunk::type msb_mask = (Bits % chunk::bits == 0) ? chunk::mask
: chunk::mask >> (chunk::bits - (Bits % chunk::bits));
@@ -81,6 +100,7 @@ struct value : public expr_base<value<Bits>> {
value<Bits> &operator=(const value<Bits> &) = default;
// A (no-op) helper that forces the cast to value<>.
+ CXXRTL_ALWAYS_INLINE
const value<Bits> &val() const {
return *this;
}
@@ -91,12 +111,42 @@ struct value : public expr_base<value<Bits>> {
return ss.str();
}
+ // Conversion operations.
+ //
+ // These functions ensure that a conversion is never out of range, and should be always used, if at all
+ // possible, instead of direct manipulation of the `data` member. For very large types, .slice() and
+ // .concat() can be used to split them into more manageable parts.
+ template<class IntegerT>
+ CXXRTL_ALWAYS_INLINE
+ IntegerT get() const {
+ static_assert(std::numeric_limits<IntegerT>::is_integer && !std::numeric_limits<IntegerT>::is_signed,
+ "get<T>() requires T to be an unsigned integral type");
+ static_assert(std::numeric_limits<IntegerT>::digits >= Bits,
+ "get<T>() requires T to be at least as wide as the value is");
+ IntegerT result = 0;
+ for (size_t n = 0; n < chunks; n++)
+ result |= IntegerT(data[n]) << (n * chunk::bits);
+ return result;
+ }
+
+ template<class IntegerT>
+ CXXRTL_ALWAYS_INLINE
+ void set(IntegerT other) {
+ static_assert(std::numeric_limits<IntegerT>::is_integer && !std::numeric_limits<IntegerT>::is_signed,
+ "set<T>() requires T to be an unsigned integral type");
+ static_assert(std::numeric_limits<IntegerT>::digits >= Bits,
+ "set<T>() requires the value to be at least as wide as T is");
+ for (size_t n = 0; n < chunks; n++)
+ data[n] = (other >> (n * chunk::bits)) & chunk::mask;
+ }
+
// Operations with compile-time parameters.
//
// These operations are used to implement slicing, concatenation, and blitting.
// The trunc, zext and sext operations add or remove most significant bits (i.e. on the left);
// the rtrunc and rzext operations add or remove least significant bits (i.e. on the right).
template<size_t NewBits>
+ CXXRTL_ALWAYS_INLINE
value<NewBits> trunc() const {
static_assert(NewBits <= Bits, "trunc() may not increase width");
value<NewBits> result;
@@ -107,6 +157,7 @@ struct value : public expr_base<value<Bits>> {
}
template<size_t NewBits>
+ CXXRTL_ALWAYS_INLINE
value<NewBits> zext() const {
static_assert(NewBits >= Bits, "zext() may not decrease width");
value<NewBits> result;
@@ -116,6 +167,7 @@ struct value : public expr_base<value<Bits>> {
}
template<size_t NewBits>
+ CXXRTL_ALWAYS_INLINE
value<NewBits> sext() const {
static_assert(NewBits >= Bits, "sext() may not decrease width");
value<NewBits> result;
@@ -131,6 +183,7 @@ struct value : public expr_base<value<Bits>> {
}
template<size_t NewBits>
+ CXXRTL_ALWAYS_INLINE
value<NewBits> rtrunc() const {
static_assert(NewBits <= Bits, "rtrunc() may not increase width");
value<NewBits> result;
@@ -150,6 +203,7 @@ struct value : public expr_base<value<Bits>> {
}
template<size_t NewBits>
+ CXXRTL_ALWAYS_INLINE
value<NewBits> rzext() const {
static_assert(NewBits >= Bits, "rzext() may not decrease width");
value<NewBits> result;
@@ -161,13 +215,14 @@ struct value : public expr_base<value<Bits>> {
carry = (shift_bits == 0) ? 0
: data[n] >> (chunk::bits - shift_bits);
}
- if (carry != 0)
- result.data[result.chunks - 1] = carry;
+ if (shift_chunks + chunks < result.chunks)
+ result.data[shift_chunks + chunks] = carry;
return result;
}
// Bit blit operation, i.e. a partial read-modify-write.
template<size_t Stop, size_t Start>
+ CXXRTL_ALWAYS_INLINE
value<Bits> blit(const value<Stop - Start + 1> &source) const {
static_assert(Stop >= Start, "blit() may not reverse bit order");
constexpr chunk::type start_mask = ~(chunk::mask << (Start % chunk::bits));
@@ -192,6 +247,7 @@ struct value : public expr_base<value<Bits>> {
// than the operand. In C++17 these can be replaced with `if constexpr`.
template<size_t NewBits, typename = void>
struct zext_cast {
+ CXXRTL_ALWAYS_INLINE
value<NewBits> operator()(const value<Bits> &val) {
return val.template zext<NewBits>();
}
@@ -199,6 +255,7 @@ struct value : public expr_base<value<Bits>> {
template<size_t NewBits>
struct zext_cast<NewBits, typename std::enable_if<(NewBits < Bits)>::type> {
+ CXXRTL_ALWAYS_INLINE
value<NewBits> operator()(const value<Bits> &val) {
return val.template trunc<NewBits>();
}
@@ -206,6 +263,7 @@ struct value : public expr_base<value<Bits>> {
template<size_t NewBits, typename = void>
struct sext_cast {
+ CXXRTL_ALWAYS_INLINE
value<NewBits> operator()(const value<Bits> &val) {
return val.template sext<NewBits>();
}
@@ -213,17 +271,20 @@ struct value : public expr_base<value<Bits>> {
template<size_t NewBits>
struct sext_cast<NewBits, typename std::enable_if<(NewBits < Bits)>::type> {
+ CXXRTL_ALWAYS_INLINE
value<NewBits> operator()(const value<Bits> &val) {
return val.template trunc<NewBits>();
}
};
template<size_t NewBits>
+ CXXRTL_ALWAYS_INLINE
value<NewBits> zcast() const {
return zext_cast<NewBits>()(*this);
}
template<size_t NewBits>
+ CXXRTL_ALWAYS_INLINE
value<NewBits> scast() const {
return sext_cast<NewBits>()(*this);
}
@@ -242,6 +303,10 @@ struct value : public expr_base<value<Bits>> {
data[offset_chunks] |= value ? 1 << offset_bits : 0;
}
+ explicit operator bool() const {
+ return !is_zero();
+ }
+
bool is_zero() const {
for (size_t n = 0; n < chunks; n++)
if (data[n] != 0)
@@ -249,10 +314,6 @@ struct value : public expr_base<value<Bits>> {
return true;
}
- explicit operator bool() const {
- return !is_zero();
- }
-
bool is_neg() const {
return data[chunks - 1] & (1 << ((Bits - 1) % chunk::bits));
}
@@ -345,10 +406,12 @@ struct value : public expr_base<value<Bits>> {
: data[chunks - 1 - n] << (chunk::bits - shift_bits);
}
if (Signed && is_neg()) {
- for (size_t n = chunks - shift_chunks; n < chunks; n++)
+ size_t top_chunk_idx = (Bits - shift_bits) / chunk::bits;
+ size_t top_chunk_bits = (Bits - shift_bits) % chunk::bits;
+ for (size_t n = top_chunk_idx + 1; n < chunks; n++)
result.data[n] = chunk::mask;
if (shift_bits != 0)
- result.data[chunks - shift_chunks] |= chunk::mask << (chunk::bits - shift_bits);
+ result.data[top_chunk_idx] |= chunk::mask << top_chunk_bits;
}
return result;
}
@@ -421,6 +484,24 @@ struct value : public expr_base<value<Bits>> {
bool overflow = (is_neg() == !other.is_neg()) && (is_neg() != result.is_neg());
return result.is_neg() ^ overflow; // a.scmp(b) ≡ a s< b
}
+
+ template<size_t ResultBits>
+ value<ResultBits> mul(const value<Bits> &other) const {
+ value<ResultBits> result;
+ wide_chunk_t wide_result[result.chunks + 1] = {};
+ for (size_t n = 0; n < chunks; n++) {
+ for (size_t m = 0; m < chunks && n + m < result.chunks; m++) {
+ wide_result[n + m] += wide_chunk_t(data[n]) * wide_chunk_t(other.data[m]);
+ wide_result[n + m + 1] += wide_result[n + m] >> chunk::bits;
+ wide_result[n + m] &= chunk::mask;
+ }
+ }
+ for (size_t n = 0; n < result.chunks; n++) {
+ result.data[n] = wide_result[n];
+ }
+ result.data[result.chunks - 1] &= result.msb_mask;
+ return result;
+ }
};
// Expression template for a slice, usable as lvalue or rvalue, and composable with other expression templates here.
@@ -435,12 +516,14 @@ struct slice_expr : public expr_base<slice_expr<T, Stop, Start>> {
slice_expr(T &expr) : expr(expr) {}
slice_expr(const slice_expr<T, Stop, Start> &) = delete;
+ CXXRTL_ALWAYS_INLINE
operator value<bits>() const {
return static_cast<const value<T::bits> &>(expr)
.template rtrunc<T::bits - Start>()
.template trunc<bits>();
}
+ CXXRTL_ALWAYS_INLINE
slice_expr<T, Stop, Start> &operator=(const value<bits> &rhs) {
// Generic partial assignment implemented using a read-modify-write operation on the sliced expression.
expr = static_cast<const value<T::bits> &>(expr)
@@ -449,6 +532,7 @@ struct slice_expr : public expr_base<slice_expr<T, Stop, Start>> {
}
// A helper that forces the cast to value<>, which allows deduction to work.
+ CXXRTL_ALWAYS_INLINE
value<bits> val() const {
return static_cast<const value<bits> &>(*this);
}
@@ -465,6 +549,7 @@ struct concat_expr : public expr_base<concat_expr<T, U>> {
concat_expr(T &ms_expr, U &ls_expr) : ms_expr(ms_expr), ls_expr(ls_expr) {}
concat_expr(const concat_expr<T, U> &) = delete;
+ CXXRTL_ALWAYS_INLINE
operator value<bits>() const {
value<bits> ms_shifted = static_cast<const value<T::bits> &>(ms_expr)
.template rzext<bits>();
@@ -473,6 +558,7 @@ struct concat_expr : public expr_base<concat_expr<T, U>> {
return ms_shifted.bit_or(ls_extended);
}
+ CXXRTL_ALWAYS_INLINE
concat_expr<T, U> &operator=(const value<bits> &rhs) {
ms_expr = rhs.template rtrunc<T::bits>();
ls_expr = rhs.template trunc<U::bits>();
@@ -480,6 +566,7 @@ struct concat_expr : public expr_base<concat_expr<T, U>> {
}
// A helper that forces the cast to value<>, which allows deduction to work.
+ CXXRTL_ALWAYS_INLINE
value<bits> val() const {
return static_cast<const value<bits> &>(*this);
}
@@ -504,21 +591,25 @@ struct concat_expr : public expr_base<concat_expr<T, U>> {
template<class T>
struct expr_base {
template<size_t Stop, size_t Start = Stop>
+ CXXRTL_ALWAYS_INLINE
slice_expr<const T, Stop, Start> slice() const {
return {*static_cast<const T *>(this)};
}
template<size_t Stop, size_t Start = Stop>
+ CXXRTL_ALWAYS_INLINE
slice_expr<T, Stop, Start> slice() {
return {*static_cast<T *>(this)};
}
template<class U>
+ CXXRTL_ALWAYS_INLINE
concat_expr<const T, typename std::remove_reference<const U>::type> concat(const U &other) const {
return {*static_cast<const T *>(this), other};
}
template<class U>
+ CXXRTL_ALWAYS_INLINE
concat_expr<T, typename std::remove_reference<U>::type> concat(U &&other) {
return {*static_cast<T *>(this), other};
}
@@ -559,6 +650,18 @@ struct wire {
wire(wire<Bits> &&) = default;
wire<Bits> &operator=(const wire<Bits> &) = delete;
+ template<class IntegerT>
+ CXXRTL_ALWAYS_INLINE
+ IntegerT get() const {
+ return curr.template get<IntegerT>();
+ }
+
+ template<class IntegerT>
+ CXXRTL_ALWAYS_INLINE
+ void set(IntegerT other) {
+ next.template set<IntegerT>(other);
+ }
+
bool commit() {
if (curr != next) {
curr = next;
@@ -604,6 +707,7 @@ struct memory {
// This utterly reprehensible construct is the most reasonable way to apply a function to every element
// of a parameter pack, if the elements all have different types and so cannot be cast to an initializer list.
auto _ = {std::move(std::begin(init.data), std::end(init.data), data.begin() + init.offset)...};
+ (void)_;
}
// An operator for direct memory reads. May be used at any time during the simulation.
@@ -672,10 +776,8 @@ struct metadata {
// In debug mode, using the wrong .as_*() function will assert.
// In release mode, using the wrong .as_*() function will safely return a default value.
- union {
- const unsigned uint_value = 0;
- const signed sint_value;
- };
+ const unsigned uint_value = 0;
+ const signed sint_value = 0;
const std::string string_value = "";
const double double_value = 0.0;
@@ -712,6 +814,139 @@ struct metadata {
typedef std::map<std::string, metadata> metadata_map;
+// Helper class to disambiguate values/wires and their aliases.
+struct debug_alias {};
+
+// This structure is intended for consumption via foreign function interfaces, like Python's ctypes.
+// Because of this it uses a C-style layout that is easy to parse rather than more idiomatic C++.
+//
+// To avoid violating strict aliasing rules, this structure has to be a subclass of the one used
+// in the C API, or it would not be possible to cast between the pointers to these.
+struct debug_item : ::cxxrtl_object {
+ enum : uint32_t {
+ VALUE = CXXRTL_VALUE,
+ WIRE = CXXRTL_WIRE,
+ MEMORY = CXXRTL_MEMORY,
+ ALIAS = CXXRTL_ALIAS,
+ };
+
+ debug_item(const ::cxxrtl_object &object) : cxxrtl_object(object) {}
+
+ template<size_t Bits>
+ debug_item(value<Bits> &item, size_t lsb_offset = 0) {
+ static_assert(sizeof(item) == value<Bits>::chunks * sizeof(chunk_t),
+ "value<Bits> is not compatible with C layout");
+ type = VALUE;
+ width = Bits;
+ lsb_at = lsb_offset;
+ depth = 1;
+ zero_at = 0;
+ curr = item.data;
+ next = item.data;
+ }
+
+ template<size_t Bits>
+ debug_item(const value<Bits> &item, size_t lsb_offset = 0) {
+ static_assert(sizeof(item) == value<Bits>::chunks * sizeof(chunk_t),
+ "value<Bits> is not compatible with C layout");
+ type = VALUE;
+ width = Bits;
+ lsb_at = lsb_offset;
+ depth = 1;
+ zero_at = 0;
+ curr = const_cast<chunk_t*>(item.data);
+ next = nullptr;
+ }
+
+ template<size_t Bits>
+ debug_item(wire<Bits> &item, size_t lsb_offset = 0) {
+ static_assert(sizeof(item.curr) == value<Bits>::chunks * sizeof(chunk_t) &&
+ sizeof(item.next) == value<Bits>::chunks * sizeof(chunk_t),
+ "wire<Bits> is not compatible with C layout");
+ type = WIRE;
+ width = Bits;
+ lsb_at = lsb_offset;
+ depth = 1;
+ zero_at = 0;
+ curr = item.curr.data;
+ next = item.next.data;
+ }
+
+ template<size_t Width>
+ debug_item(memory<Width> &item, size_t zero_offset = 0) {
+ static_assert(sizeof(item.data[0]) == value<Width>::chunks * sizeof(chunk_t),
+ "memory<Width> is not compatible with C layout");
+ type = MEMORY;
+ width = Width;
+ lsb_at = 0;
+ depth = item.data.size();
+ zero_at = zero_offset;
+ curr = item.data.empty() ? nullptr : item.data[0].data;
+ next = nullptr;
+ }
+
+ template<size_t Bits>
+ debug_item(debug_alias, const value<Bits> &item, size_t lsb_offset = 0) {
+ static_assert(sizeof(item) == value<Bits>::chunks * sizeof(chunk_t),
+ "value<Bits> is not compatible with C layout");
+ type = ALIAS;
+ width = Bits;
+ lsb_at = lsb_offset;
+ depth = 1;
+ zero_at = 0;
+ curr = const_cast<chunk_t*>(item.data);
+ next = nullptr;
+ }
+
+ template<size_t Bits>
+ debug_item(debug_alias, const wire<Bits> &item, size_t lsb_offset = 0) {
+ static_assert(sizeof(item.curr) == value<Bits>::chunks * sizeof(chunk_t) &&
+ sizeof(item.next) == value<Bits>::chunks * sizeof(chunk_t),
+ "wire<Bits> is not compatible with C layout");
+ type = ALIAS;
+ width = Bits;
+ lsb_at = lsb_offset;
+ depth = 1;
+ zero_at = 0;
+ curr = const_cast<chunk_t*>(item.curr.data);
+ next = nullptr;
+ }
+};
+static_assert(std::is_standard_layout<debug_item>::value, "debug_item is not compatible with C layout");
+
+struct debug_items {
+ std::map<std::string, std::vector<debug_item>> table;
+
+ void add(const std::string &name, debug_item &&item) {
+ std::vector<debug_item> &parts = table[name];
+ parts.emplace_back(item);
+ std::sort(parts.begin(), parts.end(),
+ [](const debug_item &a, const debug_item &b) {
+ return a.lsb_at < b.lsb_at;
+ });
+ }
+
+ size_t count(const std::string &name) const {
+ if (table.count(name) == 0)
+ return 0;
+ return table.at(name).size();
+ }
+
+ const std::vector<debug_item> &parts_at(const std::string &name) const {
+ return table.at(name);
+ }
+
+ const debug_item &at(const std::string &name) const {
+ const std::vector<debug_item> &parts = table.at(name);
+ assert(parts.size() == 1);
+ return parts.at(0);
+ }
+
+ const debug_item &operator [](const std::string &name) const {
+ return at(name);
+ }
+};
+
struct module {
module() {}
virtual ~module() {}
@@ -731,11 +966,20 @@ struct module {
} while (commit() && !converged);
return deltas;
}
+
+ virtual void debug_info(debug_items &items, std::string path = "") {
+ (void)items, (void)path;
+ }
};
} // namespace cxxrtl
-// Definitions of internal Yosys cells. Other than the functions in this namespace, cxxrtl is fully generic
+// Internal structure used to communicate with the implementation of the C interface.
+typedef struct _cxxrtl_toplevel {
+ std::unique_ptr<cxxrtl::module> module;
+} *cxxrtl_toplevel;
+
+// Definitions of internal Yosys cells. Other than the functions in this namespace, CXXRTL is fully generic
// and indepenent of Yosys implementation details.
//
// The `write_cxxrtl` pass translates internal cells (cells with names that start with `$`) to calls of these
@@ -749,309 +993,322 @@ using namespace cxxrtl;
// std::max isn't constexpr until C++14 for no particular reason (it's an oversight), so we define our own.
template<class T>
+CXXRTL_ALWAYS_INLINE
constexpr T max(const T &a, const T &b) {
return a > b ? a : b;
}
// Logic operations
template<size_t BitsY, size_t BitsA>
-value<BitsY> not_u(const value<BitsA> &a) {
- return a.template zcast<BitsY>().bit_not();
-}
-
-template<size_t BitsY, size_t BitsA>
-value<BitsY> not_s(const value<BitsA> &a) {
- return a.template scast<BitsY>().bit_not();
-}
-
-template<size_t BitsY, size_t BitsA>
-value<BitsY> logic_not_u(const value<BitsA> &a) {
+CXXRTL_ALWAYS_INLINE
+value<BitsY> logic_not(const value<BitsA> &a) {
return value<BitsY> { a ? 0u : 1u };
}
-template<size_t BitsY, size_t BitsA>
-value<BitsY> logic_not_s(const value<BitsA> &a) {
- return value<BitsY> { a ? 0u : 1u };
+template<size_t BitsY, size_t BitsA, size_t BitsB>
+CXXRTL_ALWAYS_INLINE
+value<BitsY> logic_and(const value<BitsA> &a, const value<BitsB> &b) {
+ return value<BitsY> { (bool(a) && bool(b)) ? 1u : 0u };
}
-template<size_t BitsY, size_t BitsA>
-value<BitsY> reduce_and_u(const value<BitsA> &a) {
- return value<BitsY> { a.bit_not().is_zero() ? 1u : 0u };
+template<size_t BitsY, size_t BitsA, size_t BitsB>
+CXXRTL_ALWAYS_INLINE
+value<BitsY> logic_or(const value<BitsA> &a, const value<BitsB> &b) {
+ return value<BitsY> { (bool(a) || bool(b)) ? 1u : 0u };
}
+// Reduction operations
template<size_t BitsY, size_t BitsA>
-value<BitsY> reduce_and_s(const value<BitsA> &a) {
+CXXRTL_ALWAYS_INLINE
+value<BitsY> reduce_and(const value<BitsA> &a) {
return value<BitsY> { a.bit_not().is_zero() ? 1u : 0u };
}
template<size_t BitsY, size_t BitsA>
-value<BitsY> reduce_or_u(const value<BitsA> &a) {
- return value<BitsY> { a ? 1u : 0u };
-}
-
-template<size_t BitsY, size_t BitsA>
-value<BitsY> reduce_or_s(const value<BitsA> &a) {
+CXXRTL_ALWAYS_INLINE
+value<BitsY> reduce_or(const value<BitsA> &a) {
return value<BitsY> { a ? 1u : 0u };
}
template<size_t BitsY, size_t BitsA>
-value<BitsY> reduce_xor_u(const value<BitsA> &a) {
- return value<BitsY> { (a.ctpop() % 2) ? 1u : 0u };
-}
-
-template<size_t BitsY, size_t BitsA>
-value<BitsY> reduce_xor_s(const value<BitsA> &a) {
+CXXRTL_ALWAYS_INLINE
+value<BitsY> reduce_xor(const value<BitsA> &a) {
return value<BitsY> { (a.ctpop() % 2) ? 1u : 0u };
}
template<size_t BitsY, size_t BitsA>
-value<BitsY> reduce_xnor_u(const value<BitsA> &a) {
+CXXRTL_ALWAYS_INLINE
+value<BitsY> reduce_xnor(const value<BitsA> &a) {
return value<BitsY> { (a.ctpop() % 2) ? 0u : 1u };
}
template<size_t BitsY, size_t BitsA>
-value<BitsY> reduce_xnor_s(const value<BitsA> &a) {
- return value<BitsY> { (a.ctpop() % 2) ? 0u : 1u };
+CXXRTL_ALWAYS_INLINE
+value<BitsY> reduce_bool(const value<BitsA> &a) {
+ return value<BitsY> { a ? 1u : 0u };
}
+// Bitwise operations
template<size_t BitsY, size_t BitsA>
-value<BitsY> reduce_bool_u(const value<BitsA> &a) {
- return value<BitsY> { a ? 1u : 0u };
+CXXRTL_ALWAYS_INLINE
+value<BitsY> not_u(const value<BitsA> &a) {
+ return a.template zcast<BitsY>().bit_not();
}
template<size_t BitsY, size_t BitsA>
-value<BitsY> reduce_bool_s(const value<BitsA> &a) {
- return value<BitsY> { a ? 1u : 0u };
+CXXRTL_ALWAYS_INLINE
+value<BitsY> not_s(const value<BitsA> &a) {
+ return a.template scast<BitsY>().bit_not();
}
template<size_t BitsY, size_t BitsA, size_t BitsB>
+CXXRTL_ALWAYS_INLINE
value<BitsY> and_uu(const value<BitsA> &a, const value<BitsB> &b) {
return a.template zcast<BitsY>().bit_and(b.template zcast<BitsY>());
}
template<size_t BitsY, size_t BitsA, size_t BitsB>
+CXXRTL_ALWAYS_INLINE
value<BitsY> and_ss(const value<BitsA> &a, const value<BitsB> &b) {
return a.template scast<BitsY>().bit_and(b.template scast<BitsY>());
}
template<size_t BitsY, size_t BitsA, size_t BitsB>
+CXXRTL_ALWAYS_INLINE
value<BitsY> or_uu(const value<BitsA> &a, const value<BitsB> &b) {
return a.template zcast<BitsY>().bit_or(b.template zcast<BitsY>());
}
template<size_t BitsY, size_t BitsA, size_t BitsB>
+CXXRTL_ALWAYS_INLINE
value<BitsY> or_ss(const value<BitsA> &a, const value<BitsB> &b) {
return a.template scast<BitsY>().bit_or(b.template scast<BitsY>());
}
template<size_t BitsY, size_t BitsA, size_t BitsB>
+CXXRTL_ALWAYS_INLINE
value<BitsY> xor_uu(const value<BitsA> &a, const value<BitsB> &b) {
return a.template zcast<BitsY>().bit_xor(b.template zcast<BitsY>());
}
template<size_t BitsY, size_t BitsA, size_t BitsB>
+CXXRTL_ALWAYS_INLINE
value<BitsY> xor_ss(const value<BitsA> &a, const value<BitsB> &b) {
return a.template scast<BitsY>().bit_xor(b.template scast<BitsY>());
}
template<size_t BitsY, size_t BitsA, size_t BitsB>
+CXXRTL_ALWAYS_INLINE
value<BitsY> xnor_uu(const value<BitsA> &a, const value<BitsB> &b) {
return a.template zcast<BitsY>().bit_xor(b.template zcast<BitsY>()).bit_not();
}
template<size_t BitsY, size_t BitsA, size_t BitsB>
+CXXRTL_ALWAYS_INLINE
value<BitsY> xnor_ss(const value<BitsA> &a, const value<BitsB> &b) {
return a.template scast<BitsY>().bit_xor(b.template scast<BitsY>()).bit_not();
}
template<size_t BitsY, size_t BitsA, size_t BitsB>
-value<BitsY> logic_and_uu(const value<BitsA> &a, const value<BitsB> &b) {
- return value<BitsY> { (bool(a) & bool(b)) ? 1u : 0u };
-}
-
-template<size_t BitsY, size_t BitsA, size_t BitsB>
-value<BitsY> logic_and_ss(const value<BitsA> &a, const value<BitsB> &b) {
- return value<BitsY> { (bool(a) & bool(b)) ? 1u : 0u };
-}
-
-template<size_t BitsY, size_t BitsA, size_t BitsB>
-value<BitsY> logic_or_uu(const value<BitsA> &a, const value<BitsB> &b) {
- return value<BitsY> { (bool(a) | bool(b)) ? 1u : 0u };
-}
-
-template<size_t BitsY, size_t BitsA, size_t BitsB>
-value<BitsY> logic_or_ss(const value<BitsA> &a, const value<BitsB> &b) {
- return value<BitsY> { (bool(a) | bool(b)) ? 1u : 0u };
-}
-
-template<size_t BitsY, size_t BitsA, size_t BitsB>
+CXXRTL_ALWAYS_INLINE
value<BitsY> shl_uu(const value<BitsA> &a, const value<BitsB> &b) {
return a.template zcast<BitsY>().template shl(b);
}
template<size_t BitsY, size_t BitsA, size_t BitsB>
+CXXRTL_ALWAYS_INLINE
value<BitsY> shl_su(const value<BitsA> &a, const value<BitsB> &b) {
return a.template scast<BitsY>().template shl(b);
}
template<size_t BitsY, size_t BitsA, size_t BitsB>
+CXXRTL_ALWAYS_INLINE
value<BitsY> sshl_uu(const value<BitsA> &a, const value<BitsB> &b) {
return a.template zcast<BitsY>().template shl(b);
}
template<size_t BitsY, size_t BitsA, size_t BitsB>
+CXXRTL_ALWAYS_INLINE
value<BitsY> sshl_su(const value<BitsA> &a, const value<BitsB> &b) {
return a.template scast<BitsY>().template shl(b);
}
template<size_t BitsY, size_t BitsA, size_t BitsB>
+CXXRTL_ALWAYS_INLINE
value<BitsY> shr_uu(const value<BitsA> &a, const value<BitsB> &b) {
return a.template shr(b).template zcast<BitsY>();
}
template<size_t BitsY, size_t BitsA, size_t BitsB>
+CXXRTL_ALWAYS_INLINE
value<BitsY> shr_su(const value<BitsA> &a, const value<BitsB> &b) {
return a.template shr(b).template scast<BitsY>();
}
template<size_t BitsY, size_t BitsA, size_t BitsB>
+CXXRTL_ALWAYS_INLINE
value<BitsY> sshr_uu(const value<BitsA> &a, const value<BitsB> &b) {
return a.template shr(b).template zcast<BitsY>();
}
template<size_t BitsY, size_t BitsA, size_t BitsB>
+CXXRTL_ALWAYS_INLINE
value<BitsY> sshr_su(const value<BitsA> &a, const value<BitsB> &b) {
- return a.template shr(b).template scast<BitsY>();
+ return a.template sshr(b).template scast<BitsY>();
}
template<size_t BitsY, size_t BitsA, size_t BitsB>
+CXXRTL_ALWAYS_INLINE
value<BitsY> shift_uu(const value<BitsA> &a, const value<BitsB> &b) {
return shr_uu<BitsY>(a, b);
}
template<size_t BitsY, size_t BitsA, size_t BitsB>
+CXXRTL_ALWAYS_INLINE
value<BitsY> shift_su(const value<BitsA> &a, const value<BitsB> &b) {
return shr_su<BitsY>(a, b);
}
template<size_t BitsY, size_t BitsA, size_t BitsB>
+CXXRTL_ALWAYS_INLINE
value<BitsY> shift_us(const value<BitsA> &a, const value<BitsB> &b) {
return b.is_neg() ? shl_uu<BitsY>(a, b.template sext<BitsB + 1>().neg()) : shr_uu<BitsY>(a, b);
}
template<size_t BitsY, size_t BitsA, size_t BitsB>
+CXXRTL_ALWAYS_INLINE
value<BitsY> shift_ss(const value<BitsA> &a, const value<BitsB> &b) {
return b.is_neg() ? shl_su<BitsY>(a, b.template sext<BitsB + 1>().neg()) : shr_su<BitsY>(a, b);
}
template<size_t BitsY, size_t BitsA, size_t BitsB>
+CXXRTL_ALWAYS_INLINE
value<BitsY> shiftx_uu(const value<BitsA> &a, const value<BitsB> &b) {
return shift_uu<BitsY>(a, b);
}
template<size_t BitsY, size_t BitsA, size_t BitsB>
+CXXRTL_ALWAYS_INLINE
value<BitsY> shiftx_su(const value<BitsA> &a, const value<BitsB> &b) {
return shift_su<BitsY>(a, b);
}
template<size_t BitsY, size_t BitsA, size_t BitsB>
+CXXRTL_ALWAYS_INLINE
value<BitsY> shiftx_us(const value<BitsA> &a, const value<BitsB> &b) {
return shift_us<BitsY>(a, b);
}
template<size_t BitsY, size_t BitsA, size_t BitsB>
+CXXRTL_ALWAYS_INLINE
value<BitsY> shiftx_ss(const value<BitsA> &a, const value<BitsB> &b) {
return shift_ss<BitsY>(a, b);
}
// Comparison operations
template<size_t BitsY, size_t BitsA, size_t BitsB>
+CXXRTL_ALWAYS_INLINE
value<BitsY> eq_uu(const value<BitsA> &a, const value<BitsB> &b) {
constexpr size_t BitsExt = max(BitsA, BitsB);
return value<BitsY>{ a.template zext<BitsExt>() == b.template zext<BitsExt>() ? 1u : 0u };
}
template<size_t BitsY, size_t BitsA, size_t BitsB>
+CXXRTL_ALWAYS_INLINE
value<BitsY> eq_ss(const value<BitsA> &a, const value<BitsB> &b) {
constexpr size_t BitsExt = max(BitsA, BitsB);
return value<BitsY>{ a.template sext<BitsExt>() == b.template sext<BitsExt>() ? 1u : 0u };
}
template<size_t BitsY, size_t BitsA, size_t BitsB>
+CXXRTL_ALWAYS_INLINE
value<BitsY> ne_uu(const value<BitsA> &a, const value<BitsB> &b) {
constexpr size_t BitsExt = max(BitsA, BitsB);
return value<BitsY>{ a.template zext<BitsExt>() != b.template zext<BitsExt>() ? 1u : 0u };
}
template<size_t BitsY, size_t BitsA, size_t BitsB>
+CXXRTL_ALWAYS_INLINE
value<BitsY> ne_ss(const value<BitsA> &a, const value<BitsB> &b) {
constexpr size_t BitsExt = max(BitsA, BitsB);
return value<BitsY>{ a.template sext<BitsExt>() != b.template sext<BitsExt>() ? 1u : 0u };
}
template<size_t BitsY, size_t BitsA, size_t BitsB>
+CXXRTL_ALWAYS_INLINE
value<BitsY> eqx_uu(const value<BitsA> &a, const value<BitsB> &b) {
return eq_uu<BitsY>(a, b);
}
template<size_t BitsY, size_t BitsA, size_t BitsB>
+CXXRTL_ALWAYS_INLINE
value<BitsY> eqx_ss(const value<BitsA> &a, const value<BitsB> &b) {
return eq_ss<BitsY>(a, b);
}
template<size_t BitsY, size_t BitsA, size_t BitsB>
+CXXRTL_ALWAYS_INLINE
value<BitsY> nex_uu(const value<BitsA> &a, const value<BitsB> &b) {
return ne_uu<BitsY>(a, b);
}
template<size_t BitsY, size_t BitsA, size_t BitsB>
+CXXRTL_ALWAYS_INLINE
value<BitsY> nex_ss(const value<BitsA> &a, const value<BitsB> &b) {
return ne_ss<BitsY>(a, b);
}
template<size_t BitsY, size_t BitsA, size_t BitsB>
+CXXRTL_ALWAYS_INLINE
value<BitsY> gt_uu(const value<BitsA> &a, const value<BitsB> &b) {
constexpr size_t BitsExt = max(BitsA, BitsB);
return value<BitsY> { b.template zext<BitsExt>().ucmp(a.template zext<BitsExt>()) ? 1u : 0u };
}
template<size_t BitsY, size_t BitsA, size_t BitsB>
+CXXRTL_ALWAYS_INLINE
value<BitsY> gt_ss(const value<BitsA> &a, const value<BitsB> &b) {
constexpr size_t BitsExt = max(BitsA, BitsB);
return value<BitsY> { b.template sext<BitsExt>().scmp(a.template sext<BitsExt>()) ? 1u : 0u };
}
template<size_t BitsY, size_t BitsA, size_t BitsB>
+CXXRTL_ALWAYS_INLINE
value<BitsY> ge_uu(const value<BitsA> &a, const value<BitsB> &b) {
constexpr size_t BitsExt = max(BitsA, BitsB);
return value<BitsY> { !a.template zext<BitsExt>().ucmp(b.template zext<BitsExt>()) ? 1u : 0u };
}
template<size_t BitsY, size_t BitsA, size_t BitsB>
+CXXRTL_ALWAYS_INLINE
value<BitsY> ge_ss(const value<BitsA> &a, const value<BitsB> &b) {
constexpr size_t BitsExt = max(BitsA, BitsB);
return value<BitsY> { !a.template sext<BitsExt>().scmp(b.template sext<BitsExt>()) ? 1u : 0u };
}
template<size_t BitsY, size_t BitsA, size_t BitsB>
+CXXRTL_ALWAYS_INLINE
value<BitsY> lt_uu(const value<BitsA> &a, const value<BitsB> &b) {
constexpr size_t BitsExt = max(BitsA, BitsB);
return value<BitsY> { a.template zext<BitsExt>().ucmp(b.template zext<BitsExt>()) ? 1u : 0u };
}
template<size_t BitsY, size_t BitsA, size_t BitsB>
+CXXRTL_ALWAYS_INLINE
value<BitsY> lt_ss(const value<BitsA> &a, const value<BitsB> &b) {
constexpr size_t BitsExt = max(BitsA, BitsB);
return value<BitsY> { a.template sext<BitsExt>().scmp(b.template sext<BitsExt>()) ? 1u : 0u };
}
template<size_t BitsY, size_t BitsA, size_t BitsB>
+CXXRTL_ALWAYS_INLINE
value<BitsY> le_uu(const value<BitsA> &a, const value<BitsB> &b) {
constexpr size_t BitsExt = max(BitsA, BitsB);
return value<BitsY> { !b.template zext<BitsExt>().ucmp(a.template zext<BitsExt>()) ? 1u : 0u };
}
template<size_t BitsY, size_t BitsA, size_t BitsB>
+CXXRTL_ALWAYS_INLINE
value<BitsY> le_ss(const value<BitsA> &a, const value<BitsB> &b) {
constexpr size_t BitsExt = max(BitsA, BitsB);
return value<BitsY> { !b.template sext<BitsExt>().scmp(a.template sext<BitsExt>()) ? 1u : 0u };
@@ -1059,71 +1316,68 @@ value<BitsY> le_ss(const value<BitsA> &a, const value<BitsB> &b) {
// Arithmetic operations
template<size_t BitsY, size_t BitsA>
+CXXRTL_ALWAYS_INLINE
value<BitsY> pos_u(const value<BitsA> &a) {
return a.template zcast<BitsY>();
}
template<size_t BitsY, size_t BitsA>
+CXXRTL_ALWAYS_INLINE
value<BitsY> pos_s(const value<BitsA> &a) {
return a.template scast<BitsY>();
}
template<size_t BitsY, size_t BitsA>
+CXXRTL_ALWAYS_INLINE
value<BitsY> neg_u(const value<BitsA> &a) {
return a.template zcast<BitsY>().neg();
}
template<size_t BitsY, size_t BitsA>
+CXXRTL_ALWAYS_INLINE
value<BitsY> neg_s(const value<BitsA> &a) {
return a.template scast<BitsY>().neg();
}
template<size_t BitsY, size_t BitsA, size_t BitsB>
+CXXRTL_ALWAYS_INLINE
value<BitsY> add_uu(const value<BitsA> &a, const value<BitsB> &b) {
return a.template zcast<BitsY>().add(b.template zcast<BitsY>());
}
template<size_t BitsY, size_t BitsA, size_t BitsB>
+CXXRTL_ALWAYS_INLINE
value<BitsY> add_ss(const value<BitsA> &a, const value<BitsB> &b) {
return a.template scast<BitsY>().add(b.template scast<BitsY>());
}
template<size_t BitsY, size_t BitsA, size_t BitsB>
+CXXRTL_ALWAYS_INLINE
value<BitsY> sub_uu(const value<BitsA> &a, const value<BitsB> &b) {
return a.template zcast<BitsY>().sub(b.template zcast<BitsY>());
}
template<size_t BitsY, size_t BitsA, size_t BitsB>
+CXXRTL_ALWAYS_INLINE
value<BitsY> sub_ss(const value<BitsA> &a, const value<BitsB> &b) {
return a.template scast<BitsY>().sub(b.template scast<BitsY>());
}
template<size_t BitsY, size_t BitsA, size_t BitsB>
+CXXRTL_ALWAYS_INLINE
value<BitsY> mul_uu(const value<BitsA> &a, const value<BitsB> &b) {
- value<BitsY> product;
- value<BitsY> multiplicand = a.template zcast<BitsY>();
- const value<BitsB> &multiplier = b;
- uint32_t multiplicand_shift = 0;
- for (size_t step = 0; step < BitsB; step++) {
- if (multiplier.bit(step)) {
- multiplicand = multiplicand.shl(value<32> { multiplicand_shift });
- product = product.add(multiplicand);
- multiplicand_shift = 0;
- }
- multiplicand_shift++;
- }
- return product;
+ constexpr size_t BitsM = BitsA >= BitsB ? BitsA : BitsB;
+ return a.template zcast<BitsM>().template mul<BitsY>(b.template zcast<BitsM>());
}
template<size_t BitsY, size_t BitsA, size_t BitsB>
+CXXRTL_ALWAYS_INLINE
value<BitsY> mul_ss(const value<BitsA> &a, const value<BitsB> &b) {
- value<BitsB + 1> ub = b.template sext<BitsB + 1>();
- if (ub.is_neg()) ub = ub.neg();
- value<BitsY> y = mul_uu<BitsY>(a.template scast<BitsY>(), ub);
- return b.is_neg() ? y.neg() : y;
+ return a.template scast<BitsY>().template mul<BitsY>(b.template scast<BitsY>());
}
template<size_t BitsY, size_t BitsA, size_t BitsB>
+CXXRTL_ALWAYS_INLINE
std::pair<value<BitsY>, value<BitsY>> divmod_uu(const value<BitsA> &a, const value<BitsB> &b) {
constexpr size_t Bits = max(BitsY, max(BitsA, BitsB));
value<Bits> quotient;
@@ -1145,6 +1399,7 @@ std::pair<value<BitsY>, value<BitsY>> divmod_uu(const value<BitsA> &a, const val
}
template<size_t BitsY, size_t BitsA, size_t BitsB>
+CXXRTL_ALWAYS_INLINE
std::pair<value<BitsY>, value<BitsY>> divmod_ss(const value<BitsA> &a, const value<BitsB> &b) {
value<BitsA + 1> ua = a.template sext<BitsA + 1>();
value<BitsB + 1> ub = b.template sext<BitsB + 1>();
@@ -1158,21 +1413,25 @@ std::pair<value<BitsY>, value<BitsY>> divmod_ss(const value<BitsA> &a, const val
}
template<size_t BitsY, size_t BitsA, size_t BitsB>
+CXXRTL_ALWAYS_INLINE
value<BitsY> div_uu(const value<BitsA> &a, const value<BitsB> &b) {
return divmod_uu<BitsY>(a, b).first;
}
template<size_t BitsY, size_t BitsA, size_t BitsB>
+CXXRTL_ALWAYS_INLINE
value<BitsY> div_ss(const value<BitsA> &a, const value<BitsB> &b) {
return divmod_ss<BitsY>(a, b).first;
}
template<size_t BitsY, size_t BitsA, size_t BitsB>
+CXXRTL_ALWAYS_INLINE
value<BitsY> mod_uu(const value<BitsA> &a, const value<BitsB> &b) {
return divmod_uu<BitsY>(a, b).second;
}
template<size_t BitsY, size_t BitsA, size_t BitsB>
+CXXRTL_ALWAYS_INLINE
value<BitsY> mod_ss(const value<BitsA> &a, const value<BitsB> &b) {
return divmod_ss<BitsY>(a, b).second;
}
diff --git a/backends/cxxrtl/cxxrtl.cc b/backends/cxxrtl/cxxrtl_backend.cc
index f3ed3f623..5e5ba5ac0 100644
--- a/backends/cxxrtl/cxxrtl.cc
+++ b/backends/cxxrtl/cxxrtl_backend.cc
@@ -171,11 +171,6 @@ struct Scheduler {
}
};
-bool is_input_wire(const RTLIL::Wire *wire)
-{
- return wire->port_input && !wire->port_output;
-}
-
bool is_unary_cell(RTLIL::IdString type)
{
return type.in(
@@ -192,22 +187,29 @@ bool is_binary_cell(RTLIL::IdString type)
ID($add), ID($sub), ID($mul), ID($div), ID($mod));
}
+bool is_extending_cell(RTLIL::IdString type)
+{
+ return !type.in(
+ ID($logic_not), ID($logic_and), ID($logic_or),
+ ID($reduce_and), ID($reduce_or), ID($reduce_xor), ID($reduce_xnor), ID($reduce_bool));
+}
+
bool is_elidable_cell(RTLIL::IdString type)
{
return is_unary_cell(type) || is_binary_cell(type) || type.in(
- ID($mux), ID($concat), ID($slice));
+ ID($mux), ID($concat), ID($slice), ID($pmux));
}
bool is_sync_ff_cell(RTLIL::IdString type)
{
return type.in(
- ID($dff), ID($dffe));
+ ID($dff), ID($dffe), ID($sdff), ID($sdffe), ID($sdffce));
}
bool is_ff_cell(RTLIL::IdString type)
{
return is_sync_ff_cell(type) || type.in(
- ID($adff), ID($dffsr), ID($dlatch), ID($dlatchsr), ID($sr));
+ ID($adff), ID($adffe), ID($dffsr), ID($dffsre), ID($dlatch), ID($adlatch), ID($dlatchsr), ID($sr));
}
bool is_internal_cell(RTLIL::IdString type)
@@ -359,10 +361,10 @@ struct FlowGraph {
//
// eliminating the unnecessary delta cycle. Conceptually, the CELL_SYNC node type is a series of
// connections of the form `connect \lhs \cell.\sync_output`; the right-hand side of these is not
- // as a wire in RTLIL. If it was expressible, then `\cell.\sync_output` would have a sync def,
- // and this node would be an ordinary CONNECT node, with `\lhs` having a comb def. Because it isn't,
- // a special node type is used, the right-hand side does not appear anywhere, and the left-hand
- // side has a comb def.
+ // expressible as a wire in RTLIL. If it was expressible, then `\cell.\sync_output` would have
+ // a sync def, and this node would be an ordinary CONNECT node, with `\lhs` having a comb def.
+ // Because it isn't, a special node type is used, the right-hand side does not appear anywhere,
+ // and the left-hand side has a comb def.
for (auto conn : cell->connections())
if (cell->output(conn.first))
if (is_cxxrtl_sync_port(cell, conn.first)) {
@@ -467,14 +469,16 @@ std::vector<std::string> split_by(const std::string &str, const std::string &sep
std::vector<std::string> result;
size_t prev = 0;
while (true) {
- size_t curr = str.find_first_of(sep, prev + 1);
- if (curr > str.size())
- curr = str.size();
- if (curr > prev + 1)
- result.push_back(str.substr(prev, curr - prev));
- if (curr == str.size())
+ size_t curr = str.find_first_of(sep, prev);
+ if (curr == std::string::npos) {
+ std::string part = str.substr(prev);
+ if (!part.empty()) result.push_back(part);
break;
- prev = curr;
+ } else {
+ std::string part = str.substr(prev, curr - prev);
+ if (!part.empty()) result.push_back(part);
+ prev = curr + 1;
+ }
}
return result;
}
@@ -502,6 +506,15 @@ std::string escape_cxx_string(const std::string &input)
return output;
}
+template<class T>
+std::string get_hdl_name(T *object)
+{
+ if (object->has_attribute(ID::hdlname))
+ return object->get_string_attribute(ID::hdlname);
+ else
+ return object->name.str().substr(1);
+}
+
struct CxxrtlWorker {
bool split_intf = false;
std::string intf_filename;
@@ -509,13 +522,17 @@ struct CxxrtlWorker {
std::ostream *impl_f = nullptr;
std::ostream *intf_f = nullptr;
- bool elide_internal = false;
- bool elide_public = false;
+ bool run_flatten = false;
+ bool run_proc = false;
+
+ bool unbuffer_internal = false;
+ bool unbuffer_public = false;
bool localize_internal = false;
bool localize_public = false;
- bool run_opt_clean_purge = false;
- bool run_proc_flatten = false;
- bool max_opt_level = false;
+ bool elide_internal = false;
+ bool elide_public = false;
+
+ bool debug_info = false;
std::ostringstream f;
std::string indent;
@@ -528,7 +545,10 @@ struct CxxrtlWorker {
dict<const RTLIL::Cell*, pool<const RTLIL::Cell*>> transparent_for;
dict<const RTLIL::Wire*, FlowGraph::Node> elided_wires;
dict<const RTLIL::Module*, std::vector<FlowGraph::Node>> schedule;
+ pool<const RTLIL::Wire*> unbuffered_wires;
pool<const RTLIL::Wire*> localized_wires;
+ dict<const RTLIL::Wire*, const RTLIL::Wire*> debug_alias_wires;
+ dict<const RTLIL::Wire*, RTLIL::Const> debug_const_wires;
dict<const RTLIL::Module*, pool<std::string>> blackbox_specializations;
dict<const RTLIL::Module*, bool> eval_converges;
@@ -765,7 +785,8 @@ struct CxxrtlWorker {
dump_const(chunk.data, chunk.width, chunk.offset);
return false;
} else {
- if (!is_lhs && elided_wires.count(chunk.wire)) {
+ if (elided_wires.count(chunk.wire)) {
+ log_assert(!is_lhs);
const FlowGraph::Node &node = elided_wires[chunk.wire];
switch (node.type) {
case FlowGraph::Node::Type::CONNECT:
@@ -778,7 +799,7 @@ struct CxxrtlWorker {
default:
log_assert(false);
}
- } else if (localized_wires[chunk.wire] || is_input_wire(chunk.wire)) {
+ } else if (unbuffered_wires[chunk.wire]) {
f << mangle(chunk.wire);
} else {
f << mangle(chunk.wire) << (is_lhs ? ".next" : ".curr");
@@ -895,17 +916,19 @@ struct CxxrtlWorker {
{
// Unary cells
if (is_unary_cell(cell->type)) {
- f << cell->type.substr(1) << '_' <<
- (cell->getParam(ID::A_SIGNED).as_bool() ? 's' : 'u') <<
- "<" << cell->getParam(ID::Y_WIDTH).as_int() << ">(";
+ f << cell->type.substr(1);
+ if (is_extending_cell(cell->type))
+ f << '_' << (cell->getParam(ID::A_SIGNED).as_bool() ? 's' : 'u');
+ f << "<" << cell->getParam(ID::Y_WIDTH).as_int() << ">(";
dump_sigspec_rhs(cell->getPort(ID::A));
f << ")";
// Binary cells
} else if (is_binary_cell(cell->type)) {
- f << cell->type.substr(1) << '_' <<
- (cell->getParam(ID::A_SIGNED).as_bool() ? 's' : 'u') <<
- (cell->getParam(ID::B_SIGNED).as_bool() ? 's' : 'u') <<
- "<" << cell->getParam(ID::Y_WIDTH).as_int() << ">(";
+ f << cell->type.substr(1);
+ if (is_extending_cell(cell->type))
+ f << '_' << (cell->getParam(ID::A_SIGNED).as_bool() ? 's' : 'u') <<
+ (cell->getParam(ID::B_SIGNED).as_bool() ? 's' : 'u');
+ f << "<" << cell->getParam(ID::Y_WIDTH).as_int() << ">(";
dump_sigspec_rhs(cell->getPort(ID::A));
f << ", ";
dump_sigspec_rhs(cell->getPort(ID::B));
@@ -919,6 +942,21 @@ struct CxxrtlWorker {
f << " : ";
dump_sigspec_rhs(cell->getPort(ID::A));
f << ")";
+ // Parallel (one-hot) muxes
+ } else if (cell->type == ID($pmux)) {
+ int width = cell->getParam(ID::WIDTH).as_int();
+ int s_width = cell->getParam(ID::S_WIDTH).as_int();
+ for (int part = 0; part < s_width; part++) {
+ f << "(";
+ dump_sigspec_rhs(cell->getPort(ID::S).extract(part));
+ f << " ? ";
+ dump_sigspec_rhs(cell->getPort(ID::B).extract(part * width, width));
+ f << " : ";
+ }
+ dump_sigspec_rhs(cell->getPort(ID::A));
+ for (int part = 0; part < s_width; part++) {
+ f << ")";
+ }
// Concats
} else if (cell->type == ID($concat)) {
dump_sigspec_rhs(cell->getPort(ID::B));
@@ -985,35 +1023,6 @@ struct CxxrtlWorker {
f << " = ";
dump_cell_elided(cell);
f << ";\n";
- // Parallel (one-hot) muxes
- } else if (cell->type == ID($pmux)) {
- int width = cell->getParam(ID::WIDTH).as_int();
- int s_width = cell->getParam(ID::S_WIDTH).as_int();
- bool first = true;
- for (int part = 0; part < s_width; part++) {
- f << (first ? indent : " else ");
- first = false;
- f << "if (";
- dump_sigspec_rhs(cell->getPort(ID::S).extract(part));
- f << ") {\n";
- inc_indent();
- f << indent;
- dump_sigspec_lhs(cell->getPort(ID::Y));
- f << " = ";
- dump_sigspec_rhs(cell->getPort(ID::B).extract(part * width, width));
- f << ";\n";
- dec_indent();
- f << indent << "}";
- }
- f << " else {\n";
- inc_indent();
- f << indent;
- dump_sigspec_lhs(cell->getPort(ID::Y));
- f << " = ";
- dump_sigspec_rhs(cell->getPort(ID::A));
- f << ";\n";
- dec_indent();
- f << indent << "}\n";
// Flip-flops
} else if (is_ff_cell(cell->type)) {
if (cell->hasPort(ID::CLK) && cell->getPort(ID::CLK).is_wire()) {
@@ -1023,7 +1032,7 @@ struct CxxrtlWorker {
f << indent << "if (" << (cell->getParam(ID::CLK_POLARITY).as_bool() ? "posedge_" : "negedge_")
<< mangle(clk_bit) << ") {\n";
inc_indent();
- if (cell->type == ID($dffe)) {
+ if (cell->hasPort(ID::EN)) {
f << indent << "if (";
dump_sigspec_rhs(cell->getPort(ID::EN));
f << " == value<1> {" << cell->getParam(ID::EN_POLARITY).as_bool() << "u}) {\n";
@@ -1034,7 +1043,24 @@ struct CxxrtlWorker {
f << " = ";
dump_sigspec_rhs(cell->getPort(ID::D));
f << ";\n";
- if (cell->type == ID($dffe)) {
+ if (cell->hasPort(ID::EN) && cell->type != ID($sdffce)) {
+ dec_indent();
+ f << indent << "}\n";
+ }
+ if (cell->hasPort(ID::SRST)) {
+ f << indent << "if (";
+ dump_sigspec_rhs(cell->getPort(ID::SRST));
+ f << " == value<1> {" << cell->getParam(ID::SRST_POLARITY).as_bool() << "u}) {\n";
+ inc_indent();
+ f << indent;
+ dump_sigspec_lhs(cell->getPort(ID::Q));
+ f << " = ";
+ dump_const(cell->getParam(ID::SRST_VALUE));
+ f << ";\n";
+ dec_indent();
+ f << indent << "}\n";
+ }
+ if (cell->hasPort(ID::EN) && cell->type == ID($sdffce)) {
dec_indent();
f << indent << "}\n";
}
@@ -1125,31 +1151,33 @@ struct CxxrtlWorker {
f << indent << "if(" << valid_index_temp << ".valid) {\n";
inc_indent();
if (writable_memories[memory]) {
- std::string addr_temp = fresh_temporary();
- f << indent << "const value<" << cell->getPort(ID::ADDR).size() << "> &" << addr_temp << " = ";
- dump_sigspec_rhs(cell->getPort(ID::ADDR));
- f << ";\n";
std::string lhs_temp = fresh_temporary();
f << indent << "value<" << memory->width << "> " << lhs_temp << " = "
<< mangle(memory) << "[" << valid_index_temp << ".index];\n";
std::vector<const RTLIL::Cell*> memwr_cells(transparent_for[cell].begin(), transparent_for[cell].end());
- std::sort(memwr_cells.begin(), memwr_cells.end(),
- [](const RTLIL::Cell *a, const RTLIL::Cell *b) {
- return a->getParam(ID::PRIORITY).as_int() < b->getParam(ID::PRIORITY).as_int();
- });
- for (auto memwr_cell : memwr_cells) {
- f << indent << "if (" << addr_temp << " == ";
- dump_sigspec_rhs(memwr_cell->getPort(ID::ADDR));
- f << ") {\n";
- inc_indent();
- f << indent << lhs_temp << " = " << lhs_temp;
- f << ".update(";
- dump_sigspec_rhs(memwr_cell->getPort(ID::DATA));
- f << ", ";
- dump_sigspec_rhs(memwr_cell->getPort(ID::EN));
- f << ");\n";
- dec_indent();
- f << indent << "}\n";
+ if (!memwr_cells.empty()) {
+ std::string addr_temp = fresh_temporary();
+ f << indent << "const value<" << cell->getPort(ID::ADDR).size() << "> &" << addr_temp << " = ";
+ dump_sigspec_rhs(cell->getPort(ID::ADDR));
+ f << ";\n";
+ std::sort(memwr_cells.begin(), memwr_cells.end(),
+ [](const RTLIL::Cell *a, const RTLIL::Cell *b) {
+ return a->getParam(ID::PRIORITY).as_int() < b->getParam(ID::PRIORITY).as_int();
+ });
+ for (auto memwr_cell : memwr_cells) {
+ f << indent << "if (" << addr_temp << " == ";
+ dump_sigspec_rhs(memwr_cell->getPort(ID::ADDR));
+ f << ") {\n";
+ inc_indent();
+ f << indent << lhs_temp << " = " << lhs_temp;
+ f << ".update(";
+ dump_sigspec_rhs(memwr_cell->getPort(ID::DATA));
+ f << ", ";
+ dump_sigspec_rhs(memwr_cell->getPort(ID::EN));
+ f << ");\n";
+ dec_indent();
+ f << indent << "}\n";
+ }
}
f << indent;
dump_sigspec_lhs(cell->getPort(ID::DATA));
@@ -1411,13 +1439,12 @@ struct CxxrtlWorker {
{
if (elided_wires.count(wire))
return;
- if (localized_wires.count(wire) != is_local_context)
- return;
- if (is_local_context) {
+ if (localized_wires[wire] && is_local_context) {
dump_attrs(wire);
f << indent << "value<" << wire->width << "> " << mangle(wire) << ";\n";
- } else {
+ }
+ if (!localized_wires[wire] && !is_local_context) {
std::string width;
if (wire->module->has_attribute(ID(cxxrtl_blackbox)) && wire->has_attribute(ID(cxxrtl_width))) {
width = wire->get_string_attribute(ID(cxxrtl_width));
@@ -1426,14 +1453,21 @@ struct CxxrtlWorker {
}
dump_attrs(wire);
- f << indent << (is_input_wire(wire) ? "value" : "wire") << "<" << width << "> " << mangle(wire);
+ f << indent;
+ if (wire->port_input && wire->port_output)
+ f << "/*inout*/ ";
+ else if (wire->port_input)
+ f << "/*input*/ ";
+ else if (wire->port_output)
+ f << "/*output*/ ";
+ f << (unbuffered_wires[wire] ? "value" : "wire") << "<" << width << "> " << mangle(wire);
if (wire->has_attribute(ID::init)) {
f << " ";
dump_const_init(wire->attributes.at(ID::init));
}
f << ";\n";
if (edge_wires[wire]) {
- if (is_input_wire(wire)) {
+ if (unbuffered_wires[wire]) {
f << indent << "value<" << width << "> prev_" << mangle(wire);
if (wire->has_attribute(ID::init)) {
f << " ";
@@ -1444,7 +1478,7 @@ struct CxxrtlWorker {
for (auto edge_type : edge_types) {
if (edge_type.first.wire == wire) {
std::string prev, next;
- if (is_input_wire(wire)) {
+ if (unbuffered_wires[wire]) {
prev = "prev_" + mangle(edge_type.first.wire);
next = mangle(edge_type.first.wire);
} else {
@@ -1567,9 +1601,9 @@ struct CxxrtlWorker {
inc_indent();
f << indent << "bool changed = false;\n";
for (auto wire : module->wires()) {
- if (elided_wires.count(wire) || localized_wires.count(wire))
+ if (elided_wires.count(wire))
continue;
- if (is_input_wire(wire)) {
+ if (unbuffered_wires[wire]) {
if (edge_wires[wire])
f << indent << "prev_" << mangle(wire) << " = " << mangle(wire) << ";\n";
continue;
@@ -1594,6 +1628,72 @@ struct CxxrtlWorker {
dec_indent();
}
+ void dump_debug_info_method(RTLIL::Module *module)
+ {
+ size_t count_public_wires = 0;
+ size_t count_const_wires = 0;
+ size_t count_alias_wires = 0;
+ size_t count_member_wires = 0;
+ size_t count_skipped_wires = 0;
+ inc_indent();
+ f << indent << "assert(path.empty() || path[path.size() - 1] == ' ');\n";
+ for (auto wire : module->wires()) {
+ if (wire->name[0] != '\\')
+ continue;
+ if (module->get_bool_attribute(ID(cxxrtl_blackbox)) && (wire->port_id == 0))
+ continue;
+ count_public_wires++;
+ if (debug_const_wires.count(wire)) {
+ // Wire tied to a constant
+ f << indent << "static const value<" << wire->width << "> const_" << mangle(wire) << " = ";
+ dump_const(debug_const_wires[wire]);
+ f << ";\n";
+ f << indent << "items.add(path + " << escape_cxx_string(get_hdl_name(wire));
+ f << ", debug_item(const_" << mangle(wire) << ", ";
+ f << wire->start_offset << "));\n";
+ count_const_wires++;
+ } else if (debug_alias_wires.count(wire)) {
+ // Alias of a member wire
+ f << indent << "items.add(path + " << escape_cxx_string(get_hdl_name(wire));
+ f << ", debug_item(debug_alias(), " << mangle(debug_alias_wires[wire]) << ", ";
+ f << wire->start_offset << "));\n";
+ count_alias_wires++;
+ } else if (!localized_wires.count(wire)) {
+ // Member wire
+ f << indent << "items.add(path + " << escape_cxx_string(get_hdl_name(wire));
+ f << ", debug_item(" << mangle(wire) << ", ";
+ f << wire->start_offset << "));\n";
+ count_member_wires++;
+ } else {
+ count_skipped_wires++;
+ }
+ }
+ if (!module->get_bool_attribute(ID(cxxrtl_blackbox))) {
+ for (auto &memory_it : module->memories) {
+ if (memory_it.first[0] != '\\')
+ continue;
+ f << indent << "items.add(path + " << escape_cxx_string(get_hdl_name(memory_it.second));
+ f << ", debug_item(" << mangle(memory_it.second) << ", ";
+ f << memory_it.second->start_offset << "));\n";
+ }
+ for (auto cell : module->cells()) {
+ if (is_internal_cell(cell->type))
+ continue;
+ const char *access = is_cxxrtl_blackbox_cell(cell) ? "->" : ".";
+ f << indent << mangle(cell) << access << "debug_info(items, ";
+ f << "path + " << escape_cxx_string(get_hdl_name(cell) + ' ') << ");\n";
+ }
+ }
+ dec_indent();
+
+ log_debug("Debug information statistics for module `%s':\n", log_id(module));
+ log_debug(" Public wires: %zu, of which:\n", count_public_wires);
+ log_debug(" Const wires: %zu\n", count_const_wires);
+ log_debug(" Alias wires: %zu\n", count_alias_wires);
+ log_debug(" Member wires: %zu\n", count_member_wires);
+ log_debug(" Other wires: %zu (no debug information)\n", count_skipped_wires);
+ }
+
void dump_metadata_map(const dict<RTLIL::IdString, RTLIL::Const> &metadata_map)
{
if (metadata_map.empty()) {
@@ -1642,6 +1742,12 @@ struct CxxrtlWorker {
dump_commit_method(module);
f << indent << "}\n";
f << "\n";
+ if (debug_info) {
+ f << indent << "void debug_info(debug_items &items, std::string path = \"\") override {\n";
+ dump_debug_info_method(module);
+ f << indent << "}\n";
+ f << "\n";
+ }
f << indent << "static std::unique_ptr<" << mangle(module);
f << template_params(module, /*is_decl=*/false) << "> ";
f << "create(std::string name, metadata_map parameters, metadata_map attributes);\n";
@@ -1690,7 +1796,7 @@ struct CxxrtlWorker {
if (cell_module->get_bool_attribute(ID(cxxrtl_blackbox))) {
f << indent << "std::unique_ptr<" << mangle(cell_module) << template_args(cell) << "> ";
f << mangle(cell) << " = " << mangle(cell_module) << template_args(cell);
- f << "::create(" << escape_cxx_string(cell->name.str()) << ", ";
+ f << "::create(" << escape_cxx_string(get_hdl_name(cell)) << ", ";
dump_metadata_map(cell->parameters);
f << ", ";
dump_metadata_map(cell->attributes);
@@ -1704,6 +1810,8 @@ struct CxxrtlWorker {
f << "\n";
f << indent << "bool eval() override;\n";
f << indent << "bool commit() override;\n";
+ if (debug_info)
+ f << indent << "void debug_info(debug_items &items, std::string path = \"\") override;\n";
dec_indent();
f << indent << "}; // struct " << mangle(module) << "\n";
f << "\n";
@@ -1722,10 +1830,17 @@ struct CxxrtlWorker {
dump_commit_method(module);
f << indent << "}\n";
f << "\n";
+ if (debug_info) {
+ f << indent << "void " << mangle(module) << "::debug_info(debug_items &items, std::string path) {\n";
+ dump_debug_info_method(module);
+ f << indent << "}\n";
+ f << "\n";
+ }
}
void dump_design(RTLIL::Design *design)
{
+ RTLIL::Module *top_module = nullptr;
std::vector<RTLIL::Module*> modules;
TopoSort<RTLIL::Module*> topo_design;
for (auto module : design->modules()) {
@@ -1735,6 +1850,8 @@ struct CxxrtlWorker {
modules.push_back(module); // cxxrtl blackboxes first
if (module->get_blackbox_attribute() || module->get_bool_attribute(ID(cxxrtl_blackbox)))
continue;
+ if (module->get_bool_attribute(ID::top))
+ top_module = module;
topo_design.node(module);
for (auto cell : module->cells()) {
@@ -1745,7 +1862,8 @@ struct CxxrtlWorker {
topo_design.edge(cell_module, module);
}
}
- log_assert(topo_design.sort());
+ bool no_loops = topo_design.sort();
+ log_assert(no_loops);
modules.insert(modules.end(), topo_design.sorted.begin(), topo_design.sorted.end());
if (split_intf) {
@@ -1756,6 +1874,25 @@ struct CxxrtlWorker {
f << "#ifndef " << include_guard << "\n";
f << "#define " << include_guard << "\n";
f << "\n";
+ if (top_module != nullptr && debug_info) {
+ f << "#include <backends/cxxrtl/cxxrtl_capi.h>\n";
+ f << "\n";
+ f << "#ifdef __cplusplus\n";
+ f << "extern \"C\" {\n";
+ f << "#endif\n";
+ f << "\n";
+ f << "cxxrtl_toplevel " << design_ns << "_create();\n";
+ f << "\n";
+ f << "#ifdef __cplusplus\n";
+ f << "}\n";
+ f << "#endif\n";
+ f << "\n";
+ } else {
+ f << "// The CXXRTL C API is not available because the design is built without debug information.\n";
+ f << "\n";
+ }
+ f << "#ifdef __cplusplus\n";
+ f << "\n";
f << "#include <backends/cxxrtl/cxxrtl.h>\n";
f << "\n";
f << "using namespace cxxrtl;\n";
@@ -1766,6 +1903,8 @@ struct CxxrtlWorker {
dump_module_intf(module);
f << "} // namespace " << design_ns << "\n";
f << "\n";
+ f << "#endif // __cplusplus\n";
+ f << "\n";
f << "#endif\n";
*intf_f << f.str(); f.str("");
}
@@ -1775,6 +1914,15 @@ struct CxxrtlWorker {
else
f << "#include <backends/cxxrtl/cxxrtl.h>\n";
f << "\n";
+ f << "#if defined(CXXRTL_INCLUDE_CAPI_IMPL) || \\\n";
+ f << " defined(CXXRTL_INCLUDE_VCD_CAPI_IMPL)\n";
+ f << "#include <backends/cxxrtl/cxxrtl_capi.cc>\n";
+ f << "#endif\n";
+ f << "\n";
+ f << "#if defined(CXXRTL_INCLUDE_VCD_CAPI_IMPL)\n";
+ f << "#include <backends/cxxrtl/cxxrtl_vcd_capi.cc>\n";
+ f << "#endif\n";
+ f << "\n";
f << "using namespace cxxrtl_yosys;\n";
f << "\n";
f << "namespace " << design_ns << " {\n";
@@ -1785,6 +1933,18 @@ struct CxxrtlWorker {
dump_module_impl(module);
}
f << "} // namespace " << design_ns << "\n";
+ f << "\n";
+ if (top_module != nullptr && debug_info) {
+ f << "cxxrtl_toplevel " << design_ns << "_create() {\n";
+ inc_indent();
+ std::string top_type = design_ns + "::" + mangle(top_module);
+ f << indent << "return new _cxxrtl_toplevel { ";
+ f << "std::unique_ptr<" << top_type << ">(new " + top_type + ")";
+ f << " };\n";
+ dec_indent();
+ f << "}\n";
+ }
+
*impl_f << f.str(); f.str("");
}
@@ -1813,7 +1973,7 @@ struct CxxrtlWorker {
void analyze_design(RTLIL::Design *design)
{
bool has_feedback_arcs = false;
- bool has_buffered_wires = false;
+ bool has_buffered_comb_wires = false;
for (auto module : design->modules()) {
if (!design->selected_module(module))
@@ -1825,6 +1985,8 @@ struct CxxrtlWorker {
if (module->get_bool_attribute(ID(cxxrtl_blackbox))) {
for (auto port : module->ports) {
RTLIL::Wire *wire = module->wire(port);
+ if (wire->port_input && !wire->port_output)
+ unbuffered_wires.insert(wire);
if (wire->has_attribute(ID(cxxrtl_edge))) {
RTLIL::Const edge_attr = wire->attributes[ID(cxxrtl_edge)];
if (!(edge_attr.flags & RTLIL::CONST_FLAG_STRING) || (int)edge_attr.decode_string().size() != GetSize(wire))
@@ -1880,7 +2042,7 @@ struct CxxrtlWorker {
FlowGraph::Node *node = flow.add_node(cell);
// Various DFF cells are treated like posedge/negedge processes, see above for details.
- if (cell->type.in(ID($dff), ID($dffe), ID($adff), ID($dffsr))) {
+ if (cell->type.in(ID($dff), ID($dffe), ID($adff), ID($adffe), ID($dffsr), ID($dffsre), ID($sdff), ID($sdffe), ID($sdffce))) {
if (cell->getPort(ID::CLK).is_wire())
register_edge_signal(sigmap, cell->getPort(ID::CLK),
cell->parameters[ID::CLK_POLARITY].as_bool() ? RTLIL::STp : RTLIL::STn);
@@ -2013,12 +2175,16 @@ struct CxxrtlWorker {
for (auto wire : module->wires()) {
if (feedback_wires[wire]) continue;
- if (wire->port_id != 0) continue;
+ if (wire->port_output && !module->get_bool_attribute(ID::top)) continue;
+ if (wire->name.begins_with("$") && !unbuffer_internal) continue;
+ if (wire->name.begins_with("\\") && !unbuffer_public) continue;
+ if (flow.wire_sync_defs.count(wire) > 0) continue;
+ unbuffered_wires.insert(wire);
+ if (edge_wires[wire]) continue;
if (wire->get_bool_attribute(ID::keep)) continue;
+ if (wire->port_input || wire->port_output) continue;
if (wire->name.begins_with("$") && !localize_internal) continue;
if (wire->name.begins_with("\\") && !localize_public) continue;
- if (edge_wires[wire]) continue;
- if (flow.wire_sync_defs.count(wire) > 0) continue;
localized_wires.insert(wire);
}
@@ -2028,35 +2194,72 @@ struct CxxrtlWorker {
// it is possible that a design with no feedback arcs would end up with doubly buffered wires in such cases
// as a wire with multiple drivers where one of them is combinatorial and the other is synchronous. Such designs
// also require more than one delta cycle to converge.
- pool<const RTLIL::Wire*> buffered_wires;
+ pool<const RTLIL::Wire*> buffered_comb_wires;
for (auto wire : module->wires()) {
- if (flow.wire_comb_defs[wire].size() > 0 && !elided_wires.count(wire) && !localized_wires[wire]) {
- if (!feedback_wires[wire])
- buffered_wires.insert(wire);
- }
+ if (flow.wire_comb_defs[wire].size() > 0 && !unbuffered_wires[wire] && !feedback_wires[wire])
+ buffered_comb_wires.insert(wire);
}
- if (!buffered_wires.empty()) {
- has_buffered_wires = true;
+ if (!buffered_comb_wires.empty()) {
+ has_buffered_comb_wires = true;
log("Module `%s' contains buffered combinatorial wires:\n", log_id(module));
- for (auto wire : buffered_wires)
+ for (auto wire : buffered_comb_wires)
log(" %s\n", log_id(wire));
}
- eval_converges[module] = feedback_wires.empty() && buffered_wires.empty();
+ eval_converges[module] = feedback_wires.empty() && buffered_comb_wires.empty();
+
+ if (debug_info) {
+ // Find wires that alias other wires or are tied to a constant; debug information can be enriched with these
+ // at essentially zero additional cost.
+ //
+ // Note that the information collected here can't be used for optimizing the netlist: debug information queries
+ // are pure and run on a design in a stable state, which allows assumptions that do not otherwise hold.
+ for (auto wire : module->wires()) {
+ if (wire->name[0] != '\\')
+ continue;
+ if (!unbuffered_wires[wire])
+ continue;
+ const RTLIL::Wire *wire_it = wire;
+ while (1) {
+ if (!(flow.wire_def_elidable.count(wire_it) && flow.wire_def_elidable[wire_it]))
+ break; // not an alias: complex def
+ log_assert(flow.wire_comb_defs[wire_it].size() == 1);
+ FlowGraph::Node *node = *flow.wire_comb_defs[wire_it].begin();
+ if (node->type != FlowGraph::Node::Type::CONNECT)
+ break; // not an alias: def by cell
+ RTLIL::SigSpec rhs_sig = node->connect.second;
+ if (rhs_sig.is_wire()) {
+ RTLIL::Wire *rhs_wire = rhs_sig.as_wire();
+ if (unbuffered_wires[rhs_wire]) {
+ wire_it = rhs_wire; // maybe an alias
+ } else {
+ debug_alias_wires[wire] = rhs_wire; // is an alias
+ break;
+ }
+ } else if (rhs_sig.is_fully_const()) {
+ debug_const_wires[wire] = rhs_sig.as_const(); // is a const
+ break;
+ } else {
+ break; // not an alias: complex rhs
+ }
+ }
+ }
+ }
}
- if (has_feedback_arcs || has_buffered_wires) {
+ if (has_feedback_arcs || has_buffered_comb_wires) {
// Although both non-feedback buffered combinatorial wires and apparent feedback wires may be eliminated
- // by optimizing the design, if after `opt_clean -purge` there are any feedback wires remaining, it is very
+ // by optimizing the design, if after `proc; flatten` there are any feedback wires remaining, it is very
// likely that these feedback wires are indicative of a true logic loop, so they get emphasized in the message.
const char *why_pessimistic = nullptr;
if (has_feedback_arcs)
why_pessimistic = "feedback wires";
- else if (has_buffered_wires)
+ else if (has_buffered_comb_wires)
why_pessimistic = "buffered combinatorial wires";
- log("\n");
log_warning("Design contains %s, which require delta cycles during evaluation.\n", why_pessimistic);
- if (!max_opt_level)
- log("Increasing the optimization level may eliminate %s from the design.\n", why_pessimistic);
+ if (!run_flatten)
+ log("Flattening may eliminate %s from the design.\n", why_pessimistic);
+ if (!run_proc)
+ log("Converting processes to netlists may eliminate %s from the design.\n", why_pessimistic);
}
}
@@ -2087,37 +2290,47 @@ struct CxxrtlWorker {
void prepare_design(RTLIL::Design *design)
{
+ bool did_anything = false;
bool has_sync_init, has_packed_mem;
log_push();
check_design(design, has_sync_init, has_packed_mem);
- if (run_proc_flatten) {
- Pass::call(design, "proc");
+ if (run_flatten) {
Pass::call(design, "flatten");
+ did_anything = true;
+ }
+ if (run_proc) {
+ Pass::call(design, "proc");
+ did_anything = true;
} else if (has_sync_init) {
// We're only interested in proc_init, but it depends on proc_prune and proc_clean, so call those
// in case they weren't already. (This allows `yosys foo.v -o foo.cc` to work.)
Pass::call(design, "proc_prune");
Pass::call(design, "proc_clean");
Pass::call(design, "proc_init");
+ did_anything = true;
}
- if (has_packed_mem)
+ if (has_packed_mem) {
Pass::call(design, "memory_unpack");
+ did_anything = true;
+ }
// Recheck the design if it was modified.
if (has_sync_init || has_packed_mem)
check_design(design, has_sync_init, has_packed_mem);
log_assert(!(has_sync_init || has_packed_mem));
- if (run_opt_clean_purge)
- Pass::call(design, "opt_clean -purge");
log_pop();
+ if (did_anything)
+ log_spacer();
analyze_design(design);
}
};
struct CxxrtlBackend : public Backend {
static const int DEFAULT_OPT_LEVEL = 6;
+ static const int OPT_LEVEL_DEBUG = 4;
+ static const int DEFAULT_DEBUG_LEVEL = 1;
CxxrtlBackend() : Backend("cxxrtl", "convert design to C++ RTL simulation") { }
- void help() YS_OVERRIDE
+ void help() override
{
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
log("\n");
@@ -2136,9 +2349,9 @@ struct CxxrtlBackend : public Backend {
log(" top.step();\n");
log(" while (1) {\n");
log(" /* user logic */\n");
- log(" top.p_clk = value<1> {0u};\n");
+ log(" top.p_clk.set(false);\n");
log(" top.step();\n");
- log(" top.p_clk = value<1> {1u};\n");
+ log(" top.p_clk.set(true);\n");
log(" top.step();\n");
log(" }\n");
log(" }\n");
@@ -2285,6 +2498,17 @@ struct CxxrtlBackend : public Backend {
log(" place the generated code into namespace <ns-name>. if not specified,\n");
log(" \"cxxrtl_design\" is used.\n");
log("\n");
+ log(" -noflatten\n");
+ log(" don't flatten the design. fully flattened designs can evaluate within\n");
+ log(" one delta cycle if they have no combinatorial feedback.\n");
+ log(" note that the debug interface and waveform dumps use full hierarchical\n");
+ log(" names for all wires even in flattened designs.\n");
+ log("\n");
+ log(" -noproc\n");
+ log(" don't convert processes to netlists. in most designs, converting\n");
+ log(" processes significantly improves evaluation performance at the cost of\n");
+ log(" slight increase in compilation time.\n");
+ log("\n");
log(" -O <level>\n");
log(" set the optimization level. the default is -O%d. higher optimization\n", DEFAULT_OPT_LEVEL);
log(" levels dramatically decrease compile and run time, and highest level\n");
@@ -2294,27 +2518,46 @@ struct CxxrtlBackend : public Backend {
log(" no optimization.\n");
log("\n");
log(" -O1\n");
- log(" elide internal wires if possible.\n");
+ log(" localize internal wires if possible.\n");
log("\n");
log(" -O2\n");
- log(" like -O1, and localize internal wires if possible.\n");
+ log(" like -O1, and unbuffer internal wires if possible.\n");
log("\n");
log(" -O3\n");
- log(" like -O2, and elide public wires not marked (*keep*) if possible.\n");
+ log(" like -O2, and elide internal wires if possible.\n");
log("\n");
log(" -O4\n");
- log(" like -O3, and localize public wires not marked (*keep*) if possible.\n");
+ log(" like -O3, and unbuffer public wires not marked (*keep*) if possible.\n");
log("\n");
log(" -O5\n");
- log(" like -O4, and run `opt_clean -purge` first.\n");
+ log(" like -O4, and localize public wires not marked (*keep*) if possible.\n");
log("\n");
log(" -O6\n");
- log(" like -O5, and run `proc; flatten` first.\n");
+ log(" like -O5, and elide public wires not marked (*keep*) if possible.\n");
+ log("\n");
+ log(" -Og\n");
+ log(" highest optimization level that provides debug information for all\n");
+ log(" public wires. currently, alias for -O%d.\n", OPT_LEVEL_DEBUG);
+ log("\n");
+ log(" -g <level>\n");
+ log(" set the debug level. the default is -g%d. higher debug levels provide\n", DEFAULT_DEBUG_LEVEL);
+ log(" more visibility and generate more code, but do not pessimize evaluation.\n");
+ log("\n");
+ log(" -g0\n");
+ log(" no debug information.\n");
+ log("\n");
+ log(" -g1\n");
+ log(" debug information for non-optimized public wires. this also makes it\n");
+ log(" possible to use the C API.\n");
log("\n");
}
- void execute(std::ostream *&f, std::string filename, std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
+
+ void execute(std::ostream *&f, std::string filename, std::vector<std::string> args, RTLIL::Design *design) override
{
+ bool noflatten = false;
+ bool noproc = false;
int opt_level = DEFAULT_OPT_LEVEL;
+ int debug_level = DEFAULT_DEBUG_LEVEL;
CxxrtlWorker worker;
log_header(design, "Executing CXXRTL backend.\n");
@@ -2322,6 +2565,23 @@ struct CxxrtlBackend : public Backend {
size_t argidx;
for (argidx = 1; argidx < args.size(); argidx++)
{
+ if (args[argidx] == "-noflatten") {
+ noflatten = true;
+ continue;
+ }
+ if (args[argidx] == "-noproc") {
+ noproc = true;
+ continue;
+ }
+ if (args[argidx] == "-Og") {
+ opt_level = OPT_LEVEL_DEBUG;
+ continue;
+ }
+ if (args[argidx] == "-O" && argidx+1 < args.size() && args[argidx+1] == "g") {
+ argidx++;
+ opt_level = OPT_LEVEL_DEBUG;
+ continue;
+ }
if (args[argidx] == "-O" && argidx+1 < args.size()) {
opt_level = std::stoi(args[++argidx]);
continue;
@@ -2330,6 +2590,14 @@ struct CxxrtlBackend : public Backend {
opt_level = std::stoi(args[argidx].substr(2));
continue;
}
+ if (args[argidx] == "-g" && argidx+1 < args.size()) {
+ debug_level = std::stoi(args[++argidx]);
+ continue;
+ }
+ if (args[argidx].substr(0, 2) == "-g" && args[argidx].size() == 3 && isdigit(args[argidx][2])) {
+ debug_level = std::stoi(args[argidx].substr(2));
+ continue;
+ }
if (args[argidx] == "-header") {
worker.split_intf = true;
continue;
@@ -2342,31 +2610,43 @@ struct CxxrtlBackend : public Backend {
}
extra_args(f, filename, args, argidx);
+ worker.run_flatten = !noflatten;
+ worker.run_proc = !noproc;
switch (opt_level) {
+ // the highest level here must match DEFAULT_OPT_LEVEL
case 6:
- worker.max_opt_level = true;
- worker.run_proc_flatten = true;
+ worker.elide_public = true;
YS_FALLTHROUGH
case 5:
- worker.run_opt_clean_purge = true;
+ worker.localize_public = true;
YS_FALLTHROUGH
case 4:
- worker.localize_public = true;
+ worker.unbuffer_public = true;
YS_FALLTHROUGH
case 3:
- worker.elide_public = true;
+ worker.elide_internal = true;
YS_FALLTHROUGH
case 2:
worker.localize_internal = true;
YS_FALLTHROUGH
case 1:
- worker.elide_internal = true;
+ worker.unbuffer_internal = true;
YS_FALLTHROUGH
case 0:
break;
default:
log_cmd_error("Invalid optimization level %d.\n", opt_level);
}
+ switch (debug_level) {
+ // the highest level here must match DEFAULT_DEBUG_LEVEL
+ case 1:
+ worker.debug_info = true;
+ YS_FALLTHROUGH
+ case 0:
+ break;
+ default:
+ log_cmd_error("Invalid debug information level %d.\n", debug_level);
+ }
std::ofstream intf_f;
if (worker.split_intf) {
diff --git a/backends/cxxrtl/cxxrtl_capi.cc b/backends/cxxrtl/cxxrtl_capi.cc
new file mode 100644
index 000000000..e0566e152
--- /dev/null
+++ b/backends/cxxrtl/cxxrtl_capi.cc
@@ -0,0 +1,63 @@
+/*
+ * yosys -- Yosys Open SYnthesis Suite
+ *
+ * Copyright (C) 2020 whitequark <whitequark@whitequark.org>
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ */
+
+// This file is a part of the CXXRTL C API. It should be used together with `cxxrtl_capi.h`.
+
+#include <backends/cxxrtl/cxxrtl.h>
+#include <backends/cxxrtl/cxxrtl_capi.h>
+
+struct _cxxrtl_handle {
+ std::unique_ptr<cxxrtl::module> module;
+ cxxrtl::debug_items objects;
+};
+
+// Private function for use by other units of the C API.
+const cxxrtl::debug_items &cxxrtl_debug_items_from_handle(cxxrtl_handle handle) {
+ return handle->objects;
+}
+
+cxxrtl_handle cxxrtl_create(cxxrtl_toplevel design) {
+ cxxrtl_handle handle = new _cxxrtl_handle;
+ handle->module = std::move(design->module);
+ handle->module->debug_info(handle->objects);
+ delete design;
+ return handle;
+}
+
+void cxxrtl_destroy(cxxrtl_handle handle) {
+ delete handle;
+}
+
+size_t cxxrtl_step(cxxrtl_handle handle) {
+ return handle->module->step();
+}
+
+struct cxxrtl_object *cxxrtl_get_parts(cxxrtl_handle handle, const char *name, size_t *parts) {
+ auto it = handle->objects.table.find(name);
+ if (it == handle->objects.table.end())
+ return nullptr;
+ *parts = it->second.size();
+ return static_cast<cxxrtl_object*>(&it->second[0]);
+}
+
+void cxxrtl_enum(cxxrtl_handle handle, void *data,
+ void (*callback)(void *data, const char *name,
+ cxxrtl_object *object, size_t parts)) {
+ for (auto &it : handle->objects.table)
+ callback(data, it.first.c_str(), static_cast<cxxrtl_object*>(&it.second[0]), it.second.size());
+}
diff --git a/backends/cxxrtl/cxxrtl_capi.h b/backends/cxxrtl/cxxrtl_capi.h
new file mode 100644
index 000000000..599284898
--- /dev/null
+++ b/backends/cxxrtl/cxxrtl_capi.h
@@ -0,0 +1,185 @@
+/*
+ * yosys -- Yosys Open SYnthesis Suite
+ *
+ * Copyright (C) 2020 whitequark <whitequark@whitequark.org>
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ */
+
+#ifndef CXXRTL_CAPI_H
+#define CXXRTL_CAPI_H
+
+// This file is a part of the CXXRTL C API. It should be used together with `cxxrtl_capi.cc`.
+//
+// The CXXRTL C API makes it possible to drive CXXRTL designs using C or any other language that
+// supports the C ABI, for example, Python. It does not provide a way to implement black boxes.
+
+#include <stddef.h>
+#include <stdint.h>
+#include <assert.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+// Opaque reference to a design toplevel.
+//
+// A design toplevel can only be used to create a design handle.
+typedef struct _cxxrtl_toplevel *cxxrtl_toplevel;
+
+// The constructor for a design toplevel is provided as a part of generated code for that design.
+// Its prototype matches:
+//
+// cxxrtl_toplevel <design-name>_create();
+
+// Opaque reference to a design handle.
+//
+// A design handle is required by all operations in the C API.
+typedef struct _cxxrtl_handle *cxxrtl_handle;
+
+// Create a design handle from a design toplevel.
+//
+// The `design` is consumed by this operation and cannot be used afterwards.
+cxxrtl_handle cxxrtl_create(cxxrtl_toplevel design);
+
+// Release all resources used by a design and its handle.
+void cxxrtl_destroy(cxxrtl_handle handle);
+
+// Simulate the design to a fixed point.
+//
+// Returns the number of delta cycles.
+size_t cxxrtl_step(cxxrtl_handle handle);
+
+// Type of a simulated object.
+enum cxxrtl_type {
+ // Values correspond to singly buffered netlist nodes, i.e. nodes driven exclusively by
+ // combinatorial cells, or toplevel input nodes.
+ //
+ // Values can be inspected via the `curr` pointer. If the `next` pointer is NULL, the value is
+ // driven by a constant and can never be modified. Otherwise, the value can be modified through
+ // the `next` pointer (which is equal to `curr` if not NULL). Note that changes to the bits
+ // driven by combinatorial cells will be ignored.
+ //
+ // Values always have depth 1.
+ CXXRTL_VALUE = 0,
+
+ // Wires correspond to doubly buffered netlist nodes, i.e. nodes driven, at least in part, by
+ // storage cells, or by combinatorial cells that are a part of a feedback path.
+ //
+ // Wires can be inspected via the `curr` pointer and modified via the `next` pointer (which are
+ // distinct for wires). Note that changes to the bits driven by combinatorial cells will be
+ // ignored.
+ //
+ // Wires always have depth 1.
+ CXXRTL_WIRE = 1,
+
+ // Memories correspond to memory cells.
+ //
+ // Memories can be inspected and modified via the `curr` pointer. Due to a limitation of this
+ // API, memories cannot yet be modified in a guaranteed race-free way, and the `next` pointer is
+ // always NULL.
+ CXXRTL_MEMORY = 2,
+
+ // Aliases correspond to netlist nodes driven by another node such that their value is always
+ // exactly equal, or driven by a constant value.
+ //
+ // Aliases can be inspected via the `curr` pointer. They cannot be modified, and the `next`
+ // pointer is always NULL.
+ CXXRTL_ALIAS = 3,
+
+ // More object types may be added in the future, but the existing ones will never change.
+};
+
+// Description of a simulated object.
+//
+// The `data` array can be accessed directly to inspect and, if applicable, modify the bits
+// stored in the object.
+struct cxxrtl_object {
+ // Type of the object.
+ //
+ // All objects have the same memory layout determined by `width` and `depth`, but the type
+ // determines all other properties of the object.
+ uint32_t type; // actually `enum cxxrtl_type`
+
+ // Width of the object in bits.
+ size_t width;
+
+ // Index of the least significant bit.
+ size_t lsb_at;
+
+ // Depth of the object. Only meaningful for memories; for other objects, always 1.
+ size_t depth;
+
+ // Index of the first word. Only meaningful for memories; for other objects, always 0;
+ size_t zero_at;
+
+ // Bits stored in the object, as 32-bit chunks, least significant bits first.
+ //
+ // The width is rounded up to a multiple of 32; the padding bits are always set to 0 by
+ // the simulation code, and must be always written as 0 when modified by user code.
+ // In memories, every element is stored contiguously. Therefore, the total number of chunks
+ // in any object is `((width + 31) / 32) * depth`.
+ //
+ // To allow the simulation to be partitioned into multiple independent units communicating
+ // through wires, the bits are double buffered. To avoid race conditions, user code should
+ // always read from `curr` and write to `next`. The `curr` pointer is always valid; for objects
+ // that cannot be modified, or cannot be modified in a race-free way, `next` is NULL.
+ uint32_t *curr;
+ uint32_t *next;
+
+ // More description fields may be added in the future, but the existing ones will never change.
+};
+
+// Retrieve description of a simulated object.
+//
+// The `name` is the full hierarchical name of the object in the Yosys notation, where public names
+// have a `\` prefix and hierarchy levels are separated by single spaces. For example, if
+// the top-level module instantiates a module `foo`, which in turn contains a wire `bar`, the full
+// hierarchical name is `\foo \bar`.
+//
+// The storage of a single abstract object may be split (usually with the `splitnets` pass) into
+// many physical parts, all of which correspond to the same hierarchical name. To handle such cases,
+// this function returns an array and writes its length to `parts`. The array is sorted by `lsb_at`.
+//
+// Returns the object parts if it was found, NULL otherwise. The returned parts are valid until
+// the design is destroyed.
+struct cxxrtl_object *cxxrtl_get_parts(cxxrtl_handle handle, const char *name, size_t *parts);
+
+// Retrieve description of a single part simulated object.
+//
+// This function is a shortcut for the most common use of `cxxrtl_get_parts`. It asserts that,
+// if the object exists, it consists of a single part. If assertions are disabled, it returns NULL
+// for multi-part objects.
+inline struct cxxrtl_object *cxxrtl_get(cxxrtl_handle handle, const char *name) {
+ size_t parts = 0;
+ struct cxxrtl_object *object = cxxrtl_get_parts(handle, name, &parts);
+ assert(object == NULL || parts == 1);
+ if (object == NULL || parts == 1)
+ return object;
+ return NULL;
+}
+
+// Enumerate simulated objects.
+//
+// For every object in the simulation, `callback` is called with the provided `data`, the full
+// hierarchical name of the object (see `cxxrtl_get` for details), and the object parts.
+// The provided `name` and `object` values are valid until the design is destroyed.
+void cxxrtl_enum(cxxrtl_handle handle, void *data,
+ void (*callback)(void *data, const char *name,
+ struct cxxrtl_object *object, size_t parts));
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/backends/cxxrtl/cxxrtl_vcd.h b/backends/cxxrtl/cxxrtl_vcd.h
new file mode 100644
index 000000000..dbeabbaf2
--- /dev/null
+++ b/backends/cxxrtl/cxxrtl_vcd.h
@@ -0,0 +1,244 @@
+/*
+ * yosys -- Yosys Open SYnthesis Suite
+ *
+ * Copyright (C) 2020 whitequark <whitequark@whitequark.org>
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ */
+
+#ifndef CXXRTL_VCD_H
+#define CXXRTL_VCD_H
+
+#include <backends/cxxrtl/cxxrtl.h>
+
+namespace cxxrtl {
+
+class vcd_writer {
+ struct variable {
+ size_t ident;
+ size_t width;
+ chunk_t *curr;
+ size_t prev_off;
+ };
+
+ std::vector<std::string> current_scope;
+ std::vector<variable> variables;
+ std::vector<chunk_t> cache;
+ std::map<chunk_t*, size_t> aliases;
+ bool streaming = false;
+
+ void emit_timescale(unsigned number, const std::string &unit) {
+ assert(!streaming);
+ assert(number == 1 || number == 10 || number == 100);
+ assert(unit == "s" || unit == "ms" || unit == "us" ||
+ unit == "ns" || unit == "ps" || unit == "fs");
+ buffer += "$timescale " + std::to_string(number) + " " + unit + " $end\n";
+ }
+
+ void emit_scope(const std::vector<std::string> &scope) {
+ assert(!streaming);
+ while (current_scope.size() > scope.size() ||
+ (current_scope.size() > 0 &&
+ current_scope[current_scope.size() - 1] != scope[current_scope.size() - 1])) {
+ buffer += "$upscope $end\n";
+ current_scope.pop_back();
+ }
+ while (current_scope.size() < scope.size()) {
+ buffer += "$scope module " + scope[current_scope.size()] + " $end\n";
+ current_scope.push_back(scope[current_scope.size()]);
+ }
+ }
+
+ void emit_ident(size_t ident) {
+ do {
+ buffer += '!' + ident % 94; // "base94"
+ ident /= 94;
+ } while (ident != 0);
+ }
+
+ void emit_var(const variable &var, const std::string &type, const std::string &name,
+ size_t lsb_at, bool multipart) {
+ assert(!streaming);
+ buffer += "$var " + type + " " + std::to_string(var.width) + " ";
+ emit_ident(var.ident);
+ buffer += " " + name;
+ if (multipart || name.back() == ']' || lsb_at != 0) {
+ if (var.width == 1)
+ buffer += " [" + std::to_string(lsb_at) + "]";
+ else
+ buffer += " [" + std::to_string(lsb_at + var.width - 1) + ":" + std::to_string(lsb_at) + "]";
+ }
+ buffer += " $end\n";
+ }
+
+ void emit_enddefinitions() {
+ assert(!streaming);
+ buffer += "$enddefinitions $end\n";
+ streaming = true;
+ }
+
+ void emit_time(uint64_t timestamp) {
+ assert(streaming);
+ buffer += "#" + std::to_string(timestamp) + "\n";
+ }
+
+ void emit_scalar(const variable &var) {
+ assert(streaming);
+ assert(var.width == 1);
+ buffer += (*var.curr ? '1' : '0');
+ emit_ident(var.ident);
+ buffer += '\n';
+ }
+
+ void emit_vector(const variable &var) {
+ assert(streaming);
+ buffer += 'b';
+ for (size_t bit = var.width - 1; bit != (size_t)-1; bit--) {
+ bool bit_curr = var.curr[bit / (8 * sizeof(chunk_t))] & (1 << (bit % (8 * sizeof(chunk_t))));
+ buffer += (bit_curr ? '1' : '0');
+ }
+ buffer += ' ';
+ emit_ident(var.ident);
+ buffer += '\n';
+ }
+
+ const variable &register_variable(size_t width, chunk_t *curr, bool constant = false) {
+ if (aliases.count(curr)) {
+ return variables[aliases[curr]];
+ } else {
+ const size_t chunks = (width + (sizeof(chunk_t) * 8 - 1)) / (sizeof(chunk_t) * 8);
+ aliases[curr] = variables.size();
+ if (constant) {
+ variables.emplace_back(variable { variables.size(), width, curr, (size_t)-1 });
+ } else {
+ variables.emplace_back(variable { variables.size(), width, curr, cache.size() });
+ cache.insert(cache.end(), &curr[0], &curr[chunks]);
+ }
+ return variables.back();
+ }
+ }
+
+ bool test_variable(const variable &var) {
+ if (var.prev_off == (size_t)-1)
+ return false; // constant
+ const size_t chunks = (var.width + (sizeof(chunk_t) * 8 - 1)) / (sizeof(chunk_t) * 8);
+ if (std::equal(&var.curr[0], &var.curr[chunks], &cache[var.prev_off])) {
+ return false;
+ } else {
+ std::copy(&var.curr[0], &var.curr[chunks], &cache[var.prev_off]);
+ return true;
+ }
+ }
+
+ static std::vector<std::string> split_hierarchy(const std::string &hier_name) {
+ std::vector<std::string> hierarchy;
+ size_t prev = 0;
+ while (true) {
+ size_t curr = hier_name.find_first_of(' ', prev);
+ if (curr == std::string::npos) {
+ hierarchy.push_back(hier_name.substr(prev));
+ break;
+ } else {
+ hierarchy.push_back(hier_name.substr(prev, curr - prev));
+ prev = curr + 1;
+ }
+ }
+ return hierarchy;
+ }
+
+public:
+ std::string buffer;
+
+ void timescale(unsigned number, const std::string &unit) {
+ emit_timescale(number, unit);
+ }
+
+ void add(const std::string &hier_name, const debug_item &item, bool multipart = false) {
+ std::vector<std::string> scope = split_hierarchy(hier_name);
+ std::string name = scope.back();
+ scope.pop_back();
+
+ emit_scope(scope);
+ switch (item.type) {
+ // Not the best naming but oh well...
+ case debug_item::VALUE:
+ emit_var(register_variable(item.width, item.curr, /*constant=*/item.next == nullptr),
+ "wire", name, item.lsb_at, multipart);
+ break;
+ case debug_item::WIRE:
+ emit_var(register_variable(item.width, item.curr),
+ "reg", name, item.lsb_at, multipart);
+ break;
+ case debug_item::MEMORY: {
+ const size_t stride = (item.width + (sizeof(chunk_t) * 8 - 1)) / (sizeof(chunk_t) * 8);
+ for (size_t index = 0; index < item.depth; index++) {
+ chunk_t *nth_curr = &item.curr[stride * index];
+ std::string nth_name = name + '[' + std::to_string(index) + ']';
+ emit_var(register_variable(item.width, nth_curr),
+ "reg", nth_name, item.lsb_at, multipart);
+ }
+ break;
+ }
+ case debug_item::ALIAS:
+ // Like VALUE, but, even though `item.next == nullptr` always holds, the underlying value
+ // can actually change, and must be tracked. In most cases the VCD identifier will be
+ // unified with the aliased reg, but we should handle the case where only the alias is
+ // added to the VCD writer, too.
+ emit_var(register_variable(item.width, item.curr),
+ "wire", name, item.lsb_at, multipart);
+ break;
+ }
+ }
+
+ template<class Filter>
+ void add(const debug_items &items, const Filter &filter) {
+ // `debug_items` is a map, so the items are already sorted in an order optimal for emitting
+ // VCD scope sections.
+ for (auto &it : items.table)
+ for (auto &part : it.second)
+ if (filter(it.first, part))
+ add(it.first, part, it.second.size() > 1);
+ }
+
+ void add(const debug_items &items) {
+ this->template add(items, [](const std::string &, const debug_item &) {
+ return true;
+ });
+ }
+
+ void add_without_memories(const debug_items &items) {
+ this->template add(items, [](const std::string &, const debug_item &item) {
+ return item.type != debug_item::MEMORY;
+ });
+ }
+
+ void sample(uint64_t timestamp) {
+ bool first_sample = !streaming;
+ if (first_sample) {
+ emit_scope({});
+ emit_enddefinitions();
+ }
+ emit_time(timestamp);
+ for (auto var : variables)
+ if (test_variable(var) || first_sample) {
+ if (var.width == 1)
+ emit_scalar(var);
+ else
+ emit_vector(var);
+ }
+ }
+};
+
+}
+
+#endif
diff --git a/backends/cxxrtl/cxxrtl_vcd_capi.cc b/backends/cxxrtl/cxxrtl_vcd_capi.cc
new file mode 100644
index 000000000..52a9198b8
--- /dev/null
+++ b/backends/cxxrtl/cxxrtl_vcd_capi.cc
@@ -0,0 +1,83 @@
+/*
+ * yosys -- Yosys Open SYnthesis Suite
+ *
+ * Copyright (C) 2020 whitequark <whitequark@whitequark.org>
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ */
+
+// This file is a part of the CXXRTL C API. It should be used together with `cxxrtl_vcd_capi.h`.
+
+#include <backends/cxxrtl/cxxrtl_vcd.h>
+#include <backends/cxxrtl/cxxrtl_vcd_capi.h>
+
+extern const cxxrtl::debug_items &cxxrtl_debug_items_from_handle(cxxrtl_handle handle);
+
+struct _cxxrtl_vcd {
+ cxxrtl::vcd_writer writer;
+ bool flush = false;
+};
+
+cxxrtl_vcd cxxrtl_vcd_create() {
+ return new _cxxrtl_vcd;
+}
+
+void cxxrtl_vcd_destroy(cxxrtl_vcd vcd) {
+ delete vcd;
+}
+
+void cxxrtl_vcd_timescale(cxxrtl_vcd vcd, int number, const char *unit) {
+ vcd->writer.timescale(number, unit);
+}
+
+void cxxrtl_vcd_add(cxxrtl_vcd vcd, const char *name, cxxrtl_object *object) {
+ // Note the copy. We don't know whether `object` came from a design (in which case it is
+ // an instance of `debug_item`), or from user code (in which case it is an instance of
+ // `cxxrtl_object`), so casting the pointer wouldn't be safe.
+ vcd->writer.add(name, cxxrtl::debug_item(*object));
+}
+
+void cxxrtl_vcd_add_from(cxxrtl_vcd vcd, cxxrtl_handle handle) {
+ vcd->writer.add(cxxrtl_debug_items_from_handle(handle));
+}
+
+void cxxrtl_vcd_add_from_if(cxxrtl_vcd vcd, cxxrtl_handle handle, void *data,
+ int (*filter)(void *data, const char *name,
+ const cxxrtl_object *object)) {
+ vcd->writer.add(cxxrtl_debug_items_from_handle(handle),
+ [=](const std::string &name, const cxxrtl::debug_item &item) {
+ return filter(data, name.c_str(), static_cast<const cxxrtl_object*>(&item));
+ });
+}
+
+void cxxrtl_vcd_add_from_without_memories(cxxrtl_vcd vcd, cxxrtl_handle handle) {
+ vcd->writer.add_without_memories(cxxrtl_debug_items_from_handle(handle));
+}
+
+void cxxrtl_vcd_sample(cxxrtl_vcd vcd, uint64_t time) {
+ if (vcd->flush) {
+ vcd->writer.buffer.clear();
+ vcd->flush = false;
+ }
+ vcd->writer.sample(time);
+}
+
+void cxxrtl_vcd_read(cxxrtl_vcd vcd, const char **data, size_t *size) {
+ if (vcd->flush) {
+ vcd->writer.buffer.clear();
+ vcd->flush = false;
+ }
+ *data = vcd->writer.buffer.c_str();
+ *size = vcd->writer.buffer.size();
+ vcd->flush = true;
+}
diff --git a/backends/cxxrtl/cxxrtl_vcd_capi.h b/backends/cxxrtl/cxxrtl_vcd_capi.h
new file mode 100644
index 000000000..d55afe223
--- /dev/null
+++ b/backends/cxxrtl/cxxrtl_vcd_capi.h
@@ -0,0 +1,107 @@
+/*
+ * yosys -- Yosys Open SYnthesis Suite
+ *
+ * Copyright (C) 2020 whitequark <whitequark@whitequark.org>
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ */
+
+#ifndef CXXRTL_VCD_CAPI_H
+#define CXXRTL_VCD_CAPI_H
+
+// This file is a part of the CXXRTL C API. It should be used together with `cxxrtl_vcd_capi.cc`.
+//
+// The CXXRTL C API for VCD writing makes it possible to insert virtual probes into designs and
+// dump waveforms to Value Change Dump files.
+
+#include <stddef.h>
+#include <stdint.h>
+
+#include <backends/cxxrtl/cxxrtl_capi.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+// Opaque reference to a VCD writer.
+typedef struct _cxxrtl_vcd *cxxrtl_vcd;
+
+// Create a VCD writer.
+cxxrtl_vcd cxxrtl_vcd_create();
+
+// Release all resources used by a VCD writer.
+void cxxrtl_vcd_destroy(cxxrtl_vcd vcd);
+
+// Set VCD timescale.
+//
+// The `number` must be 1, 10, or 100, and the `unit` must be one of `"s"`, `"ms"`, `"us"`, `"ns"`,
+// `"ps"`, or `"fs"`.
+//
+// Timescale can only be set before the first call to `cxxrtl_vcd_sample`.
+void cxxrtl_vcd_timescale(cxxrtl_vcd vcd, int number, const char *unit);
+
+// Schedule a specific CXXRTL object to be sampled.
+//
+// The `name` is a full hierarchical name as described for `cxxrtl_get`; it does not need to match
+// the original name of `object`, if any. The `object` must outlive the VCD writer, but there are
+// no other requirements; if desired, it can be provided by user code, rather than come from
+// a design.
+//
+// Objects can only be scheduled before the first call to `cxxrtl_vcd_sample`.
+void cxxrtl_vcd_add(cxxrtl_vcd vcd, const char *name, struct cxxrtl_object *object);
+
+// Schedule all CXXRTL objects in a simulation.
+//
+// The design `handle` must outlive the VCD writer.
+//
+// Objects can only be scheduled before the first call to `cxxrtl_vcd_sample`.
+void cxxrtl_vcd_add_from(cxxrtl_vcd vcd, cxxrtl_handle handle);
+
+// Schedule CXXRTL objects in a simulation that match a given predicate.
+//
+// For every object in the simulation, `filter` is called with the provided `data`, the full
+// hierarchical name of the object (see `cxxrtl_get` for details), and the object description.
+// The object will be sampled if the predicate returns a non-zero value.
+//
+// Objects can only be scheduled before the first call to `cxxrtl_vcd_sample`.
+void cxxrtl_vcd_add_from_if(cxxrtl_vcd vcd, cxxrtl_handle handle, void *data,
+ int (*filter)(void *data, const char *name,
+ const struct cxxrtl_object *object));
+
+// Schedule all CXXRTL objects in a simulation except for memories.
+//
+// The design `handle` must outlive the VCD writer.
+//
+// Objects can only be scheduled before the first call to `cxxrtl_vcd_sample`.
+void cxxrtl_vcd_add_from_without_memories(cxxrtl_vcd vcd, cxxrtl_handle handle);
+
+// Sample all scheduled objects.
+//
+// First, `time` is written to the internal buffer. Second, the values of every signal changed since
+// the previous call to `cxxrtl_vcd_sample` (all values if this is the first call) are written to
+// the internal buffer. The contents of the buffer can be retrieved with `cxxrtl_vcd_read`.
+void cxxrtl_vcd_sample(cxxrtl_vcd vcd, uint64_t time);
+
+// Retrieve buffered VCD data.
+//
+// The pointer to the start of the next chunk of VCD data is assigned to `*data`, and the length
+// of that chunk is assigned to `*size`. The pointer to the data is valid until the next call to
+// `cxxrtl_vcd_sample` or `cxxrtl_vcd_read`. Once all of the buffered data has been retrieved,
+// this function will always return zero sized chunks.
+void cxxrtl_vcd_read(cxxrtl_vcd vcd, const char **data, size_t *size);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/backends/edif/edif.cc b/backends/edif/edif.cc
index 7e24468c0..5e6becfd0 100644
--- a/backends/edif/edif.cc
+++ b/backends/edif/edif.cc
@@ -90,7 +90,7 @@ struct EdifNames
struct EdifBackend : public Backend {
EdifBackend() : Backend("edif", "write design to EDIF netlist file") { }
- void help() YS_OVERRIDE
+ void help() override
{
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
log("\n");
@@ -126,7 +126,7 @@ struct EdifBackend : public Backend {
log("is targeted.\n");
log("\n");
}
- void execute(std::ostream *&f, std::string filename, std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
+ void execute(std::ostream *&f, std::string filename, std::vector<std::string> args, RTLIL::Design *design) override
{
log_header(design, "Executing EDIF backend.\n");
std::string top_module_name;
diff --git a/backends/firrtl/firrtl.cc b/backends/firrtl/firrtl.cc
index f6dae1d8c..9739a7a9f 100644
--- a/backends/firrtl/firrtl.cc
+++ b/backends/firrtl/firrtl.cc
@@ -392,7 +392,34 @@ struct FirrtlWorker
return result;
}
- void run()
+ void emit_extmodule()
+ {
+ std::string moduleFileinfo = getFileinfo(module);
+ f << stringf(" extmodule %s: %s\n", make_id(module->name), moduleFileinfo.c_str());
+ vector<std::string> port_decls;
+
+ for (auto wire : module->wires())
+ {
+ const auto wireName = make_id(wire->name);
+ std::string wireFileinfo = getFileinfo(wire);
+
+ if (wire->port_input && wire->port_output)
+ {
+ log_error("Module port %s.%s is inout!\n", log_id(module), log_id(wire));
+ }
+ port_decls.push_back(stringf(" %s %s: UInt<%d> %s\n", wire->port_input ? "input" : "output",
+ wireName, wire->width, wireFileinfo.c_str()));
+ }
+
+ for (auto &str : port_decls)
+ {
+ f << str;
+ }
+
+ f << stringf("\n");
+ }
+
+ void emit_module()
{
std::string moduleFileinfo = getFileinfo(module);
f << stringf(" module %s: %s\n", make_id(module->name), moduleFileinfo.c_str());
@@ -446,7 +473,7 @@ struct FirrtlWorker
string y_id = make_id(cell->name);
std::string cellFileinfo = getFileinfo(cell);
- if (cell->type.in(ID($not), ID($logic_not), ID($neg), ID($reduce_and), ID($reduce_or), ID($reduce_xor), ID($reduce_bool), ID($reduce_xnor)))
+ if (cell->type.in(ID($not), ID($logic_not), ID($_NOT_), ID($neg), ID($reduce_and), ID($reduce_or), ID($reduce_xor), ID($reduce_bool), ID($reduce_xnor)))
{
string a_expr = make_expr(cell->getPort(ID::A));
wire_decls.push_back(stringf(" wire %s: UInt<%d> %s\n", y_id.c_str(), y_width, cellFileinfo.c_str()));
@@ -462,7 +489,7 @@ struct FirrtlWorker
// Assume the FIRRTL width is a single bit.
firrtl_width = 1;
- if (cell->type == ID($not)) primop = "not";
+ if (cell->type.in(ID($not), ID($_NOT_))) primop = "not";
else if (cell->type == ID($neg)) {
primop = "neg";
firrtl_is_signed = true; // Result of "neg" is signed (an SInt).
@@ -494,7 +521,7 @@ struct FirrtlWorker
continue;
}
- if (cell->type.in(ID($add), ID($sub), ID($mul), ID($div), ID($mod), ID($xor), ID($xnor), ID($and), ID($or), ID($eq), ID($eqx),
+ if (cell->type.in(ID($add), ID($sub), ID($mul), ID($div), ID($mod), ID($xor), ID($_XOR_), ID($xnor), ID($and), ID($_AND_), ID($or), ID($_OR_), ID($eq), ID($eqx),
ID($gt), ID($ge), ID($lt), ID($le), ID($ne), ID($nex), ID($shr), ID($sshr), ID($sshl), ID($shl),
ID($logic_and), ID($logic_or), ID($pow)))
{
@@ -524,7 +551,7 @@ struct FirrtlWorker
// For the arithmetic ops, expand operand widths to result widths befor performing the operation.
// This corresponds (according to iverilog) to what verilog compilers implement.
- if (cell->type.in(ID($add), ID($sub), ID($mul), ID($div), ID($mod), ID($xor), ID($xnor), ID($and), ID($or)))
+ if (cell->type.in(ID($add), ID($sub), ID($mul), ID($div), ID($mod), ID($xor), ID($_XOR_), ID($xnor), ID($and), ID($_AND_), ID($or), ID($_OR_)))
{
if (a_width < y_width) {
a_expr = stringf("pad(%s, %d)", a_expr.c_str(), y_width);
@@ -558,19 +585,20 @@ struct FirrtlWorker
firrtl_is_signed = a_signed | b_signed;
firrtl_width = a_width;
} else if (cell->type == ID($mod)) {
+ // "rem" = truncating modulo
primop = "rem";
firrtl_width = min(a_width, b_width);
- } else if (cell->type == ID($and)) {
+ } else if (cell->type.in(ID($and), ID($_AND_))) {
primop = "and";
always_uint = true;
firrtl_width = max(a_width, b_width);
}
- else if (cell->type == ID($or) ) {
+ else if (cell->type.in(ID($or), ID($_OR_))) {
primop = "or";
always_uint = true;
firrtl_width = max(a_width, b_width);
}
- else if (cell->type == ID($xor)) {
+ else if (cell->type.in(ID($xor), ID($_XOR_))) {
primop = "xor";
always_uint = true;
firrtl_width = max(a_width, b_width);
@@ -694,7 +722,8 @@ struct FirrtlWorker
}
}
- if (!cell->parameters.at(ID::B_SIGNED).as_bool()) {
+ auto it = cell->parameters.find(ID::B_SIGNED);
+ if (it == cell->parameters.end() || !it->second.as_bool()) {
b_expr = "asUInt(" + b_expr + ")";
}
@@ -723,9 +752,10 @@ struct FirrtlWorker
continue;
}
- if (cell->type.in(ID($mux)))
+ if (cell->type.in(ID($mux), ID($_MUX_)))
{
- int width = cell->parameters.at(ID::WIDTH).as_int();
+ auto it = cell->parameters.find(ID::WIDTH);
+ int width = it == cell->parameters.end()? 1 : it->second.as_int();
string a_expr = make_expr(cell->getPort(ID::A));
string b_expr = make_expr(cell->getPort(ID::B));
string s_expr = make_expr(cell->getPort(ID::S));
@@ -1076,12 +1106,24 @@ struct FirrtlWorker
for (auto str : wire_exprs)
f << str;
+
+ f << stringf("\n");
+ }
+
+ void run()
+ {
+ // Blackboxes should be emitted as `extmodule`s in firrtl. Only ports are
+ // emitted in such a case.
+ if (module->get_blackbox_attribute())
+ emit_extmodule();
+ else
+ emit_module();
}
};
struct FirrtlBackend : public Backend {
FirrtlBackend() : Backend("firrtl", "write design to a FIRRTL file") { }
- void help() YS_OVERRIDE
+ void help() override
{
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
log("\n");
@@ -1092,7 +1134,7 @@ struct FirrtlBackend : public Backend {
log(" pmuxtree\n");
log("\n");
}
- void execute(std::ostream *&f, std::string filename, std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
+ void execute(std::ostream *&f, std::string filename, std::vector<std::string> args, RTLIL::Design *design) override
{
size_t argidx = args.size(); // We aren't expecting any arguments.
diff --git a/backends/ilang/ilang_backend.cc b/backends/ilang/ilang_backend.cc
index 6e3882d2d..aa5a175ca 100644
--- a/backends/ilang/ilang_backend.cc
+++ b/backends/ilang/ilang_backend.cc
@@ -131,6 +131,8 @@ void ILANG_BACKEND::dump_wire(std::ostream &f, std::string indent, const RTLIL::
f << stringf("output %d ", wire->port_id);
if (wire->port_input && wire->port_output)
f << stringf("inout %d ", wire->port_id);
+ if (wire->is_signed)
+ f << stringf("signed ");
f << stringf("%s\n", wire->name.c_str());
}
@@ -360,9 +362,7 @@ void ILANG_BACKEND::dump_module(std::ostream &f, std::string indent, RTLIL::Modu
void ILANG_BACKEND::dump_design(std::ostream &f, RTLIL::Design *design, bool only_selected, bool flag_m, bool flag_n)
{
-#ifndef NDEBUG
int init_autoidx = autoidx;
-#endif
if (!flag_m) {
int count_selected_mods = 0;
@@ -398,7 +398,7 @@ PRIVATE_NAMESPACE_BEGIN
struct IlangBackend : public Backend {
IlangBackend() : Backend("ilang", "write design to ilang file") { }
- void help() YS_OVERRIDE
+ void help() override
{
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
log("\n");
@@ -411,7 +411,7 @@ struct IlangBackend : public Backend {
log(" only write selected parts of the design.\n");
log("\n");
}
- void execute(std::ostream *&f, std::string filename, std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
+ void execute(std::ostream *&f, std::string filename, std::vector<std::string> args, RTLIL::Design *design) override
{
bool selected = false;
@@ -438,7 +438,7 @@ struct IlangBackend : public Backend {
struct DumpPass : public Pass {
DumpPass() : Pass("dump", "print parts of the design in ilang format") { }
- void help() YS_OVERRIDE
+ void help() override
{
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
log("\n");
@@ -461,7 +461,7 @@ struct DumpPass : public Pass {
log(" like -outfile but append instead of overwrite\n");
log("\n");
}
- void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
+ void execute(std::vector<std::string> args, RTLIL::Design *design) override
{
std::string filename;
bool flag_m = false, flag_n = false, append = false;
diff --git a/backends/intersynth/intersynth.cc b/backends/intersynth/intersynth.cc
index 31dce1cca..98a14173b 100644
--- a/backends/intersynth/intersynth.cc
+++ b/backends/intersynth/intersynth.cc
@@ -46,7 +46,7 @@ static std::string netname(std::set<std::string> &conntypes_code, std::set<std::
struct IntersynthBackend : public Backend {
IntersynthBackend() : Backend("intersynth", "write design to InterSynth netlist file") { }
- void help() YS_OVERRIDE
+ void help() override
{
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
log("\n");
@@ -71,7 +71,7 @@ struct IntersynthBackend : public Backend {
log("http://www.clifford.at/intersynth/\n");
log("\n");
}
- void execute(std::ostream *&f, std::string filename, std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
+ void execute(std::ostream *&f, std::string filename, std::vector<std::string> args, RTLIL::Design *design) override
{
log_header(design, "Executing INTERSYNTH backend.\n");
log_push();
diff --git a/backends/json/json.cc b/backends/json/json.cc
index 1a8b757ef..eeadc1b89 100644
--- a/backends/json/json.cc
+++ b/backends/json/json.cc
@@ -160,6 +160,8 @@ struct JsonWriter
f << stringf(" \"offset\": %d,\n", w->start_offset);
if (w->upto)
f << stringf(" \"upto\": 1,\n");
+ if (w->is_signed)
+ f << stringf(" \"signed\": %d,\n", w->is_signed);
f << stringf(" \"bits\": %s\n", get_bits(w).c_str());
f << stringf(" }");
first = false;
@@ -227,6 +229,8 @@ struct JsonWriter
f << stringf(" \"offset\": %d,\n", w->start_offset);
if (w->upto)
f << stringf(" \"upto\": 1,\n");
+ if (w->is_signed)
+ f << stringf(" \"signed\": %d,\n", w->is_signed);
f << stringf(" \"attributes\": {");
write_parameters(w->attributes);
f << stringf("\n }\n");
@@ -290,7 +294,7 @@ struct JsonWriter
struct JsonBackend : public Backend {
JsonBackend() : Backend("json", "write design to a JSON file") { }
- void help() YS_OVERRIDE
+ void help() override
{
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
log("\n");
@@ -526,7 +530,7 @@ struct JsonBackend : public Backend {
log("format. A program processing this format must ignore all unknown fields.\n");
log("\n");
}
- void execute(std::ostream *&f, std::string filename, std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
+ void execute(std::ostream *&f, std::string filename, std::vector<std::string> args, RTLIL::Design *design) override
{
bool aig_mode = false;
bool compat_int_mode = false;
@@ -555,7 +559,7 @@ struct JsonBackend : public Backend {
struct JsonPass : public Pass {
JsonPass() : Pass("json", "write design in JSON format") { }
- void help() YS_OVERRIDE
+ void help() override
{
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
log("\n");
@@ -576,7 +580,7 @@ struct JsonPass : public Pass {
log("See 'help write_json' for a description of the JSON format used.\n");
log("\n");
}
- void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
+ void execute(std::vector<std::string> args, RTLIL::Design *design) override
{
std::string filename;
bool aig_mode = false;
diff --git a/backends/protobuf/protobuf.cc b/backends/protobuf/protobuf.cc
index 671686173..f6623a382 100644
--- a/backends/protobuf/protobuf.cc
+++ b/backends/protobuf/protobuf.cc
@@ -231,7 +231,7 @@ struct ProtobufDesignSerializer
struct ProtobufBackend : public Backend {
ProtobufBackend(): Backend("protobuf", "write design to a Protocol Buffer file") { }
- void help() YS_OVERRIDE
+ void help() override
{
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
log("\n");
@@ -249,7 +249,7 @@ struct ProtobufBackend : public Backend {
log("Yosys source code distribution.\n");
log("\n");
}
- void execute(std::ostream *&f, std::string filename, std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
+ void execute(std::ostream *&f, std::string filename, std::vector<std::string> args, RTLIL::Design *design) override
{
bool aig_mode = false;
bool text_mode = false;
@@ -286,7 +286,7 @@ struct ProtobufBackend : public Backend {
struct ProtobufPass : public Pass {
ProtobufPass() : Pass("protobuf", "write design in Protobuf format") { }
- void help() YS_OVERRIDE
+ void help() override
{
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
log("\n");
@@ -307,7 +307,7 @@ struct ProtobufPass : public Pass {
log("Yosys source code distribution.\n");
log("\n");
}
- void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
+ void execute(std::vector<std::string> args, RTLIL::Design *design) override
{
std::string filename;
bool aig_mode = false;
diff --git a/backends/simplec/simplec.cc b/backends/simplec/simplec.cc
index 83ed5e6e0..3adeaa6c0 100644
--- a/backends/simplec/simplec.cc
+++ b/backends/simplec/simplec.cc
@@ -744,7 +744,7 @@ struct SimplecWorker
struct SimplecBackend : public Backend {
SimplecBackend() : Backend("simplec", "convert design to simple C code") { }
- void help() YS_OVERRIDE
+ void help() override
{
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
log("\n");
@@ -763,7 +763,7 @@ struct SimplecBackend : public Backend {
log("THIS COMMAND IS UNDER CONSTRUCTION\n");
log("\n");
}
- void execute(std::ostream *&f, std::string filename, std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
+ void execute(std::ostream *&f, std::string filename, std::vector<std::string> args, RTLIL::Design *design) override
{
reserved_cids.clear();
id2cid.clear();
diff --git a/backends/smt2/smt2.cc b/backends/smt2/smt2.cc
index 3e67e55f2..526b36352 100644
--- a/backends/smt2/smt2.cc
+++ b/backends/smt2/smt2.cc
@@ -590,7 +590,17 @@ struct Smt2Worker
if (cell->type == ID($sub)) return export_bvop(cell, "(bvsub A B)");
if (cell->type == ID($mul)) return export_bvop(cell, "(bvmul A B)");
if (cell->type == ID($div)) return export_bvop(cell, "(bvUdiv A B)", 'd');
+ // "rem" = truncating modulo
if (cell->type == ID($mod)) return export_bvop(cell, "(bvUrem A B)", 'd');
+ // "mod" = flooring modulo
+ if (cell->type == ID($modfloor)) {
+ // bvumod doesn't exist because it's the same as bvurem
+ if (cell->getParam(ID::A_SIGNED).as_bool()) {
+ return export_bvop(cell, "(bvsmod A B)", 'd');
+ } else {
+ return export_bvop(cell, "(bvurem A B)", 'd');
+ }
+ }
if (cell->type.in(ID($reduce_and), ID($reduce_or), ID($reduce_bool)) &&
2*GetSize(cell->getPort(ID::A).chunks()) < GetSize(cell->getPort(ID::A))) {
@@ -1270,7 +1280,7 @@ struct Smt2Worker
struct Smt2Backend : public Backend {
Smt2Backend() : Backend("smt2", "write design to SMT-LIBv2 file") { }
- void help() YS_OVERRIDE
+ void help() override
{
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
log("\n");
@@ -1426,7 +1436,7 @@ struct Smt2Backend : public Backend {
log("from non-zero to zero in the test design.\n");
log("\n");
}
- void execute(std::ostream *&f, std::string filename, std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
+ void execute(std::ostream *&f, std::string filename, std::vector<std::string> args, RTLIL::Design *design) override
{
std::ifstream template_f;
bool bvmode = true, memmode = true, wiresmode = false, verbose = false, statebv = false, statedt = false;
diff --git a/backends/smt2/smtbmc.py b/backends/smt2/smtbmc.py
index d3015b066..03f001bfd 100644
--- a/backends/smt2/smtbmc.py
+++ b/backends/smt2/smtbmc.py
@@ -1511,7 +1511,7 @@ else: # not tempind, covermode
smt_assert_consequent(get_constr_expr(constr_assumes, i))
print_msg("Re-solving with appended steps..")
if smt_check_sat() == "unsat":
- print("%s Cannot appended steps without violating assumptions!" % smt.timestamp())
+ print("%s Cannot append steps without violating assumptions!" % smt.timestamp())
retstatus = "FAILED"
break
print_anyconsts(step)
@@ -1548,7 +1548,7 @@ else: # not tempind, covermode
break
smt_pop()
- if not retstatus:
+ if retstatus == "FAILED" or retstatus == "PREUNSAT":
break
else: # gentrace
@@ -1557,8 +1557,9 @@ else: # not tempind, covermode
smt_assert(get_constr_expr(constr_asserts, i))
print_msg("Solving for step %d.." % (last_check_step))
- if smt_check_sat() != "sat":
- print("%s No solution found!" % smt.timestamp())
+ status = smt_check_sat()
+ if status != "sat":
+ print("%s No solution found! (%s)" % (smt.timestamp(), status))
retstatus = "FAILED"
break
@@ -1568,7 +1569,7 @@ else: # not tempind, covermode
step += step_size
- if gentrace and retstatus:
+ if gentrace and retstatus == "PASSED":
print_anyconsts(0)
write_trace(0, num_steps, '%')
diff --git a/backends/smt2/smtio.py b/backends/smt2/smtio.py
index 69f59df79..72ab39d39 100644
--- a/backends/smt2/smtio.py
+++ b/backends/smt2/smtio.py
@@ -39,7 +39,7 @@ if os.name == "posix":
smtio_stacksize = 128 * 1024 * 1024
if os.uname().sysname == "Darwin":
# MacOS has rather conservative stack limits
- smtio_stacksize = 16 * 1024 * 1024
+ smtio_stacksize = 8 * 1024 * 1024
if current_rlimit_stack[1] != resource.RLIM_INFINITY:
smtio_stacksize = min(smtio_stacksize, current_rlimit_stack[1])
if current_rlimit_stack[0] < smtio_stacksize:
@@ -121,6 +121,7 @@ class SmtIo:
self.logic_bv = True
self.logic_dt = False
self.forall = False
+ self.timeout = 0
self.produce_models = True
self.smt2cache = [list()]
self.p = None
@@ -135,6 +136,7 @@ class SmtIo:
self.debug_file = opts.debug_file
self.dummy_file = opts.dummy_file
self.timeinfo = opts.timeinfo
+ self.timeout = opts.timeout
self.unroll = opts.unroll
self.noincr = opts.noincr
self.info_stmts = opts.info_stmts
@@ -147,6 +149,7 @@ class SmtIo:
self.debug_file = None
self.dummy_file = None
self.timeinfo = os.name != "nt"
+ self.timeout = 0
self.unroll = False
self.noincr = False
self.info_stmts = list()
@@ -172,22 +175,32 @@ class SmtIo:
self.unroll = False
if self.solver == "yices":
- if self.noincr:
+ if self.noincr or self.forall:
self.popen_vargs = ['yices-smt2'] + self.solver_opts
else:
self.popen_vargs = ['yices-smt2', '--incremental'] + self.solver_opts
+ if self.timeout != 0:
+ self.popen_vargs.append('-t')
+ self.popen_vargs.append('%d' % self.timeout);
if self.solver == "z3":
self.popen_vargs = ['z3', '-smt2', '-in'] + self.solver_opts
+ if self.timeout != 0:
+ self.popen_vargs.append('-T:%d' % self.timeout);
if self.solver == "cvc4":
if self.noincr:
self.popen_vargs = ['cvc4', '--lang', 'smt2.6' if self.logic_dt else 'smt2'] + self.solver_opts
else:
self.popen_vargs = ['cvc4', '--incremental', '--lang', 'smt2.6' if self.logic_dt else 'smt2'] + self.solver_opts
+ if self.timeout != 0:
+ self.popen_vargs.append('--tlimit=%d000' % self.timeout);
if self.solver == "mathsat":
self.popen_vargs = ['mathsat'] + self.solver_opts
+ if self.timeout != 0:
+ print('timeout option is not supported for mathsat.')
+ sys.exit(1)
if self.solver == "boolector":
if self.noincr:
@@ -195,6 +208,9 @@ class SmtIo:
else:
self.popen_vargs = ['boolector', '--smt2', '-i'] + self.solver_opts
self.unroll = True
+ if self.timeout != 0:
+ print('timeout option is not supported for boolector.')
+ sys.exit(1)
if self.solver == "abc":
if len(self.solver_opts) > 0:
@@ -204,6 +220,9 @@ class SmtIo:
self.logic_ax = False
self.unroll = True
self.noincr = True
+ if self.timeout != 0:
+ print('timeout option is not supported for abc.')
+ sys.exit(1)
if self.solver == "dummy":
assert self.dummy_file is not None
@@ -232,12 +251,16 @@ class SmtIo:
if self.logic_uf: self.logic += "UF"
if self.logic_bv: self.logic += "BV"
if self.logic_dt: self.logic = "ALL"
+ if self.solver == "yices" and self.forall: self.logic = "BV"
self.setup_done = True
for stmt in self.info_stmts:
self.write(stmt)
+ if self.forall and self.solver == "yices":
+ self.write("(set-option :yices-ef-max-iters 1000000000)")
+
if self.produce_models:
self.write("(set-option :produce-models true)")
@@ -706,7 +729,7 @@ class SmtIo:
if self.forall:
result = self.read()
- while result not in ["sat", "unsat", "unknown"]:
+ while result not in ["sat", "unsat", "unknown", "timeout", "interrupted", ""]:
print("%s %s: %s" % (self.timestamp(), self.solver, result))
result = self.read()
else:
@@ -717,7 +740,7 @@ class SmtIo:
print("(check-sat)", file=self.debug_file)
self.debug_file.flush()
- if result not in ["sat", "unsat"]:
+ if result not in ["sat", "unsat", "unknown", "timeout", "interrupted"]:
if result == "":
print("%s Unexpected EOF response from solver." % (self.timestamp()), flush=True)
else:
@@ -927,7 +950,7 @@ class SmtIo:
class SmtOpts:
def __init__(self):
self.shortopts = "s:S:v"
- self.longopts = ["unroll", "noincr", "noprogress", "dump-smt2=", "logic=", "dummy=", "info=", "nocomments"]
+ self.longopts = ["unroll", "noincr", "noprogress", "timeout=", "dump-smt2=", "logic=", "dummy=", "info=", "nocomments"]
self.solver = "yices"
self.solver_opts = list()
self.debug_print = False
@@ -936,6 +959,7 @@ class SmtOpts:
self.unroll = False
self.noincr = False
self.timeinfo = os.name != "nt"
+ self.timeout = 0
self.logic = None
self.info_stmts = list()
self.nocomments = False
@@ -945,6 +969,8 @@ class SmtOpts:
self.solver = a
elif o == "-S":
self.solver_opts.append(a)
+ elif o == "--timeout":
+ self.timeout = int(a)
elif o == "-v":
self.debug_print = True
elif o == "--unroll":
@@ -976,6 +1002,9 @@ class SmtOpts:
-S <opt>
pass <opt> as command line argument to the solver
+ --timeout <value>
+ set the solver timeout to the specified value (in seconds).
+
--logic <smt2_logic>
use the specified SMT2 logic (e.g. QF_AUFBV)
diff --git a/backends/smv/smv.cc b/backends/smv/smv.cc
index 7113ebc97..4e5c6050d 100644
--- a/backends/smv/smv.cc
+++ b/backends/smv/smv.cc
@@ -358,7 +358,8 @@ struct SmvWorker
continue;
}
- if (cell->type.in(ID($div), ID($mod)))
+ // SMV has a "mod" operator, but its semantics don't seem to be well-defined - to be safe, don't generate it at all
+ if (cell->type.in(ID($div)/*, ID($mod), ID($modfloor)*/))
{
int width_y = GetSize(cell->getPort(ID::Y));
int width = max(width_y, GetSize(cell->getPort(ID::A)));
@@ -366,7 +367,7 @@ struct SmvWorker
string expr_a, expr_b, op;
if (cell->type == ID($div)) op = "/";
- if (cell->type == ID($mod)) op = "mod";
+ //if (cell->type == ID($mod)) op = "mod";
if (cell->getParam(ID::A_SIGNED).as_bool())
{
@@ -701,7 +702,7 @@ struct SmvWorker
struct SmvBackend : public Backend {
SmvBackend() : Backend("smv", "write design to SMV file") { }
- void help() YS_OVERRIDE
+ void help() override
{
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
log("\n");
@@ -719,7 +720,7 @@ struct SmvBackend : public Backend {
log("THIS COMMAND IS UNDER CONSTRUCTION\n");
log("\n");
}
- void execute(std::ostream *&f, std::string filename, std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
+ void execute(std::ostream *&f, std::string filename, std::vector<std::string> args, RTLIL::Design *design) override
{
std::ifstream template_f;
bool verbose = false;
diff --git a/backends/smv/test_cells.sh b/backends/smv/test_cells.sh
index 63de465c0..145b9c33b 100644
--- a/backends/smv/test_cells.sh
+++ b/backends/smv/test_cells.sh
@@ -7,8 +7,8 @@ mkdir -p test_cells.tmp
cd test_cells.tmp
# don't test $mul to reduce runtime
-# don't test $div and $mod to reduce runtime and avoid "div by zero" message
-../../../yosys -p 'test_cell -n 5 -w test all /$alu /$fa /$lcu /$lut /$macc /$mul /$div /$mod'
+# don't test $div/$mod/$divfloor/$modfloor to reduce runtime and avoid "div by zero" message
+../../../yosys -p 'test_cell -n 5 -w test all /$alu /$fa /$lcu /$lut /$macc /$mul /$div /$mod /$divfloor /$modfloor'
cat > template.txt << "EOT"
%module main
diff --git a/backends/spice/spice.cc b/backends/spice/spice.cc
index 84e93b61b..aa20f106a 100644
--- a/backends/spice/spice.cc
+++ b/backends/spice/spice.cc
@@ -130,7 +130,7 @@ static void print_spice_module(std::ostream &f, RTLIL::Module *module, RTLIL::De
struct SpiceBackend : public Backend {
SpiceBackend() : Backend("spice", "write design to SPICE netlist file") { }
- void help() YS_OVERRIDE
+ void help() override
{
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
log("\n");
@@ -159,7 +159,7 @@ struct SpiceBackend : public Backend {
log(" set the specified module as design top module\n");
log("\n");
}
- void execute(std::ostream *&f, std::string filename, std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
+ void execute(std::ostream *&f, std::string filename, std::vector<std::string> args, RTLIL::Design *design) override
{
std::string top_module_name;
RTLIL::Module *top_module = NULL;
diff --git a/backends/table/table.cc b/backends/table/table.cc
index 796f18059..77642ccbd 100644
--- a/backends/table/table.cc
+++ b/backends/table/table.cc
@@ -29,7 +29,7 @@ PRIVATE_NAMESPACE_BEGIN
struct TableBackend : public Backend {
TableBackend() : Backend("table", "write design as connectivity table") { }
- void help() YS_OVERRIDE
+ void help() override
{
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
log("\n");
@@ -48,7 +48,7 @@ struct TableBackend : public Backend {
log("module inputs and outputs are output using cell type and port '-' and with\n");
log("'pi' (primary input) or 'po' (primary output) or 'pio' as direction.\n");
}
- void execute(std::ostream *&f, std::string filename, std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
+ void execute(std::ostream *&f, std::string filename, std::vector<std::string> args, RTLIL::Design *design) override
{
log_header(design, "Executing TABLE backend.\n");
diff --git a/backends/verilog/verilog_backend.cc b/backends/verilog/verilog_backend.cc
index 11b2ae10f..cef1dd9df 100644
--- a/backends/verilog/verilog_backend.cc
+++ b/backends/verilog/verilog_backend.cc
@@ -740,6 +740,95 @@ bool dump_cell_expr(std::ostream &f, std::string indent, RTLIL::Cell *cell)
#undef HANDLE_UNIOP
#undef HANDLE_BINOP
+ if (cell->type == ID($divfloor))
+ {
+ // wire [MAXLEN+1:0] _0_, _1_, _2_;
+ // assign _0_ = $signed(A);
+ // assign _1_ = $signed(B);
+ // assign _2_ = (A[-1] == B[-1]) || A == 0 ? _0_ : $signed(_0_ - (B[-1] ? _1_ + 1 : _1_ - 1));
+ // assign Y = $signed(_2_) / $signed(_1_);
+
+ if (cell->getParam(ID::A_SIGNED).as_bool() && cell->getParam(ID::B_SIGNED).as_bool()) {
+ SigSpec sig_a = cell->getPort(ID::A);
+ SigSpec sig_b = cell->getPort(ID::B);
+
+ std::string buf_a = next_auto_id();
+ std::string buf_b = next_auto_id();
+ std::string buf_num = next_auto_id();
+ int size_a = GetSize(sig_a);
+ int size_b = GetSize(sig_b);
+ int size_y = GetSize(cell->getPort(ID::Y));
+ int size_max = std::max(size_a, std::max(size_b, size_y));
+
+ // intentionally one wider than maximum width
+ f << stringf("%s" "wire [%d:0] %s, %s, %s;\n", indent.c_str(), size_max, buf_a.c_str(), buf_b.c_str(), buf_num.c_str());
+ f << stringf("%s" "assign %s = ", indent.c_str(), buf_a.c_str());
+ dump_cell_expr_port(f, cell, "A", true);
+ f << stringf(";\n");
+ f << stringf("%s" "assign %s = ", indent.c_str(), buf_b.c_str());
+ dump_cell_expr_port(f, cell, "B", true);
+ f << stringf(";\n");
+
+ f << stringf("%s" "assign %s = ", indent.c_str(), buf_num.c_str());
+ f << stringf("(");
+ dump_sigspec(f, sig_a.extract(sig_a.size()-1));
+ f << stringf(" == ");
+ dump_sigspec(f, sig_b.extract(sig_b.size()-1));
+ f << stringf(") || ");
+ dump_sigspec(f, sig_a);
+ f << stringf(" == 0 ? %s : ", buf_a.c_str());
+ f << stringf("$signed(%s - (", buf_a.c_str());
+ dump_sigspec(f, sig_b.extract(sig_b.size()-1));
+ f << stringf(" ? %s + 1 : %s - 1));\n", buf_b.c_str(), buf_b.c_str());
+
+
+ f << stringf("%s" "assign ", indent.c_str());
+ dump_sigspec(f, cell->getPort(ID::Y));
+ f << stringf(" = $signed(%s) / ", buf_num.c_str());
+ dump_attributes(f, "", cell->attributes, ' ');
+ f << stringf("$signed(%s);\n", buf_b.c_str());
+ return true;
+ } else {
+ // same as truncating division
+ dump_cell_expr_binop(f, indent, cell, "/");
+ return true;
+ }
+ }
+
+ if (cell->type == ID($modfloor))
+ {
+ // wire truncated = $signed(A) % $signed(B);
+ // assign Y = (A[-1] == B[-1]) || truncated == 0 ? truncated : $signed(B) + $signed(truncated);
+
+ if (cell->getParam(ID::A_SIGNED).as_bool() && cell->getParam(ID::B_SIGNED).as_bool()) {
+ SigSpec sig_a = cell->getPort(ID::A);
+ SigSpec sig_b = cell->getPort(ID::B);
+
+ std::string temp_id = next_auto_id();
+ f << stringf("%s" "wire [%d:0] %s = ", indent.c_str(), GetSize(cell->getPort(ID::A))-1, temp_id.c_str());
+ dump_cell_expr_port(f, cell, "A", true);
+ f << stringf(" %% ");
+ dump_attributes(f, "", cell->attributes, ' ');
+ dump_cell_expr_port(f, cell, "B", true);
+ f << stringf(";\n");
+
+ f << stringf("%s" "assign ", indent.c_str());
+ dump_sigspec(f, cell->getPort(ID::Y));
+ f << stringf(" = (");
+ dump_sigspec(f, sig_a.extract(sig_a.size()-1));
+ f << stringf(" == ");
+ dump_sigspec(f, sig_b.extract(sig_b.size()-1));
+ f << stringf(") || %s == 0 ? %s : ", temp_id.c_str(), temp_id.c_str());
+ dump_cell_expr_port(f, cell, "B", true);
+ f << stringf(" + $signed(%s);\n", temp_id.c_str());
+ return true;
+ } else {
+ // same as truncating modulo
+ dump_cell_expr_binop(f, indent, cell, "%");
+ return true;
+ }
+ }
+
if (cell->type == ID($shift))
{
f << stringf("%s" "assign ", indent.c_str());
@@ -1784,7 +1873,7 @@ void dump_module(std::ostream &f, std::string indent, RTLIL::Module *module)
struct VerilogBackend : public Backend {
VerilogBackend() : Backend("verilog", "write design to Verilog file") { }
- void help() YS_OVERRIDE
+ void help() override
{
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
log("\n");
@@ -1864,7 +1953,7 @@ struct VerilogBackend : public Backend {
log("this command is called on a design with RTLIL processes.\n");
log("\n");
}
- void execute(std::ostream *&f, std::string filename, std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
+ void execute(std::ostream *&f, std::string filename, std::vector<std::string> args, RTLIL::Design *design) override
{
log_header(design, "Executing Verilog backend.\n");
diff --git a/examples/cxx-api/evaldemo.cc b/examples/cxx-api/evaldemo.cc
index 756b7faac..cfe0c0804 100644
--- a/examples/cxx-api/evaldemo.cc
+++ b/examples/cxx-api/evaldemo.cc
@@ -22,7 +22,7 @@ struct EvalDemoPass : public Pass
{
EvalDemoPass() : Pass("evaldemo") { }
- void execute(vector<string>, Design *design) YS_OVERRIDE
+ void execute(vector<string>, Design *design) override
{
Module *module = design->top_module();
diff --git a/frontends/aiger/aigerparse.cc b/frontends/aiger/aigerparse.cc
index 6fda92d73..07e3cd6e0 100644
--- a/frontends/aiger/aigerparse.cc
+++ b/frontends/aiger/aigerparse.cc
@@ -69,7 +69,7 @@ struct ConstEvalAig
continue;
for (auto &it2 : it.second->connections())
if (yosys_celltypes.cell_output(it.second->type, it2.first)) {
- auto r YS_ATTRIBUTE(unused) = sig2driver.insert(std::make_pair(it2.second, it.second));
+ auto r = sig2driver.insert(std::make_pair(it2.second, it.second));
log_assert(r.second);
}
}
@@ -400,9 +400,9 @@ void AigerReader::parse_xaiger()
for (int c = f.get(); c != EOF; c = f.get()) {
// XAIGER extensions
if (c == 'm') {
- uint32_t dataSize YS_ATTRIBUTE(unused) = parse_xaiger_literal(f);
+ uint32_t dataSize = parse_xaiger_literal(f);
uint32_t lutNum = parse_xaiger_literal(f);
- uint32_t lutSize YS_ATTRIBUTE(unused) = parse_xaiger_literal(f);
+ uint32_t lutSize = parse_xaiger_literal(f);
log_debug("m: dataSize=%u lutNum=%u lutSize=%u\n", dataSize, lutNum, lutSize);
ConstEvalAig ce(module);
for (unsigned i = 0; i < lutNum; ++i) {
@@ -434,7 +434,7 @@ void AigerReader::parse_xaiger()
int gray = j ^ (j >> 1);
ce.set_incremental(input_sig, RTLIL::Const{gray, GetSize(input_sig)});
RTLIL::SigBit o(output_sig);
- bool success YS_ATTRIBUTE(unused) = ce.eval(o);
+ bool success = ce.eval(o);
log_assert(success);
log_assert(o.wire == nullptr);
lut_mask[gray] = o.data;
@@ -446,7 +446,7 @@ void AigerReader::parse_xaiger()
}
}
else if (c == 'r') {
- uint32_t dataSize YS_ATTRIBUTE(unused) = parse_xaiger_literal(f);
+ uint32_t dataSize = parse_xaiger_literal(f);
flopNum = parse_xaiger_literal(f);
log_debug("flopNum = %u\n", flopNum);
log_assert(dataSize == (flopNum+1) * sizeof(uint32_t));
@@ -454,6 +454,14 @@ void AigerReader::parse_xaiger()
for (unsigned i = 0; i < flopNum; i++)
mergeability.emplace_back(parse_xaiger_literal(f));
}
+ else if (c == 's') {
+ uint32_t dataSize = parse_xaiger_literal(f);
+ flopNum = parse_xaiger_literal(f);
+ log_assert(dataSize == (flopNum+1) * sizeof(uint32_t));
+ initial_state.reserve(flopNum);
+ for (unsigned i = 0; i < flopNum; i++)
+ initial_state.emplace_back(parse_xaiger_literal(f));
+ }
else if (c == 'n') {
parse_xaiger_literal(f);
f >> s;
@@ -461,15 +469,15 @@ void AigerReader::parse_xaiger()
}
else if (c == 'h') {
f.ignore(sizeof(uint32_t));
- uint32_t version YS_ATTRIBUTE(unused) = parse_xaiger_literal(f);
+ uint32_t version = parse_xaiger_literal(f);
log_assert(version == 1);
- uint32_t ciNum YS_ATTRIBUTE(unused) = parse_xaiger_literal(f);
+ uint32_t ciNum = parse_xaiger_literal(f);
log_debug("ciNum = %u\n", ciNum);
- uint32_t coNum YS_ATTRIBUTE(unused) = parse_xaiger_literal(f);
+ uint32_t coNum = parse_xaiger_literal(f);
log_debug("coNum = %u\n", coNum);
piNum = parse_xaiger_literal(f);
log_debug("piNum = %u\n", piNum);
- uint32_t poNum YS_ATTRIBUTE(unused) = parse_xaiger_literal(f);
+ uint32_t poNum = parse_xaiger_literal(f);
log_debug("poNum = %u\n", poNum);
uint32_t boxNum = parse_xaiger_literal(f);
log_debug("boxNum = %u\n", boxNum);
@@ -778,10 +786,9 @@ void AigerReader::post_process()
log_assert(q->port_input);
q->port_input = false;
- auto ff = module->addCell(NEW_ID, ID($__ABC9_FF_));
- ff->setPort(ID::D, d);
- ff->setPort(ID::Q, q);
+ Cell* ff = module->addFfGate(NEW_ID, d, q);
ff->attributes[ID::abc9_mergeability] = mergeability[i];
+ q->attributes[ID::init] = initial_state[i];
}
dict<RTLIL::IdString, std::pair<int,int>> wideports_cache;
@@ -887,7 +894,9 @@ void AigerReader::post_process()
}
else if (type == "box") {
RTLIL::Cell* cell = module->cell(stringf("$box%d", variable));
- if (cell) // ABC could have optimised this box away
+ if (!cell)
+ log_debug("Box %d (%s) no longer exists.\n", variable, log_id(escaped_s));
+ else
module->rename(cell, escaped_s);
}
else
@@ -899,6 +908,8 @@ void AigerReader::post_process()
auto name = wp.first;
int min = wp.second.first;
int max = wp.second.second;
+ if (min == 0 && max == 0)
+ continue;
RTLIL::Wire *wire = module->wire(name);
if (wire)
@@ -959,7 +970,7 @@ void AigerReader::post_process()
struct AigerFrontend : public Frontend {
AigerFrontend() : Frontend("aiger", "read AIGER file") { }
- void help() YS_OVERRIDE
+ void help() override
{
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
log("\n");
@@ -985,7 +996,7 @@ struct AigerFrontend : public Frontend {
log(" read XAIGER extensions\n");
log("\n");
}
- void execute(std::istream *&f, std::string filename, std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
+ void execute(std::istream *&f, std::string filename, std::vector<std::string> args, RTLIL::Design *design) override
{
log_header(design, "Executing AIGER frontend.\n");
diff --git a/frontends/aiger/aigerparse.h b/frontends/aiger/aigerparse.h
index 46ac81212..251a24977 100644
--- a/frontends/aiger/aigerparse.h
+++ b/frontends/aiger/aigerparse.h
@@ -45,7 +45,7 @@ struct AigerReader
std::vector<RTLIL::Wire*> outputs;
std::vector<RTLIL::Wire*> bad_properties;
std::vector<RTLIL::Cell*> boxes;
- std::vector<int> mergeability;
+ std::vector<int> mergeability, initial_state;
AigerReader(RTLIL::Design *design, std::istream &f, RTLIL::IdString module_name, RTLIL::IdString clk_name, std::string map_filename, bool wideports);
void parse_aiger();
diff --git a/frontends/ast/ast.cc b/frontends/ast/ast.cc
index 689fa9fb4..9520ae32c 100644
--- a/frontends/ast/ast.cc
+++ b/frontends/ast/ast.cc
@@ -95,6 +95,7 @@ std::string AST::type2str(AstNodeType type)
X(AST_TO_SIGNED)
X(AST_TO_UNSIGNED)
X(AST_SELFSZ)
+ X(AST_CAST_SIZE)
X(AST_CONCAT)
X(AST_REPLICATE)
X(AST_BIT_NOT)
@@ -171,6 +172,9 @@ std::string AST::type2str(AstNodeType type)
X(AST_PACKAGE)
X(AST_WIRETYPE)
X(AST_TYPEDEF)
+ X(AST_STRUCT)
+ X(AST_UNION)
+ X(AST_STRUCT_ITEM)
#undef X
default:
log_abort();
diff --git a/frontends/ast/ast.h b/frontends/ast/ast.h
index 8932108e3..9a5aa15f9 100644
--- a/frontends/ast/ast.h
+++ b/frontends/ast/ast.h
@@ -76,6 +76,7 @@ namespace AST
AST_TO_SIGNED,
AST_TO_UNSIGNED,
AST_SELFSZ,
+ AST_CAST_SIZE,
AST_CONCAT,
AST_REPLICATE,
AST_BIT_NOT,
@@ -143,7 +144,7 @@ namespace AST
AST_GENCASE,
AST_GENBLOCK,
AST_TECALL,
-
+
AST_POSEDGE,
AST_NEGEDGE,
AST_EDGE,
@@ -156,7 +157,10 @@ namespace AST
AST_PACKAGE,
AST_WIRETYPE,
- AST_TYPEDEF
+ AST_TYPEDEF,
+ AST_STRUCT,
+ AST_UNION,
+ AST_STRUCT_ITEM
};
struct AstSrcLocType {
@@ -254,6 +258,7 @@ namespace AST
bool mem2reg_check(pool<AstNode*> &mem2reg_set);
void mem2reg_remove(pool<AstNode*> &mem2reg_set, vector<AstNode*> &delnodes);
void meminfo(int &mem_width, int &mem_size, int &addr_bits);
+ bool detect_latch(const std::string &var);
// additional functionality for evaluating constant functions
struct varinfo_t { RTLIL::Const val; int offset; bool is_signed; };
@@ -306,6 +311,7 @@ namespace AST
// helpers for enum
void allocateDefaultEnumValues();
+ void annotateTypedEnums(AstNode *template_node);
};
// process an AST tree (ast must point to an AST_DESIGN node) and generate RTLIL code
@@ -317,12 +323,12 @@ namespace AST
struct AstModule : RTLIL::Module {
AstNode *ast;
bool nolatches, nomeminit, nomem2reg, mem2reg, noblackbox, lib, nowb, noopt, icells, pwires, autowire;
- ~AstModule() YS_OVERRIDE;
- RTLIL::IdString derive(RTLIL::Design *design, const dict<RTLIL::IdString, RTLIL::Const> &parameters, bool mayfail) YS_OVERRIDE;
- RTLIL::IdString derive(RTLIL::Design *design, const dict<RTLIL::IdString, RTLIL::Const> &parameters, const dict<RTLIL::IdString, RTLIL::Module*> &interfaces, const dict<RTLIL::IdString, RTLIL::IdString> &modports, bool mayfail) YS_OVERRIDE;
+ ~AstModule() override;
+ RTLIL::IdString derive(RTLIL::Design *design, const dict<RTLIL::IdString, RTLIL::Const> &parameters, bool mayfail) override;
+ RTLIL::IdString derive(RTLIL::Design *design, const dict<RTLIL::IdString, RTLIL::Const> &parameters, const dict<RTLIL::IdString, RTLIL::Module*> &interfaces, const dict<RTLIL::IdString, RTLIL::IdString> &modports, bool mayfail) override;
std::string derive_common(RTLIL::Design *design, const dict<RTLIL::IdString, RTLIL::Const> &parameters, AstNode **new_ast_out, bool quiet = false);
- void reprocess_module(RTLIL::Design *design, const dict<RTLIL::IdString, RTLIL::Module *> &local_interfaces) YS_OVERRIDE;
- RTLIL::Module *clone() const YS_OVERRIDE;
+ void reprocess_module(RTLIL::Design *design, const dict<RTLIL::IdString, RTLIL::Module *> &local_interfaces) override;
+ RTLIL::Module *clone() const override;
void loadconfig() const;
};
diff --git a/frontends/ast/genrtlil.cc b/frontends/ast/genrtlil.cc
index d4e9baa5f..e878d0dd2 100644
--- a/frontends/ast/genrtlil.cc
+++ b/frontends/ast/genrtlil.cc
@@ -814,6 +814,16 @@ void AstNode::detectSignWidthWorker(int &width_hint, bool &sign_hint, bool *foun
children.at(0)->detectSignWidthWorker(sub_width_hint, sign_hint);
break;
+ case AST_CAST_SIZE:
+ while (children.at(0)->simplify(true, false, false, 1, -1, false, false)) { }
+ if (children.at(0)->type != AST_CONSTANT)
+ log_file_error(filename, location.first_line, "Static cast with non constant expression!\n");
+ children.at(1)->detectSignWidthWorker(width_hint, sign_hint);
+ width_hint = children.at(0)->bitsAsConst().as_int();
+ if (width_hint <= 0)
+ log_file_error(filename, location.first_line, "Static cast with zero or negative size!\n");
+ break;
+
case AST_CONCAT:
for (auto child : children) {
sub_width_hint = 0;
@@ -991,6 +1001,8 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
case AST_MODPORT:
case AST_MODPORTMEMBER:
case AST_TYPEDEF:
+ case AST_STRUCT:
+ case AST_UNION:
break;
case AST_INTERFACEPORT: {
// If a port in a module with unknown type is found, mark it with the attribute 'is_interface'
@@ -1055,7 +1067,7 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
if (!range_valid)
log_file_error(filename, location.first_line, "Signal `%s' with non-constant width!\n", str.c_str());
- if (!(range_left >= range_right || (range_left == -1 && range_right == 0)))
+ if (!(range_left + 1 >= range_right))
log_file_error(filename, location.first_line, "Signal `%s' with invalid width range %d!\n", str.c_str(), range_left - range_right + 1);
RTLIL::Wire *wire = current_module->addWire(str, range_left - range_right + 1);
@@ -1065,6 +1077,7 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
wire->port_input = is_input;
wire->port_output = is_output;
wire->upto = range_swapped;
+ wire->is_signed = is_signed;
for (auto &attr : attributes) {
if (attr.second->type != AST_CONSTANT)
@@ -1286,6 +1299,20 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
return sig;
}
+ // changing the size of signal can be done directly using RTLIL::SigSpec
+ case AST_CAST_SIZE: {
+ RTLIL::SigSpec size = children[0]->genRTLIL();
+ RTLIL::SigSpec sig = children[1]->genRTLIL();
+ if (!size.is_fully_const())
+ log_file_error(filename, location.first_line, "Static cast with non constant expression!\n");
+ int width = size.as_int();
+ if (width <= 0)
+ log_file_error(filename, location.first_line, "Static cast with zero or negative size!\n");
+ sig.extend_u0(width, sign_hint);
+ is_signed = sign_hint;
+ return sig;
+ }
+
// concatenation of signals can be done directly using RTLIL::SigSpec
case AST_CONCAT: {
RTLIL::SigSpec sig;
diff --git a/frontends/ast/simplify.cc b/frontends/ast/simplify.cc
index f629df387..c4df5c0a0 100644
--- a/frontends/ast/simplify.cc
+++ b/frontends/ast/simplify.cc
@@ -168,6 +168,321 @@ std::string AstNode::process_format_str(const std::string &sformat, int next_arg
}
+void AstNode::annotateTypedEnums(AstNode *template_node)
+{
+ //check if enum
+ if (template_node->attributes.count(ID::enum_type)) {
+ //get reference to enum node:
+ std::string enum_type = template_node->attributes[ID::enum_type]->str.c_str();
+ // log("enum_type=%s (count=%lu)\n", enum_type.c_str(), current_scope.count(enum_type));
+ // log("current scope:\n");
+ // for (auto &it : current_scope)
+ // log(" %s\n", it.first.c_str());
+ log_assert(current_scope.count(enum_type) == 1);
+ AstNode *enum_node = current_scope.at(enum_type);
+ log_assert(enum_node->type == AST_ENUM);
+ //get width from 1st enum item:
+ log_assert(enum_node->children.size() >= 1);
+ AstNode *enum_item0 = enum_node->children[0];
+ log_assert(enum_item0->type == AST_ENUM_ITEM);
+ int width;
+ if (!enum_item0->range_valid)
+ width = 1;
+ else if (enum_item0->range_swapped)
+ width = enum_item0->range_right - enum_item0->range_left + 1;
+ else
+ width = enum_item0->range_left - enum_item0->range_right + 1;
+ log_assert(width > 0);
+ //add declared enum items:
+ for (auto enum_item : enum_node->children){
+ log_assert(enum_item->type == AST_ENUM_ITEM);
+ //get is_signed
+ bool is_signed;
+ if (enum_item->children.size() == 1){
+ is_signed = false;
+ } else if (enum_item->children.size() == 2){
+ log_assert(enum_item->children[1]->type == AST_RANGE);
+ is_signed = enum_item->children[1]->is_signed;
+ } else {
+ log_error("enum_item children size==%lu, expected 1 or 2 for %s (%s)\n",
+ enum_item->children.size(),
+ enum_item->str.c_str(), enum_node->str.c_str()
+ );
+ }
+ //start building attribute string
+ std::string enum_item_str = "\\enum_value_";
+ //get enum item value
+ if(enum_item->children[0]->type != AST_CONSTANT){
+ log_error("expected const, got %s for %s (%s)\n",
+ type2str(enum_item->children[0]->type).c_str(),
+ enum_item->str.c_str(), enum_node->str.c_str()
+ );
+ }
+ RTLIL::Const val = enum_item->children[0]->bitsAsConst(width, is_signed);
+ enum_item_str.append(val.as_string());
+ //set attribute for available val to enum item name mappings
+ attributes[enum_item_str.c_str()] = mkconst_str(enum_item->str);
+ }
+ }
+}
+
+static bool name_has_dot(const std::string &name, std::string &struct_name)
+{
+ // check if plausible struct member name \sss.mmm
+ std::string::size_type pos;
+ if (name.substr(0, 1) == "\\" && (pos = name.find('.', 0)) != std::string::npos) {
+ struct_name = name.substr(0, pos);
+ return true;
+ }
+ return false;
+}
+
+static AstNode *make_range(int left, int right, bool is_signed = false)
+{
+ // generate a pre-validated range node for a fixed signal range.
+ auto range = new AstNode(AST_RANGE);
+ range->range_left = left;
+ range->range_right = right;
+ range->range_valid = true;
+ range->children.push_back(AstNode::mkconst_int(left, true));
+ range->children.push_back(AstNode::mkconst_int(right, true));
+ range->is_signed = is_signed;
+ return range;
+}
+
+static int range_width(AstNode *node, AstNode *rnode)
+{
+ log_assert(rnode->type==AST_RANGE);
+ if (!rnode->range_valid) {
+ log_file_error(node->filename, node->location.first_line, "Size must be constant in packed struct/union member %s\n", node->str.c_str());
+
+ }
+ // note: range swapping has already been checked for
+ return rnode->range_left - rnode->range_right + 1;
+}
+
+[[noreturn]] static void struct_array_packing_error(AstNode *node)
+{
+ log_file_error(node->filename, node->location.first_line, "Unpacked array in packed struct/union member %s\n", node->str.c_str());
+}
+
+static void save_struct_array_width(AstNode *node, int width)
+{
+ // stash the stride for the array
+ node->multirange_dimensions.push_back(width);
+
+}
+
+static int get_struct_array_width(AstNode *node)
+{
+ // the stride for the array, 1 if not an array
+ return (node->multirange_dimensions.empty() ? 1 : node->multirange_dimensions.back());
+
+}
+
+static int size_packed_struct(AstNode *snode, int base_offset)
+{
+ // Struct members will be laid out in the structure contiguously from left to right.
+ // Union members all have zero offset from the start of the union.
+ // Determine total packed size and assign offsets. Store these in the member node.
+ bool is_union = (snode->type == AST_UNION);
+ int offset = 0;
+ int packed_width = -1;
+ // examine members from last to first
+ for (auto it = snode->children.rbegin(); it != snode->children.rend(); ++it) {
+ auto node = *it;
+ int width;
+ if (node->type == AST_STRUCT || node->type == AST_UNION) {
+ // embedded struct or union
+ width = size_packed_struct(node, base_offset + offset);
+ }
+ else {
+ log_assert(node->type == AST_STRUCT_ITEM);
+ if (node->children.size() > 0 && node->children[0]->type == AST_RANGE) {
+ // member width e.g. bit [7:0] a
+ width = range_width(node, node->children[0]);
+ if (node->children.size() == 2) {
+ if (node->children[1]->type == AST_RANGE) {
+ // unpacked array e.g. bit [63:0] a [0:3]
+ auto rnode = node->children[1];
+ int array_count = range_width(node, rnode);
+ if (array_count == 1) {
+ // C-type array size e.g. bit [63:0] a [4]
+ array_count = rnode->range_left;
+ }
+ save_struct_array_width(node, width);
+ width *= array_count;
+ }
+ else {
+ // array element must be single bit for a packed array
+ struct_array_packing_error(node);
+ }
+ }
+ // range nodes are now redundant
+ node->children.clear();
+ }
+ else if (node->children.size() == 1 && node->children[0]->type == AST_MULTIRANGE) {
+ // packed 2D array, e.g. bit [3:0][63:0] a
+ auto rnode = node->children[0];
+ if (rnode->children.size() != 2) {
+ // packed arrays can only be 2D
+ struct_array_packing_error(node);
+ }
+ int array_count = range_width(node, rnode->children[0]);
+ width = range_width(node, rnode->children[1]);
+ save_struct_array_width(node, width);
+ width *= array_count;
+ // range nodes are now redundant
+ node->children.clear();
+ }
+ else if (node->range_left < 0) {
+ // 1 bit signal: bit, logic or reg
+ width = 1;
+ }
+ else {
+ // already resolved and compacted
+ width = node->range_left - node->range_right + 1;
+ }
+ if (is_union) {
+ node->range_right = base_offset;
+ node->range_left = base_offset + width - 1;
+ }
+ else {
+ node->range_right = base_offset + offset;
+ node->range_left = base_offset + offset + width - 1;
+ }
+ node->range_valid = true;
+ }
+ if (is_union) {
+ // check that all members have the same size
+ if (packed_width == -1) {
+ // first member
+ packed_width = width;
+ }
+ else {
+ if (packed_width != width) {
+
+ log_file_error(node->filename, node->location.first_line, "member %s of a packed union has %d bits, expecting %d\n", node->str.c_str(), width, packed_width);
+ }
+ }
+ }
+ else {
+ offset += width;
+ }
+ }
+ return (is_union ? packed_width : offset);
+}
+
+[[noreturn]] static void struct_op_error(AstNode *node)
+{
+ log_file_error(node->filename, node->location.first_line, "Unsupported operation for struct/union member %s\n", node->str.c_str()+1);
+}
+
+static AstNode *node_int(int ival)
+{
+ // maybe mkconst_int should have default values for the common integer case
+ return AstNode::mkconst_int(ival, true, 32);
+}
+
+static AstNode *offset_indexed_range(int offset_right, int stride, AstNode *left_expr, AstNode *right_expr)
+{
+ // adjust the range expressions to add an offset into the struct
+ // and maybe index using an array stride
+ auto left = left_expr->clone();
+ auto right = right_expr->clone();
+ if (stride == 1) {
+ // just add the offset
+ left = new AstNode(AST_ADD, node_int(offset_right), left);
+ right = new AstNode(AST_ADD, node_int(offset_right), right);
+ }
+ else {
+ // newleft = offset_right - 1 + (left + 1) * stride
+ left = new AstNode(AST_ADD, new AstNode(AST_SUB, node_int(offset_right), node_int(1)),
+ new AstNode(AST_MUL, node_int(stride), new AstNode(AST_ADD, left, node_int(1))));
+ // newright = offset_right + right * stride
+ right = new AstNode(AST_ADD, node_int(offset_right), new AstNode(AST_MUL, right, node_int(stride)));
+ }
+ return new AstNode(AST_RANGE, left, right);
+}
+
+static AstNode *make_struct_member_range(AstNode *node, AstNode *member_node)
+{
+ // Work out the range in the packed array that corresponds to a struct member
+ // taking into account any range operations applicable to the current node
+ // such as array indexing or slicing
+ int range_left = member_node->range_left;
+ int range_right = member_node->range_right;
+ if (node->children.empty()) {
+ // no range operations apply, return the whole width
+ }
+ else if (node->children.size() == 1 && node->children[0]->type == AST_RANGE) {
+ auto rnode = node->children[0];
+ int stride = get_struct_array_width(member_node);
+ if (rnode->children.size() == 1) {
+ // index e.g. s.a[i]
+ return offset_indexed_range(range_right, stride, rnode->children[0], rnode->children[0]);
+ }
+ else if (rnode->children.size() == 2) {
+ // slice e.g. s.a[i:j]
+ return offset_indexed_range(range_right, stride, rnode->children[0], rnode->children[1]);
+ }
+ else {
+ struct_op_error(node);
+ }
+ }
+ else {
+ // TODO multirange, i.e. bit slice after array index s.a[i][p:q]
+ struct_op_error(node);
+ }
+ return make_range(range_left, range_right);
+}
+
+static void add_members_to_scope(AstNode *snode, std::string name)
+{
+ // add all the members in a struct or union to local scope
+ // in case later referenced in assignments
+ log_assert(snode->type==AST_STRUCT || snode->type==AST_UNION);
+ for (auto *node : snode->children) {
+ if (node->type != AST_STRUCT_ITEM) {
+ // embedded struct or union
+ add_members_to_scope(node, name + "." + node->str);
+ }
+ else {
+ auto member_name = name + "." + node->str;
+ current_scope[member_name] = node;
+ }
+ }
+}
+
+static int get_max_offset(AstNode *node)
+{
+ // get the width from the MS member in the struct
+ // as members are laid out from left to right in the packed wire
+ log_assert(node->type==AST_STRUCT || node->type==AST_UNION);
+ while (node->type != AST_STRUCT_ITEM) {
+ node = node->children[0];
+ }
+ return node->range_left;
+}
+
+static AstNode *make_packed_struct(AstNode *template_node, std::string &name)
+{
+ // create a wire for the packed struct
+ auto wnode = new AstNode(AST_WIRE);
+ wnode->str = name;
+ wnode->is_logic = true;
+ wnode->range_valid = true;
+ wnode->is_signed = template_node->is_signed;
+ int offset = get_max_offset(template_node);
+ auto range = make_range(offset, 0);
+ wnode->children.push_back(range);
+ // make sure this node is the one in scope for this name
+ current_scope[name] = wnode;
+ // add all the struct members to scope under the wire's name
+ add_members_to_scope(template_node, name);
+ return wnode;
+}
+
// convert the AST into a simpler AST that has all parameters substituted by their
// values, unrolled for-loops, expanded generate blocks, etc. when this function
// is done with an AST it can be converted into RTLIL using genRTLIL().
@@ -463,7 +778,7 @@ bool AstNode::simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage,
while (node->simplify(true, false, false, 1, -1, false, node->type == AST_PARAMETER || node->type == AST_LOCALPARAM))
did_something = true;
if (node->type == AST_ENUM) {
- for (auto enode YS_ATTRIBUTE(unused) : node->children){
+ for (auto enode : node->children){
log_assert(enode->type==AST_ENUM_ITEM);
while (node->simplify(true, false, false, 1, -1, false, in_param))
did_something = true;
@@ -567,6 +882,32 @@ bool AstNode::simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage,
}
break;
+ case AST_STRUCT:
+ case AST_UNION:
+ if (!basic_prep) {
+ for (auto *node : children) {
+ // resolve any ranges
+ while (!node->basic_prep && node->simplify(true, false, false, stage, -1, false, false)) {
+ did_something = true;
+ }
+ }
+ // determine member offsets and widths
+ size_packed_struct(this, 0);
+
+ // instance rather than just a type in a typedef or outer struct?
+ if (!str.empty() && str[0] == '\\') {
+ // instance so add a wire for the packed structure
+ auto wnode = make_packed_struct(this, str);
+ log_assert(current_ast_mod);
+ current_ast_mod->children.push_back(wnode);
+ }
+ basic_prep = true;
+ }
+ break;
+
+ case AST_STRUCT_ITEM:
+ break;
+
case AST_ENUM:
//log("\nENUM %s: %d child %d\n", str.c_str(), basic_prep, children[0]->basic_prep);
if (!basic_prep) {
@@ -609,6 +950,7 @@ bool AstNode::simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage,
case AST_TO_SIGNED:
case AST_TO_UNSIGNED:
case AST_SELFSZ:
+ case AST_CAST_SIZE:
case AST_CONCAT:
case AST_REPLICATE:
case AST_REDUCE_AND:
@@ -785,6 +1127,10 @@ bool AstNode::simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage,
bool in_param_here = in_param;
if (i == 0 && (type == AST_REPLICATE || type == AST_WIRE))
const_fold_here = true, in_param_here = true;
+ if (i == 0 && (type == AST_GENIF || type == AST_GENCASE))
+ in_param_here = true;
+ if (i == 1 && (type == AST_FOR || type == AST_GENFOR))
+ in_param_here = true;
if (type == AST_PARAMETER || type == AST_LOCALPARAM)
const_fold_here = true;
if (i == 0 && (type == AST_ASSIGN || type == AST_ASSIGN_EQ || type == AST_ASSIGN_LE))
@@ -884,10 +1230,12 @@ bool AstNode::simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage,
// resolve typedefs
if (type == AST_TYPEDEF) {
log_assert(children.size() == 1);
- log_assert(children[0]->type == AST_WIRE || children[0]->type == AST_MEMORY);
- while(children[0]->simplify(const_fold, at_zero, in_lvalue, stage, width_hint, sign_hint, in_param))
+ auto type_node = children[0];
+ log_assert(type_node->type == AST_WIRE || type_node->type == AST_MEMORY || type_node->type == AST_STRUCT || type_node->type == AST_UNION);
+ while (type_node->simplify(const_fold, at_zero, in_lvalue, stage, width_hint, sign_hint, in_param)) {
did_something = true;
- log_assert(!children[0]->is_custom_type);
+ }
+ log_assert(!type_node->is_custom_type);
}
// resolve types of wires
@@ -895,100 +1243,57 @@ bool AstNode::simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage,
if (is_custom_type) {
log_assert(children.size() >= 1);
log_assert(children[0]->type == AST_WIRETYPE);
- if (!current_scope.count(children[0]->str))
- log_file_error(filename, location.first_line, "Unknown identifier `%s' used as type name\n", children[0]->str.c_str());
- AstNode *resolved_type = current_scope.at(children[0]->str);
- if (resolved_type->type != AST_TYPEDEF)
- log_file_error(filename, location.first_line, "`%s' does not name a type\n", children[0]->str.c_str());
- log_assert(resolved_type->children.size() == 1);
- AstNode *templ = resolved_type->children[0];
+ auto type_name = children[0]->str;
+ if (!current_scope.count(type_name)) {
+ log_file_error(filename, location.first_line, "Unknown identifier `%s' used as type name\n", type_name.c_str());
+ }
+ AstNode *resolved_type_node = current_scope.at(type_name);
+ if (resolved_type_node->type != AST_TYPEDEF)
+ log_file_error(filename, location.first_line, "`%s' does not name a type\n", type_name.c_str());
+ log_assert(resolved_type_node->children.size() == 1);
+ AstNode *template_node = resolved_type_node->children[0];
+
+ // Ensure typedef itself is fully simplified
+ while (template_node->simplify(const_fold, at_zero, in_lvalue, stage, width_hint, sign_hint, in_param)) {};
+
+ if (template_node->type == AST_STRUCT || template_node->type == AST_UNION) {
+ // replace with wire representing the packed structure
+ newNode = make_packed_struct(template_node, str);
+ current_scope[str] = this;
+ goto apply_newNode;
+ }
+
// Remove type reference
delete children[0];
children.erase(children.begin());
- // Ensure typedef itself is fully simplified
- while(templ->simplify(const_fold, at_zero, in_lvalue, stage, width_hint, sign_hint, in_param)) {};
-
if (type == AST_WIRE)
- type = templ->type;
- is_reg = templ->is_reg;
- is_logic = templ->is_logic;
- is_signed = templ->is_signed;
- is_string = templ->is_string;
- is_custom_type = templ->is_custom_type;
-
- range_valid = templ->range_valid;
- range_swapped = templ->range_swapped;
- range_left = templ->range_left;
- range_right = templ->range_right;
- attributes[ID::wiretype] = mkconst_str(resolved_type->str);
- //check if enum
- if (templ->attributes.count(ID::enum_type)){
- //get reference to enum node:
- const std::string &enum_type = templ->attributes[ID::enum_type]->str;
- // log("enum_type=%s (count=%lu)\n", enum_type.c_str(), current_scope.count(enum_type));
- // log("current scope:\n");
- // for (auto &it : current_scope)
- // log(" %s\n", it.first.c_str());
- log_assert(current_scope.count(enum_type) == 1);
- AstNode *enum_node = current_scope.at(enum_type);
- log_assert(enum_node->type == AST_ENUM);
- //get width from 1st enum item:
- log_assert(enum_node->children.size() >= 1);
- AstNode *enum_item0 = enum_node->children[0];
- log_assert(enum_item0->type == AST_ENUM_ITEM);
- int width;
- if (!enum_item0->range_valid)
- width = 1;
- else if (enum_item0->range_swapped)
- width = enum_item0->range_right - enum_item0->range_left + 1;
- else
- width = enum_item0->range_left - enum_item0->range_right + 1;
- log_assert(width > 0);
- //add declared enum items:
- for (auto enum_item : enum_node->children){
- log_assert(enum_item->type == AST_ENUM_ITEM);
- //get is_signed
- bool is_signed;
- if (enum_item->children.size() == 1){
- is_signed = false;
- } else if (enum_item->children.size() == 2){
- log_assert(enum_item->children[1]->type == AST_RANGE);
- is_signed = enum_item->children[1]->is_signed;
- } else {
- log_error("enum_item children size==%lu, expected 1 or 2 for %s (%s)\n",
- enum_item->children.size(),
- enum_item->str.c_str(), enum_node->str.c_str()
- );
- }
- //start building attribute string
- std::string enum_item_str = "\\enum_value_";
- //get enum item value
- if(enum_item->children[0]->type != AST_CONSTANT){
- log_error("expected const, got %s for %s (%s)\n",
- type2str(enum_item->children[0]->type).c_str(),
- enum_item->str.c_str(), enum_node->str.c_str()
- );
- }
- RTLIL::Const val = enum_item->children[0]->bitsAsConst(width, is_signed);
- enum_item_str.append(val.as_string());
- //set attribute for available val to enum item name mappings
- attributes[enum_item_str] = mkconst_str(enum_item->str);
- }
- }
+ type = template_node->type;
+ is_reg = template_node->is_reg;
+ is_logic = template_node->is_logic;
+ is_signed = template_node->is_signed;
+ is_string = template_node->is_string;
+ is_custom_type = template_node->is_custom_type;
+
+ range_valid = template_node->range_valid;
+ range_swapped = template_node->range_swapped;
+ range_left = template_node->range_left;
+ range_right = template_node->range_right;
+
+ attributes[ID::wiretype] = mkconst_str(resolved_type_node->str);
+
+ // if an enum then add attributes to support simulator tracing
+ annotateTypedEnums(template_node);
// Insert clones children from template at beginning
- for (int i = 0; i < GetSize(templ->children); i++)
- children.insert(children.begin() + i, templ->children[i]->clone());
+ for (int i = 0; i < GetSize(template_node->children); i++)
+ children.insert(children.begin() + i, template_node->children[i]->clone());
if (type == AST_MEMORY && GetSize(children) == 1) {
// Single-bit memories must have [0:0] range
- AstNode *rng = new AstNode(AST_RANGE);
- rng->children.push_back(AstNode::mkconst_int(0, true));
- rng->children.push_back(AstNode::mkconst_int(0, true));
+ AstNode *rng = make_range(0, 0);
children.insert(children.begin(), rng);
}
-
did_something = true;
}
log_assert(!is_custom_type);
@@ -1001,29 +1306,29 @@ bool AstNode::simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage,
log_assert(children[1]->type == AST_WIRETYPE);
if (!current_scope.count(children[1]->str))
log_file_error(filename, location.first_line, "Unknown identifier `%s' used as type name\n", children[1]->str.c_str());
- AstNode *resolved_type = current_scope.at(children[1]->str);
- if (resolved_type->type != AST_TYPEDEF)
+ AstNode *resolved_type_node = current_scope.at(children[1]->str);
+ if (resolved_type_node->type != AST_TYPEDEF)
log_file_error(filename, location.first_line, "`%s' does not name a type\n", children[1]->str.c_str());
- log_assert(resolved_type->children.size() == 1);
- AstNode *templ = resolved_type->children[0];
+ log_assert(resolved_type_node->children.size() == 1);
+ AstNode *template_node = resolved_type_node->children[0];
delete children[1];
children.pop_back();
// Ensure typedef itself is fully simplified
- while(templ->simplify(const_fold, at_zero, in_lvalue, stage, width_hint, sign_hint, in_param)) {};
+ while(template_node->simplify(const_fold, at_zero, in_lvalue, stage, width_hint, sign_hint, in_param)) {};
- if (templ->type == AST_MEMORY)
+ if (template_node->type == AST_MEMORY)
log_file_error(filename, location.first_line, "unpacked array type `%s' cannot be used for a parameter\n", children[1]->str.c_str());
- is_signed = templ->is_signed;
- is_string = templ->is_string;
- is_custom_type = templ->is_custom_type;
-
- range_valid = templ->range_valid;
- range_swapped = templ->range_swapped;
- range_left = templ->range_left;
- range_right = templ->range_right;
- attributes[ID::wiretype] = mkconst_str(resolved_type->str);
- for (auto template_child : templ->children)
+ is_signed = template_node->is_signed;
+ is_string = template_node->is_string;
+ is_custom_type = template_node->is_custom_type;
+
+ range_valid = template_node->range_valid;
+ range_swapped = template_node->range_swapped;
+ range_left = template_node->range_left;
+ range_right = template_node->range_right;
+ attributes[ID::wiretype] = mkconst_str(resolved_type_node->str);
+ for (auto template_child : template_node->children)
children.push_back(template_child->clone());
did_something = true;
}
@@ -1098,6 +1403,25 @@ bool AstNode::simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage,
range_swapped = children[0]->range_swapped;
range_left = children[0]->range_left;
range_right = children[0]->range_right;
+ bool force_upto = false, force_downto = false;
+ if (attributes.count(ID::force_upto)) {
+ AstNode *val = attributes[ID::force_upto];
+ if (val->type != AST_CONSTANT)
+ log_file_error(filename, location.first_line, "Attribute `force_upto' with non-constant value!\n");
+ force_upto = val->asAttrConst().as_bool();
+ }
+ if (attributes.count(ID::force_downto)) {
+ AstNode *val = attributes[ID::force_downto];
+ if (val->type != AST_CONSTANT)
+ log_file_error(filename, location.first_line, "Attribute `force_downto' with non-constant value!\n");
+ force_downto = val->asAttrConst().as_bool();
+ }
+ if (force_upto && force_downto)
+ log_file_error(filename, location.first_line, "Attributes `force_downto' and `force_upto' cannot be both set!\n");
+ if ((force_upto && !range_swapped) || (force_downto && range_swapped)) {
+ std::swap(range_left, range_right);
+ range_swapped = force_upto;
+ }
}
} else {
if (!range_valid)
@@ -1197,6 +1521,23 @@ bool AstNode::simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage,
}
}
+ if (type == AST_IDENTIFIER && !basic_prep) {
+ // check if a plausible struct member sss.mmmm
+ std::string sname;
+ if (name_has_dot(str, sname)) {
+ if (current_scope.count(str) > 0) {
+ auto item_node = current_scope[str];
+ if (item_node->type == AST_STRUCT_ITEM) {
+ // structure member, rewrite this node to reference the packed struct wire
+ auto range = make_struct_member_range(this, item_node);
+ newNode = new AstNode(AST_IDENTIFIER, range);
+ newNode->str = sname;
+ newNode->basic_prep = true;
+ goto apply_newNode;
+ }
+ }
+ }
+ }
// annotate identifiers using scope resolution and create auto-wires as needed
if (type == AST_IDENTIFIER) {
if (current_scope.count(str) == 0) {
@@ -1606,7 +1947,7 @@ bool AstNode::simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage,
continue;
buf = child->clone();
- while (buf->simplify(true, false, false, stage, width_hint, sign_hint, false)) { }
+ while (buf->simplify(true, false, false, stage, width_hint, sign_hint, true)) { }
if (buf->type != AST_CONSTANT) {
// for (auto f : log_files)
// dumpAst(f, "verilog-ast> ");
@@ -1800,6 +2141,9 @@ bool AstNode::simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage,
use_case_method = true;
}
+ if (!use_case_method && current_always->detect_latch(children[0]->str))
+ use_case_method = true;
+
if (use_case_method)
{
// big case block
@@ -3144,6 +3488,13 @@ replace_fcall_later:;
}
}
break;
+ case AST_CAST_SIZE:
+ if (children.at(0)->type == AST_CONSTANT && children.at(1)->type == AST_CONSTANT) {
+ int width = children[0]->bitsAsConst().as_int();
+ RTLIL::Const val = children[1]->bitsAsConst(width);
+ newNode = mkconst_bits(val.bits, children[1]->is_signed);
+ }
+ break;
case AST_CONCAT:
string_op = !children.empty();
for (auto it = children.begin(); it != children.end(); it++) {
@@ -3521,8 +3872,8 @@ void AstNode::mem2reg_as_needed_pass1(dict<AstNode*, pool<std::string>> &mem2reg
}
}
- // also activate if requested, either by using mem2reg attribute or by declaring array as 'wire' instead of 'reg'
- if (type == AST_MEMORY && (get_bool_attribute(ID::mem2reg) || (flags & AstNode::MEM2REG_FL_ALL) || !is_reg))
+ // also activate if requested, either by using mem2reg attribute or by declaring array as 'wire' instead of 'reg' or 'logic'
+ if (type == AST_MEMORY && (get_bool_attribute(ID::mem2reg) || (flags & AstNode::MEM2REG_FL_ALL) || !(is_reg || is_logic)))
mem2reg_candidates[this] |= AstNode::MEM2REG_FL_FORCED;
if (type == AST_MODULE && get_bool_attribute(ID::mem2reg))
@@ -3868,6 +4219,60 @@ void AstNode::meminfo(int &mem_width, int &mem_size, int &addr_bits)
addr_bits++;
}
+bool AstNode::detect_latch(const std::string &var)
+{
+ switch (type)
+ {
+ case AST_ALWAYS:
+ for (auto &c : children)
+ {
+ switch (c->type)
+ {
+ case AST_POSEDGE:
+ case AST_NEGEDGE:
+ return false;
+ case AST_BLOCK:
+ if (!c->detect_latch(var))
+ return false;
+ break;
+ default:
+ log_abort();
+ }
+ }
+ return true;
+ case AST_BLOCK:
+ for (auto &c : children)
+ if (!c->detect_latch(var))
+ return false;
+ return true;
+ case AST_CASE:
+ {
+ bool r = true;
+ for (auto &c : children) {
+ if (c->type == AST_COND) {
+ if (c->children.at(1)->detect_latch(var))
+ return true;
+ r = false;
+ }
+ if (c->type == AST_DEFAULT) {
+ if (c->children.at(0)->detect_latch(var))
+ return true;
+ r = false;
+ }
+ }
+ return r;
+ }
+ case AST_ASSIGN_EQ:
+ case AST_ASSIGN_LE:
+ if (children.at(0)->type == AST_IDENTIFIER &&
+ children.at(0)->children.empty() && children.at(0)->str == var)
+ return false;
+ return true;
+ default:
+ return true;
+ }
+}
+
bool AstNode::has_const_only_constructs(bool &recommend_const_eval)
{
if (type == AST_FOR)
diff --git a/frontends/blif/blifparse.cc b/frontends/blif/blifparse.cc
index 7cc157e49..9ae3fac2c 100644
--- a/frontends/blif/blifparse.cc
+++ b/frontends/blif/blifparse.cc
@@ -586,7 +586,7 @@ error_with_reason:
struct BlifFrontend : public Frontend {
BlifFrontend() : Frontend("blif", "read BLIF file") { }
- void help() YS_OVERRIDE
+ void help() override
{
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
log("\n");
@@ -602,7 +602,7 @@ struct BlifFrontend : public Frontend {
log(" multi-bit port 'name'.\n");
log("\n");
}
- void execute(std::istream *&f, std::string filename, std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
+ void execute(std::istream *&f, std::string filename, std::vector<std::string> args, RTLIL::Design *design) override
{
bool sop_mode = false;
bool wideports = false;
diff --git a/frontends/ilang/ilang_frontend.cc b/frontends/ilang/ilang_frontend.cc
index 30d9ff79d..973e62f2c 100644
--- a/frontends/ilang/ilang_frontend.cc
+++ b/frontends/ilang/ilang_frontend.cc
@@ -35,7 +35,7 @@ YOSYS_NAMESPACE_BEGIN
struct IlangFrontend : public Frontend {
IlangFrontend() : Frontend("ilang", "read modules from ilang file") { }
- void help() YS_OVERRIDE
+ void help() override
{
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
log("\n");
@@ -56,7 +56,7 @@ struct IlangFrontend : public Frontend {
log(" only create empty blackbox modules\n");
log("\n");
}
- void execute(std::istream *&f, std::string filename, std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
+ void execute(std::istream *&f, std::string filename, std::vector<std::string> args, RTLIL::Design *design) override
{
ILANG_FRONTEND::flag_nooverwrite = false;
ILANG_FRONTEND::flag_overwrite = false;
diff --git a/frontends/ilang/ilang_lexer.l b/frontends/ilang/ilang_lexer.l
index 62f53d18e..3362ed641 100644
--- a/frontends/ilang/ilang_lexer.l
+++ b/frontends/ilang/ilang_lexer.l
@@ -91,8 +91,10 @@ USING_YOSYS_NAMESPACE
[0-9]+'[01xzm-]* { rtlil_frontend_ilang_yylval.string = strdup(yytext); return TOK_VALUE; }
-?[0-9]+ {
char *end = nullptr;
+ errno = 0;
long value = strtol(yytext, &end, 10);
- if (end != yytext + strlen(yytext))
+ log_assert(end == yytext + strlen(yytext));
+ if (errno == ERANGE)
return TOK_INVALID; // literal out of range of long
if (value < INT_MIN || value > INT_MAX)
return TOK_INVALID; // literal out of range of int (relevant mostly for LP64 platforms)
diff --git a/frontends/ilang/ilang_parser.y b/frontends/ilang/ilang_parser.y
index 118f13de9..879ef4af9 100644
--- a/frontends/ilang/ilang_parser.y
+++ b/frontends/ilang/ilang_parser.y
@@ -192,6 +192,9 @@ wire_options:
wire_options TOK_UPTO {
current_wire->upto = true;
} |
+ wire_options TOK_SIGNED {
+ current_wire->is_signed = true;
+ } |
wire_options TOK_OFFSET TOK_INT {
current_wire->start_offset = $3;
} |
diff --git a/frontends/json/jsonparse.cc b/frontends/json/jsonparse.cc
index 7aceffbfc..1b34aaf3a 100644
--- a/frontends/json/jsonparse.cc
+++ b/frontends/json/jsonparse.cc
@@ -309,6 +309,12 @@ void json_import(Design *design, string &modname, JsonNode *node)
port_wire->upto = val->data_number != 0;
}
+ if (port_node->data_dict.count("signed") != 0) {
+ JsonNode *val = port_node->data_dict.at("signed");
+ if (val->type == 'N')
+ port_wire->is_signed = val->data_number != 0;
+ }
+
if (port_node->data_dict.count("offset") != 0) {
JsonNode *val = port_node->data_dict.at("offset");
if (val->type == 'N')
@@ -529,7 +535,7 @@ void json_import(Design *design, string &modname, JsonNode *node)
struct JsonFrontend : public Frontend {
JsonFrontend() : Frontend("json", "read JSON file") { }
- void help() YS_OVERRIDE
+ void help() override
{
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
log("\n");
@@ -539,7 +545,7 @@ struct JsonFrontend : public Frontend {
log("for a description of the file format.\n");
log("\n");
}
- void execute(std::istream *&f, std::string filename, std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
+ void execute(std::istream *&f, std::string filename, std::vector<std::string> args, RTLIL::Design *design) override
{
log_header(design, "Executing JSON frontend.\n");
@@ -573,4 +579,3 @@ struct JsonFrontend : public Frontend {
} JsonFrontend;
YOSYS_NAMESPACE_END
-
diff --git a/frontends/liberty/liberty.cc b/frontends/liberty/liberty.cc
index 6f0c3fefa..f77d7da56 100644
--- a/frontends/liberty/liberty.cc
+++ b/frontends/liberty/liberty.cc
@@ -453,7 +453,7 @@ void parse_type_map(std::map<std::string, std::tuple<int, int, bool>> &type_map,
struct LibertyFrontend : public Frontend {
LibertyFrontend() : Frontend("liberty", "read cells from liberty file") { }
- void help() YS_OVERRIDE
+ void help() override
{
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
log("\n");
@@ -486,7 +486,7 @@ struct LibertyFrontend : public Frontend {
log(" set the specified attribute (to the value 1) on all loaded modules\n");
log("\n");
}
- void execute(std::istream *&f, std::string filename, std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
+ void execute(std::istream *&f, std::string filename, std::vector<std::string> args, RTLIL::Design *design) override
{
bool flag_lib = false;
bool flag_nooverwrite = false;
diff --git a/frontends/rpc/rpc_frontend.cc b/frontends/rpc/rpc_frontend.cc
index 46ee6a733..6d72cbff5 100644
--- a/frontends/rpc/rpc_frontend.cc
+++ b/frontends/rpc/rpc_frontend.cc
@@ -157,7 +157,7 @@ struct RpcServer {
struct RpcModule : RTLIL::Module {
std::shared_ptr<RpcServer> server;
- RTLIL::IdString derive(RTLIL::Design *design, const dict<RTLIL::IdString, RTLIL::Const> &parameters, bool /*mayfail*/) YS_OVERRIDE {
+ RTLIL::IdString derive(RTLIL::Design *design, const dict<RTLIL::IdString, RTLIL::Const> &parameters, bool /*mayfail*/) override {
std::string stripped_name = name.str();
if (stripped_name.compare(0, 9, "$abstract") == 0)
stripped_name = stripped_name.substr(9);
@@ -229,7 +229,7 @@ struct RpcModule : RTLIL::Module {
return derived_name;
}
- RTLIL::Module *clone() const YS_OVERRIDE {
+ RTLIL::Module *clone() const override {
RpcModule *new_mod = new RpcModule;
new_mod->server = server;
cloneInto(new_mod);
@@ -250,7 +250,7 @@ struct HandleRpcServer : RpcServer {
HandleRpcServer(const std::string &name, HANDLE hsend, HANDLE hrecv)
: RpcServer(name), hsend(hsend), hrecv(hrecv) { }
- void write(const std::string &data) YS_OVERRIDE {
+ void write(const std::string &data) override {
log_assert(data.length() >= 1 && data.find('\n') == data.length() - 1);
ssize_t offset = 0;
do {
@@ -261,7 +261,7 @@ struct HandleRpcServer : RpcServer {
} while(offset < (ssize_t)data.length());
}
- std::string read() YS_OVERRIDE {
+ std::string read() override {
std::string data;
ssize_t offset = 0;
while (data.length() == 0 || data[data.length() - 1] != '\n') {
@@ -304,7 +304,7 @@ struct FdRpcServer : RpcServer {
log_cmd_error("RPC frontend terminated unexpectedly\n");
}
- void write(const std::string &data) YS_OVERRIDE {
+ void write(const std::string &data) override {
log_assert(data.length() >= 1 && data.find('\n') == data.length() - 1);
ssize_t offset = 0;
do {
@@ -316,7 +316,7 @@ struct FdRpcServer : RpcServer {
} while(offset < (ssize_t)data.length());
}
- std::string read() YS_OVERRIDE {
+ std::string read() override {
std::string data;
ssize_t offset = 0;
while (data.length() == 0 || data[data.length() - 1] != '\n') {
@@ -346,7 +346,7 @@ struct FdRpcServer : RpcServer {
// RpcFrontend does not inherit from Frontend since it does not read files.
struct RpcFrontend : public Pass {
RpcFrontend() : Pass("connect_rpc", "connect to RPC frontend") { }
- void help() YS_OVERRIDE
+ void help() override
{
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
log("\n");
@@ -390,7 +390,7 @@ struct RpcFrontend : public Pass {
log(" so the response should be the same whenever the same set of parameters\n");
log(" is provided.\n");
}
- void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
+ void execute(std::vector<std::string> args, RTLIL::Design *design) override
{
log_header(design, "Connecting to RPC frontend.\n");
diff --git a/frontends/verific/verific.cc b/frontends/verific/verific.cc
index ae0970aac..0276618b4 100644
--- a/frontends/verific/verific.cc
+++ b/frontends/verific/verific.cc
@@ -54,7 +54,7 @@ USING_YOSYS_NAMESPACE
# error "Only Symbiotic EDA flavored Verific is supported. Please contact office@symbioticeda.com for commercial support for Yosys+Verific."
#endif
-#if SYMBIOTIC_VERIFIC_API_VERSION < 1
+#if SYMBIOTIC_VERIFIC_API_VERSION < 202006
# error "Please update your version of Symbiotic EDA flavored Verific."
#endif
@@ -975,6 +975,7 @@ void VerificImporter::import_netlist(RTLIL::Design *design, Netlist *nl, std::se
module->memories[memory->name] = memory;
int number_of_bits = net->Size();
+ number_of_bits = 1 << ceil_log2(number_of_bits);
int bits_in_word = number_of_bits;
FOREACH_PORTREF_OF_NET(net, si, pr) {
if (pr->GetInst()->Type() == OPER_READ_PORT) {
@@ -1109,7 +1110,12 @@ void VerificImporter::import_netlist(RTLIL::Design *design, Netlist *nl, std::se
RTLIL::Wire *wire = module->addWire(wire_name, netbus->Size());
wire->start_offset = min(netbus->LeftIndex(), netbus->RightIndex());
- import_attributes(wire->attributes, netbus, nl);
+ MapIter mibus;
+ FOREACH_NET_OF_NETBUS(netbus, mibus, net) {
+ if (net)
+ import_attributes(wire->attributes, net, nl);
+ break;
+ }
RTLIL::Const initval = Const(State::Sx, GetSize(wire));
bool initval_valid = false;
@@ -1262,23 +1268,18 @@ void VerificImporter::import_netlist(RTLIL::Design *design, Netlist *nl, std::se
if (inst->Type() == OPER_READ_PORT)
{
- RTLIL::Memory *memory = module->memories.at(RTLIL::escape_id(inst->GetInput()->Name()));
+ RTLIL::Memory *memory = module->memories.at(RTLIL::escape_id(inst->GetInput()->Name()), nullptr);
+ if (!memory)
+ log_error("Memory net '%s' missing, possibly no driver, use verific -flatten.\n", inst->GetInput()->Name());
+
int numchunks = int(inst->OutputSize()) / memory->width;
int chunksbits = ceil_log2(numchunks);
- if ((numchunks * memory->width) != int(inst->OutputSize()))
- log_error("Import of asymmetric memories of this type is not supported yet: %s %s\n", inst->Name(), inst->GetInput()->Name());
-
for (int i = 0; i < numchunks; i++)
{
RTLIL::SigSpec addr = {operatorInput1(inst), RTLIL::Const(i, chunksbits)};
RTLIL::SigSpec data = operatorOutput(inst).extract(i * memory->width, memory->width);
- if ((numchunks & (numchunks - 1)) != 0) {
- addr = module->Mul(NEW_ID, operatorInput1(inst), RTLIL::Const(numchunks));
- addr = module->Add(NEW_ID, addr, RTLIL::Const(i));
- }
-
RTLIL::Cell *cell = module->addCell(numchunks == 1 ? inst_name :
RTLIL::IdString(stringf("%s_%d", inst_name.c_str(), i)), ID($memrd));
cell->parameters[ID::MEMID] = memory->name.str();
@@ -1297,23 +1298,17 @@ void VerificImporter::import_netlist(RTLIL::Design *design, Netlist *nl, std::se
if (inst->Type() == OPER_WRITE_PORT || inst->Type() == OPER_CLOCKED_WRITE_PORT)
{
- RTLIL::Memory *memory = module->memories.at(RTLIL::escape_id(inst->GetOutput()->Name()));
+ RTLIL::Memory *memory = module->memories.at(RTLIL::escape_id(inst->GetOutput()->Name()), nullptr);
+ if (!memory)
+ log_error("Memory net '%s' missing, possibly no driver, use verific -flatten.\n", inst->GetInput()->Name());
int numchunks = int(inst->Input2Size()) / memory->width;
int chunksbits = ceil_log2(numchunks);
- if ((numchunks * memory->width) != int(inst->Input2Size()))
- log_error("Import of asymmetric memories of this type is not supported yet: %s %s\n", inst->Name(), inst->GetOutput()->Name());
-
for (int i = 0; i < numchunks; i++)
{
RTLIL::SigSpec addr = {operatorInput1(inst), RTLIL::Const(i, chunksbits)};
RTLIL::SigSpec data = operatorInput2(inst).extract(i * memory->width, memory->width);
- if ((numchunks & (numchunks - 1)) != 0) {
- addr = module->Mul(NEW_ID, operatorInput1(inst), RTLIL::Const(numchunks));
- addr = module->Add(NEW_ID, addr, RTLIL::Const(i));
- }
-
RTLIL::Cell *cell = module->addCell(numchunks == 1 ? inst_name :
RTLIL::IdString(stringf("%s_%d", inst_name.c_str(), i)), ID($memwr));
cell->parameters[ID::MEMID] = memory->name.str();
@@ -1903,7 +1898,7 @@ struct VerificExtNets
new_net = new Net(name.c_str());
nl->Add(new_net);
- Net *n YS_ATTRIBUTE(unused) = route_up(new_net, port->IsOutput(), ca_nl, ca_net);
+ Net *n = route_up(new_net, port->IsOutput(), ca_nl, ca_net);
log_assert(n == ca_net);
}
@@ -2032,7 +2027,7 @@ bool check_noverific_env()
struct VerificPass : public Pass {
VerificPass() : Pass("verific", "load Verilog and VHDL designs using Verific") { }
- void help() YS_OVERRIDE
+ void help() override
{
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
log("\n");
@@ -2171,7 +2166,7 @@ struct VerificPass : public Pass {
log("\n");
}
#ifdef YOSYS_ENABLE_VERIFIC
- void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
+ void execute(std::vector<std::string> args, RTLIL::Design *design) override
{
static bool set_verific_global_flags = true;
@@ -2204,6 +2199,9 @@ struct VerificPass : public Pass {
RuntimeFlags::SetVar("vhdl_support_variable_slice", 1);
RuntimeFlags::SetVar("vhdl_ignore_assertion_statements", 0);
+ RuntimeFlags::SetVar("veri_preserve_assignments", 1);
+ RuntimeFlags::SetVar("vhdl_preserve_assignments", 1);
+
// Workaround for VIPER #13851
RuntimeFlags::SetVar("veri_create_name_for_unnamed_gen_block", 1);
@@ -2608,7 +2606,7 @@ struct VerificPass : public Pass {
}
#else /* YOSYS_ENABLE_VERIFIC */
- void execute(std::vector<std::string>, RTLIL::Design *) YS_OVERRIDE {
+ void execute(std::vector<std::string>, RTLIL::Design *) override {
log_cmd_error("This version of Yosys is built without Verific support.\n"
"\n"
"Use Symbiotic EDA Suite if you need Yosys+Verifc.\n"
@@ -2622,7 +2620,7 @@ struct VerificPass : public Pass {
struct ReadPass : public Pass {
ReadPass() : Pass("read", "load HDL designs") { }
- void help() YS_OVERRIDE
+ void help() override
{
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
log("\n");
@@ -2663,7 +2661,7 @@ struct ReadPass : public Pass {
log("Verific support. The default is to use Verific if it is available.\n");
log("\n");
}
- void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
+ void execute(std::vector<std::string> args, RTLIL::Design *design) override
{
#ifdef YOSYS_ENABLE_VERIFIC
static bool verific_available = !check_noverific_env();
diff --git a/frontends/verilog/preproc.cc b/frontends/verilog/preproc.cc
index 7905ea598..ea23139e2 100644
--- a/frontends/verilog/preproc.cc
+++ b/frontends/verilog/preproc.cc
@@ -591,7 +591,7 @@ read_define_args()
default:
// The only FSM states are 0-2 and we dealt with 2 at the start of the loop.
- __builtin_unreachable();
+ log_assert(false);
}
}
diff --git a/frontends/verilog/verilog_frontend.cc b/frontends/verilog/verilog_frontend.cc
index 26abe49b5..2e9c9b2e2 100644
--- a/frontends/verilog/verilog_frontend.cc
+++ b/frontends/verilog/verilog_frontend.cc
@@ -67,7 +67,7 @@ static void add_package_types(dict<std::string, AST::AstNode *> &user_types, std
struct VerilogFrontend : public Frontend {
VerilogFrontend() : Frontend("verilog", "read modules from Verilog file") { }
- void help() YS_OVERRIDE
+ void help() override
{
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
log("\n");
@@ -232,7 +232,7 @@ struct VerilogFrontend : public Frontend {
log("supported by the Yosys Verilog front-end.\n");
log("\n");
}
- void execute(std::istream *&f, std::string filename, std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
+ void execute(std::istream *&f, std::string filename, std::vector<std::string> args, RTLIL::Design *design) override
{
bool flag_dump_ast1 = false;
bool flag_dump_ast2 = false;
@@ -503,7 +503,7 @@ struct VerilogFrontend : public Frontend {
struct VerilogDefaults : public Pass {
VerilogDefaults() : Pass("verilog_defaults", "set default options for read_verilog") { }
- void help() YS_OVERRIDE
+ void help() override
{
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
log("\n");
@@ -524,7 +524,7 @@ struct VerilogDefaults : public Pass {
log("not imply -clear.\n");
log("\n");
}
- void execute(std::vector<std::string> args, RTLIL::Design*) YS_OVERRIDE
+ void execute(std::vector<std::string> args, RTLIL::Design*) override
{
if (args.size() < 2)
cmd_error(args, 1, "Missing argument.");
@@ -561,7 +561,7 @@ struct VerilogDefaults : public Pass {
struct VerilogDefines : public Pass {
VerilogDefines() : Pass("verilog_defines", "define and undefine verilog defines") { }
- void help() YS_OVERRIDE
+ void help() override
{
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
log("\n");
@@ -583,7 +583,7 @@ struct VerilogDefines : public Pass {
log(" list currently defined preprocessor symbols\n");
log("\n");
}
- void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
+ void execute(std::vector<std::string> args, RTLIL::Design *design) override
{
size_t argidx;
for (argidx = 1; argidx < args.size(); argidx++) {
diff --git a/frontends/verilog/verilog_lexer.l b/frontends/verilog/verilog_lexer.l
index f6a3ac4db..f2241066f 100644
--- a/frontends/verilog/verilog_lexer.l
+++ b/frontends/verilog/verilog_lexer.l
@@ -48,16 +48,18 @@ USING_YOSYS_NAMESPACE
using namespace AST;
using namespace VERILOG_FRONTEND;
+#define YYSTYPE FRONTEND_VERILOG_YYSTYPE
+#define YYLTYPE FRONTEND_VERILOG_YYLTYPE
+
YOSYS_NAMESPACE_BEGIN
namespace VERILOG_FRONTEND {
std::vector<std::string> fn_stack;
std::vector<int> ln_stack;
+ YYLTYPE real_location;
+ YYLTYPE old_location;
}
YOSYS_NAMESPACE_END
-#define YYSTYPE FRONTEND_VERILOG_YYSTYPE
-#define YYLTYPE FRONTEND_VERILOG_YYLTYPE
-
#define SV_KEYWORD(_tok) \
if (sv_mode) return _tok; \
log("Lexer warning: The SystemVerilog keyword `%s' (at %s:%d) is not "\
@@ -73,9 +75,6 @@ YOSYS_NAMESPACE_END
#define YY_INPUT(buf,result,max_size) \
result = readsome(*VERILOG_FRONTEND::lexin, buf, max_size)
-YYLTYPE real_location;
-YYLTYPE old_location;
-
#define YY_USER_ACTION \
old_location = real_location; \
real_location.first_line = real_location.last_line; \
@@ -128,7 +127,9 @@ static bool isUserType(std::string &s)
%x BASED_CONST
%%
- int comment_caller;
+ // Initialise comment_caller to something to avoid a "maybe undefined"
+ // warning from GCC.
+ int comment_caller = INITIAL;
<INITIAL,SYNOPSYS_TRANSLATE_OFF>"`file_push "[^\n]* {
fn_stack.push_back(current_filename);
@@ -262,7 +263,10 @@ static bool isUserType(std::string &s)
"final" { SV_KEYWORD(TOK_FINAL); }
"logic" { SV_KEYWORD(TOK_LOGIC); }
"var" { SV_KEYWORD(TOK_VAR); }
-"bit" { SV_KEYWORD(TOK_REG); }
+"bit" { SV_KEYWORD(TOK_LOGIC); }
+"int" { SV_KEYWORD(TOK_INT); }
+"byte" { SV_KEYWORD(TOK_BYTE); }
+"shortint" { SV_KEYWORD(TOK_SHORTINT); }
"eventually" { if (formal_mode) return TOK_EVENTUALLY; SV_KEYWORD(TOK_EVENTUALLY); }
"s_eventually" { if (formal_mode) return TOK_EVENTUALLY; SV_KEYWORD(TOK_EVENTUALLY); }
@@ -276,11 +280,15 @@ static bool isUserType(std::string &s)
"reg" { return TOK_REG; }
"integer" { return TOK_INTEGER; }
"signed" { return TOK_SIGNED; }
+"unsigned" { SV_KEYWORD(TOK_UNSIGNED); }
"genvar" { return TOK_GENVAR; }
"real" { return TOK_REAL; }
"enum" { SV_KEYWORD(TOK_ENUM); }
"typedef" { SV_KEYWORD(TOK_TYPEDEF); }
+"struct" { SV_KEYWORD(TOK_STRUCT); }
+"union" { SV_KEYWORD(TOK_UNION); }
+"packed" { SV_KEYWORD(TOK_PACKED); }
[0-9][0-9_]* {
yylval->string = new std::string(yytext);
@@ -509,6 +517,8 @@ import[ \t\r\n]+\"(DPI|DPI-C)\"[ \t\r\n]+function[ \t\r\n]+ {
"<<<" { return OP_SSHL; }
">>>" { return OP_SSHR; }
+"'" { return OP_CAST; }
+
"::" { return TOK_PACKAGESEP; }
"++" { return TOK_INCREMENT; }
"--" { return TOK_DECREMENT; }
@@ -518,6 +528,12 @@ import[ \t\r\n]+\"(DPI|DPI-C)\"[ \t\r\n]+function[ \t\r\n]+ {
".*" { return TOK_WILDCARD_CONNECT; }
+"|=" { SV_KEYWORD(TOK_OR_ASSIGN); }
+"&=" { SV_KEYWORD(TOK_AND_ASSIGN); }
+"+=" { SV_KEYWORD(TOK_PLUS_ASSIGN); }
+"-=" { SV_KEYWORD(TOK_SUB_ASSIGN); }
+"^=" { SV_KEYWORD(TOK_XOR_ASSIGN); }
+
[-+]?[=*]> {
if (!specify_mode) REJECT;
yylval->string = new std::string(yytext);
diff --git a/frontends/verilog/verilog_parser.y b/frontends/verilog/verilog_parser.y
index f250d7685..656910c0c 100644
--- a/frontends/verilog/verilog_parser.y
+++ b/frontends/verilog/verilog_parser.y
@@ -161,6 +161,23 @@ static bool isInLocalScope(const std::string *name)
return (user_types->count(*name) > 0);
}
+static AstNode *getTypeDefinitionNode(std::string type_name)
+{
+ // return the definition nodes from the typedef statement
+ auto user_types = user_type_stack.back();
+ log_assert(user_types->count(type_name) > 0);
+ auto typedef_node = (*user_types)[type_name];
+ log_assert(typedef_node->type == AST_TYPEDEF);
+ return typedef_node->children[0];
+}
+
+static AstNode *copyTypeDefinition(std::string type_name)
+{
+ // return a copy of the template from a typedef definition
+ auto typedef_node = getTypeDefinitionNode(type_name);
+ return typedef_node->clone();
+}
+
static AstNode *makeRange(int msb = 31, int lsb = 0, bool isSigned = true)
{
auto range = new AstNode(AST_RANGE);
@@ -175,6 +192,35 @@ static void addRange(AstNode *parent, int msb = 31, int lsb = 0, bool isSigned =
auto range = makeRange(msb, lsb, isSigned);
parent->children.push_back(range);
}
+
+static AstNode *checkRange(AstNode *type_node, AstNode *range_node)
+{
+ if (type_node->range_left >= 0 && type_node->range_right >= 0) {
+ // type already restricts the range
+ if (range_node) {
+ frontend_verilog_yyerror("integer/genvar types cannot have packed dimensions.");
+ }
+ else {
+ range_node = makeRange(type_node->range_left, type_node->range_right, false);
+ }
+ }
+ if (range_node && range_node->children.size() != 2) {
+ frontend_verilog_yyerror("wire/reg/logic packed dimension must be of the form: [<expr>:<expr>], [<expr>+:<expr>], or [<expr>-:<expr>]");
+ }
+ return range_node;
+}
+
+static void rewriteAsMemoryNode(AstNode *node, AstNode *rangeNode)
+{
+ node->type = AST_MEMORY;
+ if (rangeNode->type == AST_RANGE && rangeNode->children.size() == 1) {
+ // SV array size [n], rewrite as [n-1:0]
+ rangeNode->children[0] = new AstNode(AST_SUB, rangeNode->children[0], AstNode::mkconst_int(1, true));
+ rangeNode->children.push_back(AstNode::mkconst_int(0, false));
+ }
+ node->children.push_back(rangeNode);
+}
+
%}
%define api.prefix {frontend_verilog_yy}
@@ -210,7 +256,7 @@ static void addRange(AstNode *parent, int msb = 31, int lsb = 0, bool isSigned =
%token TOK_PACKAGE TOK_ENDPACKAGE TOK_PACKAGESEP
%token TOK_INTERFACE TOK_ENDINTERFACE TOK_MODPORT TOK_VAR TOK_WILDCARD_CONNECT
%token TOK_INPUT TOK_OUTPUT TOK_INOUT TOK_WIRE TOK_WAND TOK_WOR TOK_REG TOK_LOGIC
-%token TOK_INTEGER TOK_SIGNED TOK_ASSIGN TOK_ALWAYS TOK_INITIAL
+%token TOK_INTEGER TOK_SIGNED TOK_ASSIGN TOK_PLUS_ASSIGN TOK_ALWAYS TOK_INITIAL
%token TOK_ALWAYS_FF TOK_ALWAYS_COMB TOK_ALWAYS_LATCH
%token TOK_BEGIN TOK_END TOK_IF TOK_ELSE TOK_FOR TOK_WHILE TOK_REPEAT
%token TOK_DPI_FUNCTION TOK_POSEDGE TOK_NEGEDGE TOK_OR TOK_AUTOMATIC
@@ -223,14 +269,17 @@ static void addRange(AstNode *parent, int msb = 31, int lsb = 0, bool isSigned =
%token TOK_POS_INDEXED TOK_NEG_INDEXED TOK_PROPERTY TOK_ENUM TOK_TYPEDEF
%token TOK_RAND TOK_CONST TOK_CHECKER TOK_ENDCHECKER TOK_EVENTUALLY
%token TOK_INCREMENT TOK_DECREMENT TOK_UNIQUE TOK_PRIORITY
+%token TOK_STRUCT TOK_PACKED TOK_UNSIGNED TOK_INT TOK_BYTE TOK_SHORTINT TOK_UNION
+%token TOK_OR_ASSIGN TOK_XOR_ASSIGN TOK_AND_ASSIGN TOK_SUB_ASSIGN
%type <ast> range range_or_multirange non_opt_range non_opt_multirange range_or_signed_int
%type <ast> wire_type expr basic_expr concat_list rvalue lvalue lvalue_concat_list
%type <string> opt_label opt_sva_label tok_prim_wrapper hierarchical_id hierarchical_type_id integral_number
%type <string> type_name
-%type <ast> opt_enum_init
+%type <ast> opt_enum_init enum_type struct_type non_wire_data_type
%type <boolean> opt_signed opt_property unique_case_attr always_comb_or_latch always_or_always_ff
%type <al> attr case_attr
+%type <ast> struct_union
%type <specify_target_ptr> specify_target
%type <specify_triple_ptr> specify_triple specify_opt_triple
@@ -250,6 +299,7 @@ static void addRange(AstNode *parent, int msb = 31, int lsb = 0, bool isSigned =
%left '+' '-'
%left '*' '/' '%'
%left OP_POW
+%left OP_CAST
%right UNARY_OPS
%define parse.error verbose
@@ -387,7 +437,7 @@ module:
mod->str = *$4;
append_attr(mod, $1);
delete $4;
- } module_para_opt module_args_opt ';' module_body TOK_ENDMODULE {
+ } module_para_opt module_args_opt ';' module_body TOK_ENDMODULE opt_label {
if (port_stubs.size() != 0)
frontend_verilog_yyerror("Missing details for module port `%s'.",
port_stubs.begin()->first.c_str());
@@ -508,7 +558,7 @@ package:
current_ast_mod = mod;
mod->str = *$4;
append_attr(mod, $1);
- } ';' package_body TOK_ENDPACKAGE {
+ } ';' package_body TOK_ENDPACKAGE opt_label {
ast_stack.pop_back();
current_ast_mod = NULL;
exitTypeScope();
@@ -520,9 +570,10 @@ package_body:
;
package_body_stmt:
- typedef_decl |
- localparam_decl |
- param_decl;
+ typedef_decl
+ | localparam_decl
+ | param_decl
+ ;
interface:
TOK_INTERFACE {
@@ -582,6 +633,7 @@ wire_type_token_list:
astbuf3->is_custom_type = true;
astbuf3->children.push_back(new AstNode(AST_WIRETYPE));
astbuf3->children.back()->str = *$1;
+ delete $1;
};
wire_type_token_io:
@@ -682,15 +734,9 @@ range_or_multirange:
non_opt_multirange { $$ = $1; };
range_or_signed_int:
- range {
- $$ = $1;
- } |
- TOK_INTEGER {
- $$ = new AstNode(AST_RANGE);
- $$->children.push_back(AstNode::mkconst_int(31, true));
- $$->children.push_back(AstNode::mkconst_int(0, true));
- $$->is_signed = true;
- };
+ range { $$ = $1; }
+ | TOK_INTEGER { $$ = makeRange(); }
+ ;
module_body:
module_body module_body_stmt |
@@ -700,8 +746,8 @@ module_body:
module_body_stmt:
task_func_decl | specify_block | param_decl | localparam_decl | typedef_decl | defparam_decl | specparam_declaration | wire_decl | assign_stmt | cell_stmt |
- enum_decl |
- always_stmt | TOK_GENERATE module_gen_body TOK_ENDGENERATE | defattr | assert_property | checker_decl | ignored_specify_block;
+ enum_decl | struct_decl |
+ always_stmt | TOK_GENERATE module_gen_body TOK_ENDGENERATE | defattr | assert_property | checker_decl | ignored_specify_block | /* empty statement */ ';';
checker_decl:
TOK_CHECKER TOK_ID ';' {
@@ -841,18 +887,7 @@ task_func_port:
}
albuf = $1;
astbuf1 = $2;
- astbuf2 = $3;
- if (astbuf1->range_left >= 0 && astbuf1->range_right >= 0) {
- if (astbuf2) {
- frontend_verilog_yyerror("integer/genvar types cannot have packed dimensions (task/function arguments)");
- } else {
- astbuf2 = new AstNode(AST_RANGE);
- astbuf2->children.push_back(AstNode::mkconst_int(astbuf1->range_left, true));
- astbuf2->children.push_back(AstNode::mkconst_int(astbuf1->range_right, true));
- }
- }
- if (astbuf2 && astbuf2->children.size() != 2)
- frontend_verilog_yyerror("task/function argument range must be of the form: [<expr>:<expr>], [<expr>+:<expr>], or [<expr>-:<expr>]");
+ astbuf2 = checkRange(astbuf1, $3);
} wire_name |
{
if (!astbuf1) {
@@ -1296,6 +1331,8 @@ ignspec_id:
param_signed:
TOK_SIGNED {
astbuf1->is_signed = true;
+ } | TOK_UNSIGNED {
+ astbuf1->is_signed = false;
} | /* empty */;
param_integer:
@@ -1306,14 +1343,14 @@ param_integer:
astbuf1->children.back()->children.push_back(AstNode::mkconst_int(31, true));
astbuf1->children.back()->children.push_back(AstNode::mkconst_int(0, true));
astbuf1->is_signed = true;
- } | /* empty */;
+ }
param_real:
TOK_REAL {
if (astbuf1->children.size() != 1)
frontend_verilog_yyerror("Parameter already declared as integer, cannot set to real.");
astbuf1->children.push_back(new AstNode(AST_REALVALUE));
- } | /* empty */;
+ }
param_range:
range {
@@ -1324,8 +1361,12 @@ param_range:
}
};
+param_integer_type: param_integer param_signed
+param_range_type: type_vec param_signed param_range
+param_implicit_type: param_signed param_range
+
param_type:
- param_signed param_integer param_real param_range |
+ param_integer_type | param_real | param_range_type | param_implicit_type |
hierarchical_type_id {
astbuf1->is_custom_type = true;
astbuf1->children.push_back(new AstNode(AST_WIRETYPE));
@@ -1387,6 +1428,10 @@ single_defparam_decl:
ast_stack.back()->children.push_back(node);
};
+/////////
+// enum
+/////////
+
enum_type: TOK_ENUM {
static int enum_count;
// create parent node for the enum
@@ -1397,31 +1442,40 @@ enum_type: TOK_ENUM {
// create the template for the names
astbuf1 = new AstNode(AST_ENUM_ITEM);
astbuf1->children.push_back(AstNode::mkconst_int(0, true));
- } param_signed enum_base_type '{' enum_name_list '}' { // create template for the enum vars
- auto tnode = astbuf1->clone();
- delete astbuf1;
- astbuf1 = tnode;
- tnode->type = AST_WIRE;
- tnode->attributes[ID::enum_type] = AstNode::mkconst_str(astbuf2->str);
- // drop constant but keep any range
- delete tnode->children[0];
- tnode->children.erase(tnode->children.begin()); }
+ } enum_base_type '{' enum_name_list '}' { // create template for the enum vars
+ auto tnode = astbuf1->clone();
+ delete astbuf1;
+ astbuf1 = tnode;
+ tnode->type = AST_WIRE;
+ tnode->attributes[ID::enum_type] = AstNode::mkconst_str(astbuf2->str);
+ // drop constant but keep any range
+ delete tnode->children[0];
+ tnode->children.erase(tnode->children.begin());
+ $$ = astbuf1; }
;
-enum_base_type: int_vec param_range
- | int_atom
- | /* nothing */ {astbuf1->is_reg = true; addRange(astbuf1); }
+enum_base_type: type_atom type_signing
+ | type_vec type_signing range { if ($3) astbuf1->children.push_back($3); }
+ | /* nothing */ { astbuf1->is_reg = true; addRange(astbuf1); }
;
-int_atom: TOK_INTEGER {astbuf1->is_reg=true; addRange(astbuf1); } // probably should do byte, range [7:0] here
+type_atom: TOK_INTEGER { astbuf1->is_reg = true; addRange(astbuf1); } // 4-state signed
+ | TOK_INT { astbuf1->is_reg = true; addRange(astbuf1); } // 2-state signed
+ | TOK_SHORTINT { astbuf1->is_reg = true; addRange(astbuf1, 15, 0); } // 2-state signed
+ | TOK_BYTE { astbuf1->is_reg = true; addRange(astbuf1, 7, 0); } // 2-state signed
;
-int_vec: TOK_REG {astbuf1->is_reg = true;}
- | TOK_LOGIC {astbuf1->is_logic = true;}
+type_vec: TOK_REG { astbuf1->is_reg = true; } // unsigned
+ | TOK_LOGIC { astbuf1->is_logic = true; } // unsigned
;
-enum_name_list:
- enum_name_decl
+type_signing:
+ TOK_SIGNED { astbuf1->is_signed = true; }
+ | TOK_UNSIGNED { astbuf1->is_signed = false; }
+ | // optional
+ ;
+
+enum_name_list: enum_name_decl
| enum_name_list ',' enum_name_decl
;
@@ -1433,8 +1487,9 @@ enum_name_decl:
auto node = astbuf1->clone();
node->str = *$1;
delete $1;
+ SET_AST_NODE_LOC(node, @1, @1);
delete node->children[0];
- node->children[0] = $2 ?: new AstNode(AST_NONE);
+ node->children[0] = $2 ? $2 : new AstNode(AST_NONE);
astbuf2->children.push_back(node);
}
;
@@ -1456,32 +1511,122 @@ enum_var: TOK_ID {
ast_stack.back()->children.push_back(node);
node->str = *$1;
delete $1;
+ SET_AST_NODE_LOC(node, @1, @1);
node->is_enum = true;
}
;
-enum_decl: enum_type enum_var_list ';' {
- //enum_type creates astbuf1 for use by typedef only
- delete astbuf1;
- }
+enum_decl: enum_type enum_var_list ';' { delete $1; }
+ ;
+
+//////////////////
+// struct or union
+//////////////////
+
+struct_decl: struct_type struct_var_list ';' { delete astbuf2; }
;
+struct_type: struct_union { astbuf2 = $1; } struct_body { $$ = astbuf2; }
+ ;
+
+struct_union:
+ TOK_STRUCT { $$ = new AstNode(AST_STRUCT); }
+ | TOK_UNION { $$ = new AstNode(AST_UNION); }
+ ;
+
+struct_body: opt_packed '{' struct_member_list '}'
+ ;
+
+opt_packed: TOK_PACKED opt_signed_struct
+ | { frontend_verilog_yyerror("Only PACKED supported at this time"); }
+ ;
+
+opt_signed_struct:
+ TOK_SIGNED { astbuf2->is_signed = true; }
+ | TOK_UNSIGNED { astbuf2->is_signed = false; }
+ | // default is unsigned
+ ;
+
+struct_member_list: struct_member
+ | struct_member_list struct_member
+ ;
+
+struct_member: struct_member_type member_name_list ';' { delete astbuf1; }
+ ;
+
+member_name_list:
+ member_name
+ | member_name_list ',' member_name
+ ;
+
+member_name: TOK_ID {
+ astbuf1->str = $1->substr(1);
+ delete $1;
+ astbuf3 = astbuf1->clone();
+ SET_AST_NODE_LOC(astbuf3, @1, @1);
+ astbuf2->children.push_back(astbuf3);
+ } range { if ($3) astbuf3->children.push_back($3); }
+ ;
+
+struct_member_type: { astbuf1 = new AstNode(AST_STRUCT_ITEM); } member_type_token
+ ;
+
+member_type_token:
+ member_type
+ | hierarchical_type_id {
+ // use a clone of the typedef definition nodes
+ auto template_node = copyTypeDefinition(*$1);
+ delete $1;
+ switch (template_node->type) {
+ case AST_WIRE:
+ template_node->type = AST_STRUCT_ITEM;
+ break;
+ case AST_STRUCT:
+ case AST_UNION:
+ break;
+ default:
+ frontend_verilog_yyerror("Invalid type for struct member: %s", type2str(template_node->type).c_str());
+ }
+ delete astbuf1;
+ astbuf1 = template_node;
+ }
+ | struct_union {
+ // stash state on ast_stack
+ ast_stack.push_back(astbuf2);
+ astbuf2 = $1;
+ } struct_body {
+ astbuf1 = astbuf2;
+ // recover state
+ astbuf2 = ast_stack.back();
+ ast_stack.pop_back();
+ }
+ ;
+
+member_type: type_atom type_signing
+ | type_vec type_signing range_or_multirange { if ($3) astbuf1->children.push_back($3); }
+ ;
+
+struct_var_list: struct_var
+ | struct_var_list ',' struct_var
+ ;
+
+struct_var: TOK_ID { auto *var_node = astbuf2->clone();
+ var_node->str = *$1;
+ delete $1;
+ SET_AST_NODE_LOC(var_node, @1, @1);
+ ast_stack.back()->children.push_back(var_node);
+ }
+ ;
+
+/////////
+// wire
+/////////
+
wire_decl:
attr wire_type range {
albuf = $1;
astbuf1 = $2;
- astbuf2 = $3;
- if (astbuf1->range_left >= 0 && astbuf1->range_right >= 0) {
- if (astbuf2) {
- frontend_verilog_yyerror("integer/genvar types cannot have packed dimensions.");
- } else {
- astbuf2 = new AstNode(AST_RANGE);
- astbuf2->children.push_back(AstNode::mkconst_int(astbuf1->range_left, true));
- astbuf2->children.push_back(AstNode::mkconst_int(astbuf1->range_right, true));
- }
- }
- if (astbuf2 && astbuf2->children.size() != 2)
- frontend_verilog_yyerror("wire/reg/logic packed dimension must be of the form: [<expr>:<expr>], [<expr>+:<expr>], or [<expr>-:<expr>]");
+ astbuf2 = checkRange(astbuf1, $3);
} delay wire_name_list {
delete astbuf1;
if (astbuf2 != NULL)
@@ -1603,19 +1748,9 @@ wire_name:
if (node->is_input || node->is_output)
frontend_verilog_yyerror("input/output/inout ports cannot have unpacked dimensions.");
if (!astbuf2 && !node->is_custom_type) {
- AstNode *rng = new AstNode(AST_RANGE);
- rng->children.push_back(AstNode::mkconst_int(0, true));
- rng->children.push_back(AstNode::mkconst_int(0, true));
- node->children.push_back(rng);
+ addRange(node, 0, 0, false);
}
- node->type = AST_MEMORY;
- auto *rangeNode = $2;
- if (rangeNode->type == AST_RANGE && rangeNode->children.size() == 1) {
- // SV array size [n], rewrite as [n-1:0]
- rangeNode->children[0] = new AstNode(AST_SUB, rangeNode->children[0], AstNode::mkconst_int(1, true));
- rangeNode->children.push_back(AstNode::mkconst_int(0, false));
- }
- node->children.push_back(rangeNode);
+ rewriteAsMemoryNode(node, $2);
}
if (current_function_or_task == NULL) {
if (do_not_require_port_stubs && (node->is_input || node->is_output) && port_stubs.count(*$1) == 0) {
@@ -1663,42 +1798,23 @@ type_name: TOK_ID // first time seen
typedef_decl:
TOK_TYPEDEF wire_type range type_name range_or_multirange ';' {
astbuf1 = $2;
- astbuf2 = $3;
- if (astbuf1->range_left >= 0 && astbuf1->range_right >= 0) {
- if (astbuf2) {
- frontend_verilog_yyerror("integer/genvar types cannot have packed dimensions.");
- } else {
- astbuf2 = new AstNode(AST_RANGE);
- astbuf2->children.push_back(AstNode::mkconst_int(astbuf1->range_left, true));
- astbuf2->children.push_back(AstNode::mkconst_int(astbuf1->range_right, true));
- }
- }
- if (astbuf2 && astbuf2->children.size() != 2)
- frontend_verilog_yyerror("wire/reg/logic packed dimension must be of the form: [<expr>:<expr>], [<expr>+:<expr>], or [<expr>-:<expr>]");
+ astbuf2 = checkRange(astbuf1, $3);
if (astbuf2)
astbuf1->children.push_back(astbuf2);
if ($5 != NULL) {
if (!astbuf2) {
- AstNode *rng = new AstNode(AST_RANGE);
- rng->children.push_back(AstNode::mkconst_int(0, true));
- rng->children.push_back(AstNode::mkconst_int(0, true));
- astbuf1->children.push_back(rng);
+ addRange(astbuf1, 0, 0, false);
}
- astbuf1->type = AST_MEMORY;
- auto *rangeNode = $5;
- if (rangeNode->type == AST_RANGE && rangeNode->children.size() == 1) {
- // SV array size [n], rewrite as [n-1:0]
- rangeNode->children[0] = new AstNode(AST_SUB, rangeNode->children[0], AstNode::mkconst_int(1, true));
- rangeNode->children.push_back(AstNode::mkconst_int(0, false));
- }
- astbuf1->children.push_back(rangeNode);
+ rewriteAsMemoryNode(astbuf1, $5);
}
- addTypedefNode($4, astbuf1);
- } |
- TOK_TYPEDEF enum_type type_name ';' {
- addTypedefNode($3, astbuf1);
- }
+ addTypedefNode($4, astbuf1); }
+ | TOK_TYPEDEF non_wire_data_type type_name ';' { addTypedefNode($3, $2); }
+ ;
+
+non_wire_data_type:
+ enum_type
+ | struct_type
;
cell_stmt:
@@ -2203,49 +2319,96 @@ assert_property:
};
simple_behavioral_stmt:
- lvalue '=' delay expr {
- AstNode *node = new AstNode(AST_ASSIGN_EQ, $1, $4);
+ attr lvalue '=' delay expr {
+ AstNode *node = new AstNode(AST_ASSIGN_EQ, $2, $5);
ast_stack.back()->children.push_back(node);
- SET_AST_NODE_LOC(node, @1, @4);
+ SET_AST_NODE_LOC(node, @2, @5);
+ append_attr(node, $1);
} |
- lvalue TOK_INCREMENT {
- AstNode *node = new AstNode(AST_ASSIGN_EQ, $1, new AstNode(AST_ADD, $1->clone(), AstNode::mkconst_int(1, true)));
+ attr lvalue TOK_INCREMENT {
+ AstNode *node = new AstNode(AST_ASSIGN_EQ, $2, new AstNode(AST_ADD, $2->clone(), AstNode::mkconst_int(1, true)));
ast_stack.back()->children.push_back(node);
- SET_AST_NODE_LOC(node, @1, @2);
+ SET_AST_NODE_LOC(node, @2, @3);
+ append_attr(node, $1);
} |
- lvalue TOK_DECREMENT {
- AstNode *node = new AstNode(AST_ASSIGN_EQ, $1, new AstNode(AST_SUB, $1->clone(), AstNode::mkconst_int(1, true)));
+ attr lvalue TOK_DECREMENT {
+ AstNode *node = new AstNode(AST_ASSIGN_EQ, $2, new AstNode(AST_SUB, $2->clone(), AstNode::mkconst_int(1, true)));
ast_stack.back()->children.push_back(node);
- SET_AST_NODE_LOC(node, @1, @2);
+ SET_AST_NODE_LOC(node, @2, @3);
+ append_attr(node, $1);
+ } |
+ attr lvalue OP_LE delay expr {
+ AstNode *node = new AstNode(AST_ASSIGN_LE, $2, $5);
+ ast_stack.back()->children.push_back(node);
+ SET_AST_NODE_LOC(node, @2, @5);
+ append_attr(node, $1);
+ } |
+ attr lvalue TOK_XOR_ASSIGN delay expr {
+ AstNode *xor_node = new AstNode(AST_BIT_XOR, $2->clone(), $5);
+ AstNode *node = new AstNode(AST_ASSIGN_EQ, $2, xor_node);
+ SET_AST_NODE_LOC(xor_node, @2, @5);
+ SET_AST_NODE_LOC(node, @2, @5);
+ ast_stack.back()->children.push_back(node);
+ append_attr(node, $1);
+ } |
+ attr lvalue TOK_OR_ASSIGN delay expr {
+ AstNode *or_node = new AstNode(AST_BIT_OR, $2->clone(), $5);
+ SET_AST_NODE_LOC(or_node, @2, @5);
+ AstNode *node = new AstNode(AST_ASSIGN_EQ, $2, or_node);
+ SET_AST_NODE_LOC(node, @2, @5);
+ ast_stack.back()->children.push_back(node);
+ append_attr(node, $1);
+ } |
+ attr lvalue TOK_PLUS_ASSIGN delay expr {
+ AstNode *add_node = new AstNode(AST_ADD, $2->clone(), $5);
+ AstNode *node = new AstNode(AST_ASSIGN_EQ, $2, add_node);
+ SET_AST_NODE_LOC(node, @2, @5);
+ SET_AST_NODE_LOC(add_node, @2, @5);
+ ast_stack.back()->children.push_back(node);
+ append_attr(node, $1);
+ } |
+ attr lvalue TOK_SUB_ASSIGN delay expr {
+ AstNode *sub_node = new AstNode(AST_SUB, $2->clone(), $5);
+ AstNode *node = new AstNode(AST_ASSIGN_EQ, $2, sub_node);
+ SET_AST_NODE_LOC(node, @2, @5);
+ SET_AST_NODE_LOC(sub_node, @2, @5);
+ ast_stack.back()->children.push_back(node);
+ append_attr(node, $1);
} |
- lvalue OP_LE delay expr {
- AstNode *node = new AstNode(AST_ASSIGN_LE, $1, $4);
+ attr lvalue TOK_AND_ASSIGN delay expr {
+ AstNode *and_node = new AstNode(AST_BIT_AND, $2->clone(), $5);
+ AstNode *node = new AstNode(AST_ASSIGN_EQ, $2, and_node);
+ SET_AST_NODE_LOC(node, @2, @5);
+ SET_AST_NODE_LOC(and_node, @2, @5);
ast_stack.back()->children.push_back(node);
- SET_AST_NODE_LOC(node, @1, @4);
+ append_attr(node, $1);
};
// this production creates the obligatory if-else shift/reduce conflict
behavioral_stmt:
defattr | assert | wire_decl | param_decl | localparam_decl | typedef_decl |
non_opt_delay behavioral_stmt |
- simple_behavioral_stmt ';' | ';' |
- hierarchical_id attr {
+ simple_behavioral_stmt ';' |
+ attr ';' {
+ free_attr($1);
+ } |
+ attr hierarchical_id {
AstNode *node = new AstNode(AST_TCALL);
- node->str = *$1;
- delete $1;
+ node->str = *$2;
+ delete $2;
ast_stack.back()->children.push_back(node);
ast_stack.push_back(node);
- append_attr(node, $2);
+ append_attr(node, $1);
} opt_arg_list ';'{
ast_stack.pop_back();
} |
- TOK_MSG_TASKS attr {
+ attr TOK_MSG_TASKS {
AstNode *node = new AstNode(AST_TCALL);
- node->str = *$1;
- delete $1;
+ node->str = *$2;
+ delete $2;
ast_stack.back()->children.push_back(node);
ast_stack.push_back(node);
- append_attr(node, $2);
+ append_attr(node, $1);
} opt_arg_list ';'{
ast_stack.pop_back();
} |
@@ -2342,8 +2505,6 @@ behavioral_stmt:
ast_stack.pop_back();
};
- ;
-
unique_case_attr:
/* empty */ {
$$ = false;
@@ -2438,7 +2599,7 @@ gen_case_item:
} case_select {
case_type_stack.push_back(0);
SET_AST_NODE_LOC(ast_stack.back(), @2, @2);
- } gen_stmt_or_null {
+ } gen_stmt_block {
case_type_stack.pop_back();
ast_stack.pop_back();
};
@@ -2530,7 +2691,10 @@ module_gen_body:
/* empty */;
gen_stmt_or_module_body_stmt:
- gen_stmt | module_body_stmt;
+ gen_stmt | module_body_stmt |
+ attr ';' {
+ free_attr($1);
+ };
// this production creates the obligatory if-else shift/reduce conflict
gen_stmt:
@@ -2552,7 +2716,7 @@ gen_stmt:
AstNode *block = new AstNode(AST_GENBLOCK);
ast_stack.back()->children.push_back(block);
ast_stack.push_back(block);
- } gen_stmt_or_null {
+ } gen_stmt_block {
ast_stack.pop_back();
} opt_gen_else {
SET_AST_NODE_LOC(ast_stack.back(), @1, @7);
@@ -2602,11 +2766,8 @@ gen_stmt_block:
ast_stack.pop_back();
};
-gen_stmt_or_null:
- gen_stmt_block | ';';
-
opt_gen_else:
- TOK_ELSE gen_stmt_or_null | /* empty */ %prec FAKE_THEN;
+ TOK_ELSE gen_stmt_block | /* empty */ %prec FAKE_THEN;
expr:
basic_expr {
@@ -2888,6 +3049,24 @@ basic_expr:
$$ = new AstNode(AST_LOGIC_NOT, $3);
SET_AST_NODE_LOC($$, @1, @3);
append_attr($$, $2);
+ } |
+ TOK_SIGNED OP_CAST '(' expr ')' {
+ if (!sv_mode)
+ frontend_verilog_yyerror("Static cast is only supported in SystemVerilog mode.");
+ $$ = new AstNode(AST_TO_SIGNED, $4);
+ SET_AST_NODE_LOC($$, @1, @4);
+ } |
+ TOK_UNSIGNED OP_CAST '(' expr ')' {
+ if (!sv_mode)
+ frontend_verilog_yyerror("Static cast is only supported in SystemVerilog mode.");
+ $$ = new AstNode(AST_TO_UNSIGNED, $4);
+ SET_AST_NODE_LOC($$, @1, @4);
+ } |
+ basic_expr OP_CAST '(' expr ')' {
+ if (!sv_mode)
+ frontend_verilog_yyerror("Static cast is only supported in SystemVerilog mode.");
+ $$ = new AstNode(AST_CAST_SIZE, $1, $4);
+ SET_AST_NODE_LOC($$, @1, @4);
};
concat_list:
diff --git a/kernel/calc.cc b/kernel/calc.cc
index 4a4840771..ae18809d3 100644
--- a/kernel/calc.cc
+++ b/kernel/calc.cc
@@ -489,6 +489,7 @@ RTLIL::Const RTLIL::const_mul(const RTLIL::Const &arg1, const RTLIL::Const &arg2
return big2const(y, result_len >= 0 ? result_len : max(arg1.bits.size(), arg2.bits.size()), min(undef_bit_pos, 0));
}
+// truncating division
RTLIL::Const RTLIL::const_div(const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len)
{
int undef_bit_pos = -1;
@@ -502,6 +503,7 @@ RTLIL::Const RTLIL::const_div(const RTLIL::Const &arg1, const RTLIL::Const &arg2
return big2const(result_neg ? -(a / b) : (a / b), result_len >= 0 ? result_len : max(arg1.bits.size(), arg2.bits.size()), min(undef_bit_pos, 0));
}
+// truncating modulo
RTLIL::Const RTLIL::const_mod(const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len)
{
int undef_bit_pos = -1;
@@ -515,6 +517,51 @@ RTLIL::Const RTLIL::const_mod(const RTLIL::Const &arg1, const RTLIL::Const &arg2
return big2const(result_neg ? -(a % b) : (a % b), result_len >= 0 ? result_len : max(arg1.bits.size(), arg2.bits.size()), min(undef_bit_pos, 0));
}
+RTLIL::Const RTLIL::const_divfloor(const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len)
+{
+ int undef_bit_pos = -1;
+ BigInteger a = const2big(arg1, signed1, undef_bit_pos);
+ BigInteger b = const2big(arg2, signed2, undef_bit_pos);
+ if (b.isZero())
+ return RTLIL::Const(RTLIL::State::Sx, result_len);
+
+ bool result_pos = (a.getSign() == BigInteger::negative) == (b.getSign() == BigInteger::negative);
+ a = a.getSign() == BigInteger::negative ? -a : a;
+ b = b.getSign() == BigInteger::negative ? -b : b;
+ BigInteger result;
+
+ if (result_pos || a == 0) {
+ result = a / b;
+ } else {
+ // bigint division with negative numbers is wonky, make sure we only negate at the very end
+ result = -((a + b - 1) / b);
+ }
+ return big2const(result, result_len >= 0 ? result_len : max(arg1.bits.size(), arg2.bits.size()), min(undef_bit_pos, 0));
+}
+
+RTLIL::Const RTLIL::const_modfloor(const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len)
+{
+ int undef_bit_pos = -1;
+ BigInteger a = const2big(arg1, signed1, undef_bit_pos);
+ BigInteger b = const2big(arg2, signed2, undef_bit_pos);
+ if (b.isZero())
+ return RTLIL::Const(RTLIL::State::Sx, result_len);
+
+ BigInteger::Sign a_sign = a.getSign();
+ BigInteger::Sign b_sign = b.getSign();
+ a = a_sign == BigInteger::negative ? -a : a;
+ b = b_sign == BigInteger::negative ? -b : b;
+ BigInteger truncated = a_sign == BigInteger::negative ? -(a % b) : (a % b);
+ BigInteger modulo;
+
+ if (truncated == 0 || (a_sign == b_sign)) {
+ modulo = truncated;
+ } else {
+ modulo = b_sign == BigInteger::negative ? truncated - b : truncated + b;
+ }
+ return big2const(modulo, result_len >= 0 ? result_len : max(arg1.bits.size(), arg2.bits.size()), min(undef_bit_pos, 0));
+}
+
RTLIL::Const RTLIL::const_pow(const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len)
{
int undef_bit_pos = -1;
diff --git a/kernel/celledges.cc b/kernel/celledges.cc
index 54e0168e2..314e7c77e 100644
--- a/kernel/celledges.cc
+++ b/kernel/celledges.cc
@@ -187,7 +187,7 @@ bool YOSYS_NAMESPACE_PREFIX AbstractCellEdgesDatabase::add_edges_from_cell(RTLIL
return true;
}
- // FIXME: $mul $div $mod $slice $concat
+ // FIXME: $mul $div $mod $divfloor $modfloor $slice $concat
// FIXME: $lut $sop $alu $lcu $macc $fa
return false;
diff --git a/kernel/celledges.h b/kernel/celledges.h
index 2cc297cb2..d105e4009 100644
--- a/kernel/celledges.h
+++ b/kernel/celledges.h
@@ -38,7 +38,7 @@ struct FwdCellEdgesDatabase : AbstractCellEdgesDatabase
dict<SigBit, pool<SigBit>> db;
FwdCellEdgesDatabase(SigMap &sigmap) : sigmap(sigmap) { }
- void add_edge(RTLIL::Cell *cell, RTLIL::IdString from_port, int from_bit, RTLIL::IdString to_port, int to_bit, int) YS_OVERRIDE {
+ void add_edge(RTLIL::Cell *cell, RTLIL::IdString from_port, int from_bit, RTLIL::IdString to_port, int to_bit, int) override {
SigBit from_sigbit = sigmap(cell->getPort(from_port)[from_bit]);
SigBit to_sigbit = sigmap(cell->getPort(to_port)[to_bit]);
db[from_sigbit].insert(to_sigbit);
@@ -51,7 +51,7 @@ struct RevCellEdgesDatabase : AbstractCellEdgesDatabase
dict<SigBit, pool<SigBit>> db;
RevCellEdgesDatabase(SigMap &sigmap) : sigmap(sigmap) { }
- void add_edge(RTLIL::Cell *cell, RTLIL::IdString from_port, int from_bit, RTLIL::IdString to_port, int to_bit, int) YS_OVERRIDE {
+ void add_edge(RTLIL::Cell *cell, RTLIL::IdString from_port, int from_bit, RTLIL::IdString to_port, int to_bit, int) override {
SigBit from_sigbit = sigmap(cell->getPort(from_port)[from_bit]);
SigBit to_sigbit = sigmap(cell->getPort(to_port)[to_bit]);
db[to_sigbit].insert(from_sigbit);
diff --git a/kernel/celltypes.h b/kernel/celltypes.h
index 450865ce9..12dea93b8 100644
--- a/kernel/celltypes.h
+++ b/kernel/celltypes.h
@@ -114,7 +114,7 @@ struct CellTypes
ID($and), ID($or), ID($xor), ID($xnor),
ID($shl), ID($shr), ID($sshl), ID($sshr), ID($shift), ID($shiftx),
ID($lt), ID($le), ID($eq), ID($ne), ID($eqx), ID($nex), ID($ge), ID($gt),
- ID($add), ID($sub), ID($mul), ID($div), ID($mod), ID($pow),
+ ID($add), ID($sub), ID($mul), ID($div), ID($mod), ID($divfloor), ID($modfloor), ID($pow),
ID($logic_and), ID($logic_or), ID($concat), ID($macc)
};
@@ -139,8 +139,14 @@ struct CellTypes
setup_type(ID($dff), {ID::CLK, ID::D}, {ID::Q});
setup_type(ID($dffe), {ID::CLK, ID::EN, ID::D}, {ID::Q});
setup_type(ID($dffsr), {ID::CLK, ID::SET, ID::CLR, ID::D}, {ID::Q});
+ setup_type(ID($dffsre), {ID::CLK, ID::SET, ID::CLR, ID::D, ID::E}, {ID::Q});
setup_type(ID($adff), {ID::CLK, ID::ARST, ID::D}, {ID::Q});
+ setup_type(ID($adffe), {ID::CLK, ID::ARST, ID::D, ID::E}, {ID::Q});
+ setup_type(ID($sdff), {ID::CLK, ID::SRST, ID::D}, {ID::Q});
+ setup_type(ID($sdffe), {ID::CLK, ID::SRST, ID::D, ID::E}, {ID::Q});
+ setup_type(ID($sdffce), {ID::CLK, ID::SRST, ID::D, ID::E}, {ID::Q});
setup_type(ID($dlatch), {ID::EN, ID::D}, {ID::Q});
+ setup_type(ID($adlatch), {ID::EN, ID::D, ID::ARST}, {ID::Q});
setup_type(ID($dlatchsr), {ID::EN, ID::SET, ID::CLR, ID::D}, {ID::Q});
}
@@ -210,14 +216,48 @@ struct CellTypes
for (auto c1 : list_np)
for (auto c2 : list_np)
+ for (auto c3 : list_01)
+ for (auto c4 : list_np)
+ setup_type(stringf("$_DFFE_%c%c%c%c_", c1, c2, c3, c4), {ID::C, ID::R, ID::D, ID::E}, {ID::Q});
+
+ for (auto c1 : list_np)
+ for (auto c2 : list_np)
for (auto c3 : list_np)
setup_type(stringf("$_DFFSR_%c%c%c_", c1, c2, c3), {ID::C, ID::S, ID::R, ID::D}, {ID::Q});
for (auto c1 : list_np)
+ for (auto c2 : list_np)
+ for (auto c3 : list_np)
+ for (auto c4 : list_np)
+ setup_type(stringf("$_DFFSRE_%c%c%c%c_", c1, c2, c3, c4), {ID::C, ID::S, ID::R, ID::D, ID::E}, {ID::Q});
+
+ for (auto c1 : list_np)
+ for (auto c2 : list_np)
+ for (auto c3 : list_01)
+ setup_type(stringf("$_SDFF_%c%c%c_", c1, c2, c3), {ID::C, ID::R, ID::D}, {ID::Q});
+
+ for (auto c1 : list_np)
+ for (auto c2 : list_np)
+ for (auto c3 : list_01)
+ for (auto c4 : list_np)
+ setup_type(stringf("$_SDFFE_%c%c%c%c_", c1, c2, c3, c4), {ID::C, ID::R, ID::D, ID::E}, {ID::Q});
+
+ for (auto c1 : list_np)
+ for (auto c2 : list_np)
+ for (auto c3 : list_01)
+ for (auto c4 : list_np)
+ setup_type(stringf("$_SDFFCE_%c%c%c%c_", c1, c2, c3, c4), {ID::C, ID::R, ID::D, ID::E}, {ID::Q});
+
+ for (auto c1 : list_np)
setup_type(stringf("$_DLATCH_%c_", c1), {ID::E, ID::D}, {ID::Q});
for (auto c1 : list_np)
for (auto c2 : list_np)
+ for (auto c3 : list_01)
+ setup_type(stringf("$_DLATCH_%c%c%c_", c1, c2, c3), {ID::E, ID::R, ID::D}, {ID::Q});
+
+ for (auto c1 : list_np)
+ for (auto c2 : list_np)
for (auto c3 : list_np)
setup_type(stringf("$_DLATCHSR_%c%c%c_", c1, c2, c3), {ID::E, ID::S, ID::R, ID::D}, {ID::Q});
}
@@ -304,6 +344,8 @@ struct CellTypes
HANDLE_CELL_TYPE(mul)
HANDLE_CELL_TYPE(div)
HANDLE_CELL_TYPE(mod)
+ HANDLE_CELL_TYPE(divfloor)
+ HANDLE_CELL_TYPE(modfloor)
HANDLE_CELL_TYPE(pow)
HANDLE_CELL_TYPE(pos)
HANDLE_CELL_TYPE(neg)
diff --git a/kernel/constids.inc b/kernel/constids.inc
index 6b40a5908..69bc06d2c 100644
--- a/kernel/constids.inc
+++ b/kernel/constids.inc
@@ -2,13 +2,12 @@ X(A)
X(abc9_box)
X(abc9_box_id)
X(abc9_box_seq)
+X(abc9_bypass)
X(abc9_carry)
X(abc9_flop)
-X(abc9_holes)
-X(abc9_init)
+X(abc9_keep)
X(abc9_lut)
X(abc9_mergeability)
-X(abc9_scc)
X(abc9_scc_id)
X(abcgroup)
X(ABITS)
@@ -80,6 +79,8 @@ X(equiv_merged)
X(equiv_region)
X(extract_order)
X(F)
+X(force_downto)
+X(force_upto)
X(fsm_encoding)
X(fsm_export)
X(FULL)
@@ -157,6 +158,9 @@ X(SRC_EN)
X(SRC_PEN)
X(SRC_POL)
X(SRC_WIDTH)
+X(SRST)
+X(SRST_POLARITY)
+X(SRST_VALUE)
X(STATE_BITS)
X(STATE_NUM)
X(STATE_NUM_LOG2)
@@ -170,6 +174,7 @@ X(techmap_autopurge)
X(_TECHMAP_BITS_CONNMAP_)
X(_TECHMAP_CELLTYPE_)
X(techmap_celltype)
+X(_TECHMAP_FAIL_)
X(techmap_maccmap)
X(_TECHMAP_REPLACE_)
X(techmap_simplemap)
diff --git a/kernel/hashlib.h b/kernel/hashlib.h
index 592d6e577..a523afadd 100644
--- a/kernel/hashlib.h
+++ b/kernel/hashlib.h
@@ -207,6 +207,7 @@ class dict
entry_t() { }
entry_t(const std::pair<K, T> &udata, int next) : udata(udata), next(next) { }
entry_t(std::pair<K, T> &&udata, int next) : udata(std::move(udata)), next(next) { }
+ bool operator<(const entry_t &other) const { return udata.first < other.udata.first; }
};
std::vector<int> hashtable;
@@ -362,6 +363,7 @@ public:
public:
const_iterator() { }
const_iterator operator++() { index--; return *this; }
+ const_iterator operator+=(int amt) { index -= amt; return *this; }
bool operator<(const const_iterator &other) const { return index > other.index; }
bool operator==(const const_iterator &other) const { return index == other.index; }
bool operator!=(const const_iterator &other) const { return index != other.index; }
@@ -379,6 +381,7 @@ public:
public:
iterator() { }
iterator operator++() { index--; return *this; }
+ iterator operator+=(int amt) { index -= amt; return *this; }
bool operator<(const iterator &other) const { return index > other.index; }
bool operator==(const iterator &other) const { return index == other.index; }
bool operator!=(const iterator &other) const { return index != other.index; }
@@ -615,6 +618,15 @@ public:
return !operator==(other);
}
+ unsigned int hash() const {
+ unsigned int h = mkhash_init;
+ for (auto &entry : entries) {
+ h ^= hash_ops<K>::hash(entry.udata.first);
+ h ^= hash_ops<T>::hash(entry.udata.second);
+ }
+ return h;
+ }
+
void reserve(size_t n) { entries.reserve(n); }
size_t size() const { return entries.size(); }
bool empty() const { return entries.empty(); }
diff --git a/kernel/log.cc b/kernel/log.cc
index a21ba480a..1c1d0182e 100644
--- a/kernel/log.cc
+++ b/kernel/log.cc
@@ -42,7 +42,7 @@ std::vector<FILE*> log_files;
std::vector<std::ostream*> log_streams;
std::map<std::string, std::set<std::string>> log_hdump;
std::vector<YS_REGEX_TYPE> log_warn_regexes, log_nowarn_regexes, log_werror_regexes;
-std::vector<std::pair<YS_REGEX_TYPE,LogExpectedItem>> log_expect_log, log_expect_warning, log_expect_error;
+dict<std::string, LogExpectedItem> log_expect_log, log_expect_warning, log_expect_error;
std::set<std::string> log_warnings, log_experimentals, log_experimentals_ignored;
int log_warnings_count = 0;
int log_warnings_count_noexpect = 0;
@@ -181,7 +181,7 @@ void logv(const char *format, va_list ap)
log_warning("Found log message matching -W regex:\n%s", str.c_str());
for (auto &item : log_expect_log)
- if (YS_REGEX_NS::regex_search(linebuffer, item.first))
+ if (YS_REGEX_NS::regex_search(linebuffer, item.second.pattern))
item.second.current_count++;
linebuffer.clear();
@@ -256,7 +256,7 @@ static void logv_warning_with_prefix(const char *prefix,
bool warning_match = false;
for (auto &item : log_expect_warning)
- if (YS_REGEX_NS::regex_search(message, item.first)) {
+ if (YS_REGEX_NS::regex_search(message, item.second.pattern)) {
item.second.current_count++;
warning_match = true;
}
@@ -319,7 +319,7 @@ void log_file_info(const std::string &filename, int lineno,
va_end(ap);
}
-YS_ATTRIBUTE(noreturn)
+[[noreturn]]
static void logv_error_with_prefix(const char *prefix,
const char *format, va_list ap)
{
@@ -349,7 +349,7 @@ static void logv_error_with_prefix(const char *prefix,
log_error_atexit();
for (auto &item : log_expect_error)
- if (YS_REGEX_NS::regex_search(log_last_error, item.first))
+ if (YS_REGEX_NS::regex_search(log_last_error, item.second.pattern))
item.second.current_count++;
if (check_expected_logs)
@@ -672,31 +672,31 @@ void log_check_expected()
for (auto &item : log_expect_warning) {
if (item.second.current_count == 0) {
log_warn_regexes.clear();
- log_error("Expected warning pattern '%s' not found !\n", item.second.pattern.c_str());
+ log_error("Expected warning pattern '%s' not found !\n", item.first.c_str());
}
if (item.second.current_count != item.second.expected_count) {
log_warn_regexes.clear();
log_error("Expected warning pattern '%s' found %d time(s), instead of %d time(s) !\n",
- item.second.pattern.c_str(), item.second.current_count, item.second.expected_count);
+ item.first.c_str(), item.second.current_count, item.second.expected_count);
}
}
for (auto &item : log_expect_log) {
if (item.second.current_count == 0) {
log_warn_regexes.clear();
- log_error("Expected log pattern '%s' not found !\n", item.second.pattern.c_str());
+ log_error("Expected log pattern '%s' not found !\n", item.first.c_str());
}
if (item.second.current_count != item.second.expected_count) {
log_warn_regexes.clear();
log_error("Expected log pattern '%s' found %d time(s), instead of %d time(s) !\n",
- item.second.pattern.c_str(), item.second.current_count, item.second.expected_count);
+ item.first.c_str(), item.second.current_count, item.second.expected_count);
}
}
for (auto &item : log_expect_error)
if (item.second.current_count == item.second.expected_count) {
log_warn_regexes.clear();
- log("Expected error pattern '%s' found !!!\n", item.second.pattern.c_str());
+ log("Expected error pattern '%s' found !!!\n", item.first.c_str());
#ifdef EMSCRIPTEN
throw 0;
#elif defined(_MSC_VER)
@@ -707,7 +707,7 @@ void log_check_expected()
} else {
display_error_log_msg = false;
log_warn_regexes.clear();
- log_error("Expected error pattern '%s' not found !\n", item.second.pattern.c_str());
+ log_error("Expected error pattern '%s' not found !\n", item.first.c_str());
}
}
diff --git a/kernel/log.h b/kernel/log.h
index dee5d44d7..8981c4cde 100644
--- a/kernel/log.h
+++ b/kernel/log.h
@@ -55,7 +55,9 @@
#else
# include <sys/time.h>
# include <sys/resource.h>
-# include <signal.h>
+# if defined(__unix__) || (defined(__APPLE__) && defined(__MACH__))
+# include <signal.h>
+# endif
#endif
#if defined(_MSC_VER)
@@ -86,7 +88,7 @@ YOSYS_NAMESPACE_BEGIN
# endif
# if __has_builtin(__builtin_debugtrap)
# define YS_DEBUGTRAP __builtin_debugtrap()
-# elif defined(__unix__)
+# elif defined(__unix__) || (defined(__APPLE__) && defined(__MACH__))
# define YS_DEBUGTRAP raise(SIGTRAP)
# else
# define YS_DEBUGTRAP do {} while(0)
@@ -97,11 +99,11 @@ YOSYS_NAMESPACE_BEGIN
// if a debugger is attached, and does nothing otherwise.
#if defined(_WIN32)
# define YS_DEBUGTRAP_IF_DEBUGGING do { if (IsDebuggerPresent()) DebugBreak(); } while(0)
-#elif defined(__unix__)
+# elif defined(__unix__) || (defined(__APPLE__) && defined(__MACH__))
// There is no reliable (or portable) *nix equivalent of IsDebuggerPresent(). However,
// debuggers will stop when SIGTRAP is raised, even if the action is set to ignore.
# define YS_DEBUGTRAP_IF_DEBUGGING do { \
- sighandler_t old = signal(SIGTRAP, SIG_IGN); raise(SIGTRAP); signal(SIGTRAP, old); \
+ auto old = signal(SIGTRAP, SIG_IGN); raise(SIGTRAP); signal(SIGTRAP, old); \
} while(0)
#else
# define YS_DEBUGTRAP_IF_DEBUGGING do {} while(0)
@@ -137,7 +139,7 @@ void logv(const char *format, va_list ap);
void logv_header(RTLIL::Design *design, const char *format, va_list ap);
void logv_warning(const char *format, va_list ap);
void logv_warning_noprefix(const char *format, va_list ap);
-YS_NORETURN void logv_error(const char *format, va_list ap) YS_ATTRIBUTE(noreturn);
+[[noreturn]] void logv_error(const char *format, va_list ap);
void log(const char *format, ...) YS_ATTRIBUTE(format(printf, 1, 2));
void log_header(RTLIL::Design *design, const char *format, ...) YS_ATTRIBUTE(format(printf, 2, 3));
@@ -149,17 +151,16 @@ void log_file_warning(const std::string &filename, int lineno, const char *forma
void log_file_info(const std::string &filename, int lineno, const char *format, ...) YS_ATTRIBUTE(format(printf, 3, 4));
void log_warning_noprefix(const char *format, ...) YS_ATTRIBUTE(format(printf, 1, 2));
-YS_NORETURN void log_error(const char *format, ...) YS_ATTRIBUTE(format(printf, 1, 2), noreturn);
-void log_file_error(const string &filename, int lineno, const char *format, ...) YS_ATTRIBUTE(format(printf, 3, 4), noreturn);
-YS_NORETURN void log_cmd_error(const char *format, ...) YS_ATTRIBUTE(format(printf, 1, 2), noreturn);
+[[noreturn]] void log_error(const char *format, ...) YS_ATTRIBUTE(format(printf, 1, 2));
+[[noreturn]] void log_file_error(const string &filename, int lineno, const char *format, ...) YS_ATTRIBUTE(format(printf, 3, 4));
+[[noreturn]] void log_cmd_error(const char *format, ...) YS_ATTRIBUTE(format(printf, 1, 2));
#ifndef NDEBUG
static inline bool ys_debug(int n = 0) { if (log_force_debug) return true; log_debug_suppressed += n; return false; }
-# define log_debug(...) do { if (ys_debug(1)) log(__VA_ARGS__); } while (0)
#else
static inline bool ys_debug(int = 0) { return false; }
-# define log_debug(_fmt, ...) do { } while (0)
#endif
+# define log_debug(...) do { if (ys_debug(1)) log(__VA_ARGS__); } while (0)
static inline void log_suppressed() {
if (log_debug_suppressed && !log_make_debug) {
@@ -202,19 +203,16 @@ void log_flush();
struct LogExpectedItem
{
- LogExpectedItem(std::string pattern, int expected) :
- expected_count(expected),
- current_count(0),
- pattern(pattern)
- {
- }
+ LogExpectedItem(const YS_REGEX_TYPE &pat, int expected) :
+ pattern(pat), expected_count(expected), current_count(0) {}
+ LogExpectedItem() : expected_count(0), current_count(0) {}
+ YS_REGEX_TYPE pattern;
int expected_count;
int current_count;
- std::string pattern;
};
-extern std::vector<std::pair<YS_REGEX_TYPE,LogExpectedItem>> log_expect_log, log_expect_warning, log_expect_error;
+extern dict<std::string, LogExpectedItem> log_expect_log, log_expect_warning, log_expect_error;
void log_check_expected();
const char *log_signal(const RTLIL::SigSpec &sig, bool autoint = true);
@@ -237,7 +235,7 @@ static inline void log_assert_worker(bool cond, const char *expr, const char *fi
}
# define log_assert(_assert_expr_) YOSYS_NAMESPACE_PREFIX log_assert_worker(_assert_expr_, #_assert_expr_, __FILE__, __LINE__)
#else
-# define log_assert(_assert_expr_)
+# define log_assert(_assert_expr_) do { if (0) { (void)(_assert_expr_); } } while(0)
#endif
#define log_abort() YOSYS_NAMESPACE_PREFIX log_error("Abort in %s:%d.\n", __FILE__, __LINE__)
@@ -309,19 +307,17 @@ struct PerformanceTimer
static int64_t query() {
# ifdef _WIN32
return 0;
-# elif defined(_POSIX_TIMERS) && (_POSIX_TIMERS > 0)
- struct timespec ts;
- clock_gettime(CLOCK_PROCESS_CPUTIME_ID, &ts);
- return int64_t(ts.tv_sec)*1000000000 + ts.tv_nsec;
# elif defined(RUSAGE_SELF)
struct rusage rusage;
- int64_t t;
- if (getrusage(RUSAGE_SELF, &rusage) == -1) {
- log_cmd_error("getrusage failed!\n");
- log_abort();
+ int64_t t = 0;
+ for (int who : {RUSAGE_SELF, RUSAGE_CHILDREN}) {
+ if (getrusage(who, &rusage) == -1) {
+ log_cmd_error("getrusage failed!\n");
+ log_abort();
+ }
+ t += 1000000000ULL * (int64_t) rusage.ru_utime.tv_sec + (int64_t) rusage.ru_utime.tv_usec * 1000ULL;
+ t += 1000000000ULL * (int64_t) rusage.ru_stime.tv_sec + (int64_t) rusage.ru_stime.tv_usec * 1000ULL;
}
- t = 1000000000ULL * (int64_t) rusage.ru_utime.tv_sec + (int64_t) rusage.ru_utime.tv_usec * 1000ULL;
- t += 1000000000ULL * (int64_t) rusage.ru_stime.tv_sec + (int64_t) rusage.ru_stime.tv_usec * 1000ULL;
return t;
# else
# error "Don't know how to measure per-process CPU time. Need alternative method (times()/clocks()/gettimeofday()?)."
@@ -372,7 +368,7 @@ static inline void log_dump_val_worker(char *v) { log("%s", v); }
static inline void log_dump_val_worker(const char *v) { log("%s", v); }
static inline void log_dump_val_worker(std::string v) { log("%s", v.c_str()); }
static inline void log_dump_val_worker(PerformanceTimer p) { log("%f seconds", p.sec()); }
-static inline void log_dump_args_worker(const char *p YS_ATTRIBUTE(unused)) { log_assert(*p == 0); }
+static inline void log_dump_args_worker(const char *p) { log_assert(*p == 0); }
void log_dump_val_worker(RTLIL::IdString v);
void log_dump_val_worker(RTLIL::SigSpec v);
void log_dump_val_worker(RTLIL::State v);
diff --git a/kernel/macc.h b/kernel/macc.h
index e9f6f05e9..d216e6772 100644
--- a/kernel/macc.h
+++ b/kernel/macc.h
@@ -107,10 +107,8 @@ struct Macc
std::vector<RTLIL::State> config_bits = cell->getParam(ID::CONFIG).bits;
int config_cursor = 0;
-#ifndef NDEBUG
int config_width = cell->getParam(ID::CONFIG_WIDTH).as_int();
log_assert(GetSize(config_bits) >= config_width);
-#endif
int num_bits = 0;
if (config_bits[config_cursor++] == State::S1) num_bits |= 1;
diff --git a/kernel/modtools.h b/kernel/modtools.h
index fbc5482ee..29c510059 100644
--- a/kernel/modtools.h
+++ b/kernel/modtools.h
@@ -158,7 +158,7 @@ struct ModIndex : public RTLIL::Monitor
#endif
}
- void notify_connect(RTLIL::Cell *cell, const RTLIL::IdString &port, const RTLIL::SigSpec &old_sig, const RTLIL::SigSpec &sig) YS_OVERRIDE
+ void notify_connect(RTLIL::Cell *cell, const RTLIL::IdString &port, const RTLIL::SigSpec &old_sig, const RTLIL::SigSpec &sig) override
{
log_assert(module == cell->module);
@@ -169,7 +169,7 @@ struct ModIndex : public RTLIL::Monitor
port_add(cell, port, sig);
}
- void notify_connect(RTLIL::Module *mod YS_ATTRIBUTE(unused), const RTLIL::SigSig &sigsig) YS_OVERRIDE
+ void notify_connect(RTLIL::Module *mod, const RTLIL::SigSig &sigsig) override
{
log_assert(module == mod);
@@ -214,13 +214,13 @@ struct ModIndex : public RTLIL::Monitor
}
}
- void notify_connect(RTLIL::Module *mod YS_ATTRIBUTE(unused), const std::vector<RTLIL::SigSig>&) YS_OVERRIDE
+ void notify_connect(RTLIL::Module *mod, const std::vector<RTLIL::SigSig>&) override
{
log_assert(module == mod);
auto_reload_module = true;
}
- void notify_blackout(RTLIL::Module *mod YS_ATTRIBUTE(unused)) YS_OVERRIDE
+ void notify_blackout(RTLIL::Module *mod) override
{
log_assert(module == mod);
auto_reload_module = true;
diff --git a/kernel/register.cc b/kernel/register.cc
index 02974e534..34735a608 100644
--- a/kernel/register.cc
+++ b/kernel/register.cc
@@ -753,7 +753,7 @@ static struct CellHelpMessages {
struct HelpPass : public Pass {
HelpPass() : Pass("help", "display help messages") { }
- void help() YS_OVERRIDE
+ void help() override
{
log("\n");
log(" help ................ list all commands\n");
@@ -822,7 +822,7 @@ struct HelpPass : public Pass {
fclose(f);
}
- void execute(std::vector<std::string> args, RTLIL::Design*) YS_OVERRIDE
+ void execute(std::vector<std::string> args, RTLIL::Design*) override
{
if (args.size() == 1) {
log("\n");
@@ -926,7 +926,7 @@ struct HelpPass : public Pass {
struct EchoPass : public Pass {
EchoPass() : Pass("echo", "turning echoing back of commands on and off") { }
- void help() YS_OVERRIDE
+ void help() override
{
log("\n");
log(" echo on\n");
@@ -939,7 +939,7 @@ struct EchoPass : public Pass {
log("Do not print all commands to log before executing them. (default)\n");
log("\n");
}
- void execute(std::vector<std::string> args, RTLIL::Design*) YS_OVERRIDE
+ void execute(std::vector<std::string> args, RTLIL::Design*) override
{
if (args.size() > 2)
cmd_error(args, 2, "Unexpected argument.");
@@ -964,7 +964,7 @@ struct MinisatSatSolver : public SatSolver {
MinisatSatSolver() : SatSolver("minisat") {
yosys_satsolver = this;
}
- ezSAT *create() YS_OVERRIDE {
+ ezSAT *create() override {
return new ezMiniSAT();
}
} MinisatSatSolver;
diff --git a/kernel/register.h b/kernel/register.h
index 3d89386b7..5cd849082 100644
--- a/kernel/register.h
+++ b/kernel/register.h
@@ -97,9 +97,9 @@ struct Frontend : Pass
std::string frontend_name;
Frontend(std::string name, std::string short_help = "** document me **");
- void run_register() YS_OVERRIDE;
- ~Frontend() YS_OVERRIDE;
- void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE YS_FINAL;
+ void run_register() override;
+ ~Frontend() override;
+ void execute(std::vector<std::string> args, RTLIL::Design *design) override final;
virtual void execute(std::istream *&f, std::string filename, std::vector<std::string> args, RTLIL::Design *design) = 0;
static std::vector<std::string> next_args;
@@ -113,9 +113,9 @@ struct Backend : Pass
{
std::string backend_name;
Backend(std::string name, std::string short_help = "** document me **");
- void run_register() YS_OVERRIDE;
- ~Backend() YS_OVERRIDE;
- void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE YS_FINAL;
+ void run_register() override;
+ ~Backend() override;
+ void execute(std::vector<std::string> args, RTLIL::Design *design) override final;
virtual void execute(std::ostream *&f, std::string filename, std::vector<std::string> args, RTLIL::Design *design) = 0;
void extra_args(std::ostream *&f, std::string &filename, std::vector<std::string> args, size_t argidx, bool bin_output = false);
@@ -125,7 +125,7 @@ struct Backend : Pass
};
// implemented in passes/cmds/select.cc
-extern void handle_extra_select_args(Pass *pass, std::vector<std::string> args, size_t argidx, size_t args_size, RTLIL::Design *design);
+extern void handle_extra_select_args(Pass *pass, const std::vector<std::string> &args, size_t argidx, size_t args_size, RTLIL::Design *design);
extern RTLIL::Selection eval_select_args(const vector<string> &args, RTLIL::Design *design);
extern void eval_select_op(vector<RTLIL::Selection> &work, const string &op, RTLIL::Design *design);
diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc
index 196e301b6..d7d226942 100644
--- a/kernel/rtlil.cc
+++ b/kernel/rtlil.cc
@@ -54,8 +54,14 @@ const pool<IdString> &RTLIL::builtin_ff_cell_types() {
ID($dff),
ID($dffe),
ID($dffsr),
+ ID($dffsre),
ID($adff),
+ ID($adffe),
+ ID($sdff),
+ ID($sdffe),
+ ID($sdffce),
ID($dlatch),
+ ID($adlatch),
ID($dlatchsr),
ID($_DFFE_NN_),
ID($_DFFE_NP_),
@@ -69,16 +75,102 @@ const pool<IdString> &RTLIL::builtin_ff_cell_types() {
ID($_DFFSR_PNP_),
ID($_DFFSR_PPN_),
ID($_DFFSR_PPP_),
+ ID($_DFFSRE_NNNN_),
+ ID($_DFFSRE_NNNP_),
+ ID($_DFFSRE_NNPN_),
+ ID($_DFFSRE_NNPP_),
+ ID($_DFFSRE_NPNN_),
+ ID($_DFFSRE_NPNP_),
+ ID($_DFFSRE_NPPN_),
+ ID($_DFFSRE_NPPP_),
+ ID($_DFFSRE_PNNN_),
+ ID($_DFFSRE_PNNP_),
+ ID($_DFFSRE_PNPN_),
+ ID($_DFFSRE_PNPP_),
+ ID($_DFFSRE_PPNN_),
+ ID($_DFFSRE_PPNP_),
+ ID($_DFFSRE_PPPN_),
+ ID($_DFFSRE_PPPP_),
+ ID($_DFF_N_),
+ ID($_DFF_P_),
ID($_DFF_NN0_),
ID($_DFF_NN1_),
ID($_DFF_NP0_),
ID($_DFF_NP1_),
- ID($_DFF_N_),
ID($_DFF_PN0_),
ID($_DFF_PN1_),
ID($_DFF_PP0_),
ID($_DFF_PP1_),
- ID($_DFF_P_),
+ ID($_DFFE_NN0N_),
+ ID($_DFFE_NN0P_),
+ ID($_DFFE_NN1N_),
+ ID($_DFFE_NN1P_),
+ ID($_DFFE_NP0N_),
+ ID($_DFFE_NP0P_),
+ ID($_DFFE_NP1N_),
+ ID($_DFFE_NP1P_),
+ ID($_DFFE_PN0N_),
+ ID($_DFFE_PN0P_),
+ ID($_DFFE_PN1N_),
+ ID($_DFFE_PN1P_),
+ ID($_DFFE_PP0N_),
+ ID($_DFFE_PP0P_),
+ ID($_DFFE_PP1N_),
+ ID($_DFFE_PP1P_),
+ ID($_SDFF_NN0_),
+ ID($_SDFF_NN1_),
+ ID($_SDFF_NP0_),
+ ID($_SDFF_NP1_),
+ ID($_SDFF_PN0_),
+ ID($_SDFF_PN1_),
+ ID($_SDFF_PP0_),
+ ID($_SDFF_PP1_),
+ ID($_SDFFE_NN0N_),
+ ID($_SDFFE_NN0P_),
+ ID($_SDFFE_NN1N_),
+ ID($_SDFFE_NN1P_),
+ ID($_SDFFE_NP0N_),
+ ID($_SDFFE_NP0P_),
+ ID($_SDFFE_NP1N_),
+ ID($_SDFFE_NP1P_),
+ ID($_SDFFE_PN0N_),
+ ID($_SDFFE_PN0P_),
+ ID($_SDFFE_PN1N_),
+ ID($_SDFFE_PN1P_),
+ ID($_SDFFE_PP0N_),
+ ID($_SDFFE_PP0P_),
+ ID($_SDFFE_PP1N_),
+ ID($_SDFFE_PP1P_),
+ ID($_SDFFCE_NN0N_),
+ ID($_SDFFCE_NN0P_),
+ ID($_SDFFCE_NN1N_),
+ ID($_SDFFCE_NN1P_),
+ ID($_SDFFCE_NP0N_),
+ ID($_SDFFCE_NP0P_),
+ ID($_SDFFCE_NP1N_),
+ ID($_SDFFCE_NP1P_),
+ ID($_SDFFCE_PN0N_),
+ ID($_SDFFCE_PN0P_),
+ ID($_SDFFCE_PN1N_),
+ ID($_SDFFCE_PN1P_),
+ ID($_SDFFCE_PP0N_),
+ ID($_SDFFCE_PP0P_),
+ ID($_SDFFCE_PP1N_),
+ ID($_SDFFCE_PP1P_),
+ ID($_SR_NN_),
+ ID($_SR_NP_),
+ ID($_SR_PN_),
+ ID($_SR_PP_),
+ ID($_DLATCH_N_),
+ ID($_DLATCH_P_),
+ ID($_DLATCH_NN0_),
+ ID($_DLATCH_NN1_),
+ ID($_DLATCH_NP0_),
+ ID($_DLATCH_NP1_),
+ ID($_DLATCH_PN0_),
+ ID($_DLATCH_PN1_),
+ ID($_DLATCH_PP0_),
+ ID($_DLATCH_PP1_),
ID($_DLATCHSR_NNN_),
ID($_DLATCHSR_NNP_),
ID($_DLATCHSR_NPN_),
@@ -87,8 +179,6 @@ const pool<IdString> &RTLIL::builtin_ff_cell_types() {
ID($_DLATCHSR_PNP_),
ID($_DLATCHSR_PPN_),
ID($_DLATCHSR_PPP_),
- ID($_DLATCH_N_),
- ID($_DLATCH_P_),
ID($_FF_),
};
return res;
@@ -319,7 +409,7 @@ void RTLIL::AttrObject::set_strpool_attribute(RTLIL::IdString id, const pool<str
attrval += "|";
attrval += s;
}
- attributes[id] = RTLIL::Const(attrval);
+ set_string_attribute(id, attrval);
}
void RTLIL::AttrObject::add_strpool_attribute(RTLIL::IdString id, const pool<string> &data)
@@ -334,11 +424,27 @@ pool<string> RTLIL::AttrObject::get_strpool_attribute(RTLIL::IdString id) const
{
pool<string> data;
if (attributes.count(id) != 0)
- for (auto s : split_tokens(attributes.at(id).decode_string(), "|"))
+ for (auto s : split_tokens(get_string_attribute(id), "|"))
data.insert(s);
return data;
}
+void RTLIL::AttrObject::set_hdlname_attribute(const vector<string> &hierarchy)
+{
+ string attrval;
+ for (const auto &ident : hierarchy) {
+ if (!attrval.empty())
+ attrval += " ";
+ attrval += ident;
+ }
+ set_string_attribute(ID::hdlname, attrval);
+}
+
+vector<string> RTLIL::AttrObject::get_hdlname_attribute() const
+{
+ return split_tokens(get_string_attribute(ID::hdlname), " ");
+}
+
bool RTLIL::Selection::selected_module(RTLIL::IdString mod_name) const
{
if (full_selection)
@@ -948,7 +1054,7 @@ namespace {
return;
}
- if (cell->type.in(ID($add), ID($sub), ID($mul), ID($div), ID($mod), ID($pow))) {
+ if (cell->type.in(ID($add), ID($sub), ID($mul), ID($div), ID($mod), ID($divfloor), ID($modfloor), ID($pow))) {
param_bool(ID::A_SIGNED);
param_bool(ID::B_SIGNED);
port(ID::A, param(ID::A_WIDTH));
@@ -1123,6 +1229,21 @@ namespace {
return;
}
+ if (cell->type == ID($dffsre)) {
+ param_bool(ID::CLK_POLARITY);
+ param_bool(ID::SET_POLARITY);
+ param_bool(ID::CLR_POLARITY);
+ param_bool(ID::EN_POLARITY);
+ port(ID::CLK, 1);
+ port(ID::EN, 1);
+ port(ID::SET, param(ID::WIDTH));
+ port(ID::CLR, param(ID::WIDTH));
+ port(ID::D, param(ID::WIDTH));
+ port(ID::Q, param(ID::WIDTH));
+ check_expected();
+ return;
+ }
+
if (cell->type == ID($adff)) {
param_bool(ID::CLK_POLARITY);
param_bool(ID::ARST_POLARITY);
@@ -1135,6 +1256,46 @@ namespace {
return;
}
+ if (cell->type == ID($sdff)) {
+ param_bool(ID::CLK_POLARITY);
+ param_bool(ID::SRST_POLARITY);
+ param_bits(ID::SRST_VALUE, param(ID::WIDTH));
+ port(ID::CLK, 1);
+ port(ID::SRST, 1);
+ port(ID::D, param(ID::WIDTH));
+ port(ID::Q, param(ID::WIDTH));
+ check_expected();
+ return;
+ }
+
+ if (cell->type.in(ID($sdffe), ID($sdffce))) {
+ param_bool(ID::CLK_POLARITY);
+ param_bool(ID::EN_POLARITY);
+ param_bool(ID::SRST_POLARITY);
+ param_bits(ID::SRST_VALUE, param(ID::WIDTH));
+ port(ID::CLK, 1);
+ port(ID::EN, 1);
+ port(ID::SRST, 1);
+ port(ID::D, param(ID::WIDTH));
+ port(ID::Q, param(ID::WIDTH));
+ check_expected();
+ return;
+ }
+
+ if (cell->type == ID($adffe)) {
+ param_bool(ID::CLK_POLARITY);
+ param_bool(ID::EN_POLARITY);
+ param_bool(ID::ARST_POLARITY);
+ param_bits(ID::ARST_VALUE, param(ID::WIDTH));
+ port(ID::CLK, 1);
+ port(ID::EN, 1);
+ port(ID::ARST, 1);
+ port(ID::D, param(ID::WIDTH));
+ port(ID::Q, param(ID::WIDTH));
+ check_expected();
+ return;
+ }
+
if (cell->type == ID($dlatch)) {
param_bool(ID::EN_POLARITY);
port(ID::EN, 1);
@@ -1144,6 +1305,18 @@ namespace {
return;
}
+ if (cell->type == ID($adlatch)) {
+ param_bool(ID::EN_POLARITY);
+ param_bool(ID::ARST_POLARITY);
+ param_bits(ID::ARST_VALUE, param(ID::WIDTH));
+ port(ID::EN, 1);
+ port(ID::ARST, 1);
+ port(ID::D, param(ID::WIDTH));
+ port(ID::Q, param(ID::WIDTH));
+ check_expected();
+ return;
+ }
+
if (cell->type == ID($dlatchsr)) {
param_bool(ID::EN_POLARITY);
param_bool(ID::SET_POLARITY);
@@ -1335,49 +1508,69 @@ namespace {
if (cell->type == ID($_MUX8_)) { port(ID::A,1); port(ID::B,1); port(ID::C,1); port(ID::D,1); port(ID::E,1); port(ID::F,1); port(ID::G,1); port(ID::H,1); port(ID::S,1); port(ID::T,1); port(ID::U,1); port(ID::Y,1); check_expected(); return; }
if (cell->type == ID($_MUX16_)) { port(ID::A,1); port(ID::B,1); port(ID::C,1); port(ID::D,1); port(ID::E,1); port(ID::F,1); port(ID::G,1); port(ID::H,1); port(ID::I,1); port(ID::J,1); port(ID::K,1); port(ID::L,1); port(ID::M,1); port(ID::N,1); port(ID::O,1); port(ID::P,1); port(ID::S,1); port(ID::T,1); port(ID::U,1); port(ID::V,1); port(ID::Y,1); check_expected(); return; }
- if (cell->type == ID($_SR_NN_)) { port(ID::S,1); port(ID::R,1); port(ID::Q,1); check_expected(); return; }
- if (cell->type == ID($_SR_NP_)) { port(ID::S,1); port(ID::R,1); port(ID::Q,1); check_expected(); return; }
- if (cell->type == ID($_SR_PN_)) { port(ID::S,1); port(ID::R,1); port(ID::Q,1); check_expected(); return; }
- if (cell->type == ID($_SR_PP_)) { port(ID::S,1); port(ID::R,1); port(ID::Q,1); check_expected(); return; }
-
- if (cell->type == ID($_FF_)) { port(ID::D,1); port(ID::Q,1); check_expected(); return; }
- if (cell->type == ID($_DFF_N_)) { port(ID::D,1); port(ID::Q,1); port(ID::C,1); check_expected(); return; }
- if (cell->type == ID($_DFF_P_)) { port(ID::D,1); port(ID::Q,1); port(ID::C,1); check_expected(); return; }
-
- if (cell->type == ID($_DFFE_NN_)) { port(ID::D,1); port(ID::Q,1); port(ID::C,1); port(ID::E,1); check_expected(); return; }
- if (cell->type == ID($_DFFE_NP_)) { port(ID::D,1); port(ID::Q,1); port(ID::C,1); port(ID::E,1); check_expected(); return; }
- if (cell->type == ID($_DFFE_PN_)) { port(ID::D,1); port(ID::Q,1); port(ID::C,1); port(ID::E,1); check_expected(); return; }
- if (cell->type == ID($_DFFE_PP_)) { port(ID::D,1); port(ID::Q,1); port(ID::C,1); port(ID::E,1); check_expected(); return; }
-
- if (cell->type == ID($_DFF_NN0_)) { port(ID::D,1); port(ID::Q,1); port(ID::C,1); port(ID::R,1); check_expected(); return; }
- if (cell->type == ID($_DFF_NN1_)) { port(ID::D,1); port(ID::Q,1); port(ID::C,1); port(ID::R,1); check_expected(); return; }
- if (cell->type == ID($_DFF_NP0_)) { port(ID::D,1); port(ID::Q,1); port(ID::C,1); port(ID::R,1); check_expected(); return; }
- if (cell->type == ID($_DFF_NP1_)) { port(ID::D,1); port(ID::Q,1); port(ID::C,1); port(ID::R,1); check_expected(); return; }
- if (cell->type == ID($_DFF_PN0_)) { port(ID::D,1); port(ID::Q,1); port(ID::C,1); port(ID::R,1); check_expected(); return; }
- if (cell->type == ID($_DFF_PN1_)) { port(ID::D,1); port(ID::Q,1); port(ID::C,1); port(ID::R,1); check_expected(); return; }
- if (cell->type == ID($_DFF_PP0_)) { port(ID::D,1); port(ID::Q,1); port(ID::C,1); port(ID::R,1); check_expected(); return; }
- if (cell->type == ID($_DFF_PP1_)) { port(ID::D,1); port(ID::Q,1); port(ID::C,1); port(ID::R,1); check_expected(); return; }
-
- if (cell->type == ID($_DFFSR_NNN_)) { port(ID::C,1); port(ID::S,1); port(ID::R,1); port(ID::D,1); port(ID::Q,1); check_expected(); return; }
- if (cell->type == ID($_DFFSR_NNP_)) { port(ID::C,1); port(ID::S,1); port(ID::R,1); port(ID::D,1); port(ID::Q,1); check_expected(); return; }
- if (cell->type == ID($_DFFSR_NPN_)) { port(ID::C,1); port(ID::S,1); port(ID::R,1); port(ID::D,1); port(ID::Q,1); check_expected(); return; }
- if (cell->type == ID($_DFFSR_NPP_)) { port(ID::C,1); port(ID::S,1); port(ID::R,1); port(ID::D,1); port(ID::Q,1); check_expected(); return; }
- if (cell->type == ID($_DFFSR_PNN_)) { port(ID::C,1); port(ID::S,1); port(ID::R,1); port(ID::D,1); port(ID::Q,1); check_expected(); return; }
- if (cell->type == ID($_DFFSR_PNP_)) { port(ID::C,1); port(ID::S,1); port(ID::R,1); port(ID::D,1); port(ID::Q,1); check_expected(); return; }
- if (cell->type == ID($_DFFSR_PPN_)) { port(ID::C,1); port(ID::S,1); port(ID::R,1); port(ID::D,1); port(ID::Q,1); check_expected(); return; }
- if (cell->type == ID($_DFFSR_PPP_)) { port(ID::C,1); port(ID::S,1); port(ID::R,1); port(ID::D,1); port(ID::Q,1); check_expected(); return; }
-
- if (cell->type == ID($_DLATCH_N_)) { port(ID::E,1); port(ID::D,1); port(ID::Q,1); check_expected(); return; }
- if (cell->type == ID($_DLATCH_P_)) { port(ID::E,1); port(ID::D,1); port(ID::Q,1); check_expected(); return; }
-
- if (cell->type == ID($_DLATCHSR_NNN_)) { port(ID::E,1); port(ID::S,1); port(ID::R,1); port(ID::D,1); port(ID::Q,1); check_expected(); return; }
- if (cell->type == ID($_DLATCHSR_NNP_)) { port(ID::E,1); port(ID::S,1); port(ID::R,1); port(ID::D,1); port(ID::Q,1); check_expected(); return; }
- if (cell->type == ID($_DLATCHSR_NPN_)) { port(ID::E,1); port(ID::S,1); port(ID::R,1); port(ID::D,1); port(ID::Q,1); check_expected(); return; }
- if (cell->type == ID($_DLATCHSR_NPP_)) { port(ID::E,1); port(ID::S,1); port(ID::R,1); port(ID::D,1); port(ID::Q,1); check_expected(); return; }
- if (cell->type == ID($_DLATCHSR_PNN_)) { port(ID::E,1); port(ID::S,1); port(ID::R,1); port(ID::D,1); port(ID::Q,1); check_expected(); return; }
- if (cell->type == ID($_DLATCHSR_PNP_)) { port(ID::E,1); port(ID::S,1); port(ID::R,1); port(ID::D,1); port(ID::Q,1); check_expected(); return; }
- if (cell->type == ID($_DLATCHSR_PPN_)) { port(ID::E,1); port(ID::S,1); port(ID::R,1); port(ID::D,1); port(ID::Q,1); check_expected(); return; }
- if (cell->type == ID($_DLATCHSR_PPP_)) { port(ID::E,1); port(ID::S,1); port(ID::R,1); port(ID::D,1); port(ID::Q,1); check_expected(); return; }
+ if (cell->type.in(ID($_SR_NN_), ID($_SR_NP_), ID($_SR_PN_), ID($_SR_PP_)))
+ { port(ID::S,1); port(ID::R,1); port(ID::Q,1); check_expected(); return; }
+
+ if (cell->type == ID($_FF_)) { port(ID::D,1); port(ID::Q,1); check_expected(); return; }
+
+ if (cell->type.in(ID($_DFF_N_), ID($_DFF_P_)))
+ { port(ID::D,1); port(ID::Q,1); port(ID::C,1); check_expected(); return; }
+
+ if (cell->type.in(ID($_DFFE_NN_), ID($_DFFE_NP_), ID($_DFFE_PN_), ID($_DFFE_PP_)))
+ { port(ID::D,1); port(ID::Q,1); port(ID::C,1); port(ID::E,1); check_expected(); return; }
+
+ if (cell->type.in(
+ ID($_DFF_NN0_), ID($_DFF_NN1_), ID($_DFF_NP0_), ID($_DFF_NP1_),
+ ID($_DFF_PN0_), ID($_DFF_PN1_), ID($_DFF_PP0_), ID($_DFF_PP1_)))
+ { port(ID::D,1); port(ID::Q,1); port(ID::C,1); port(ID::R,1); check_expected(); return; }
+
+ if (cell->type.in(
+ ID($_DFFE_NN0N_), ID($_DFFE_NN0P_), ID($_DFFE_NN1N_), ID($_DFFE_NN1P_),
+ ID($_DFFE_NP0N_), ID($_DFFE_NP0P_), ID($_DFFE_NP1N_), ID($_DFFE_NP1P_),
+ ID($_DFFE_PN0N_), ID($_DFFE_PN0P_), ID($_DFFE_PN1N_), ID($_DFFE_PN1P_),
+ ID($_DFFE_PP0N_), ID($_DFFE_PP0P_), ID($_DFFE_PP1N_), ID($_DFFE_PP1P_)))
+ { port(ID::D,1); port(ID::Q,1); port(ID::C,1); port(ID::R,1); port(ID::E,1); check_expected(); return; }
+
+ if (cell->type.in(
+ ID($_DFFSR_NNN_), ID($_DFFSR_NNP_), ID($_DFFSR_NPN_), ID($_DFFSR_NPP_),
+ ID($_DFFSR_PNN_), ID($_DFFSR_PNP_), ID($_DFFSR_PPN_), ID($_DFFSR_PPP_)))
+ { port(ID::C,1); port(ID::S,1); port(ID::R,1); port(ID::D,1); port(ID::Q,1); check_expected(); return; }
+
+ if (cell->type.in(
+ ID($_DFFSRE_NNNN_), ID($_DFFSRE_NNNP_), ID($_DFFSRE_NNPN_), ID($_DFFSRE_NNPP_),
+ ID($_DFFSRE_NPNN_), ID($_DFFSRE_NPNP_), ID($_DFFSRE_NPPN_), ID($_DFFSRE_NPPP_),
+ ID($_DFFSRE_PNNN_), ID($_DFFSRE_PNNP_), ID($_DFFSRE_PNPN_), ID($_DFFSRE_PNPP_),
+ ID($_DFFSRE_PPNN_), ID($_DFFSRE_PPNP_), ID($_DFFSRE_PPPN_), ID($_DFFSRE_PPPP_)))
+ { port(ID::C,1); port(ID::S,1); port(ID::R,1); port(ID::D,1); port(ID::E,1); port(ID::Q,1); check_expected(); return; }
+
+ if (cell->type.in(
+ ID($_SDFF_NN0_), ID($_SDFF_NN1_), ID($_SDFF_NP0_), ID($_SDFF_NP1_),
+ ID($_SDFF_PN0_), ID($_SDFF_PN1_), ID($_SDFF_PP0_), ID($_SDFF_PP1_)))
+ { port(ID::D,1); port(ID::Q,1); port(ID::C,1); port(ID::R,1); check_expected(); return; }
+
+ if (cell->type.in(
+ ID($_SDFFE_NN0N_), ID($_SDFFE_NN0P_), ID($_SDFFE_NN1N_), ID($_SDFFE_NN1P_),
+ ID($_SDFFE_NP0N_), ID($_SDFFE_NP0P_), ID($_SDFFE_NP1N_), ID($_SDFFE_NP1P_),
+ ID($_SDFFE_PN0N_), ID($_SDFFE_PN0P_), ID($_SDFFE_PN1N_), ID($_SDFFE_PN1P_),
+ ID($_SDFFE_PP0N_), ID($_SDFFE_PP0P_), ID($_SDFFE_PP1N_), ID($_SDFFE_PP1P_),
+ ID($_SDFFCE_NN0N_), ID($_SDFFCE_NN0P_), ID($_SDFFCE_NN1N_), ID($_SDFFCE_NN1P_),
+ ID($_SDFFCE_NP0N_), ID($_SDFFCE_NP0P_), ID($_SDFFCE_NP1N_), ID($_SDFFCE_NP1P_),
+ ID($_SDFFCE_PN0N_), ID($_SDFFCE_PN0P_), ID($_SDFFCE_PN1N_), ID($_SDFFCE_PN1P_),
+ ID($_SDFFCE_PP0N_), ID($_SDFFCE_PP0P_), ID($_SDFFCE_PP1N_), ID($_SDFFCE_PP1P_)))
+ { port(ID::D,1); port(ID::Q,1); port(ID::C,1); port(ID::R,1); port(ID::E,1); check_expected(); return; }
+
+ if (cell->type.in(ID($_DLATCH_N_), ID($_DLATCH_P_)))
+ { port(ID::E,1); port(ID::D,1); port(ID::Q,1); check_expected(); return; }
+
+ if (cell->type.in(
+ ID($_DLATCH_NN0_), ID($_DLATCH_NN1_), ID($_DLATCH_NP0_), ID($_DLATCH_NP1_),
+ ID($_DLATCH_PN0_), ID($_DLATCH_PN1_), ID($_DLATCH_PP0_), ID($_DLATCH_PP1_)))
+ { port(ID::E,1); port(ID::R,1); port(ID::D,1); port(ID::Q,1); check_expected(); return; }
+
+ if (cell->type.in(
+ ID($_DLATCHSR_NNN_), ID($_DLATCHSR_NNP_), ID($_DLATCHSR_NPN_), ID($_DLATCHSR_NPP_),
+ ID($_DLATCHSR_PNN_), ID($_DLATCHSR_PNP_), ID($_DLATCHSR_PPN_), ID($_DLATCHSR_PPP_)))
+ { port(ID::E,1); port(ID::S,1); port(ID::R,1); port(ID::D,1); port(ID::Q,1); check_expected(); return; }
error(__LINE__);
}
@@ -1520,13 +1713,13 @@ void RTLIL::Module::cloneInto(RTLIL::Module *new_mod) const
new_mod->addWire(it.first, it.second);
for (auto &it : memories)
- new_mod->memories[it.first] = new RTLIL::Memory(*it.second);
+ new_mod->addMemory(it.first, it.second);
for (auto &it : cells_)
new_mod->addCell(it.first, it.second);
for (auto &it : processes)
- new_mod->processes[it.first] = it.second->clone();
+ new_mod->addProcess(it.first, it.second);
struct RewriteSigSpecWorker
{
@@ -1862,6 +2055,7 @@ RTLIL::Wire *RTLIL::Module::addWire(RTLIL::IdString name, const RTLIL::Wire *oth
wire->port_input = other->port_input;
wire->port_output = other->port_output;
wire->upto = other->upto;
+ wire->is_signed = other->is_signed;
wire->attributes = other->attributes;
return wire;
}
@@ -1884,6 +2078,26 @@ RTLIL::Cell *RTLIL::Module::addCell(RTLIL::IdString name, const RTLIL::Cell *oth
return cell;
}
+RTLIL::Memory *RTLIL::Module::addMemory(RTLIL::IdString name, const RTLIL::Memory *other)
+{
+ RTLIL::Memory *mem = new RTLIL::Memory;
+ mem->name = name;
+ mem->width = other->width;
+ mem->start_offset = other->start_offset;
+ mem->size = other->size;
+ mem->attributes = other->attributes;
+ memories[mem->name] = mem;
+ return mem;
+}
+
+RTLIL::Process *RTLIL::Module::addProcess(RTLIL::IdString name, const RTLIL::Process *other)
+{
+ RTLIL::Process *proc = other->clone();
+ proc->name = name;
+ processes[name] = proc;
+ return proc;
+}
+
#define DEF_METHOD(_func, _y_size, _type) \
RTLIL::Cell* RTLIL::Module::add ## _func(RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_y, bool is_signed, const std::string &src) { \
RTLIL::Cell *cell = addCell(name, _type); \
@@ -1949,6 +2163,8 @@ DEF_METHOD(Sub, max(sig_a.size(), sig_b.size()), ID($sub))
DEF_METHOD(Mul, max(sig_a.size(), sig_b.size()), ID($mul))
DEF_METHOD(Div, max(sig_a.size(), sig_b.size()), ID($div))
DEF_METHOD(Mod, max(sig_a.size(), sig_b.size()), ID($mod))
+DEF_METHOD(DivFloor, max(sig_a.size(), sig_b.size()), ID($divfloor))
+DEF_METHOD(ModFloor, max(sig_a.size(), sig_b.size()), ID($modfloor))
DEF_METHOD(LogicAnd, 1, ID($logic_and))
DEF_METHOD(LogicOr, 1, ID($logic_or))
#undef DEF_METHOD
@@ -2260,6 +2476,25 @@ RTLIL::Cell* RTLIL::Module::addDffsr(RTLIL::IdString name, const RTLIL::SigSpec
return cell;
}
+RTLIL::Cell* RTLIL::Module::addDffsre(RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_set, const RTLIL::SigSpec &sig_clr,
+ RTLIL::SigSpec sig_d, const RTLIL::SigSpec &sig_q, bool clk_polarity, bool en_polarity, bool set_polarity, bool clr_polarity, const std::string &src)
+{
+ RTLIL::Cell *cell = addCell(name, ID($dffsre));
+ cell->parameters[ID::CLK_POLARITY] = clk_polarity;
+ cell->parameters[ID::EN_POLARITY] = en_polarity;
+ cell->parameters[ID::SET_POLARITY] = set_polarity;
+ cell->parameters[ID::CLR_POLARITY] = clr_polarity;
+ cell->parameters[ID::WIDTH] = sig_q.size();
+ cell->setPort(ID::CLK, sig_clk);
+ cell->setPort(ID::EN, sig_en);
+ cell->setPort(ID::SET, sig_set);
+ cell->setPort(ID::CLR, sig_clr);
+ cell->setPort(ID::D, sig_d);
+ cell->setPort(ID::Q, sig_q);
+ cell->set_src_attribute(src);
+ return cell;
+}
+
RTLIL::Cell* RTLIL::Module::addAdff(RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_arst, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q,
RTLIL::Const arst_value, bool clk_polarity, bool arst_polarity, const std::string &src)
{
@@ -2276,6 +2511,76 @@ RTLIL::Cell* RTLIL::Module::addAdff(RTLIL::IdString name, const RTLIL::SigSpec &
return cell;
}
+RTLIL::Cell* RTLIL::Module::addAdffe(RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_arst, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q,
+ RTLIL::Const arst_value, bool clk_polarity, bool en_polarity, bool arst_polarity, const std::string &src)
+{
+ RTLIL::Cell *cell = addCell(name, ID($adffe));
+ cell->parameters[ID::CLK_POLARITY] = clk_polarity;
+ cell->parameters[ID::EN_POLARITY] = en_polarity;
+ cell->parameters[ID::ARST_POLARITY] = arst_polarity;
+ cell->parameters[ID::ARST_VALUE] = arst_value;
+ cell->parameters[ID::WIDTH] = sig_q.size();
+ cell->setPort(ID::CLK, sig_clk);
+ cell->setPort(ID::EN, sig_en);
+ cell->setPort(ID::ARST, sig_arst);
+ cell->setPort(ID::D, sig_d);
+ cell->setPort(ID::Q, sig_q);
+ cell->set_src_attribute(src);
+ return cell;
+}
+
+RTLIL::Cell* RTLIL::Module::addSdff(RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_srst, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q,
+ RTLIL::Const srst_value, bool clk_polarity, bool srst_polarity, const std::string &src)
+{
+ RTLIL::Cell *cell = addCell(name, ID($sdff));
+ cell->parameters[ID::CLK_POLARITY] = clk_polarity;
+ cell->parameters[ID::SRST_POLARITY] = srst_polarity;
+ cell->parameters[ID::SRST_VALUE] = srst_value;
+ cell->parameters[ID::WIDTH] = sig_q.size();
+ cell->setPort(ID::CLK, sig_clk);
+ cell->setPort(ID::SRST, sig_srst);
+ cell->setPort(ID::D, sig_d);
+ cell->setPort(ID::Q, sig_q);
+ cell->set_src_attribute(src);
+ return cell;
+}
+
+RTLIL::Cell* RTLIL::Module::addSdffe(RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_srst, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q,
+ RTLIL::Const srst_value, bool clk_polarity, bool en_polarity, bool srst_polarity, const std::string &src)
+{
+ RTLIL::Cell *cell = addCell(name, ID($sdffe));
+ cell->parameters[ID::CLK_POLARITY] = clk_polarity;
+ cell->parameters[ID::EN_POLARITY] = en_polarity;
+ cell->parameters[ID::SRST_POLARITY] = srst_polarity;
+ cell->parameters[ID::SRST_VALUE] = srst_value;
+ cell->parameters[ID::WIDTH] = sig_q.size();
+ cell->setPort(ID::CLK, sig_clk);
+ cell->setPort(ID::EN, sig_en);
+ cell->setPort(ID::SRST, sig_srst);
+ cell->setPort(ID::D, sig_d);
+ cell->setPort(ID::Q, sig_q);
+ cell->set_src_attribute(src);
+ return cell;
+}
+
+RTLIL::Cell* RTLIL::Module::addSdffce(RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_srst, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q,
+ RTLIL::Const srst_value, bool clk_polarity, bool en_polarity, bool srst_polarity, const std::string &src)
+{
+ RTLIL::Cell *cell = addCell(name, ID($sdffce));
+ cell->parameters[ID::CLK_POLARITY] = clk_polarity;
+ cell->parameters[ID::EN_POLARITY] = en_polarity;
+ cell->parameters[ID::SRST_POLARITY] = srst_polarity;
+ cell->parameters[ID::SRST_VALUE] = srst_value;
+ cell->parameters[ID::WIDTH] = sig_q.size();
+ cell->setPort(ID::CLK, sig_clk);
+ cell->setPort(ID::EN, sig_en);
+ cell->setPort(ID::SRST, sig_srst);
+ cell->setPort(ID::D, sig_d);
+ cell->setPort(ID::Q, sig_q);
+ cell->set_src_attribute(src);
+ return cell;
+}
+
RTLIL::Cell* RTLIL::Module::addDlatch(RTLIL::IdString name, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, bool en_polarity, const std::string &src)
{
RTLIL::Cell *cell = addCell(name, ID($dlatch));
@@ -2288,6 +2593,22 @@ RTLIL::Cell* RTLIL::Module::addDlatch(RTLIL::IdString name, const RTLIL::SigSpec
return cell;
}
+RTLIL::Cell* RTLIL::Module::addAdlatch(RTLIL::IdString name, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_arst, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q,
+ RTLIL::Const arst_value, bool en_polarity, bool arst_polarity, const std::string &src)
+{
+ RTLIL::Cell *cell = addCell(name, ID($adlatch));
+ cell->parameters[ID::EN_POLARITY] = en_polarity;
+ cell->parameters[ID::ARST_POLARITY] = arst_polarity;
+ cell->parameters[ID::ARST_VALUE] = arst_value;
+ cell->parameters[ID::WIDTH] = sig_q.size();
+ cell->setPort(ID::EN, sig_en);
+ cell->setPort(ID::ARST, sig_arst);
+ cell->setPort(ID::D, sig_d);
+ cell->setPort(ID::Q, sig_q);
+ cell->set_src_attribute(src);
+ return cell;
+}
+
RTLIL::Cell* RTLIL::Module::addDlatchsr(RTLIL::IdString name, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_set, const RTLIL::SigSpec &sig_clr,
RTLIL::SigSpec sig_d, const RTLIL::SigSpec &sig_q, bool en_polarity, bool set_polarity, bool clr_polarity, const std::string &src)
{
@@ -2305,6 +2626,17 @@ RTLIL::Cell* RTLIL::Module::addDlatchsr(RTLIL::IdString name, const RTLIL::SigSp
return cell;
}
+RTLIL::Cell* RTLIL::Module::addSrGate(RTLIL::IdString name, const RTLIL::SigSpec &sig_set, const RTLIL::SigSpec &sig_clr,
+ const RTLIL::SigSpec &sig_q, bool set_polarity, bool clr_polarity, const std::string &src)
+{
+ RTLIL::Cell *cell = addCell(name, stringf("$_SR_%c%c_", set_polarity ? 'P' : 'N', clr_polarity ? 'P' : 'N'));
+ cell->setPort(ID::S, sig_set);
+ cell->setPort(ID::R, sig_clr);
+ cell->setPort(ID::Q, sig_q);
+ cell->set_src_attribute(src);
+ return cell;
+}
+
RTLIL::Cell* RTLIL::Module::addFfGate(RTLIL::IdString name, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, const std::string &src)
{
RTLIL::Cell *cell = addCell(name, ID($_FF_));
@@ -2348,6 +2680,20 @@ RTLIL::Cell* RTLIL::Module::addDffsrGate(RTLIL::IdString name, const RTLIL::SigS
return cell;
}
+RTLIL::Cell* RTLIL::Module::addDffsreGate(RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_set, const RTLIL::SigSpec &sig_clr,
+ RTLIL::SigSpec sig_d, const RTLIL::SigSpec &sig_q, bool clk_polarity, bool en_polarity, bool set_polarity, bool clr_polarity, const std::string &src)
+{
+ RTLIL::Cell *cell = addCell(name, stringf("$_DFFSRE_%c%c%c%c_", clk_polarity ? 'P' : 'N', set_polarity ? 'P' : 'N', clr_polarity ? 'P' : 'N', en_polarity ? 'P' : 'N'));
+ cell->setPort(ID::C, sig_clk);
+ cell->setPort(ID::S, sig_set);
+ cell->setPort(ID::R, sig_clr);
+ cell->setPort(ID::E, sig_en);
+ cell->setPort(ID::D, sig_d);
+ cell->setPort(ID::Q, sig_q);
+ cell->set_src_attribute(src);
+ return cell;
+}
+
RTLIL::Cell* RTLIL::Module::addAdffGate(RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_arst, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q,
bool arst_value, bool clk_polarity, bool arst_polarity, const std::string &src)
{
@@ -2360,6 +2706,57 @@ RTLIL::Cell* RTLIL::Module::addAdffGate(RTLIL::IdString name, const RTLIL::SigSp
return cell;
}
+RTLIL::Cell* RTLIL::Module::addAdffeGate(RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_arst, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q,
+ bool arst_value, bool clk_polarity, bool en_polarity, bool arst_polarity, const std::string &src)
+{
+ RTLIL::Cell *cell = addCell(name, stringf("$_DFFE_%c%c%c%c_", clk_polarity ? 'P' : 'N', arst_polarity ? 'P' : 'N', arst_value ? '1' : '0', en_polarity ? 'P' : 'N'));
+ cell->setPort(ID::C, sig_clk);
+ cell->setPort(ID::R, sig_arst);
+ cell->setPort(ID::E, sig_en);
+ cell->setPort(ID::D, sig_d);
+ cell->setPort(ID::Q, sig_q);
+ cell->set_src_attribute(src);
+ return cell;
+}
+
+RTLIL::Cell* RTLIL::Module::addSdffGate(RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_srst, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q,
+ bool srst_value, bool clk_polarity, bool srst_polarity, const std::string &src)
+{
+ RTLIL::Cell *cell = addCell(name, stringf("$_SDFF_%c%c%c_", clk_polarity ? 'P' : 'N', srst_polarity ? 'P' : 'N', srst_value ? '1' : '0'));
+ cell->setPort(ID::C, sig_clk);
+ cell->setPort(ID::R, sig_srst);
+ cell->setPort(ID::D, sig_d);
+ cell->setPort(ID::Q, sig_q);
+ cell->set_src_attribute(src);
+ return cell;
+}
+
+RTLIL::Cell* RTLIL::Module::addSdffeGate(RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_srst, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q,
+ bool srst_value, bool clk_polarity, bool en_polarity, bool srst_polarity, const std::string &src)
+{
+ RTLIL::Cell *cell = addCell(name, stringf("$_SDFFE_%c%c%c%c_", clk_polarity ? 'P' : 'N', srst_polarity ? 'P' : 'N', srst_value ? '1' : '0', en_polarity ? 'P' : 'N'));
+ cell->setPort(ID::C, sig_clk);
+ cell->setPort(ID::R, sig_srst);
+ cell->setPort(ID::E, sig_en);
+ cell->setPort(ID::D, sig_d);
+ cell->setPort(ID::Q, sig_q);
+ cell->set_src_attribute(src);
+ return cell;
+}
+
+RTLIL::Cell* RTLIL::Module::addSdffceGate(RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_srst, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q,
+ bool srst_value, bool clk_polarity, bool en_polarity, bool srst_polarity, const std::string &src)
+{
+ RTLIL::Cell *cell = addCell(name, stringf("$_SDFFCE_%c%c%c%c_", clk_polarity ? 'P' : 'N', srst_polarity ? 'P' : 'N', srst_value ? '1' : '0', en_polarity ? 'P' : 'N'));
+ cell->setPort(ID::C, sig_clk);
+ cell->setPort(ID::R, sig_srst);
+ cell->setPort(ID::E, sig_en);
+ cell->setPort(ID::D, sig_d);
+ cell->setPort(ID::Q, sig_q);
+ cell->set_src_attribute(src);
+ return cell;
+}
+
RTLIL::Cell* RTLIL::Module::addDlatchGate(RTLIL::IdString name, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, bool en_polarity, const std::string &src)
{
RTLIL::Cell *cell = addCell(name, stringf("$_DLATCH_%c_", en_polarity ? 'P' : 'N'));
@@ -2370,6 +2767,18 @@ RTLIL::Cell* RTLIL::Module::addDlatchGate(RTLIL::IdString name, const RTLIL::Sig
return cell;
}
+RTLIL::Cell* RTLIL::Module::addAdlatchGate(RTLIL::IdString name, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_arst, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q,
+ bool arst_value, bool en_polarity, bool arst_polarity, const std::string &src)
+{
+ RTLIL::Cell *cell = addCell(name, stringf("$_DLATCH_%c%c%c_", en_polarity ? 'P' : 'N', arst_polarity ? 'P' : 'N', arst_value ? '1' : '0'));
+ cell->setPort(ID::E, sig_en);
+ cell->setPort(ID::R, sig_arst);
+ cell->setPort(ID::D, sig_d);
+ cell->setPort(ID::Q, sig_q);
+ cell->set_src_attribute(src);
+ return cell;
+}
+
RTLIL::Cell* RTLIL::Module::addDlatchsrGate(RTLIL::IdString name, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_set, const RTLIL::SigSpec &sig_clr,
RTLIL::SigSpec sig_d, const RTLIL::SigSpec &sig_q, bool en_polarity, bool set_polarity, bool clr_polarity, const std::string &src)
{
@@ -2445,6 +2854,7 @@ RTLIL::Wire::Wire()
port_input = false;
port_output = false;
upto = false;
+ is_signed = false;
#ifdef WITH_PYTHON
RTLIL::Wire::get_all_wires()->insert(std::pair<unsigned int, RTLIL::Wire*>(hashidx_, this));
diff --git a/kernel/rtlil.h b/kernel/rtlil.h
index 11c45bbec..6c561cb85 100644
--- a/kernel/rtlil.h
+++ b/kernel/rtlil.h
@@ -150,9 +150,6 @@ namespace RTLIL
if (!p[0])
return 0;
- log_assert(p[0] == '$' || p[0] == '\\');
- log_assert(p[1] != 0);
-
auto it = global_id_index_.find((char*)p);
if (it != global_id_index_.end()) {
#ifndef YOSYS_NO_IDS_REFCNT
@@ -165,6 +162,11 @@ namespace RTLIL
return it->second;
}
+ log_assert(p[0] == '$' || p[0] == '\\');
+ log_assert(p[1] != 0);
+ for (const char *c = p; *c; c++)
+ log_assert((unsigned)*c > (unsigned)' ');
+
#ifndef YOSYS_NO_IDS_REFCNT
if (global_free_idx_list_.empty()) {
if (global_id_storage_.empty()) {
@@ -296,8 +298,8 @@ namespace RTLIL
// The methods below are just convenience functions for better compatibility with std::string.
- bool operator==(const std::string &rhs) const { return str() == rhs; }
- bool operator!=(const std::string &rhs) const { return str() != rhs; }
+ bool operator==(const std::string &rhs) const { return c_str() == rhs; }
+ bool operator!=(const std::string &rhs) const { return c_str() != rhs; }
bool operator==(const char *rhs) const { return strcmp(c_str(), rhs) == 0; }
bool operator!=(const char *rhs) const { return strcmp(c_str(), rhs) != 0; }
@@ -466,6 +468,8 @@ namespace RTLIL
RTLIL::Const const_sub (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);
RTLIL::Const const_mul (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);
RTLIL::Const const_div (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);
+ RTLIL::Const const_divfloor (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);
+ RTLIL::Const const_modfloor (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);
RTLIL::Const const_mod (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);
RTLIL::Const const_pow (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);
@@ -550,6 +554,29 @@ namespace RTLIL
return *this;
}
+ inline ObjIterator<T>& operator+=(int amt) {
+ log_assert(list_p != nullptr);
+ it += amt;
+ if (it == list_p->end()) {
+ (*refcount_p)--;
+ list_p = nullptr;
+ refcount_p = nullptr;
+ }
+ return *this;
+ }
+
+ inline ObjIterator<T> operator+(int amt) {
+ log_assert(list_p != nullptr);
+ ObjIterator<T> new_obj(*this);
+ new_obj.it += amt;
+ if (new_obj.it == list_p->end()) {
+ (*(new_obj.refcount_p))--;
+ new_obj.list_p = nullptr;
+ new_obj.refcount_p = nullptr;
+ }
+ return new_obj;
+ }
+
inline const ObjIterator<T> operator++(int) {
ObjIterator<T> result(*this);
++(*this);
@@ -678,6 +705,9 @@ struct RTLIL::AttrObject
std::string get_src_attribute() const {
return get_string_attribute(ID::src);
}
+
+ void set_hdlname_attribute(const vector<string> &hierarchy);
+ vector<string> get_hdlname_attribute() const;
};
struct RTLIL::SigChunk
@@ -721,7 +751,7 @@ struct RTLIL::SigBit
SigBit(const RTLIL::SigChunk &chunk);
SigBit(const RTLIL::SigChunk &chunk, int index);
SigBit(const RTLIL::SigSpec &sig);
- SigBit(const RTLIL::SigBit &sigbit);
+ SigBit(const RTLIL::SigBit &sigbit) = default;
RTLIL::SigBit &operator =(const RTLIL::SigBit &other) = default;
bool operator <(const RTLIL::SigBit &other) const;
@@ -1054,6 +1084,13 @@ struct RTLIL::Design
return selected_member(module->name, member->name);
}
+ template<typename T1> void select(T1 *module) {
+ if (selection_stack.size() > 0) {
+ RTLIL::Selection &sel = selection_stack.back();
+ sel.select(module);
+ }
+ }
+
template<typename T1, typename T2> void select(T1 *module, T2 *member) {
if (selection_stack.size() > 0) {
RTLIL::Selection &sel = selection_stack.back();
@@ -1134,8 +1171,14 @@ public:
return design->selected_member(name, member->name);
}
- RTLIL::Wire* wire(RTLIL::IdString id) { return wires_.count(id) ? wires_.at(id) : nullptr; }
- RTLIL::Cell* cell(RTLIL::IdString id) { return cells_.count(id) ? cells_.at(id) : nullptr; }
+ RTLIL::Wire* wire(RTLIL::IdString id) {
+ auto it = wires_.find(id);
+ return it == wires_.end() ? nullptr : it->second;
+ }
+ RTLIL::Cell* cell(RTLIL::IdString id) {
+ auto it = cells_.find(id);
+ return it == cells_.end() ? nullptr : it->second;
+ }
RTLIL::ObjRange<RTLIL::Wire*> wires() { return RTLIL::ObjRange<RTLIL::Wire*>(&wires_, &refcount_wires_); }
RTLIL::ObjRange<RTLIL::Cell*> cells() { return RTLIL::ObjRange<RTLIL::Cell*>(&cells_, &refcount_cells_); }
@@ -1160,6 +1203,10 @@ public:
RTLIL::Cell *addCell(RTLIL::IdString name, RTLIL::IdString type);
RTLIL::Cell *addCell(RTLIL::IdString name, const RTLIL::Cell *other);
+ RTLIL::Memory *addMemory(RTLIL::IdString name, const RTLIL::Memory *other);
+
+ RTLIL::Process *addProcess(RTLIL::IdString name, const RTLIL::Process *other);
+
// The add* methods create a cell and return the created cell. All signals must exist in advance.
RTLIL::Cell* addNot (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = "");
@@ -1196,8 +1243,12 @@ public:
RTLIL::Cell* addAdd (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = "");
RTLIL::Cell* addSub (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = "");
RTLIL::Cell* addMul (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = "");
+ // truncating division
RTLIL::Cell* addDiv (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = "");
+ // truncating modulo
RTLIL::Cell* addMod (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = "");
+ RTLIL::Cell* addDivFloor (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = "");
+ RTLIL::Cell* addModFloor (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = "");
RTLIL::Cell* addPow (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool a_signed = false, bool b_signed = false, const std::string &src = "");
RTLIL::Cell* addLogicNot (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = "");
@@ -1222,13 +1273,16 @@ public:
RTLIL::Cell* addFf (RTLIL::IdString name, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, const std::string &src = "");
RTLIL::Cell* addDff (RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, bool clk_polarity = true, const std::string &src = "");
RTLIL::Cell* addDffe (RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, bool clk_polarity = true, bool en_polarity = true, const std::string &src = "");
- RTLIL::Cell* addDffsr (RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_set, const RTLIL::SigSpec &sig_clr,
- RTLIL::SigSpec sig_d, const RTLIL::SigSpec &sig_q, bool clk_polarity = true, bool set_polarity = true, bool clr_polarity = true, const std::string &src = "");
- RTLIL::Cell* addAdff (RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_arst, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q,
- RTLIL::Const arst_value, bool clk_polarity = true, bool arst_polarity = true, const std::string &src = "");
+ RTLIL::Cell* addDffsr (RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_set, const RTLIL::SigSpec &sig_clr, RTLIL::SigSpec sig_d, const RTLIL::SigSpec &sig_q, bool clk_polarity = true, bool set_polarity = true, bool clr_polarity = true, const std::string &src = "");
+ RTLIL::Cell* addDffsre (RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_set, const RTLIL::SigSpec &sig_clr, RTLIL::SigSpec sig_d, const RTLIL::SigSpec &sig_q, bool clk_polarity = true, bool en_polarity = true, bool set_polarity = true, bool clr_polarity = true, const std::string &src = "");
+ RTLIL::Cell* addAdff (RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_arst, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, RTLIL::Const arst_value, bool clk_polarity = true, bool arst_polarity = true, const std::string &src = "");
+ RTLIL::Cell* addAdffe (RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_arst, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, RTLIL::Const arst_value, bool clk_polarity = true, bool en_polarity = true, bool arst_polarity = true, const std::string &src = "");
+ RTLIL::Cell* addSdff (RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_srst, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, RTLIL::Const srst_value, bool clk_polarity = true, bool srst_polarity = true, const std::string &src = "");
+ RTLIL::Cell* addSdffe (RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_srst, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, RTLIL::Const srst_value, bool clk_polarity = true, bool en_polarity = true, bool srst_polarity = true, const std::string &src = "");
+ RTLIL::Cell* addSdffce (RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_srst, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, RTLIL::Const srst_value, bool clk_polarity = true, bool en_polarity = true, bool srst_polarity = true, const std::string &src = "");
RTLIL::Cell* addDlatch (RTLIL::IdString name, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, bool en_polarity = true, const std::string &src = "");
- RTLIL::Cell* addDlatchsr (RTLIL::IdString name, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_set, const RTLIL::SigSpec &sig_clr,
- RTLIL::SigSpec sig_d, const RTLIL::SigSpec &sig_q, bool en_polarity = true, bool set_polarity = true, bool clr_polarity = true, const std::string &src = "");
+ RTLIL::Cell* addAdlatch (RTLIL::IdString name, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_arst, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, RTLIL::Const arst_value, bool en_polarity = true, bool arst_polarity = true, const std::string &src = "");
+ RTLIL::Cell* addDlatchsr (RTLIL::IdString name, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_set, const RTLIL::SigSpec &sig_clr, RTLIL::SigSpec sig_d, const RTLIL::SigSpec &sig_q, bool en_polarity = true, bool set_polarity = true, bool clr_polarity = true, const std::string &src = "");
RTLIL::Cell* addBufGate (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_y, const std::string &src = "");
RTLIL::Cell* addNotGate (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_y, const std::string &src = "");
@@ -1247,14 +1301,28 @@ public:
RTLIL::Cell* addAoi4Gate (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const RTLIL::SigBit &sig_c, const RTLIL::SigBit &sig_d, const RTLIL::SigBit &sig_y, const std::string &src = "");
RTLIL::Cell* addOai4Gate (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const RTLIL::SigBit &sig_c, const RTLIL::SigBit &sig_d, const RTLIL::SigBit &sig_y, const std::string &src = "");
+ RTLIL::Cell* addSrGate (RTLIL::IdString name, const RTLIL::SigSpec &sig_set, const RTLIL::SigSpec &sig_clr,
+ const RTLIL::SigSpec &sig_q, bool set_polarity = true, bool clr_polarity = true, const std::string &src = "");
RTLIL::Cell* addFfGate (RTLIL::IdString name, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, const std::string &src = "");
RTLIL::Cell* addDffGate (RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, bool clk_polarity = true, const std::string &src = "");
RTLIL::Cell* addDffeGate (RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, bool clk_polarity = true, bool en_polarity = true, const std::string &src = "");
RTLIL::Cell* addDffsrGate (RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_set, const RTLIL::SigSpec &sig_clr,
RTLIL::SigSpec sig_d, const RTLIL::SigSpec &sig_q, bool clk_polarity = true, bool set_polarity = true, bool clr_polarity = true, const std::string &src = "");
+ RTLIL::Cell* addDffsreGate (RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_set, const RTLIL::SigSpec &sig_clr,
+ RTLIL::SigSpec sig_d, const RTLIL::SigSpec &sig_q, bool clk_polarity = true, bool en_polarity = true, bool set_polarity = true, bool clr_polarity = true, const std::string &src = "");
RTLIL::Cell* addAdffGate (RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_arst, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q,
bool arst_value = false, bool clk_polarity = true, bool arst_polarity = true, const std::string &src = "");
+ RTLIL::Cell* addAdffeGate (RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_arst, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q,
+ bool arst_value = false, bool clk_polarity = true, bool en_polarity = true, bool arst_polarity = true, const std::string &src = "");
+ RTLIL::Cell* addSdffGate (RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_srst, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q,
+ bool srst_value = false, bool clk_polarity = true, bool srst_polarity = true, const std::string &src = "");
+ RTLIL::Cell* addSdffeGate (RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_srst, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q,
+ bool srst_value = false, bool clk_polarity = true, bool en_polarity = true, bool srst_polarity = true, const std::string &src = "");
+ RTLIL::Cell* addSdffceGate (RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_srst, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q,
+ bool srst_value = false, bool clk_polarity = true, bool en_polarity = true, bool srst_polarity = true, const std::string &src = "");
RTLIL::Cell* addDlatchGate (RTLIL::IdString name, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, bool en_polarity = true, const std::string &src = "");
+ RTLIL::Cell* addAdlatchGate(RTLIL::IdString name, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_arst, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q,
+ bool arst_value = false, bool en_polarity = true, bool arst_polarity = true, const std::string &src = "");
RTLIL::Cell* addDlatchsrGate (RTLIL::IdString name, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_set, const RTLIL::SigSpec &sig_clr,
RTLIL::SigSpec sig_d, const RTLIL::SigSpec &sig_q, bool en_polarity = true, bool set_polarity = true, bool clr_polarity = true, const std::string &src = "");
@@ -1295,8 +1363,12 @@ public:
RTLIL::SigSpec Add (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, const std::string &src = "");
RTLIL::SigSpec Sub (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, const std::string &src = "");
RTLIL::SigSpec Mul (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, const std::string &src = "");
+ // truncating division
RTLIL::SigSpec Div (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, const std::string &src = "");
+ // truncating modulo
RTLIL::SigSpec Mod (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, const std::string &src = "");
+ RTLIL::SigSpec DivFloor (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, const std::string &src = "");
+ RTLIL::SigSpec ModFloor (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, const std::string &src = "");
RTLIL::SigSpec Pow (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool a_signed = false, bool b_signed = false, const std::string &src = "");
RTLIL::SigSpec LogicNot (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, bool is_signed = false, const std::string &src = "");
@@ -1353,7 +1425,7 @@ public:
RTLIL::Module *module;
RTLIL::IdString name;
int width, start_offset, port_id;
- bool port_input, port_output, upto;
+ bool port_input, port_output, upto, is_signed;
#ifdef WITH_PYTHON
static std::map<unsigned int, RTLIL::Wire*> *get_all_wires(void);
@@ -1494,7 +1566,6 @@ inline RTLIL::SigBit::SigBit(RTLIL::Wire *wire) : wire(wire), offset(0) { log_as
inline RTLIL::SigBit::SigBit(RTLIL::Wire *wire, int offset) : wire(wire), offset(offset) { log_assert(wire != nullptr); }
inline RTLIL::SigBit::SigBit(const RTLIL::SigChunk &chunk) : wire(chunk.wire) { log_assert(chunk.width == 1); if (wire) offset = chunk.offset; else data = chunk.data[0]; }
inline RTLIL::SigBit::SigBit(const RTLIL::SigChunk &chunk, int index) : wire(chunk.wire) { if (wire) offset = chunk.offset + index; else data = chunk.data[index]; }
-inline RTLIL::SigBit::SigBit(const RTLIL::SigBit &sigbit) : wire(sigbit.wire), data(sigbit.data){ if (wire) offset = sigbit.offset; }
inline bool RTLIL::SigBit::operator<(const RTLIL::SigBit &other) const {
if (wire == other.wire)
diff --git a/kernel/satgen.h b/kernel/satgen.h
index 88b84b7e6..3929a8708 100644
--- a/kernel/satgen.h
+++ b/kernel/satgen.h
@@ -279,7 +279,7 @@ struct SatGen
bool arith_undef_handled = false;
bool is_arith_compare = cell->type.in(ID($lt), ID($le), ID($ge), ID($gt));
- if (model_undef && (cell->type.in(ID($add), ID($sub), ID($mul), ID($div), ID($mod)) || is_arith_compare))
+ if (model_undef && (cell->type.in(ID($add), ID($sub), ID($mul), ID($div), ID($mod), ID($divfloor), ID($modfloor)) || is_arith_compare))
{
std::vector<int> undef_a = importUndefSigSpec(cell->getPort(ID::A), timestep);
std::vector<int> undef_b = importUndefSigSpec(cell->getPort(ID::B), timestep);
@@ -293,7 +293,7 @@ struct SatGen
int undef_any_b = ez->expression(ezSAT::OpOr, undef_b);
int undef_y_bit = ez->OR(undef_any_a, undef_any_b);
- if (cell->type.in(ID($div), ID($mod))) {
+ if (cell->type.in(ID($div), ID($mod), ID($divfloor), ID($modfloor))) {
std::vector<int> b = importSigSpec(cell->getPort(ID::B), timestep);
undef_y_bit = ez->OR(undef_y_bit, ez->NOT(ez->expression(ezSAT::OpOr, b)));
}
@@ -935,7 +935,7 @@ struct SatGen
return true;
}
- if (cell->type.in(ID($div), ID($mod)))
+ if (cell->type.in(ID($div), ID($mod), ID($divfloor), ID($modfloor)))
{
std::vector<int> a = importDefSigSpec(cell->getPort(ID::A), timestep);
std::vector<int> b = importDefSigSpec(cell->getPort(ID::B), timestep);
@@ -970,23 +970,48 @@ struct SatGen
}
std::vector<int> y_tmp = ignore_div_by_zero ? yy : ez->vec_var(y.size());
+
+ // modulo calculation
+ std::vector<int> modulo_trunc;
+ int floored_eq_trunc;
+ if (cell->parameters[ID::A_SIGNED].as_bool() && cell->parameters[ID::B_SIGNED].as_bool()) {
+ modulo_trunc = ez->vec_ite(a.back(), ez->vec_neg(chain_buf), chain_buf);
+ // floor == trunc when sgn(a) == sgn(b) or trunc == 0
+ floored_eq_trunc = ez->OR(ez->IFF(a.back(), b.back()), ez->NOT(ez->expression(ezSAT::OpOr, modulo_trunc)));
+ } else {
+ modulo_trunc = chain_buf;
+ floored_eq_trunc = ez->CONST_TRUE;
+ }
+
if (cell->type == ID($div)) {
if (cell->parameters[ID::A_SIGNED].as_bool() && cell->parameters[ID::B_SIGNED].as_bool())
ez->assume(ez->vec_eq(y_tmp, ez->vec_ite(ez->XOR(a.back(), b.back()), ez->vec_neg(y_u), y_u)));
else
ez->assume(ez->vec_eq(y_tmp, y_u));
- } else {
+ } else if (cell->type == ID($mod)) {
+ ez->assume(ez->vec_eq(y_tmp, modulo_trunc));
+ } else if (cell->type == ID($divfloor)) {
if (cell->parameters[ID::A_SIGNED].as_bool() && cell->parameters[ID::B_SIGNED].as_bool())
- ez->assume(ez->vec_eq(y_tmp, ez->vec_ite(a.back(), ez->vec_neg(chain_buf), chain_buf)));
+ ez->assume(ez->vec_eq(y_tmp, ez->vec_ite(
+ ez->XOR(a.back(), b.back()),
+ ez->vec_neg(ez->vec_ite(
+ ez->vec_reduce_or(modulo_trunc),
+ ez->vec_add(y_u, ez->vec_const_unsigned(1, y_u.size())),
+ y_u
+ )),
+ y_u
+ )));
else
- ez->assume(ez->vec_eq(y_tmp, chain_buf));
+ ez->assume(ez->vec_eq(y_tmp, y_u));
+ } else if (cell->type == ID($modfloor)) {
+ ez->assume(ez->vec_eq(y_tmp, ez->vec_ite(floored_eq_trunc, modulo_trunc, ez->vec_add(modulo_trunc, b))));
}
if (ignore_div_by_zero) {
ez->assume(ez->expression(ezSAT::OpOr, b));
} else {
std::vector<int> div_zero_result;
- if (cell->type == ID($div)) {
+ if (cell->type.in(ID($div), ID($divfloor))) {
if (cell->parameters[ID::A_SIGNED].as_bool() && cell->parameters[ID::B_SIGNED].as_bool()) {
std::vector<int> all_ones(y.size(), ez->CONST_TRUE);
std::vector<int> only_first_one(y.size(), ez->CONST_FALSE);
@@ -996,7 +1021,8 @@ struct SatGen
div_zero_result.insert(div_zero_result.end(), cell->getPort(ID::A).size(), ez->CONST_TRUE);
div_zero_result.insert(div_zero_result.end(), y.size() - div_zero_result.size(), ez->CONST_FALSE);
}
- } else {
+ } else if (cell->type.in(ID($mod), ID($modfloor))) {
+ // a mod 0 = a
int copy_a_bits = min(cell->getPort(ID::A).size(), cell->getPort(ID::B).size());
div_zero_result.insert(div_zero_result.end(), a.begin(), a.begin() + copy_a_bits);
if (cell->parameters[ID::A_SIGNED].as_bool() && cell->parameters[ID::B_SIGNED].as_bool())
diff --git a/kernel/timinginfo.h b/kernel/timinginfo.h
index fb4e0930d..d818e580b 100644
--- a/kernel/timinginfo.h
+++ b/kernel/timinginfo.h
@@ -82,6 +82,9 @@ struct TimingInfo
for (auto cell : module->cells()) {
if (cell->type == ID($specify2)) {
+ auto en = cell->getPort(ID::EN);
+ if (en.is_fully_const() && !en.as_bool())
+ continue;
auto src = cell->getPort(ID::SRC);
auto dst = cell->getPort(ID::DST);
for (const auto &c : src.chunks())
@@ -128,11 +131,9 @@ struct TimingInfo
int rise_max = cell->getParam(ID::T_RISE_MAX).as_int();
int fall_max = cell->getParam(ID::T_FALL_MAX).as_int();
int max = std::max(rise_max,fall_max);
- if (max < 0)
- log_warning("Module '%s' contains specify cell '%s' with T_{RISE,FALL}_MAX < 0 which is currently unsupported. Ignoring.\n", log_id(module), log_id(cell));
- if (max <= 0) {
- log_debug("Module '%s' contains specify cell '%s' with T_{RISE,FALL}_MAX <= 0 which is currently unsupported. Ignoring.\n", log_id(module), log_id(cell));
- continue;
+ if (max < 0) {
+ log_warning("Module '%s' contains specify cell '%s' with T_{RISE,FALL}_MAX < 0 which is currently unsupported. Clamping to 0.\n", log_id(module), log_id(cell));
+ max = 0;
}
for (const auto &d : dst) {
auto &v = t.arrival[NameBit(d)];
@@ -152,11 +153,9 @@ struct TimingInfo
if (!c.wire->port_input)
log_error("Module '%s' contains specify cell '%s' where DST '%s' is not a module input.\n", log_id(module), log_id(cell), log_signal(dst));
int max = cell->getParam(ID::T_LIMIT_MAX).as_int();
- if (max < 0)
- log_warning("Module '%s' contains specify cell '%s' with T_LIMIT_MAX < 0 which is currently unsupported. Ignoring.\n", log_id(module), log_id(cell));
- if (max <= 0) {
- log_debug("Module '%s' contains specify cell '%s' with T_LIMIT_MAX <= 0 which is currently unsupported. Ignoring.\n", log_id(module), log_id(cell));
- continue;
+ if (max < 0) {
+ log_warning("Module '%s' contains specify cell '%s' with T_LIMIT_MAX < 0 which is currently unsupported. Clamping to 0.\n", log_id(module), log_id(cell));
+ max = 0;
}
for (const auto &s : src) {
auto &v = t.required[NameBit(s)];
diff --git a/kernel/yosys.cc b/kernel/yosys.cc
index 2ec3dca0c..7e9f320e0 100644
--- a/kernel/yosys.cc
+++ b/kernel/yosys.cc
@@ -713,7 +713,7 @@ extern Tcl_Interp *yosys_get_tcl_interp()
struct TclPass : public Pass {
TclPass() : Pass("tcl", "execute a TCL script file") { }
- void help() YS_OVERRIDE {
+ void help() override {
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
log("\n");
log(" tcl <filename> [args]\n");
@@ -730,7 +730,7 @@ struct TclPass : public Pass {
log("the standard $argc and $argv variables.\n");
log("\n");
}
- void execute(std::vector<std::string> args, RTLIL::Design *) YS_OVERRIDE {
+ void execute(std::vector<std::string> args, RTLIL::Design *) override {
if (args.size() < 2)
log_cmd_error("Missing script file.\n");
@@ -1220,7 +1220,7 @@ void shell(RTLIL::Design *design)
struct ShellPass : public Pass {
ShellPass() : Pass("shell", "enter interactive command mode") { }
- void help() YS_OVERRIDE {
+ void help() override {
log("\n");
log(" shell\n");
log("\n");
@@ -1252,7 +1252,7 @@ struct ShellPass : public Pass {
log("Press Ctrl-D or type 'exit' to leave the interactive shell.\n");
log("\n");
}
- void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE {
+ void execute(std::vector<std::string> args, RTLIL::Design *design) override {
extra_args(args, 1, design, false);
shell(design);
}
@@ -1261,7 +1261,7 @@ struct ShellPass : public Pass {
#if defined(YOSYS_ENABLE_READLINE) || defined(YOSYS_ENABLE_EDITLINE)
struct HistoryPass : public Pass {
HistoryPass() : Pass("history", "show last interactive commands") { }
- void help() YS_OVERRIDE {
+ void help() override {
log("\n");
log(" history\n");
log("\n");
@@ -1270,7 +1270,7 @@ struct HistoryPass : public Pass {
log("from executed scripts.\n");
log("\n");
}
- void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE {
+ void execute(std::vector<std::string> args, RTLIL::Design *design) override {
extra_args(args, 1, design, false);
#ifdef YOSYS_ENABLE_READLINE
for(HIST_ENTRY **list = history_list(); *list != NULL; list++)
@@ -1285,7 +1285,7 @@ struct HistoryPass : public Pass {
struct ScriptCmdPass : public Pass {
ScriptCmdPass() : Pass("script", "execute commands from file or wire") { }
- void help() YS_OVERRIDE {
+ void help() override {
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
log("\n");
log(" script <filename> [<from_label>:<to_label>]\n");
@@ -1308,7 +1308,7 @@ struct ScriptCmdPass : public Pass {
log("'-module' mode can be exited by using the 'cd' command.\n");
log("\n");
}
- void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
+ void execute(std::vector<std::string> args, RTLIL::Design *design) override
{
bool scriptwire = false;
diff --git a/kernel/yosys.h b/kernel/yosys.h
index c922faf26..f1646d6bc 100644
--- a/kernel/yosys.h
+++ b/kernel/yosys.h
@@ -117,11 +117,11 @@ extern Tcl_Obj *Tcl_ObjSetVar2(Tcl_Interp *interp, Tcl_Obj *part1Ptr, Tcl_Obj *p
# define PATH_MAX MAX_PATH
# define isatty _isatty
# define fileno _fileno
-# else
-// mingw includes `wingdi.h` which defines a TRANSPARENT macro
-// that conflicts with X(TRANSPARENT) entry in kernel/constids.inc
-# undef TRANSPARENT
# endif
+
+// mingw and msvc include `wingdi.h` which defines a TRANSPARENT macro
+// that conflicts with X(TRANSPARENT) entry in kernel/constids.inc
+# undef TRANSPARENT
#endif
#ifndef PATH_MAX
@@ -136,23 +136,20 @@ extern Tcl_Obj *Tcl_ObjSetVar2(Tcl_Interp *interp, Tcl_Obj *part1Ptr, Tcl_Obj *p
#define YOSYS_NAMESPACE_PREFIX Yosys::
#define USING_YOSYS_NAMESPACE using namespace Yosys;
-#if __cplusplus >= 201103L
-# define YS_OVERRIDE override
-# define YS_FINAL final
-#else
-# define YS_OVERRIDE
-# define YS_FINAL
-#endif
-
#if defined(__GNUC__) || defined(__clang__)
# define YS_ATTRIBUTE(...) __attribute__((__VA_ARGS__))
-# define YS_NORETURN
#elif defined(_MSC_VER)
# define YS_ATTRIBUTE(...)
-# define YS_NORETURN __declspec(noreturn)
#else
# define YS_ATTRIBUTE(...)
-# define YS_NORETURN
+#endif
+
+#if __cplusplus >= 201703L
+# define YS_MAYBE_UNUSED [[maybe_unused]];
+#elif defined(__GNUC__) || defined(__clang__)
+# define YS_MAYBE_UNUSED __attribute__((__unused__))
+#else
+# define YS_MAYBE_UNUSED
#endif
#if __cplusplus >= 201703L
diff --git a/libs/minisat/00_PATCH_wasm.patch b/libs/minisat/00_PATCH_wasm.patch
index 0bcff7d77..384930047 100644
--- a/libs/minisat/00_PATCH_wasm.patch
+++ b/libs/minisat/00_PATCH_wasm.patch
@@ -32,3 +32,15 @@
#endif
+#endif
}
+--- System.cc
++++ System.cc
+@@ -24,7 +24,9 @@
+ OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ **************************************************************************************************/
+
++#if !defined(__wasm)
+ #include <signal.h>
++#endif
+ #include <stdio.h>
+
+ #include "System.h"
diff --git a/libs/minisat/System.cc b/libs/minisat/System.cc
index 345be8c4c..807e46c69 100644
--- a/libs/minisat/System.cc
+++ b/libs/minisat/System.cc
@@ -24,7 +24,9 @@ DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
**************************************************************************************************/
+#if !defined(__wasm)
#include <signal.h>
+#endif
#include <stdio.h>
#include "System.h"
diff --git a/manual/CHAPTER_CellLib.tex b/manual/CHAPTER_CellLib.tex
index 55abd9b96..d4572a88a 100644
--- a/manual/CHAPTER_CellLib.tex
+++ b/manual/CHAPTER_CellLib.tex
@@ -139,6 +139,8 @@ Verilog & Cell Type \\
\lstinline[language=Verilog]; Y = A * B; & {\tt \$mul} \\
\lstinline[language=Verilog]; Y = A / B; & {\tt \$div} \\
\lstinline[language=Verilog]; Y = A % B; & {\tt \$mod} \\
+\multicolumn{1}{c}{\tt [N/A]} & {\tt \$divfloor} \\
+\multicolumn{1}{c}{\tt [N/A]} & {\tt \$modfoor} \\
\lstinline[language=Verilog]; Y = A ** B; & {\tt \$pow} \\
\end{tabular}
\caption{Cell types for binary operators with their corresponding Verilog expressions.}
@@ -161,6 +163,27 @@ For the binary cells that output a logical value ({\tt \$logic\_and}, {\tt \$log
{\tt \$gt}), when the \B{Y\_WIDTH} parameter is greater than 1, the output is zero-extended,
and only the least significant bit varies.
+Division and modulo cells are available in two rounding modes. The original {\tt \$div} and {\tt \$mod}
+cells are based on truncating division, and correspond to the semantics of the verilog {\tt /} and
+{\tt \%} operators. The {\tt \$divfloor} and {\tt \$modfloor} cells represent flooring division and
+flooring modulo, the latter of which is also known as ``remainder'' in several languages. See
+table~\ref{tab:CellLib_divmod} for a side-by-side comparison between the different semantics.
+
+\begin{table}[h]
+\hfil
+\begin{tabular}{lr|rr|rr}
+\multirow{2}{*}{Division} & \multirow{2}{*}{Result} & \multicolumn{2}{c|}{Truncating} & \multicolumn{2}{c}{Flooring} \\
+ & & {\tt \$div} & {\tt \$mod} & {\tt \$divfloor} & {\tt \$modfloor} \\
+\hline
+{\tt -10 / 3} & {\tt -3.3} & {\tt -3} & {\tt -1} & {\tt -4} & {\tt 2} \\
+{\tt 10 / -3} & {\tt -3.3} & {\tt -3} & {\tt 1} & {\tt -4} & {\tt -2} \\
+{\tt -10 / -3} & {\tt 3.3} & {\tt 3} & {\tt -1} & {\tt 3} & {\tt -1} \\
+{\tt 10 / 3} & {\tt 3.3} & {\tt 3} & {\tt 1} & {\tt 3} & {\tt 1} \\
+\end{tabular}
+\caption{Comparison between different rounding modes for division and modulo cells.}
+\label{tab:CellLib_divmod}
+\end{table}
+
\subsection{Multiplexers}
Multiplexers are generated by the Verilog HDL frontend for {\tt
@@ -198,6 +221,26 @@ calculated signal and a constant zero with an {\tt \$and} gate).
\subsection{Registers}
+SR-type latches are represented by {\tt \$sr} cells. These cells have input ports
+\B{SET} and \B{CLR} and an output port \B{Q}. They have the following parameters:
+
+\begin{itemize}
+\item \B{WIDTH} \\
+The width of inputs \B{SET} and \B{CLR} and output \B{Q}.
+
+\item \B{SET\_POLARITY} \\
+The set input bits are active-high if this parameter has the value {\tt 1'b1} and active-low
+if this parameter is {\tt 1'b0}.
+
+\item \B{CLR\_POLARITY} \\
+The reset input bits are active-high if this parameter has the value {\tt 1'b1} and active-low
+if this parameter is {\tt 1'b0}.
+\end{itemize}
+
+Both set and reset inputs have separate bits for every output bit.
+When both the set and reset inputs of an {\tt \$sr} cell are active for a given bit
+index, the reset input takes precedence.
+
D-type flip-flops are represented by {\tt \$dff} cells. These cells have a clock port \B{CLK},
an input port \B{D} and an output port \B{Q}. The following parameters are available for {\tt \$dff}
cells:
@@ -211,16 +254,6 @@ Clock is active on the positive edge if this parameter has the value {\tt 1'b1}
edge if this parameter is {\tt 1'b0}.
\end{itemize}
-D-type flip-flops with enable are represented by {\tt \$dffe} cells. As the {\tt \$dff}
-cells they have \B{CLK}, \B{D} and \B{Q} ports. In addition they also have a single-bit \B{EN}
-input port for the enable pin and the following parameter:
-
-\begin{itemize}
-\item \B{EN\_POLARITY} \\
-The enable input is active-high if this parameter has the value {\tt 1'b1} and active-low
-if this parameter is {\tt 1'b0}.
-\end{itemize}
-
D-type flip-flops with asynchronous reset are represented by {\tt \$adff} cells. As the {\tt \$dff}
cells they have \B{CLK}, \B{D} and \B{Q} ports. In addition they also have a single-bit \B{ARST}
input port for the reset pin and the following additional two parameters:
@@ -234,35 +267,73 @@ if this parameter is {\tt 1'b0}.
The state of \B{Q} will be set to this value when the reset is active.
\end{itemize}
-Note that the {\tt \$adff} cell can only be used when the reset value is constant.
-
\begin{sloppypar}
Usually these cells are generated by the {\tt proc} pass using the information
in the designs RTLIL::Process objects.
\end{sloppypar}
+D-type flip-flops with synchronous reset are represented by {\tt \$sdff} cells. As the {\tt \$dff}
+cells they have \B{CLK}, \B{D} and \B{Q} ports. In addition they also have a single-bit \B{SRST}
+input port for the reset pin and the following additional two parameters:
+
+\begin{itemize}
+\item \B{SRST\_POLARITY} \\
+The synchronous reset is active-high if this parameter has the value {\tt 1'b1} and active-low
+if this parameter is {\tt 1'b0}.
+
+\item \B{SRST\_VALUE} \\
+The state of \B{Q} will be set to this value when the reset is active.
+\end{itemize}
+
+Note that the {\tt \$adff} and {\tt \$sdff} cells can only be used when the reset value is constant.
+
D-type flip-flops with asynchronous set and reset are represented by {\tt \$dffsr} cells.
As the {\tt \$dff} cells they have \B{CLK}, \B{D} and \B{Q} ports. In addition they also have
-a single-bit \B{SET} input port for the set pin, a single-bit \B{CLR} input port for the reset pin,
-and the following two parameters:
+multi-bit \B{SET} and \B{CLR} input ports and the corresponding polarity parameters, like
+{\tt \$sr} cells.
+
+D-type flip-flops with enable are represented by {\tt \$dffe}, {\tt \$adffe}, {\tt \$dffsre},
+{\tt \$sdffe}, and {\tt \$sdffce} cells, which are enhanced variants of {\tt \$dff}, {\tt \$adff}, {\tt \$dffsr},
+{\tt \$sdff} (with reset over enable) and {\tt \$sdff} (with enable over reset)
+cells, respectively. They have the same ports and parameters as their base cell.
+In addition they also have a single-bit \B{EN} input port for the enable pin and the following parameter:
\begin{itemize}
-\item \B{SET\_POLARITY} \\
-The set input is active-high if this parameter has the value {\tt 1'b1} and active-low
+\item \B{EN\_POLARITY} \\
+The enable input is active-high if this parameter has the value {\tt 1'b1} and active-low
if this parameter is {\tt 1'b0}.
+\end{itemize}
-\item \B{CLR\_POLARITY} \\
-The reset input is active-high if this parameter has the value {\tt 1'b1} and active-low
+D-type latches are represented by {\tt \$dlatch} cells. These cells have an enable port \B{EN},
+an input port \B{D}, and an output port \B{Q}. The following parameters are available for {\tt \$dlatch} cells:
+
+\begin{itemize}
+\item \B{WIDTH} \\
+The width of input \B{D} and output \B{Q}.
+
+\item \B{EN\_POLARITY} \\
+The enable input is active-high if this parameter has the value {\tt 1'b1} and active-low
if this parameter is {\tt 1'b0}.
\end{itemize}
-When both the set and reset inputs of a {\tt \$dffsr} cell are active, the reset input takes
-precedence.
+The latch is transparent when the \B{EN} input is active.
-\begin{fixme}
-Add information about {\tt \$sr} cells (set-reset flip-flops), {\tt \$dlatch} cells (d-type latches),
-and {\tt \$dlatchsr} cells (d-type latches with set/reset).
-\end{fixme}
+D-type latches with reset are represented by {\tt \$adlatch} cells. In addition to {\tt \$dlatch}
+ports and parameters, they also have a single-bit \B{ARST} input port for the reset pin and the following additional parameters:
+
+\begin{itemize}
+\item \B{ARST\_POLARITY} \\
+The asynchronous reset is active-high if this parameter has the value {\tt 1'b1} and active-low
+if this parameter is {\tt 1'b0}.
+
+\item \B{ARST\_VALUE} \\
+The state of \B{Q} will be set to this value when the reset is active.
+\end{itemize}
+
+D-type latches with set and reset are represented by {\tt \$dlatchsr} cells.
+In addition to {\tt \$dlatch} ports and parameters, they also have multi-bit
+\B{SET} and \B{CLR} input ports and the corresponding polarity parameters, like
+{\tt \$sr} cells.
\subsection{Memories}
\label{sec:memcells}
@@ -438,6 +509,23 @@ The {\tt memory\_map} pass can be used to implement {\tt \$mem} cells as basic l
Add a brief description of the {\tt \$fsm} cell type.
\end{fixme}
+\subsection{Specify rules}
+
+\begin{fixme}
+Add information about {\tt \$specify2}, {\tt \$specify3}, and {\tt \$specrule} cells.
+\end{fixme}
+
+\subsection{Formal verification cells}
+
+\begin{fixme}
+Add information about {\tt \$assert}, {\tt \$assume}, {\tt \$live}, {\tt \$fair}, {\tt \$cover}, {\tt \$equiv},
+{\tt \$initstate}, {\tt \$anyconst}, {\tt \$anyseq}, {\tt \$allconst}, {\tt \$allseq} cells.
+\end{fixme}
+
+\begin{fixme}
+Add information about {\tt \$ff} and {\tt \$\_FF\_} cells.
+\end{fixme}
+
\section{Gates}
\label{sec:celllib_gates}
@@ -452,6 +540,7 @@ source tree.
\begin{tabular}[t]{ll}
Verilog & Cell Type \\
\hline
+\lstinline[language=Verilog]; Y = A; & {\tt \$\_BUF\_} \\
\lstinline[language=Verilog]; Y = ~A; & {\tt \$\_NOT\_} \\
\lstinline[language=Verilog]; Y = A & B; & {\tt \$\_AND\_} \\
\lstinline[language=Verilog]; Y = ~(A & B); & {\tt \$\_NAND\_} \\
@@ -461,26 +550,45 @@ Verilog & Cell Type \\
\lstinline[language=Verilog]; Y = A | ~B; & {\tt \$\_ORNOT\_} \\
\lstinline[language=Verilog]; Y = A ^ B; & {\tt \$\_XOR\_} \\
\lstinline[language=Verilog]; Y = ~(A ^ B); & {\tt \$\_XNOR\_} \\
+\lstinline[language=Verilog]; Y = ~((A & B) | C); & {\tt \$\_AOI3\_} \\
+\lstinline[language=Verilog]; Y = ~((A | B) & C); & {\tt \$\_OAI3\_} \\
+\lstinline[language=Verilog]; Y = ~((A & B) | (C & D)); & {\tt \$\_AOI4\_} \\
+\lstinline[language=Verilog]; Y = ~((A | B) & (C | D)); & {\tt \$\_OAI4\_} \\
\lstinline[language=Verilog]; Y = S ? B : A; & {\tt \$\_MUX\_} \\
-\lstinline[language=Verilog]; Y = EN ? A : 'bz; & {\tt \$\_TBUF\_} \\
+\lstinline[language=Verilog]; Y = ~(S ? B : A); & {\tt \$\_NMUX\_} \\
+(see below) & {\tt \$\_MUX4\_} \\
+(see below) & {\tt \$\_MUX8\_} \\
+(see below) & {\tt \$\_MUX16\_} \\
+\lstinline[language=Verilog]; Y = EN ? A : 1'bz; & {\tt \$\_TBUF\_} \\
\hline
\lstinline[language=Verilog]; always @(negedge C) Q <= D; & {\tt \$\_DFF\_N\_} \\
\lstinline[language=Verilog]; always @(posedge C) Q <= D; & {\tt \$\_DFF\_P\_} \\
+\lstinline[language=Verilog]; always @* if (!E) Q <= D; & {\tt \$\_DLATCH\_N\_} \\
+\lstinline[language=Verilog]; always @* if (E) Q <= D; & {\tt \$\_DLATCH\_P\_} \\
\end{tabular}
+\caption{Cell types for gate level logic networks (main list)}
+\label{tab:CellLib_gates}
+\end{table}
+
+\begin{table}[t]
\hfil
\begin{tabular}[t]{llll}
$ClkEdge$ & $RstLvl$ & $RstVal$ & Cell Type \\
\hline
-\lstinline[language=Verilog];negedge; & \lstinline[language=Verilog];0; & \lstinline[language=Verilog];0; & {\tt \$\_DFF\_NN0\_} \\
-\lstinline[language=Verilog];negedge; & \lstinline[language=Verilog];0; & \lstinline[language=Verilog];1; & {\tt \$\_DFF\_NN1\_} \\
-\lstinline[language=Verilog];negedge; & \lstinline[language=Verilog];1; & \lstinline[language=Verilog];0; & {\tt \$\_DFF\_NP0\_} \\
-\lstinline[language=Verilog];negedge; & \lstinline[language=Verilog];1; & \lstinline[language=Verilog];1; & {\tt \$\_DFF\_NP1\_} \\
-\lstinline[language=Verilog];posedge; & \lstinline[language=Verilog];0; & \lstinline[language=Verilog];0; & {\tt \$\_DFF\_PN0\_} \\
-\lstinline[language=Verilog];posedge; & \lstinline[language=Verilog];0; & \lstinline[language=Verilog];1; & {\tt \$\_DFF\_PN1\_} \\
-\lstinline[language=Verilog];posedge; & \lstinline[language=Verilog];1; & \lstinline[language=Verilog];0; & {\tt \$\_DFF\_PP0\_} \\
-\lstinline[language=Verilog];posedge; & \lstinline[language=Verilog];1; & \lstinline[language=Verilog];1; & {\tt \$\_DFF\_PP1\_} \\
+\lstinline[language=Verilog];negedge; & \lstinline[language=Verilog];0; & \lstinline[language=Verilog];0; & {\tt \$\_DFF\_NN0\_}, {\tt \$\_SDFF\_NN0\_} \\
+\lstinline[language=Verilog];negedge; & \lstinline[language=Verilog];0; & \lstinline[language=Verilog];1; & {\tt \$\_DFF\_NN1\_}, {\tt \$\_SDFF\_NN1\_} \\
+\lstinline[language=Verilog];negedge; & \lstinline[language=Verilog];1; & \lstinline[language=Verilog];0; & {\tt \$\_DFF\_NP0\_}, {\tt \$\_SDFF\_NP0\_} \\
+\lstinline[language=Verilog];negedge; & \lstinline[language=Verilog];1; & \lstinline[language=Verilog];1; & {\tt \$\_DFF\_NP1\_}, {\tt \$\_SDFF\_NP1\_} \\
+\lstinline[language=Verilog];posedge; & \lstinline[language=Verilog];0; & \lstinline[language=Verilog];0; & {\tt \$\_DFF\_PN0\_}, {\tt \$\_SDFF\_PN0\_} \\
+\lstinline[language=Verilog];posedge; & \lstinline[language=Verilog];0; & \lstinline[language=Verilog];1; & {\tt \$\_DFF\_PN1\_}, {\tt \$\_SDFF\_PN1\_} \\
+\lstinline[language=Verilog];posedge; & \lstinline[language=Verilog];1; & \lstinline[language=Verilog];0; & {\tt \$\_DFF\_PP0\_}, {\tt \$\_SDFF\_PP0\_} \\
+\lstinline[language=Verilog];posedge; & \lstinline[language=Verilog];1; & \lstinline[language=Verilog];1; & {\tt \$\_DFF\_PP1\_}, {\tt \$\_SDFF\_PP1\_} \\
\end{tabular}
-% FIXME: the layout of this is broken and I have no idea how to fix it
+\caption{Cell types for gate level logic networks (FFs with reset)}
+\label{tab:CellLib_gates_adff}
+\end{table}
+
+\begin{table}[t]
\hfil
\begin{tabular}[t]{lll}
$ClkEdge$ & $EnLvl$ & Cell Type \\
@@ -490,7 +598,36 @@ $ClkEdge$ & $EnLvl$ & Cell Type \\
\lstinline[language=Verilog];posedge; & \lstinline[language=Verilog];0; & {\tt \$\_DFFE\_PN\_} \\
\lstinline[language=Verilog];posedge; & \lstinline[language=Verilog];1; & {\tt \$\_DFFE\_PP\_} \\
\end{tabular}
-% FIXME: the layout of this is broken too
+\caption{Cell types for gate level logic networks (FFs with enable)}
+\label{tab:CellLib_gates_dffe}
+\end{table}
+
+\begin{table}[t]
+\begin{tabular}[t]{lllll}
+$ClkEdge$ & $RstLvl$ & $RstVal$ & $EnLvl$ & Cell Type \\
+\hline
+\lstinline[language=Verilog];negedge; & \lstinline[language=Verilog];0; & \lstinline[language=Verilog];0; & \lstinline[language=Verilog];0; & {\tt \$\_DFFE\_NN0N\_}, {\tt \$\_SDFFE\_NN0N\_}, {\tt \$\_SDFFCE\_NN0N\_} \\
+\lstinline[language=Verilog];negedge; & \lstinline[language=Verilog];0; & \lstinline[language=Verilog];0; & \lstinline[language=Verilog];1; & {\tt \$\_DFFE\_NN0P\_}, {\tt \$\_SDFFE\_NN0P\_}, {\tt \$\_SDFFCE\_NN0P\_} \\
+\lstinline[language=Verilog];negedge; & \lstinline[language=Verilog];0; & \lstinline[language=Verilog];1; & \lstinline[language=Verilog];0; & {\tt \$\_DFFE\_NN1N\_}, {\tt \$\_SDFFE\_NN1N\_}, {\tt \$\_SDFFCE\_NN1N\_} \\
+\lstinline[language=Verilog];negedge; & \lstinline[language=Verilog];0; & \lstinline[language=Verilog];1; & \lstinline[language=Verilog];1; & {\tt \$\_DFFE\_NN1P\_}, {\tt \$\_SDFFE\_NN1P\_}, {\tt \$\_SDFFCE\_NN1P\_} \\
+\lstinline[language=Verilog];negedge; & \lstinline[language=Verilog];1; & \lstinline[language=Verilog];0; & \lstinline[language=Verilog];0; & {\tt \$\_DFFE\_NP0N\_}, {\tt \$\_SDFFE\_NP0N\_}, {\tt \$\_SDFFCE\_NP0N\_} \\
+\lstinline[language=Verilog];negedge; & \lstinline[language=Verilog];1; & \lstinline[language=Verilog];0; & \lstinline[language=Verilog];1; & {\tt \$\_DFFE\_NP0P\_}, {\tt \$\_SDFFE\_NP0P\_}, {\tt \$\_SDFFCE\_NP0P\_} \\
+\lstinline[language=Verilog];negedge; & \lstinline[language=Verilog];1; & \lstinline[language=Verilog];1; & \lstinline[language=Verilog];0; & {\tt \$\_DFFE\_NP1N\_}, {\tt \$\_SDFFE\_NP1N\_}, {\tt \$\_SDFFCE\_NP1N\_} \\
+\lstinline[language=Verilog];negedge; & \lstinline[language=Verilog];1; & \lstinline[language=Verilog];1; & \lstinline[language=Verilog];1; & {\tt \$\_DFFE\_NP1P\_}, {\tt \$\_SDFFE\_NP1P\_}, {\tt \$\_SDFFCE\_NP1P\_} \\
+\lstinline[language=Verilog];posedge; & \lstinline[language=Verilog];0; & \lstinline[language=Verilog];0; & \lstinline[language=Verilog];0; & {\tt \$\_DFFE\_PN0N\_}, {\tt \$\_SDFFE\_PN0N\_}, {\tt \$\_SDFFCE\_PN0N\_} \\
+\lstinline[language=Verilog];posedge; & \lstinline[language=Verilog];0; & \lstinline[language=Verilog];0; & \lstinline[language=Verilog];1; & {\tt \$\_DFFE\_PN0P\_}, {\tt \$\_SDFFE\_PN0P\_}, {\tt \$\_SDFFCE\_PN0P\_} \\
+\lstinline[language=Verilog];posedge; & \lstinline[language=Verilog];0; & \lstinline[language=Verilog];1; & \lstinline[language=Verilog];0; & {\tt \$\_DFFE\_PN1N\_}, {\tt \$\_SDFFE\_PN1N\_}, {\tt \$\_SDFFCE\_PN1N\_} \\
+\lstinline[language=Verilog];posedge; & \lstinline[language=Verilog];0; & \lstinline[language=Verilog];1; & \lstinline[language=Verilog];1; & {\tt \$\_DFFE\_PN1P\_}, {\tt \$\_SDFFE\_PN1P\_}, {\tt \$\_SDFFCE\_PN1P\_} \\
+\lstinline[language=Verilog];posedge; & \lstinline[language=Verilog];1; & \lstinline[language=Verilog];0; & \lstinline[language=Verilog];0; & {\tt \$\_DFFE\_PP0N\_}, {\tt \$\_SDFFE\_PP0N\_}, {\tt \$\_SDFFCE\_PP0N\_} \\
+\lstinline[language=Verilog];posedge; & \lstinline[language=Verilog];1; & \lstinline[language=Verilog];0; & \lstinline[language=Verilog];1; & {\tt \$\_DFFE\_PP0P\_}, {\tt \$\_SDFFE\_PP0P\_}, {\tt \$\_SDFFCE\_PP0P\_} \\
+\lstinline[language=Verilog];posedge; & \lstinline[language=Verilog];1; & \lstinline[language=Verilog];1; & \lstinline[language=Verilog];0; & {\tt \$\_DFFE\_PP1N\_}, {\tt \$\_SDFFE\_PP1N\_}, {\tt \$\_SDFFCE\_PP1N\_} \\
+\lstinline[language=Verilog];posedge; & \lstinline[language=Verilog];1; & \lstinline[language=Verilog];1; & \lstinline[language=Verilog];1; & {\tt \$\_DFFE\_PP1P\_}, {\tt \$\_SDFFE\_PP1P\_}, {\tt \$\_SDFFCE\_PP1P\_} \\
+\end{tabular}
+\caption{Cell types for gate level logic networks (FFs with reset and enable)}
+\label{tab:CellLib_gates_adffe}
+\end{table}
+
+\begin{table}[t]
\hfil
\begin{tabular}[t]{llll}
$ClkEdge$ & $SetLvl$ & $RstLvl$ & Cell Type \\
@@ -504,18 +641,118 @@ $ClkEdge$ & $SetLvl$ & $RstLvl$ & Cell Type \\
\lstinline[language=Verilog];posedge; & \lstinline[language=Verilog];1; & \lstinline[language=Verilog];0; & {\tt \$\_DFFSR\_PPN\_} \\
\lstinline[language=Verilog];posedge; & \lstinline[language=Verilog];1; & \lstinline[language=Verilog];1; & {\tt \$\_DFFSR\_PPP\_} \\
\end{tabular}
-\caption{Cell types for gate level logic networks}
-\label{tab:CellLib_gates}
+\caption{Cell types for gate level logic networks (FFs with set and reset)}
+\label{tab:CellLib_gates_dffsr}
+\end{table}
+
+\begin{table}[t]
+\hfil
+\begin{tabular}[t]{lllll}
+$ClkEdge$ & $SetLvl$ & $RstLvl$ & $EnLvl$ & Cell Type \\
+\hline
+\lstinline[language=Verilog];negedge; & \lstinline[language=Verilog];0; & \lstinline[language=Verilog];0; & \lstinline[language=Verilog];0; & {\tt \$\_DFFSRE\_NNNN\_} \\
+\lstinline[language=Verilog];negedge; & \lstinline[language=Verilog];0; & \lstinline[language=Verilog];0; & \lstinline[language=Verilog];1; & {\tt \$\_DFFSRE\_NNNP\_} \\
+\lstinline[language=Verilog];negedge; & \lstinline[language=Verilog];0; & \lstinline[language=Verilog];1; & \lstinline[language=Verilog];0; & {\tt \$\_DFFSRE\_NNPN\_} \\
+\lstinline[language=Verilog];negedge; & \lstinline[language=Verilog];0; & \lstinline[language=Verilog];1; & \lstinline[language=Verilog];1; & {\tt \$\_DFFSRE\_NNPP\_} \\
+\lstinline[language=Verilog];negedge; & \lstinline[language=Verilog];1; & \lstinline[language=Verilog];0; & \lstinline[language=Verilog];0; & {\tt \$\_DFFSRE\_NPNN\_} \\
+\lstinline[language=Verilog];negedge; & \lstinline[language=Verilog];1; & \lstinline[language=Verilog];0; & \lstinline[language=Verilog];1; & {\tt \$\_DFFSRE\_NPNP\_} \\
+\lstinline[language=Verilog];negedge; & \lstinline[language=Verilog];1; & \lstinline[language=Verilog];1; & \lstinline[language=Verilog];0; & {\tt \$\_DFFSRE\_NPPN\_} \\
+\lstinline[language=Verilog];negedge; & \lstinline[language=Verilog];1; & \lstinline[language=Verilog];1; & \lstinline[language=Verilog];1; & {\tt \$\_DFFSRE\_NPPP\_} \\
+\lstinline[language=Verilog];posedge; & \lstinline[language=Verilog];0; & \lstinline[language=Verilog];0; & \lstinline[language=Verilog];0; & {\tt \$\_DFFSRE\_PNNN\_} \\
+\lstinline[language=Verilog];posedge; & \lstinline[language=Verilog];0; & \lstinline[language=Verilog];0; & \lstinline[language=Verilog];1; & {\tt \$\_DFFSRE\_PNNP\_} \\
+\lstinline[language=Verilog];posedge; & \lstinline[language=Verilog];0; & \lstinline[language=Verilog];1; & \lstinline[language=Verilog];0; & {\tt \$\_DFFSRE\_PNPN\_} \\
+\lstinline[language=Verilog];posedge; & \lstinline[language=Verilog];0; & \lstinline[language=Verilog];1; & \lstinline[language=Verilog];1; & {\tt \$\_DFFSRE\_PNPP\_} \\
+\lstinline[language=Verilog];posedge; & \lstinline[language=Verilog];1; & \lstinline[language=Verilog];0; & \lstinline[language=Verilog];0; & {\tt \$\_DFFSRE\_PPNN\_} \\
+\lstinline[language=Verilog];posedge; & \lstinline[language=Verilog];1; & \lstinline[language=Verilog];0; & \lstinline[language=Verilog];1; & {\tt \$\_DFFSRE\_PPNP\_} \\
+\lstinline[language=Verilog];posedge; & \lstinline[language=Verilog];1; & \lstinline[language=Verilog];1; & \lstinline[language=Verilog];0; & {\tt \$\_DFFSRE\_PPPN\_} \\
+\lstinline[language=Verilog];posedge; & \lstinline[language=Verilog];1; & \lstinline[language=Verilog];1; & \lstinline[language=Verilog];1; & {\tt \$\_DFFSRE\_PPPP\_} \\
+\end{tabular}
+\caption{Cell types for gate level logic networks (FFs with set and reset and enable)}
+\label{tab:CellLib_gates_dffsre}
+\end{table}
+
+\begin{table}[t]
+\hfil
+\begin{tabular}[t]{llll}
+$EnLvl$ & $RstLvl$ & $RstVal$ & Cell Type \\
+\hline
+\lstinline[language=Verilog];0; & \lstinline[language=Verilog];0; & \lstinline[language=Verilog];0; & {\tt \$\_DLATCH\_NN0\_} \\
+\lstinline[language=Verilog];0; & \lstinline[language=Verilog];0; & \lstinline[language=Verilog];1; & {\tt \$\_DLATCH\_NN1\_} \\
+\lstinline[language=Verilog];0; & \lstinline[language=Verilog];1; & \lstinline[language=Verilog];0; & {\tt \$\_DLATCH\_NP0\_} \\
+\lstinline[language=Verilog];0; & \lstinline[language=Verilog];1; & \lstinline[language=Verilog];1; & {\tt \$\_DLATCH\_NP1\_} \\
+\lstinline[language=Verilog];1; & \lstinline[language=Verilog];0; & \lstinline[language=Verilog];0; & {\tt \$\_DLATCH\_PN0\_} \\
+\lstinline[language=Verilog];1; & \lstinline[language=Verilog];0; & \lstinline[language=Verilog];1; & {\tt \$\_DLATCH\_PN1\_} \\
+\lstinline[language=Verilog];1; & \lstinline[language=Verilog];1; & \lstinline[language=Verilog];0; & {\tt \$\_DLATCH\_PP0\_} \\
+\lstinline[language=Verilog];1; & \lstinline[language=Verilog];1; & \lstinline[language=Verilog];1; & {\tt \$\_DLATCH\_PP1\_} \\
+\end{tabular}
+\caption{Cell types for gate level logic networks (latches with reset)}
+\label{tab:CellLib_gates_adlatch}
+\end{table}
+
+\begin{table}[t]
+\hfil
+\begin{tabular}[t]{llll}
+$EnLvl$ & $SetLvl$ & $RstLvl$ & Cell Type \\
+\hline
+\lstinline[language=Verilog];0; & \lstinline[language=Verilog];0; & \lstinline[language=Verilog];0; & {\tt \$\_DLATCHSR\_NNN\_} \\
+\lstinline[language=Verilog];0; & \lstinline[language=Verilog];0; & \lstinline[language=Verilog];1; & {\tt \$\_DLATCHSR\_NNP\_} \\
+\lstinline[language=Verilog];0; & \lstinline[language=Verilog];1; & \lstinline[language=Verilog];0; & {\tt \$\_DLATCHSR\_NPN\_} \\
+\lstinline[language=Verilog];0; & \lstinline[language=Verilog];1; & \lstinline[language=Verilog];1; & {\tt \$\_DLATCHSR\_NPP\_} \\
+\lstinline[language=Verilog];1; & \lstinline[language=Verilog];0; & \lstinline[language=Verilog];0; & {\tt \$\_DLATCHSR\_PNN\_} \\
+\lstinline[language=Verilog];1; & \lstinline[language=Verilog];0; & \lstinline[language=Verilog];1; & {\tt \$\_DLATCHSR\_PNP\_} \\
+\lstinline[language=Verilog];1; & \lstinline[language=Verilog];1; & \lstinline[language=Verilog];0; & {\tt \$\_DLATCHSR\_PPN\_} \\
+\lstinline[language=Verilog];1; & \lstinline[language=Verilog];1; & \lstinline[language=Verilog];1; & {\tt \$\_DLATCHSR\_PPP\_} \\
+\end{tabular}
+\caption{Cell types for gate level logic networks (latches with set and reset)}
+\label{tab:CellLib_gates_dlatchsr}
+\end{table}
+
+\begin{table}[t]
+\hfil
+\begin{tabular}[t]{llll}
+$SetLvl$ & $RstLvl$ & Cell Type \\
+\hline
+\lstinline[language=Verilog];0; & \lstinline[language=Verilog];0; & {\tt \$\_SR\_NN\_} \\
+\lstinline[language=Verilog];0; & \lstinline[language=Verilog];1; & {\tt \$\_SR\_NP\_} \\
+\lstinline[language=Verilog];1; & \lstinline[language=Verilog];0; & {\tt \$\_SR\_PN\_} \\
+\lstinline[language=Verilog];1; & \lstinline[language=Verilog];1; & {\tt \$\_SR\_PP\_} \\
+\end{tabular}
+\caption{Cell types for gate level logic networks (SR latches)}
+\label{tab:CellLib_gates_sr}
\end{table}
-Table~\ref{tab:CellLib_gates} lists all cell types used for gate level logic. The cell types
-{\tt \$\_NOT\_}, {\tt \$\_AND\_}, {\tt \$\_NAND\_}, {\tt \$\_ANDNOT\_}, {\tt \$\_OR\_}, {\tt \$\_NOR\_},
-{\tt \$\_ORNOT\_}, {\tt \$\_XOR\_}, {\tt \$\_XNOR\_} and {\tt \$\_MUX\_} are used to model combinatorial logic.
+Tables~\ref{tab:CellLib_gates}, \ref{tab:CellLib_gates_dffe}, \ref{tab:CellLib_gates_adff}, \ref{tab:CellLib_gates_adffe}, \ref{tab:CellLib_gates_dffsr}, \ref{tab:CellLib_gates_dffsre}, \ref{tab:CellLib_gates_adlatch}, \ref{tab:CellLib_gates_dlatchsr} and \ref{tab:CellLib_gates_sr} list all cell types used for gate level logic. The cell types
+{\tt \$\_BUF\_}, {\tt \$\_NOT\_}, {\tt \$\_AND\_}, {\tt \$\_NAND\_}, {\tt \$\_ANDNOT\_},
+{\tt \$\_OR\_}, {\tt \$\_NOR\_}, {\tt \$\_ORNOT\_}, {\tt \$\_XOR\_}, {\tt \$\_XNOR\_},
+{\tt \$\_AOI3\_}, {\tt \$\_OAI3\_}, {\tt \$\_AOI4\_}, {\tt \$\_OAI4\_},
+{\tt \$\_MUX\_}, {\tt \$\_MUX4\_}, {\tt \$\_MUX8\_}, {\tt \$\_MUX16\_} and {\tt \$\_NMUX\_} are used to model combinatorial logic.
The cell type {\tt \$\_TBUF\_} is used to model tristate logic.
+The {\tt \$\_MUX4\_}, {\tt \$\_MUX8\_} and {\tt \$\_MUX16\_} cells are used to model wide muxes, and correspond to the following Verilog code:
+
+\begin{lstlisting}[language=Verilog]
+// $_MUX4_
+assign Y = T ? (S ? D : C) :
+ (S ? B : A);
+// $_MUX8_
+assign Y = U ? T ? (S ? H : G) :
+ (S ? F : E) :
+ T ? (S ? D : C) :
+ (S ? B : A);
+// $_MUX16_
+assign Y = V ? U ? T ? (S ? P : O) :
+ (S ? N : M) :
+ T ? (S ? L : K) :
+ (S ? J : I) :
+ U ? T ? (S ? H : G) :
+ (S ? F : E) :
+ T ? (S ? D : C) :
+ (S ? B : A);
+\end{lstlisting}
+
The cell types {\tt \$\_DFF\_N\_} and {\tt \$\_DFF\_P\_} represent d-type flip-flops.
-The cell types {\tt \$\_DFFE\_NN\_}, {\tt \$\_DFFE\_NP\_}, {\tt \$\_DFFE\_PN\_} and {\tt \$\_DFFE\_PP\_}
+The cell types {\tt \$\_DFFE\_[NP][NP]\_}
implement d-type flip-flops with enable. The values in the table for these cell types relate to the
following Verilog code template.
@@ -525,8 +762,7 @@ following Verilog code template.
Q <= D;
\end{lstlisting}
-The cell types {\tt \$\_DFF\_NN0\_}, {\tt \$\_DFF\_NN1\_}, {\tt \$\_DFF\_NP0\_}, {\tt \$\_DFF\_NP1\_},
-{\tt \$\_DFF\_PN0\_}, {\tt \$\_DFF\_PN1\_}, {\tt \$\_DFF\_PP0\_} and {\tt \$\_DFF\_PP1\_} implement
+The cell types {\tt \$\_DFF\_[NP][NP][01]\_} implement
d-type flip-flops with asynchronous reset. The values in the table for these cell types relate to the
following Verilog code template, where \lstinline[mathescape,language=Verilog];$RstEdge$; is \lstinline[language=Verilog];posedge;
if \lstinline[mathescape,language=Verilog];$RstLvl$; if \lstinline[language=Verilog];1;, and \lstinline[language=Verilog];negedge;
@@ -540,8 +776,60 @@ otherwise.
Q <= D;
\end{lstlisting}
-The cell types {\tt \$\_DFFSR\_NNN\_}, {\tt \$\_DFFSR\_NNP\_}, {\tt \$\_DFFSR\_NPN\_}, {\tt \$\_DFFSR\_NPP\_},
-{\tt \$\_DFFSR\_PNN\_}, {\tt \$\_DFFSR\_PNP\_}, {\tt \$\_DFFSR\_PPN\_} and {\tt \$\_DFFSR\_PPP\_} implement
+The cell types {\tt \$\_SDFF\_[NP][NP][01]\_} implement
+d-type flip-flops with synchronous reset. The values in the table for these cell types relate to the
+following Verilog code template:
+
+\begin{lstlisting}[mathescape,language=Verilog]
+ always @($ClkEdge$ C)
+ if (R == $RstLvl$)
+ Q <= $RstVal$;
+ else
+ Q <= D;
+\end{lstlisting}
+
+The cell types {\tt \$\_DFFE\_[NP][NP][01][NP]\_} implement
+d-type flip-flops with asynchronous reset and enable. The values in the table for these cell types relate to the
+following Verilog code template, where \lstinline[mathescape,language=Verilog];$RstEdge$; is \lstinline[language=Verilog];posedge;
+if \lstinline[mathescape,language=Verilog];$RstLvl$; if \lstinline[language=Verilog];1;, and \lstinline[language=Verilog];negedge;
+otherwise.
+
+\begin{lstlisting}[mathescape,language=Verilog]
+ always @($ClkEdge$ C, $RstEdge$ R)
+ if (R == $RstLvl$)
+ Q <= $RstVal$;
+ else if (EN == $EnLvl$)
+ Q <= D;
+\end{lstlisting}
+
+The cell types {\tt \$\_SDFFE\_[NP][NP][01][NP]\_} implement d-type flip-flops
+with synchronous reset and enable, with reset having priority over enable.
+The values in the table for these cell types relate to the
+following Verilog code template:
+
+\begin{lstlisting}[mathescape,language=Verilog]
+ always @($ClkEdge$ C)
+ if (R == $RstLvl$)
+ Q <= $RstVal$;
+ else if (EN == $EnLvl$)
+ Q <= D;
+\end{lstlisting}
+
+The cell types {\tt \$\_SDFFCE\_[NP][NP][01][NP]\_} implement d-type flip-flops
+with synchronous reset and enable, with enable having priority over reset.
+The values in the table for these cell types relate to the
+following Verilog code template:
+
+\begin{lstlisting}[mathescape,language=Verilog]
+ always @($ClkEdge$ C)
+ if (EN == $EnLvl$)
+ if (R == $RstLvl$)
+ Q <= $RstVal$;
+ else
+ Q <= D;
+\end{lstlisting}
+
+The cell types {\tt \$\_DFFSR\_[NP][NP][NP]\_} implement
d-type flip-flops with asynchronous set and reset. The values in the table for these cell types relate to the
following Verilog code template, where \lstinline[mathescape,language=Verilog];$RstEdge$; is \lstinline[language=Verilog];posedge;
if \lstinline[mathescape,language=Verilog];$RstLvl$; if \lstinline[language=Verilog];1;, \lstinline[language=Verilog];negedge;
@@ -559,21 +847,70 @@ otherwise.
Q <= D;
\end{lstlisting}
+The cell types {\tt \$\_DFFSRE\_[NP][NP][NP][NP]\_} implement
+d-type flip-flops with asynchronous set and reset and enable. The values in the table for these cell types relate to the
+following Verilog code template, where \lstinline[mathescape,language=Verilog];$RstEdge$; is \lstinline[language=Verilog];posedge;
+if \lstinline[mathescape,language=Verilog];$RstLvl$; if \lstinline[language=Verilog];1;, \lstinline[language=Verilog];negedge;
+otherwise, and \lstinline[mathescape,language=Verilog];$SetEdge$; is \lstinline[language=Verilog];posedge;
+if \lstinline[mathescape,language=Verilog];$SetLvl$; if \lstinline[language=Verilog];1;, \lstinline[language=Verilog];negedge;
+otherwise.
+
+\begin{lstlisting}[mathescape,language=Verilog]
+ always @($ClkEdge$ C, $RstEdge$ R, $SetEdge$ S)
+ if (R == $RstLvl$)
+ Q <= 0;
+ else if (S == $SetLvl$)
+ Q <= 1;
+ else if (E == $EnLvl$)
+ Q <= D;
+\end{lstlisting}
+
+The cell types {\tt \$\_DLATCH\_N\_} and {\tt \$\_DLATCH\_P\_} represent d-type latches.
+
+The cell types {\tt \$\_DLATCH\_[NP][NP][01]\_} implement
+d-type latches with reset. The values in the table for these cell types relate to the
+following Verilog code template:
+
+\begin{lstlisting}[mathescape,language=Verilog]
+ always @*
+ if (R == $RstLvl$)
+ Q <= $RstVal$;
+ else if (E == $EnLvl$)
+ Q <= D;
+\end{lstlisting}
+
+The cell types {\tt \$\_DLATCHSR\_[NP][NP][NP]\_} implement
+d-type latches with set and reset. The values in the table for these cell types relate to the
+following Verilog code template:
+
+\begin{lstlisting}[mathescape,language=Verilog]
+ always @*
+ if (R == $RstLvl$)
+ Q <= 0;
+ else if (S == $SetLvl$)
+ Q <= 1;
+ else if (E == $EnLvl$)
+ Q <= D;
+\end{lstlisting}
+
+The cell types {\tt \$\_SR\_[NP][NP]\_} implement
+sr-type latches. The values in the table for these cell types relate to the
+following Verilog code template:
+
+\begin{lstlisting}[mathescape,language=Verilog]
+ always @*
+ if (R == $RstLvl$)
+ Q <= 0;
+ else if (S == $SetLvl$)
+ Q <= 1;
+\end{lstlisting}
+
In most cases gate level logic networks are created from RTL networks using the {\tt techmap} pass. The flip-flop cells
from the gate level logic network can be mapped to physical flip-flop cells from a Liberty file using the {\tt dfflibmap}
pass. The combinatorial logic cells can be mapped to physical cells from a Liberty file via ABC \citeweblink{ABC}
using the {\tt abc} pass.
\begin{fixme}
-Add information about {\tt \$assert}, {\tt \$assume}, {\tt \$live}, {\tt \$fair}, {\tt \$cover}, {\tt \$equiv},
-{\tt \$initstate}, {\tt \$anyconst}, {\tt \$anyseq}, {\tt \$allconst}, {\tt \$allseq} cells.
-\end{fixme}
-
-\begin{fixme}
-Add information about {\tt \$specify2}, {\tt \$specify3}, and {\tt \$specrule} cells.
-\end{fixme}
-
-\begin{fixme}
Add information about {\tt \$slice} and {\tt \$concat} cells.
\end{fixme}
@@ -584,16 +921,3 @@ Add information about {\tt \$lut} and {\tt \$sop} cells.
\begin{fixme}
Add information about {\tt \$alu}, {\tt \$macc}, {\tt \$fa}, and {\tt \$lcu} cells.
\end{fixme}
-
-\begin{fixme}
-Add information about {\tt \$ff} and {\tt \$\_FF\_} cells.
-\end{fixme}
-
-\begin{fixme}
-Add information about {\tt \$\_DLATCH\_?\_}, and {\tt \$\_DLATCHSR\_???\_} cells.
-\end{fixme}
-
-\begin{fixme}
-Add information about {\tt \$\_AOI3\_}, {\tt \$\_OAI3\_}, {\tt \$\_AOI4\_}, {\tt \$\_OAI4\_}, and {\tt \$\_NMUX\_} cells.
-\end{fixme}
-
diff --git a/manual/CHAPTER_Overview.tex b/manual/CHAPTER_Overview.tex
index be37d8d39..83cfa5cc4 100644
--- a/manual/CHAPTER_Overview.tex
+++ b/manual/CHAPTER_Overview.tex
@@ -184,12 +184,22 @@ may hold important information for Yosys developers can be used without
disturbing external tools. For example the Verilog backend assigns names in the form {\tt \_{\it integer}\_}.
\end{itemize}
-In order to avoid programming errors, the RTLIL data structures check if all
-identifiers start with either a backslash or a dollar sign and generate a
-runtime error if this rule is violated.
+Whitespace and control characters (any character with an ASCII code 32 or less) are not allowed
+in RTLIL identifiers; most frontends and backends cannot support these characters in identifiers.
+
+In order to avoid programming errors, the RTLIL data structures check if all identifiers start
+with either a backslash or a dollar sign, and contain no whitespace or control characters.
+Violating these rules results in a runtime error.
All RTLIL identifiers are case sensitive.
+Some transformations, such as flattening, may have to change identifiers provided by the user
+to avoid name collisions. When that happens, attribute ``{\tt hdlname}`` is attached to the object
+with the changed identifier. This attribute contains one name (if emitted directly by the frontend,
+or is a result of disambiguation) or multiple names separated by spaces (if a result of flattening).
+All names specified in the ``{\tt hdlname}`` attribute are public and do not include the leading
+``\textbackslash``.
+
\subsection{RTLIL::Design and RTLIL::Module}
The RTLIL::Design object is basically just a container for RTLIL::Module objects. In addition to
diff --git a/manual/CHAPTER_Prog/stubnets.cc b/manual/CHAPTER_Prog/stubnets.cc
index 8123e63db..566d24b18 100644
--- a/manual/CHAPTER_Prog/stubnets.cc
+++ b/manual/CHAPTER_Prog/stubnets.cc
@@ -98,7 +98,7 @@ static void find_stub_nets(RTLIL::Design *design, RTLIL::Module *module, bool re
// each pass contains a singleton object that is derived from Pass
struct StubnetsPass : public Pass {
StubnetsPass() : Pass("stubnets") { }
- void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
+ void execute(std::vector<std::string> args, RTLIL::Design *design) override
{
// variables to mirror information from passed options
bool report_bits = 0;
diff --git a/manual/PRESENTATION_Prog.tex b/manual/PRESENTATION_Prog.tex
index b85eda892..a9416f82a 100644
--- a/manual/PRESENTATION_Prog.tex
+++ b/manual/PRESENTATION_Prog.tex
@@ -307,7 +307,7 @@ cell name from the internal cell library:
\begin{lstlisting}[xleftmargin=1cm, basicstyle=\ttfamily\fontsize{6pt}{7pt}\selectfont]
$not $pos $neg $and $or $xor $xnor $reduce_and $reduce_or $reduce_xor $reduce_xnor
$reduce_bool $shl $shr $sshl $sshr $lt $le $eq $ne $eqx $nex $ge $gt $add $sub $mul $div $mod
-$pow $logic_not $logic_and $logic_or $mux $pmux $slice $concat $lut $assert $sr $dff
+$divfloor $modfloor $pow $logic_not $logic_and $logic_or $mux $pmux $slice $concat $lut $assert $sr $dff
$dffsr $adff $dlatch $dlatchsr $memrd $memwr $mem $fsm $_NOT_ $_AND_ $_OR_ $_XOR_ $_MUX_ $_SR_NN_
$_SR_NP_ $_SR_PN_ $_SR_PP_ $_DFF_N_ $_DFF_P_ $_DFF_NN0_ $_DFF_NN1_ $_DFF_NP0_ $_DFF_NP1_ $_DFF_PN0_
$_DFF_PN1_ $_DFF_PP0_ $_DFF_PP1_ $_DFFSR_NNN_ $_DFFSR_NNP_ $_DFFSR_NPN_ $_DFFSR_NPP_ $_DFFSR_PNN_
diff --git a/manual/PRESENTATION_Prog/Makefile b/manual/PRESENTATION_Prog/Makefile
index 794f5c12c..7e3cf814b 100644
--- a/manual/PRESENTATION_Prog/Makefile
+++ b/manual/PRESENTATION_Prog/Makefile
@@ -1,8 +1,11 @@
all: test0.log test1.log test2.log
+CXXFLAGS=$(shell ../../yosys-config --cxxflags)
+DATDIR=$(shell ../../yosys-config --datdir)
+
my_cmd.so: my_cmd.cc
- ../../yosys-config --exec --cxx --cxxflags --ldflags -o my_cmd.so -shared my_cmd.cc --ldlibs
+ ../../yosys-config --exec --cxx $(subst $(DATDIR),../../share,$(CXXFLAGS)) --ldflags -o my_cmd.so -shared my_cmd.cc --ldlibs
test0.log: my_cmd.so
../../yosys -Ql test0.log_new -m ./my_cmd.so -p 'my_cmd foo bar' absval_ref.v
diff --git a/manual/PRESENTATION_Prog/my_cmd.cc b/manual/PRESENTATION_Prog/my_cmd.cc
index 5d9a7e13b..9cb4b8e38 100644
--- a/manual/PRESENTATION_Prog/my_cmd.cc
+++ b/manual/PRESENTATION_Prog/my_cmd.cc
@@ -6,7 +6,7 @@ PRIVATE_NAMESPACE_BEGIN
struct MyPass : public Pass {
MyPass() : Pass("my_cmd", "just a simple test") { }
- void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
+ void execute(std::vector<std::string> args, RTLIL::Design *design) override
{
log("Arguments to my_cmd:\n");
for (auto &arg : args)
@@ -22,7 +22,7 @@ struct MyPass : public Pass {
struct Test1Pass : public Pass {
Test1Pass() : Pass("test1", "creating the absval module") { }
- void execute(std::vector<std::string>, RTLIL::Design *design) YS_OVERRIDE
+ void execute(std::vector<std::string>, RTLIL::Design *design) override
{
if (design->has("\\absval") != 0)
log_error("A module with the name absval already exists!\n");
@@ -49,7 +49,7 @@ struct Test1Pass : public Pass {
struct Test2Pass : public Pass {
Test2Pass() : Pass("test2", "demonstrating sigmap on test module") { }
- void execute(std::vector<std::string>, RTLIL::Design *design) YS_OVERRIDE
+ void execute(std::vector<std::string>, RTLIL::Design *design) override
{
if (design->selection_stack.back().empty())
log_cmd_error("This command can't operator on an empty selection!\n");
diff --git a/misc/py_wrap_generator.py b/misc/py_wrap_generator.py
index fac5b48a4..38bd6129e 100644
--- a/misc/py_wrap_generator.py
+++ b/misc/py_wrap_generator.py
@@ -312,16 +312,16 @@ class PythonListTranslator(Translator):
text += prefix + "\t" + known_containers[types[0].name].typename + " " + tmp_name + " = boost::python::extract<" + known_containers[types[0].name].typename + ">(" + varname + "[" + cntr_name + "]);"
text += known_containers[types[0].name].translate(tmp_name, types[0].cont.args, prefix+"\t")
tmp_name = tmp_name + "___tmp"
- text += prefix + "\t" + varname + "___tmp." + c.insert_name + "(" + tmp_name + ");"
+ text += prefix + "\t" + varname + "___tmp" + c.insert_name + "(" + tmp_name + ");"
elif types[0].name in classnames:
text += prefix + "\t" + types[0].name + "* " + tmp_name + " = boost::python::extract<" + types[0].name + "*>(" + varname + "[" + cntr_name + "]);"
if types[0].attr_type == attr_types.star:
- text += prefix + "\t" + varname + "___tmp." + c.insert_name + "(" + tmp_name + "->get_cpp_obj());"
+ text += prefix + "\t" + varname + "___tmp" + c.insert_name + "(" + tmp_name + "->get_cpp_obj());"
else:
- text += prefix + "\t" + varname + "___tmp." + c.insert_name + "(*" + tmp_name + "->get_cpp_obj());"
+ text += prefix + "\t" + varname + "___tmp" + c.insert_name + "(*" + tmp_name + "->get_cpp_obj());"
else:
text += prefix + "\t" + types[0].name + " " + tmp_name + " = boost::python::extract<" + types[0].name + ">(" + varname + "[" + cntr_name + "]);"
- text += prefix + "\t" + varname + "___tmp." + c.insert_name + "(" + tmp_name + ");"
+ text += prefix + "\t" + varname + "___tmp" + c.insert_name + "(" + tmp_name + ");"
text += prefix + "}"
return text
@@ -349,19 +349,24 @@ class PythonListTranslator(Translator):
text += prefix + "}"
return text
+class IDictTranslator(PythonListTranslator):
+ typename = "boost::python::list"
+ orig_name = "idict"
+ insert_name = ""
+
#Sub-type for std::set
class SetTranslator(PythonListTranslator):
- insert_name = "insert"
+ insert_name = ".insert"
orig_name = "std::set"
#Sub-type for std::vector
class VectorTranslator(PythonListTranslator):
- insert_name = "push_back"
+ insert_name = ".push_back"
orig_name = "std::vector"
#Sub-type for pool
class PoolTranslator(PythonListTranslator):
- insert_name = "insert"
+ insert_name = ".insert"
orig_name = "pool"
#Translates dict-types (dict, std::map), that only differ in their name and
@@ -528,6 +533,7 @@ known_containers = {
"std::set" : SetTranslator,
"std::vector" : VectorTranslator,
"pool" : PoolTranslator,
+ "idict" : IDictTranslator,
"dict" : DictTranslator,
"std::pair" : TupleTranslator,
"std::map" : MapTranslator
@@ -1408,7 +1414,7 @@ class WFunction:
text += ", "
if len(self.args) > 0:
text = text[:-2]
- text += ") YS_OVERRIDE;\n"
+ text += ") override;\n"
return text
def gen_decl_hash_py(self):
diff --git a/passes/cmds/Makefile.inc b/passes/cmds/Makefile.inc
index a88980eaf..53bfd40c6 100644
--- a/passes/cmds/Makefile.inc
+++ b/passes/cmds/Makefile.inc
@@ -39,3 +39,4 @@ OBJS += passes/cmds/bugpoint.o
endif
OBJS += passes/cmds/scratchpad.o
OBJS += passes/cmds/logger.o
+OBJS += passes/cmds/printattrs.o
diff --git a/passes/cmds/add.cc b/passes/cmds/add.cc
index 91f8c2add..a2f4a9100 100644
--- a/passes/cmds/add.cc
+++ b/passes/cmds/add.cc
@@ -116,7 +116,7 @@ static void add_wire(RTLIL::Design *design, RTLIL::Module *module, std::string n
struct AddPass : public Pass {
AddPass() : Pass("add", "add objects to the design") { }
- void help() YS_OVERRIDE
+ void help() override
{
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
log("\n");
@@ -150,7 +150,7 @@ struct AddPass : public Pass {
log("Add module[s] with the specified name[s].\n");
log("\n");
}
- void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
+ void execute(std::vector<std::string> args, RTLIL::Design *design) override
{
std::string command;
std::string arg_name;
diff --git a/passes/cmds/autoname.cc b/passes/cmds/autoname.cc
index 50632201e..28d4012c4 100644
--- a/passes/cmds/autoname.cc
+++ b/passes/cmds/autoname.cc
@@ -92,7 +92,7 @@ int autoname_worker(Module *module)
struct AutonamePass : public Pass {
AutonamePass() : Pass("autoname", "automatically assign names to objects") { }
- void help() YS_OVERRIDE
+ void help() override
{
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
log("\n");
@@ -102,7 +102,7 @@ struct AutonamePass : public Pass {
log("with $-prefix).\n");
log("\n");
}
- void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
+ void execute(std::vector<std::string> args, RTLIL::Design *design) override
{
size_t argidx;
for (argidx = 1; argidx < args.size(); argidx++)
diff --git a/passes/cmds/blackbox.cc b/passes/cmds/blackbox.cc
index 5c0405f15..08a635514 100644
--- a/passes/cmds/blackbox.cc
+++ b/passes/cmds/blackbox.cc
@@ -24,7 +24,7 @@ PRIVATE_NAMESPACE_BEGIN
struct BlackboxPass : public Pass {
BlackboxPass() : Pass("blackbox", "convert modules into blackbox modules") { }
- void help() YS_OVERRIDE
+ void help() override
{
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
log("\n");
@@ -34,7 +34,7 @@ struct BlackboxPass : public Pass {
log("module attribute).\n");
log("\n");
}
- void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
+ void execute(std::vector<std::string> args, RTLIL::Design *design) override
{
size_t argidx;
for (argidx = 1; argidx < args.size(); argidx++)
@@ -48,31 +48,7 @@ struct BlackboxPass : public Pass {
for (auto module : design->selected_whole_modules_warn())
{
- pool<Cell*> remove_cells;
- pool<Wire*> remove_wires;
-
- for (auto cell : module->cells())
- remove_cells.insert(cell);
-
- for (auto wire : module->wires())
- if (wire->port_id == 0)
- remove_wires.insert(wire);
-
- for (auto it = module->memories.begin(); it != module->memories.end(); ++it)
- delete it->second;
- module->memories.clear();
-
- for (auto it = module->processes.begin(); it != module->processes.end(); ++it)
- delete it->second;
- module->processes.clear();
-
- module->new_connections(std::vector<RTLIL::SigSig>());
-
- for (auto cell : remove_cells)
- module->remove(cell);
-
- module->remove(remove_wires);
-
+ module->makeblackbox();
module->set_bool_attribute(ID::blackbox);
}
}
diff --git a/passes/cmds/bugpoint.cc b/passes/cmds/bugpoint.cc
index 00aac596f..98d42aa83 100644
--- a/passes/cmds/bugpoint.cc
+++ b/passes/cmds/bugpoint.cc
@@ -26,7 +26,7 @@ PRIVATE_NAMESPACE_BEGIN
struct BugpointPass : public Pass {
BugpointPass() : Pass("bugpoint", "minimize testcases") { }
- void help() YS_OVERRIDE
+ void help() override
{
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
log("\n");
@@ -313,7 +313,7 @@ struct BugpointPass : public Pass {
return nullptr;
}
- void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
+ void execute(std::vector<std::string> args, RTLIL::Design *design) override
{
string yosys_cmd = "yosys", script, grep;
bool fast = false, clean = false;
diff --git a/passes/cmds/check.cc b/passes/cmds/check.cc
index ba29e6f4b..a8b5362b3 100644
--- a/passes/cmds/check.cc
+++ b/passes/cmds/check.cc
@@ -27,7 +27,7 @@ PRIVATE_NAMESPACE_BEGIN
struct CheckPass : public Pass {
CheckPass() : Pass("check", "check for obvious problems in the design") { }
- void help() YS_OVERRIDE
+ void help() override
{
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
log("\n");
@@ -61,7 +61,7 @@ struct CheckPass : public Pass {
log(" Produce a runtime error if any problems are found in the current design.\n");
log("\n");
}
- void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
+ void execute(std::vector<std::string> args, RTLIL::Design *design) override
{
int counter = 0;
bool noinit = false;
diff --git a/passes/cmds/chformal.cc b/passes/cmds/chformal.cc
index d6e7f2ccf..a1b3fbef7 100644
--- a/passes/cmds/chformal.cc
+++ b/passes/cmds/chformal.cc
@@ -25,7 +25,7 @@ PRIVATE_NAMESPACE_BEGIN
struct ChformalPass : public Pass {
ChformalPass() : Pass("chformal", "change formal constraints of the design") { }
- void help() YS_OVERRIDE
+ void help() override
{
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
log("\n");
@@ -62,7 +62,7 @@ struct ChformalPass : public Pass {
log(" change the roles of cells as indicated. these options can be combined\n");
log("\n");
}
- void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
+ void execute(std::vector<std::string> args, RTLIL::Design *design) override
{
bool assert2assume = false;
bool assume2assert = false;
diff --git a/passes/cmds/chtype.cc b/passes/cmds/chtype.cc
index 979aeadd4..b894f334c 100644
--- a/passes/cmds/chtype.cc
+++ b/passes/cmds/chtype.cc
@@ -24,7 +24,7 @@ PRIVATE_NAMESPACE_BEGIN
struct ChtypePass : public Pass {
ChtypePass() : Pass("chtype", "change type of cells in the design") { }
- void help() YS_OVERRIDE
+ void help() override
{
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
log("\n");
@@ -40,7 +40,7 @@ struct ChtypePass : public Pass {
log("\n");
log("\n");
}
- void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
+ void execute(std::vector<std::string> args, RTLIL::Design *design) override
{
IdString set_type;
dict<IdString, IdString> map_types;
diff --git a/passes/cmds/connect.cc b/passes/cmds/connect.cc
index 0b0868dfb..0cc6cbe52 100644
--- a/passes/cmds/connect.cc
+++ b/passes/cmds/connect.cc
@@ -43,7 +43,7 @@ static void unset_drivers(RTLIL::Design *design, RTLIL::Module *module, SigMap &
struct ConnectPass : public Pass {
ConnectPass() : Pass("connect", "create or remove connections") { }
- void help() YS_OVERRIDE
+ void help() override
{
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
log("\n");
@@ -75,7 +75,7 @@ struct ConnectPass : public Pass {
log("This command does not operate on module with processes.\n");
log("\n");
}
- void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
+ void execute(std::vector<std::string> args, RTLIL::Design *design) override
{
RTLIL::Module *module = nullptr;
for (auto mod : design->selected_modules()) {
diff --git a/passes/cmds/connwrappers.cc b/passes/cmds/connwrappers.cc
index 6ae7c9304..9235dda2b 100644
--- a/passes/cmds/connwrappers.cc
+++ b/passes/cmds/connwrappers.cc
@@ -143,7 +143,7 @@ struct ConnwrappersWorker
struct ConnwrappersPass : public Pass {
ConnwrappersPass() : Pass("connwrappers", "match width of input-output port pairs") { }
- void help() YS_OVERRIDE
+ void help() override
{
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
log("\n");
@@ -165,7 +165,7 @@ struct ConnwrappersPass : public Pass {
log("The options -signed, -unsigned, and -port can be specified multiple times.\n");
log("\n");
}
- void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
+ void execute(std::vector<std::string> args, RTLIL::Design *design) override
{
ConnwrappersWorker worker;
diff --git a/passes/cmds/copy.cc b/passes/cmds/copy.cc
index 99f1f69cf..c351065f3 100644
--- a/passes/cmds/copy.cc
+++ b/passes/cmds/copy.cc
@@ -26,7 +26,7 @@ PRIVATE_NAMESPACE_BEGIN
struct CopyPass : public Pass {
CopyPass() : Pass("copy", "copy modules in the design") { }
- void help() YS_OVERRIDE
+ void help() override
{
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
log("\n");
@@ -36,7 +36,7 @@ struct CopyPass : public Pass {
log("by this command.\n");
log("\n");
}
- void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
+ void execute(std::vector<std::string> args, RTLIL::Design *design) override
{
if (args.size() != 3)
log_cmd_error("Invalid number of arguments!\n");
diff --git a/passes/cmds/cover.cc b/passes/cmds/cover.cc
index 89d27c9aa..0867e3b4f 100644
--- a/passes/cmds/cover.cc
+++ b/passes/cmds/cover.cc
@@ -35,7 +35,7 @@ PRIVATE_NAMESPACE_BEGIN
struct CoverPass : public Pass {
CoverPass() : Pass("cover", "print code coverage counters") { }
- void help() YS_OVERRIDE
+ void help() override
{
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
log("\n");
@@ -83,7 +83,7 @@ struct CoverPass : public Pass {
log("Coverage counters are only available in Yosys for Linux.\n");
log("\n");
}
- void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
+ void execute(std::vector<std::string> args, RTLIL::Design *design) override
{
std::vector<FILE*> out_files;
std::vector<std::string> patterns;
diff --git a/passes/cmds/delete.cc b/passes/cmds/delete.cc
index b124e3b0f..684fa37b0 100644
--- a/passes/cmds/delete.cc
+++ b/passes/cmds/delete.cc
@@ -24,7 +24,7 @@ PRIVATE_NAMESPACE_BEGIN
struct DeletePass : public Pass {
DeletePass() : Pass("delete", "delete objects in the design") { }
- void help() YS_OVERRIDE
+ void help() override
{
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
log("\n");
@@ -40,7 +40,7 @@ struct DeletePass : public Pass {
log("selected wires, thus 'deleting' module ports.\n");
log("\n");
}
- void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
+ void execute(std::vector<std::string> args, RTLIL::Design *design) override
{
bool flag_input = false;
bool flag_output = false;
diff --git a/passes/cmds/design.cc b/passes/cmds/design.cc
index 421defe0c..2d7ba1fef 100644
--- a/passes/cmds/design.cc
+++ b/passes/cmds/design.cc
@@ -28,7 +28,7 @@ std::vector<RTLIL::Design*> pushed_designs;
struct DesignPass : public Pass {
DesignPass() : Pass("design", "save, restore and reset current design") { }
- ~DesignPass() YS_OVERRIDE {
+ ~DesignPass() override {
for (auto &it : saved_designs)
delete it.second;
saved_designs.clear();
@@ -36,7 +36,7 @@ struct DesignPass : public Pass {
delete it;
pushed_designs.clear();
}
- void help() YS_OVERRIDE
+ void help() override
{
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
log("\n");
@@ -105,7 +105,7 @@ struct DesignPass : public Pass {
log("\n");
}
- void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
+ void execute(std::vector<std::string> args, RTLIL::Design *design) override
{
bool got_mode = false;
bool reset_mode = false;
diff --git a/passes/cmds/edgetypes.cc b/passes/cmds/edgetypes.cc
index 58ed6457d..37c420400 100644
--- a/passes/cmds/edgetypes.cc
+++ b/passes/cmds/edgetypes.cc
@@ -25,7 +25,7 @@ PRIVATE_NAMESPACE_BEGIN
struct EdgetypePass : public Pass {
EdgetypePass() : Pass("edgetypes", "list all types of edges in selection") { }
- void help() YS_OVERRIDE
+ void help() override
{
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
log("\n");
@@ -35,7 +35,7 @@ struct EdgetypePass : public Pass {
log("is a 4-tuple of source and sink cell type and port name.\n");
log("\n");
}
- void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
+ void execute(std::vector<std::string> args, RTLIL::Design *design) override
{
size_t argidx;
for (argidx = 1; argidx < args.size(); argidx++) {
diff --git a/passes/cmds/exec.cc b/passes/cmds/exec.cc
index 7eeefe705..951fa53fc 100644
--- a/passes/cmds/exec.cc
+++ b/passes/cmds/exec.cc
@@ -38,7 +38,7 @@ PRIVATE_NAMESPACE_BEGIN
struct ExecPass : public Pass {
ExecPass() : Pass("exec", "execute commands in the operating system shell") { }
- void help() YS_OVERRIDE
+ void help() override
{
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
log("\n");
@@ -71,7 +71,7 @@ struct ExecPass : public Pass {
log("\n");
log("\n");
}
- void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
+ void execute(std::vector<std::string> args, RTLIL::Design *design) override
{
std::string cmd = "";
char buf[1024] = {};
diff --git a/passes/cmds/logcmd.cc b/passes/cmds/logcmd.cc
index 522e1089d..12c43ecec 100644
--- a/passes/cmds/logcmd.cc
+++ b/passes/cmds/logcmd.cc
@@ -27,7 +27,7 @@ PRIVATE_NAMESPACE_BEGIN
struct LogPass : public Pass {
LogPass() : Pass("log", "print text and log files") { }
- void help() YS_OVERRIDE
+ void help() override
{
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
log("\n");
@@ -52,7 +52,7 @@ struct LogPass : public Pass {
log(" do not append a newline\n");
log("\n");
}
- void execute(std::vector<std::string> args, RTLIL::Design*) YS_OVERRIDE
+ void execute(std::vector<std::string> args, RTLIL::Design*) override
{
size_t argidx;
bool to_stdout = false;
diff --git a/passes/cmds/logger.cc b/passes/cmds/logger.cc
index 50b89d92f..6a9ed6036 100644
--- a/passes/cmds/logger.cc
+++ b/passes/cmds/logger.cc
@@ -25,7 +25,7 @@ PRIVATE_NAMESPACE_BEGIN
struct LoggerPass : public Pass {
LoggerPass() : Pass("logger", "set logger properties") { }
- void help() YS_OVERRIDE
+ void help() override
{
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
log("\n");
@@ -66,7 +66,7 @@ struct LoggerPass : public Pass {
log("\n");
}
- void execute(std::vector<std::string> args, RTLIL::Design * design) YS_OVERRIDE
+ void execute(std::vector<std::string> args, RTLIL::Design * design) override
{
size_t argidx;
for (argidx = 1; argidx < args.size(); argidx++)
@@ -159,39 +159,12 @@ struct LoggerPass : public Pass {
log_cmd_error("Expected error message occurrences must be 1 !\n");
log("Added regex '%s' for warnings to expected %s list.\n", pattern.c_str(), type.c_str());
try {
- if (type=="error") {
- auto it = log_expect_error.begin();
- auto ie = log_expect_error.end();
- for (; it != ie; it++)
- if (it->second.pattern == pattern) {
- it->second.expected_count = count;
- break;
- }
- if (it == ie)
- log_expect_error.emplace_back(YS_REGEX_COMPILE(pattern), LogExpectedItem(pattern, count));
- }
- else if (type=="warning") {
- auto it = log_expect_warning.begin();
- auto ie = log_expect_warning.end();
- for (; it != ie; it++)
- if (it->second.pattern == pattern) {
- it->second.expected_count = count;
- break;
- }
- if (it == ie)
- log_expect_warning.emplace_back(YS_REGEX_COMPILE(pattern), LogExpectedItem(pattern, count));
- }
- else if (type=="log") {
- auto it = log_expect_log.begin();
- auto ie = log_expect_log.end();
- for (; it != ie; it++)
- if (it->second.pattern == pattern) {
- it->second.expected_count = count;
- break;
- }
- if (it == ie)
- log_expect_log.emplace_back(YS_REGEX_COMPILE(pattern), LogExpectedItem(pattern, count));
- }
+ if (type == "error")
+ log_expect_error[pattern] = LogExpectedItem(YS_REGEX_COMPILE(pattern), count);
+ else if (type == "warning")
+ log_expect_warning[pattern] = LogExpectedItem(YS_REGEX_COMPILE(pattern), count);
+ else if (type == "log")
+ log_expect_log[pattern] = LogExpectedItem(YS_REGEX_COMPILE(pattern), count);
else log_abort();
}
catch (const YS_REGEX_NS::regex_error& e) {
diff --git a/passes/cmds/ltp.cc b/passes/cmds/ltp.cc
index 05701710b..39ec432c2 100644
--- a/passes/cmds/ltp.cc
+++ b/passes/cmds/ltp.cc
@@ -141,7 +141,7 @@ struct LtpWorker
struct LtpPass : public Pass {
LtpPass() : Pass("ltp", "print longest topological path") { }
- void help() YS_OVERRIDE
+ void help() override
{
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
log("\n");
@@ -154,7 +154,7 @@ struct LtpPass : public Pass {
log(" automatically exclude FF cell types\n");
log("\n");
}
- void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
+ void execute(std::vector<std::string> args, RTLIL::Design *design) override
{
bool noff = false;
diff --git a/passes/cmds/plugin.cc b/passes/cmds/plugin.cc
index 4c16b56c4..3ed19497d 100644
--- a/passes/cmds/plugin.cc
+++ b/passes/cmds/plugin.cc
@@ -99,7 +99,7 @@ void load_plugin(std::string, std::vector<std::string>)
struct PluginPass : public Pass {
PluginPass() : Pass("plugin", "load and list loaded plugins") { }
- void help() YS_OVERRIDE
+ void help() override
{
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
log("\n");
@@ -117,7 +117,7 @@ struct PluginPass : public Pass {
log(" List loaded plugins\n");
log("\n");
}
- void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
+ void execute(std::vector<std::string> args, RTLIL::Design *design) override
{
std::string plugin_filename;
std::vector<std::string> plugin_aliases;
diff --git a/passes/cmds/portlist.cc b/passes/cmds/portlist.cc
index 38c4a8597..97f4bfd99 100644
--- a/passes/cmds/portlist.cc
+++ b/passes/cmds/portlist.cc
@@ -25,7 +25,7 @@ PRIVATE_NAMESPACE_BEGIN
struct PortlistPass : public Pass {
PortlistPass() : Pass("portlist", "list (top-level) ports") { }
- void help() YS_OVERRIDE
+ void help() override
{
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
log("\n");
@@ -39,7 +39,7 @@ struct PortlistPass : public Pass {
log(" print verilog blackbox module definitions instead of port lists\n");
log("\n");
}
- void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
+ void execute(std::vector<std::string> args, RTLIL::Design *design) override
{
bool m_mode = false;
diff --git a/passes/cmds/printattrs.cc b/passes/cmds/printattrs.cc
new file mode 100644
index 000000000..7973ac262
--- /dev/null
+++ b/passes/cmds/printattrs.cc
@@ -0,0 +1,90 @@
+/*
+ * yosys -- Yosys Open SYnthesis Suite
+ *
+ * Copyright (C) 2020 Alberto Gonzalez <boqwxp@airmail.cc>
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ */
+
+#include "kernel/yosys.h"
+
+USING_YOSYS_NAMESPACE
+PRIVATE_NAMESPACE_BEGIN
+
+struct PrintAttrsPass : public Pass {
+ PrintAttrsPass() : Pass("printattrs", "print attributes of selected objects") { }
+ void help() override
+ {
+ // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
+ log("\n");
+ log(" printattrs [selection]\n");
+ log("\n");
+ log("Print all attributes of the selected objects.\n");
+ log("\n");
+ log("\n");
+ }
+
+ static std::string get_indent_str(const unsigned int indent) {
+ return stringf("%*s", indent, "");
+ }
+
+ static void log_const(const RTLIL::IdString &s, const RTLIL::Const &x, const unsigned int indent) {
+ if (x.flags == RTLIL::CONST_FLAG_STRING)
+ log("%s(* %s=\"%s\" *)\n", get_indent_str(indent).c_str(), log_id(s), x.decode_string().c_str());
+ else if (x.flags == RTLIL::CONST_FLAG_NONE)
+ log("%s(* %s=%s *)\n", get_indent_str(indent).c_str(), log_id(s), x.as_string().c_str());
+ else
+ log_assert(x.flags == RTLIL::CONST_FLAG_STRING || x.flags == RTLIL::CONST_FLAG_NONE); //intended to fail
+ }
+
+ void execute(std::vector<std::string> args, RTLIL::Design *design) override
+ {
+ size_t argidx = 1;
+ extra_args(args, argidx, design);
+
+ unsigned int indent = 0;
+ for (auto mod : design->selected_modules())
+ {
+ if (design->selected_whole_module(mod)) {
+ log("%s%s\n", get_indent_str(indent).c_str(), log_id(mod->name));
+ indent += 2;
+ for (auto &it : mod->attributes)
+ log_const(it.first, it.second, indent);
+ }
+
+ for (auto cell : mod->selected_cells()) {
+ log("%s%s\n", get_indent_str(indent).c_str(), log_id(cell->name));
+ indent += 2;
+ for (auto &it : cell->attributes)
+ log_const(it.first, it.second, indent);
+ indent -= 2;
+ }
+
+ for (auto wire : mod->selected_wires()) {
+ log("%s%s\n", get_indent_str(indent).c_str(), log_id(wire->name));
+ indent += 2;
+ for (auto &it : wire->attributes)
+ log_const(it.first, it.second, indent);
+ indent -= 2;
+ }
+
+ if (design->selected_whole_module(mod))
+ indent -= 2;
+ }
+
+ log("\n");
+ }
+} PrintAttrsPass;
+
+PRIVATE_NAMESPACE_END
diff --git a/passes/cmds/qwp.cc b/passes/cmds/qwp.cc
index b178ef951..cf0f6d0de 100644
--- a/passes/cmds/qwp.cc
+++ b/passes/cmds/qwp.cc
@@ -778,7 +778,7 @@ struct QwpWorker
struct QwpPass : public Pass {
QwpPass() : Pass("qwp", "quadratic wirelength placer") { }
- void help() YS_OVERRIDE
+ void help() override
{
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
log("\n");
@@ -808,7 +808,7 @@ struct QwpPass : public Pass {
log("dense matrix operations. It is only a toy-placer for small circuits.\n");
log("\n");
}
- void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
+ void execute(std::vector<std::string> args, RTLIL::Design *design) override
{
QwpConfig config;
xorshift32_state = 123456789;
diff --git a/passes/cmds/rename.cc b/passes/cmds/rename.cc
index 7d6d84d42..6326b4b15 100644
--- a/passes/cmds/rename.cc
+++ b/passes/cmds/rename.cc
@@ -104,7 +104,7 @@ static IdString derive_name_from_cell_output_wire(const RTLIL::Cell *cell)
struct RenamePass : public Pass {
RenamePass() : Pass("rename", "rename object in the design") { }
- void help() YS_OVERRIDE
+ void help() override
{
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
log("\n");
@@ -152,7 +152,7 @@ struct RenamePass : public Pass {
log("Rename top module.\n");
log("\n");
}
- void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
+ void execute(std::vector<std::string> args, RTLIL::Design *design) override
{
std::string pattern_prefix = "_", pattern_suffix = "_";
bool flag_src = false;
diff --git a/passes/cmds/scatter.cc b/passes/cmds/scatter.cc
index a5ef95f02..a70dd3086 100644
--- a/passes/cmds/scatter.cc
+++ b/passes/cmds/scatter.cc
@@ -27,7 +27,7 @@ PRIVATE_NAMESPACE_BEGIN
struct ScatterPass : public Pass {
ScatterPass() : Pass("scatter", "add additional intermediate nets") { }
- void help() YS_OVERRIDE
+ void help() override
{
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
log("\n");
@@ -41,7 +41,7 @@ struct ScatterPass : public Pass {
log("Use the opt_clean command to get rid of the additional nets.\n");
log("\n");
}
- void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
+ void execute(std::vector<std::string> args, RTLIL::Design *design) override
{
CellTypes ct(design);
extra_args(args, 1, design);
diff --git a/passes/cmds/scc.cc b/passes/cmds/scc.cc
index ad0554bae..8e7f3f990 100644
--- a/passes/cmds/scc.cc
+++ b/passes/cmds/scc.cc
@@ -218,7 +218,7 @@ struct SccWorker
struct SccPass : public Pass {
SccPass() : Pass("scc", "detect strongly connected components (logic loops)") { }
- void help() YS_OVERRIDE
+ void help() override
{
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
log("\n");
@@ -255,7 +255,7 @@ struct SccPass : public Pass {
log(" that are part of a found logic loop\n");
log("\n");
}
- void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
+ void execute(std::vector<std::string> args, RTLIL::Design *design) override
{
std::map<std::string, std::string> setAttr;
bool allCellTypes = false;
diff --git a/passes/cmds/scratchpad.cc b/passes/cmds/scratchpad.cc
index 34ec0863a..9369f5312 100644
--- a/passes/cmds/scratchpad.cc
+++ b/passes/cmds/scratchpad.cc
@@ -27,7 +27,7 @@ PRIVATE_NAMESPACE_BEGIN
struct ScratchpadPass : public Pass {
ScratchpadPass() : Pass("scratchpad", "get/set values in the scratchpad") { }
- void help() YS_OVERRIDE
+ void help() override
{
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
log("\n");
@@ -63,7 +63,7 @@ struct ScratchpadPass : public Pass {
log("\n");
}
- void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
+ void execute(std::vector<std::string> args, RTLIL::Design *design) override
{
size_t argidx;
for (argidx = 1; argidx < args.size(); argidx++)
diff --git a/passes/cmds/select.cc b/passes/cmds/select.cc
index 6e728c16f..b4f3994a2 100644
--- a/passes/cmds/select.cc
+++ b/passes/cmds/select.cc
@@ -30,26 +30,31 @@ using RTLIL::id2cstr;
static std::vector<RTLIL::Selection> work_stack;
-static bool match_ids(RTLIL::IdString id, std::string pattern)
+static bool match_ids(RTLIL::IdString id, const std::string &pattern)
{
if (id == pattern)
return true;
- if (id.size() > 0 && id[0] == '\\' && id.compare(1, std::string::npos, pattern.c_str()) == 0)
+
+ const char *id_c = id.c_str();
+ const char *pat_c = pattern.c_str();
+ size_t id_size = strlen(id_c);
+ size_t pat_size = pattern.size();
+
+ if (*id_c == '\\' && id_size == 1 + pat_size && memcmp(id_c + 1, pat_c, pat_size) == 0)
return true;
- if (patmatch(pattern.c_str(), id.c_str()))
+ if (patmatch(pat_c, id_c))
return true;
- if (id.size() > 0 && id[0] == '\\' && patmatch(pattern.c_str(), id.substr(1).c_str()))
+ if (*id_c == '\\' && patmatch(pat_c, id_c + 1))
return true;
- if (id.size() > 0 && id[0] == '$' && pattern.size() > 0 && pattern[0] == '$') {
- const char *p = id.c_str();
- const char *q = strrchr(p, '$');
+ if (*id_c == '$' && *pat_c == '$') {
+ const char *q = strrchr(id_c, '$');
if (pattern == q)
return true;
}
return false;
}
-static bool match_attr_val(const RTLIL::Const &value, std::string pattern, char match_op)
+static bool match_attr_val(const RTLIL::Const &value, const std::string &pattern, char match_op)
{
if (match_op == 0)
return true;
@@ -101,7 +106,7 @@ static bool match_attr_val(const RTLIL::Const &value, std::string pattern, char
log_abort();
}
-static bool match_attr(const dict<RTLIL::IdString, RTLIL::Const> &attributes, std::string name_pat, std::string value_pat, char match_op)
+static bool match_attr(const dict<RTLIL::IdString, RTLIL::Const> &attributes, const std::string &name_pat, const std::string &value_pat, char match_op)
{
if (name_pat.find('*') != std::string::npos || name_pat.find('?') != std::string::npos || name_pat.find('[') != std::string::npos) {
for (auto &it : attributes) {
@@ -119,7 +124,7 @@ static bool match_attr(const dict<RTLIL::IdString, RTLIL::Const> &attributes, st
return false;
}
-static bool match_attr(const dict<RTLIL::IdString, RTLIL::Const> &attributes, std::string match_expr)
+static bool match_attr(const dict<RTLIL::IdString, RTLIL::Const> &attributes, const std::string &match_expr)
{
size_t pos = match_expr.find_first_of("<!=>");
@@ -410,7 +415,7 @@ namespace {
};
}
-static int parse_comma_list(std::set<RTLIL::IdString> &tokens, std::string str, size_t pos, std::string stopchar)
+static int parse_comma_list(std::set<RTLIL::IdString> &tokens, const std::string &str, size_t pos, std::string stopchar)
{
stopchar += ',';
while (1) {
@@ -495,7 +500,7 @@ static int select_op_expand(RTLIL::Design *design, RTLIL::Selection &lhs, std::v
return sel_objects;
}
-static void select_op_expand(RTLIL::Design *design, std::string arg, char mode, bool eval_only)
+static void select_op_expand(RTLIL::Design *design, const std::string &arg, char mode, bool eval_only)
{
int pos = (mode == 'x' ? 2 : 3) + (eval_only ? 1 : 0);
int levels = 1, rem_objects = -1;
@@ -966,7 +971,7 @@ PRIVATE_NAMESPACE_END
YOSYS_NAMESPACE_BEGIN
// used in kernel/register.cc and maybe other locations, extern decl. in register.h
-void handle_extra_select_args(Pass *pass, vector<string> args, size_t argidx, size_t args_size, RTLIL::Design *design)
+void handle_extra_select_args(Pass *pass, const vector<string> &args, size_t argidx, size_t args_size, RTLIL::Design *design)
{
work_stack.clear();
for (; argidx < args_size; argidx++) {
@@ -1016,7 +1021,7 @@ PRIVATE_NAMESPACE_BEGIN
struct SelectPass : public Pass {
SelectPass() : Pass("select", "modify and view the list of selected objects") { }
- void help() YS_OVERRIDE
+ void help() override
{
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
log("\n");
@@ -1245,7 +1250,7 @@ struct SelectPass : public Pass {
log(" select */t:SWITCH %%x:+[GATE] */t:SWITCH %%d\n");
log("\n");
}
- void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
+ void execute(std::vector<std::string> args, RTLIL::Design *design) override
{
bool add_mode = false;
bool del_mode = false;
@@ -1582,7 +1587,7 @@ struct SelectPass : public Pass {
struct CdPass : public Pass {
CdPass() : Pass("cd", "a shortcut for 'select -module <name>'") { }
- void help() YS_OVERRIDE
+ void help() override
{
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
log("\n");
@@ -1608,7 +1613,7 @@ struct CdPass : public Pass {
log("This is just a shortcut for 'select -clear'.\n");
log("\n");
}
- void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
+ void execute(std::vector<std::string> args, RTLIL::Design *design) override
{
if (args.size() != 1 && args.size() != 2)
log_cmd_error("Invalid number of arguments.\n");
@@ -1670,7 +1675,7 @@ struct CdPass : public Pass {
} CdPass;
template<typename T>
-static void log_matches(const char *title, Module *module, T list)
+static void log_matches(const char *title, Module *module, const T &list)
{
std::vector<IdString> matches;
@@ -1688,7 +1693,7 @@ static void log_matches(const char *title, Module *module, T list)
struct LsPass : public Pass {
LsPass() : Pass("ls", "list modules or objects in modules") { }
- void help() YS_OVERRIDE
+ void help() override
{
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
log("\n");
@@ -1699,7 +1704,7 @@ struct LsPass : public Pass {
log("When an active module is selected, this prints a list of objects in the module.\n");
log("\n");
}
- void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
+ void execute(std::vector<std::string> args, RTLIL::Design *design) override
{
size_t argidx = 1;
extra_args(args, argidx, design);
diff --git a/passes/cmds/setattr.cc b/passes/cmds/setattr.cc
index 515f5a4ef..3a94209d4 100644
--- a/passes/cmds/setattr.cc
+++ b/passes/cmds/setattr.cc
@@ -56,7 +56,7 @@ static void do_setunset(dict<RTLIL::IdString, RTLIL::Const> &attrs, const std::v
struct SetattrPass : public Pass {
SetattrPass() : Pass("setattr", "set/unset attributes on objects") { }
- void help() YS_OVERRIDE
+ void help() override
{
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
log("\n");
@@ -69,7 +69,7 @@ struct SetattrPass : public Pass {
log("instead of objects within modules.\n");
log("\n");
}
- void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
+ void execute(std::vector<std::string> args, RTLIL::Design *design) override
{
std::vector<setunset_t> setunset_list;
bool flag_mod = false;
@@ -128,7 +128,7 @@ struct SetattrPass : public Pass {
struct WbflipPass : public Pass {
WbflipPass() : Pass("wbflip", "flip the whitebox attribute") { }
- void help() YS_OVERRIDE
+ void help() override
{
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
log("\n");
@@ -138,7 +138,7 @@ struct WbflipPass : public Pass {
log("vice-versa. Blackbox cells are not effected by this command.\n");
log("\n");
}
- void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
+ void execute(std::vector<std::string> args, RTLIL::Design *design) override
{
size_t argidx;
for (argidx = 1; argidx < args.size(); argidx++)
@@ -167,7 +167,7 @@ struct WbflipPass : public Pass {
struct SetparamPass : public Pass {
SetparamPass() : Pass("setparam", "set/unset parameters on objects") { }
- void help() YS_OVERRIDE
+ void help() override
{
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
log("\n");
@@ -179,7 +179,7 @@ struct SetparamPass : public Pass {
log("The -type option can be used to change the cell type of the selected cells.\n");
log("\n");
}
- void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
+ void execute(std::vector<std::string> args, RTLIL::Design *design) override
{
vector<setunset_t> setunset_list;
string new_cell_type;
@@ -219,7 +219,7 @@ struct SetparamPass : public Pass {
struct ChparamPass : public Pass {
ChparamPass() : Pass("chparam", "re-evaluate modules with new parameters") { }
- void help() YS_OVERRIDE
+ void help() override
{
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
log("\n");
@@ -234,7 +234,7 @@ struct ChparamPass : public Pass {
log("List the available parameters of the selected modules.\n");
log("\n");
}
- void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
+ void execute(std::vector<std::string> args, RTLIL::Design *design) override
{
std::vector<setunset_t> setunset_list;
dict<RTLIL::IdString, RTLIL::Const> new_parameters;
diff --git a/passes/cmds/setundef.cc b/passes/cmds/setundef.cc
index 8d973869e..cf8d76619 100644
--- a/passes/cmds/setundef.cc
+++ b/passes/cmds/setundef.cc
@@ -107,7 +107,7 @@ struct SetundefWorker
struct SetundefPass : public Pass {
SetundefPass() : Pass("setundef", "replace undef values with defined constants") { }
- void help() YS_OVERRIDE
+ void help() override
{
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
log("\n");
@@ -147,7 +147,7 @@ struct SetundefPass : public Pass {
log(" replace undef in cell parameters\n");
log("\n");
}
- void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
+ void execute(std::vector<std::string> args, RTLIL::Design *design) override
{
int got_value = 0;
bool undriven_mode = false;
diff --git a/passes/cmds/show.cc b/passes/cmds/show.cc
index fa922454a..cbed08a3f 100644
--- a/passes/cmds/show.cc
+++ b/passes/cmds/show.cc
@@ -587,7 +587,7 @@ struct ShowWorker
struct ShowPass : public Pass {
ShowPass() : Pass("show", "generate schematics using graphviz") { }
- void help() YS_OVERRIDE
+ void help() override
{
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
log("\n");
@@ -674,7 +674,7 @@ struct ShowPass : public Pass {
log("the 'show' command is executed.\n");
log("\n");
}
- void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
+ void execute(std::vector<std::string> args, RTLIL::Design *design) override
{
log_header(design, "Generating Graphviz representation of design.\n");
log_push();
diff --git a/passes/cmds/splice.cc b/passes/cmds/splice.cc
index ea9e06979..20627d601 100644
--- a/passes/cmds/splice.cc
+++ b/passes/cmds/splice.cc
@@ -246,7 +246,7 @@ struct SpliceWorker
struct SplicePass : public Pass {
SplicePass() : Pass("splice", "create explicit splicing cells") { }
- void help() YS_OVERRIDE
+ void help() override
{
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
log("\n");
@@ -287,7 +287,7 @@ struct SplicePass : public Pass {
log("by selected wires are rewired.\n");
log("\n");
}
- void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
+ void execute(std::vector<std::string> args, RTLIL::Design *design) override
{
bool sel_by_cell = false;
bool sel_by_wire = false;
diff --git a/passes/cmds/splitnets.cc b/passes/cmds/splitnets.cc
index 1e7dedd70..fff8a0d3e 100644
--- a/passes/cmds/splitnets.cc
+++ b/passes/cmds/splitnets.cc
@@ -59,18 +59,26 @@ struct SplitnetsWorker
new_wire->port_id = wire->port_id ? wire->port_id + offset : 0;
new_wire->port_input = wire->port_input;
new_wire->port_output = wire->port_output;
+ new_wire->start_offset = wire->start_offset + offset;
- if (wire->attributes.count(ID::src))
- new_wire->attributes[ID::src] = wire->attributes.at(ID::src);
+ auto it = wire->attributes.find(ID::src);
+ if (it != wire->attributes.end())
+ new_wire->attributes.emplace(ID::src, it->second);
- if (wire->attributes.count(ID::keep))
- new_wire->attributes[ID::keep] = wire->attributes.at(ID::keep);
+ it = wire->attributes.find(ID::hdlname);
+ if (it != wire->attributes.end())
+ new_wire->attributes.emplace(ID::hdlname, it->second);
- if (wire->attributes.count(ID::init)) {
- Const old_init = wire->attributes.at(ID::init), new_init;
+ it = wire->attributes.find(ID::keep);
+ if (it != wire->attributes.end())
+ new_wire->attributes.emplace(ID::keep, it->second);
+
+ it = wire->attributes.find(ID::init);
+ if (it != wire->attributes.end()) {
+ Const old_init = it->second, new_init;
for (int i = offset; i < offset+width; i++)
new_init.bits.push_back(i < GetSize(old_init) ? old_init.bits.at(i) : State::Sx);
- new_wire->attributes[ID::init] = new_init;
+ new_wire->attributes.emplace(ID::init, new_init);
}
std::vector<RTLIL::SigBit> sigvec = RTLIL::SigSpec(new_wire).to_sigbit_vector();
@@ -87,7 +95,7 @@ struct SplitnetsWorker
struct SplitnetsPass : public Pass {
SplitnetsPass() : Pass("splitnets", "split up multi-bit nets") { }
- void help() YS_OVERRIDE
+ void help() override
{
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
log("\n");
@@ -109,7 +117,7 @@ struct SplitnetsPass : public Pass {
log(" and split nets so that no driver drives only part of a net.\n");
log("\n");
}
- void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
+ void execute(std::vector<std::string> args, RTLIL::Design *design) override
{
bool flag_ports = false;
bool flag_driver = false;
@@ -166,12 +174,12 @@ struct SplitnetsPass : public Pass {
std::map<RTLIL::Wire*, std::set<int>> split_wires_at;
- for (auto &c : module->cells_)
- for (auto &p : c.second->connections())
+ for (auto c : module->cells())
+ for (auto &p : c->connections())
{
- if (!ct.cell_known(c.second->type))
+ if (!ct.cell_known(c->type))
continue;
- if (!ct.cell_output(c.second->type, p.first))
+ if (!ct.cell_output(c->type, p.first))
continue;
RTLIL::SigSpec sig = p.second;
@@ -198,9 +206,8 @@ struct SplitnetsPass : public Pass {
}
else
{
- for (auto &w : module->wires_) {
- RTLIL::Wire *wire = w.second;
- if (wire->width > 1 && (wire->port_id == 0 || flag_ports) && design->selected(module, w.second))
+ for (auto wire : module->wires()) {
+ if (wire->width > 1 && (wire->port_id == 0 || flag_ports) && design->selected(module, wire))
worker.splitmap[wire] = std::vector<RTLIL::SigBit>();
}
diff --git a/passes/cmds/stat.cc b/passes/cmds/stat.cc
index 6c4bc0e5b..ed51fdc24 100644
--- a/passes/cmds/stat.cc
+++ b/passes/cmds/stat.cc
@@ -109,7 +109,7 @@ struct statdata_t
ID($lut), ID($and), ID($or), ID($xor), ID($xnor),
ID($shl), ID($shr), ID($sshl), ID($sshr), ID($shift), ID($shiftx),
ID($lt), ID($le), ID($eq), ID($ne), ID($eqx), ID($nex), ID($ge), ID($gt),
- ID($add), ID($sub), ID($mul), ID($div), ID($mod), ID($pow), ID($alu))) {
+ ID($add), ID($sub), ID($mul), ID($div), ID($mod), ID($divfloor), ID($modfloor), ID($pow), ID($alu))) {
int width_a = cell->hasPort(ID::A) ? GetSize(cell->getPort(ID::A)) : 0;
int width_b = cell->hasPort(ID::B) ? GetSize(cell->getPort(ID::B)) : 0;
int width_y = cell->hasPort(ID::Y) ? GetSize(cell->getPort(ID::Y)) : 0;
@@ -117,7 +117,10 @@ struct statdata_t
}
else if (cell_type.in(ID($mux), ID($pmux)))
cell_type = stringf("%s_%d", cell_type.c_str(), GetSize(cell->getPort(ID::Y)));
- else if (cell_type.in(ID($sr), ID($dff), ID($dffsr), ID($adff), ID($dlatch), ID($dlatchsr)))
+ else if (cell_type.in(
+ ID($sr), ID($ff), ID($dff), ID($dffe), ID($dffsr), ID($dffsre),
+ ID($adff), ID($adffe), ID($sdff), ID($sdffe), ID($sdffce),
+ ID($dlatch), ID($adlatch), ID($dlatchsr)))
cell_type = stringf("%s_%d", cell_type.c_str(), GetSize(cell->getPort(ID::Q)));
}
@@ -282,7 +285,7 @@ void read_liberty_cellarea(dict<IdString, double> &cell_area, string liberty_fil
struct StatPass : public Pass {
StatPass() : Pass("stat", "print some statistics") { }
- void help() YS_OVERRIDE
+ void help() override
{
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
log("\n");
@@ -308,7 +311,7 @@ struct StatPass : public Pass {
log(" e.g. $add_8 for an 8 bit wide $add cell.\n");
log("\n");
}
- void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
+ void execute(std::vector<std::string> args, RTLIL::Design *design) override
{
log_header(design, "Printing statistics.\n");
diff --git a/passes/cmds/tee.cc b/passes/cmds/tee.cc
index 1a44bdaec..60689fc82 100644
--- a/passes/cmds/tee.cc
+++ b/passes/cmds/tee.cc
@@ -27,7 +27,7 @@ PRIVATE_NAMESPACE_BEGIN
struct TeePass : public Pass {
TeePass() : Pass("tee", "redirect command output to file") { }
- void help() YS_OVERRIDE
+ void help() override
{
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
log("\n");
@@ -49,7 +49,7 @@ struct TeePass : public Pass {
log(" Add/subtract INT from the -v setting for this command.\n");
log("\n");
}
- void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
+ void execute(std::vector<std::string> args, RTLIL::Design *design) override
{
std::vector<FILE*> backup_log_files, files_to_close;
std::vector<std::ostream*> backup_log_streams;
diff --git a/passes/cmds/torder.cc b/passes/cmds/torder.cc
index 5748ff7f0..30e76081e 100644
--- a/passes/cmds/torder.cc
+++ b/passes/cmds/torder.cc
@@ -27,7 +27,7 @@ PRIVATE_NAMESPACE_BEGIN
struct TorderPass : public Pass {
TorderPass() : Pass("torder", "print cells in topological order") { }
- void help() YS_OVERRIDE
+ void help() override
{
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
log("\n");
@@ -43,7 +43,7 @@ struct TorderPass : public Pass {
log(" are not used in topological sorting. this option deactivates that.\n");
log("\n");
}
- void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
+ void execute(std::vector<std::string> args, RTLIL::Design *design) override
{
bool noautostop = false;
dict<IdString, pool<IdString>> stop_db;
diff --git a/passes/cmds/trace.cc b/passes/cmds/trace.cc
index 8446e27b3..10742c370 100644
--- a/passes/cmds/trace.cc
+++ b/passes/cmds/trace.cc
@@ -25,34 +25,34 @@ PRIVATE_NAMESPACE_BEGIN
struct TraceMonitor : public RTLIL::Monitor
{
- void notify_module_add(RTLIL::Module *module) YS_OVERRIDE
+ void notify_module_add(RTLIL::Module *module) override
{
log("#TRACE# Module add: %s\n", log_id(module));
}
- void notify_module_del(RTLIL::Module *module) YS_OVERRIDE
+ void notify_module_del(RTLIL::Module *module) override
{
log("#TRACE# Module delete: %s\n", log_id(module));
}
- void notify_connect(RTLIL::Cell *cell, const RTLIL::IdString &port, const RTLIL::SigSpec &old_sig, const RTLIL::SigSpec &sig) YS_OVERRIDE
+ void notify_connect(RTLIL::Cell *cell, const RTLIL::IdString &port, const RTLIL::SigSpec &old_sig, const RTLIL::SigSpec &sig) override
{
log("#TRACE# Cell connect: %s.%s.%s = %s (was: %s)\n", log_id(cell->module), log_id(cell), log_id(port), log_signal(sig), log_signal(old_sig));
}
- void notify_connect(RTLIL::Module *module, const RTLIL::SigSig &sigsig) YS_OVERRIDE
+ void notify_connect(RTLIL::Module *module, const RTLIL::SigSig &sigsig) override
{
log("#TRACE# Connection in module %s: %s = %s\n", log_id(module), log_signal(sigsig.first), log_signal(sigsig.second));
}
- void notify_connect(RTLIL::Module *module, const std::vector<RTLIL::SigSig> &sigsig_vec) YS_OVERRIDE
+ void notify_connect(RTLIL::Module *module, const std::vector<RTLIL::SigSig> &sigsig_vec) override
{
log("#TRACE# New connections in module %s:\n", log_id(module));
for (auto &sigsig : sigsig_vec)
log("## %s = %s\n", log_signal(sigsig.first), log_signal(sigsig.second));
}
- void notify_blackout(RTLIL::Module *module) YS_OVERRIDE
+ void notify_blackout(RTLIL::Module *module) override
{
log("#TRACE# Blackout in module %s:\n", log_id(module));
}
@@ -60,7 +60,7 @@ struct TraceMonitor : public RTLIL::Monitor
struct TracePass : public Pass {
TracePass() : Pass("trace", "redirect command output to file") { }
- void help() YS_OVERRIDE
+ void help() override
{
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
log("\n");
@@ -70,7 +70,7 @@ struct TracePass : public Pass {
log("the design in real time.\n");
log("\n");
}
- void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
+ void execute(std::vector<std::string> args, RTLIL::Design *design) override
{
size_t argidx;
for (argidx = 1; argidx < args.size(); argidx++)
@@ -96,7 +96,7 @@ struct TracePass : public Pass {
struct DebugPass : public Pass {
DebugPass() : Pass("debug", "run command with debug log messages enabled") { }
- void help() YS_OVERRIDE
+ void help() override
{
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
log("\n");
@@ -105,7 +105,7 @@ struct DebugPass : public Pass {
log("Execute the specified command with debug log messages enabled\n");
log("\n");
}
- void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
+ void execute(std::vector<std::string> args, RTLIL::Design *design) override
{
size_t argidx;
for (argidx = 1; argidx < args.size(); argidx++)
diff --git a/passes/cmds/write_file.cc b/passes/cmds/write_file.cc
index 64a762d7c..3d898a5ef 100644
--- a/passes/cmds/write_file.cc
+++ b/passes/cmds/write_file.cc
@@ -25,7 +25,7 @@ PRIVATE_NAMESPACE_BEGIN
struct WriteFileFrontend : public Frontend {
WriteFileFrontend() : Frontend("=write_file", "write a text to a file") { }
- void help() YS_OVERRIDE
+ void help() override
{
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
log("\n");
@@ -44,7 +44,7 @@ struct WriteFileFrontend : public Frontend {
log(" EOT\n");
log("\n");
}
- void execute(std::istream *&f, std::string filename, std::vector<std::string> args, RTLIL::Design*) YS_OVERRIDE
+ void execute(std::istream *&f, std::string filename, std::vector<std::string> args, RTLIL::Design*) override
{
bool append_mode = false;
std::string output_filename;
diff --git a/passes/equiv/equiv_add.cc b/passes/equiv/equiv_add.cc
index cdc74b0b2..2abbb59bb 100644
--- a/passes/equiv/equiv_add.cc
+++ b/passes/equiv/equiv_add.cc
@@ -25,7 +25,7 @@ PRIVATE_NAMESPACE_BEGIN
struct EquivAddPass : public Pass {
EquivAddPass() : Pass("equiv_add", "add a $equiv cell") { }
- void help() YS_OVERRIDE
+ void help() override
{
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
log("\n");
@@ -39,7 +39,7 @@ struct EquivAddPass : public Pass {
log("This command adds $equiv cells for the ports of the specified cells.\n");
log("\n");
}
- void execute(std::vector<std::string> args, Design *design) YS_OVERRIDE
+ void execute(std::vector<std::string> args, Design *design) override
{
bool try_mode = false;
diff --git a/passes/equiv/equiv_induct.cc b/passes/equiv/equiv_induct.cc
index ec651193e..596c938fc 100644
--- a/passes/equiv/equiv_induct.cc
+++ b/passes/equiv/equiv_induct.cc
@@ -162,7 +162,7 @@ struct EquivInductWorker
struct EquivInductPass : public Pass {
EquivInductPass() : Pass("equiv_induct", "proving $equiv cells using temporal induction") { }
- void help() YS_OVERRIDE
+ void help() override
{
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
log("\n");
@@ -192,7 +192,7 @@ struct EquivInductPass : public Pass {
log("after reset.\n");
log("\n");
}
- void execute(std::vector<std::string> args, Design *design) YS_OVERRIDE
+ void execute(std::vector<std::string> args, Design *design) override
{
int success_counter = 0;
bool model_undef = false;
diff --git a/passes/equiv/equiv_make.cc b/passes/equiv/equiv_make.cc
index 50572ae5c..51b4ad0f1 100644
--- a/passes/equiv/equiv_make.cc
+++ b/passes/equiv/equiv_make.cc
@@ -466,7 +466,7 @@ struct EquivMakeWorker
struct EquivMakePass : public Pass {
EquivMakePass() : Pass("equiv_make", "prepare a circuit for equivalence checking") { }
- void help() YS_OVERRIDE
+ void help() override
{
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
log("\n");
@@ -491,7 +491,7 @@ struct EquivMakePass : public Pass {
log("checking problem. Use 'miter -equiv' if you want to create a miter circuit.\n");
log("\n");
}
- void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
+ void execute(std::vector<std::string> args, RTLIL::Design *design) override
{
EquivMakeWorker worker;
worker.ct.setup(design);
diff --git a/passes/equiv/equiv_mark.cc b/passes/equiv/equiv_mark.cc
index 737de25d9..a722b5ed6 100644
--- a/passes/equiv/equiv_mark.cc
+++ b/passes/equiv/equiv_mark.cc
@@ -204,7 +204,7 @@ struct EquivMarkWorker
struct EquivMarkPass : public Pass {
EquivMarkPass() : Pass("equiv_mark", "mark equivalence checking regions") { }
- void help() YS_OVERRIDE
+ void help() override
{
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
log("\n");
@@ -216,7 +216,7 @@ struct EquivMarkPass : public Pass {
log("wires and cells.\n");
log("\n");
}
- void execute(std::vector<std::string> args, Design *design) YS_OVERRIDE
+ void execute(std::vector<std::string> args, Design *design) override
{
log_header(design, "Executing EQUIV_MARK pass.\n");
diff --git a/passes/equiv/equiv_miter.cc b/passes/equiv/equiv_miter.cc
index 085970189..e028f806a 100644
--- a/passes/equiv/equiv_miter.cc
+++ b/passes/equiv/equiv_miter.cc
@@ -261,7 +261,7 @@ struct EquivMiterWorker
struct EquivMiterPass : public Pass {
EquivMiterPass() : Pass("equiv_miter", "extract miter from equiv circuit") { }
- void help() YS_OVERRIDE
+ void help() override
{
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
log("\n");
@@ -282,7 +282,7 @@ struct EquivMiterPass : public Pass {
log(" Create compare logic that handles undefs correctly\n");
log("\n");
}
- void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
+ void execute(std::vector<std::string> args, RTLIL::Design *design) override
{
EquivMiterWorker worker;
worker.ct.setup(design);
diff --git a/passes/equiv/equiv_opt.cc b/passes/equiv/equiv_opt.cc
index 7c6c2e685..4d0400448 100644
--- a/passes/equiv/equiv_opt.cc
+++ b/passes/equiv/equiv_opt.cc
@@ -26,7 +26,7 @@ struct EquivOptPass:public ScriptPass
{
EquivOptPass() : ScriptPass("equiv_opt", "prove equivalence for optimized circuit") { }
- void help() YS_OVERRIDE
+ void help() override
{
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
log("\n");
@@ -68,7 +68,7 @@ struct EquivOptPass:public ScriptPass
std::string command, techmap_opts, make_opts;
bool assert, undef, multiclock, async2sync;
- void clear_flags() YS_OVERRIDE
+ void clear_flags() override
{
command = "";
techmap_opts = "";
@@ -79,7 +79,7 @@ struct EquivOptPass:public ScriptPass
async2sync = false;
}
- void execute(std::vector < std::string > args, RTLIL::Design * design) YS_OVERRIDE
+ void execute(std::vector < std::string > args, RTLIL::Design * design) override
{
string run_from, run_to;
clear_flags();
@@ -148,7 +148,7 @@ struct EquivOptPass:public ScriptPass
log_pop();
}
- void script() YS_OVERRIDE
+ void script() override
{
if (check_label("run_pass")) {
run("hierarchy -auto-top");
diff --git a/passes/equiv/equiv_purge.cc b/passes/equiv/equiv_purge.cc
index 688c20f43..d15c8d183 100644
--- a/passes/equiv/equiv_purge.cc
+++ b/passes/equiv/equiv_purge.cc
@@ -176,7 +176,7 @@ struct EquivPurgeWorker
struct EquivPurgePass : public Pass {
EquivPurgePass() : Pass("equiv_purge", "purge equivalence checking module") { }
- void help() YS_OVERRIDE
+ void help() override
{
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
log("\n");
@@ -187,7 +187,7 @@ struct EquivPurgePass : public Pass {
log("ports as needed.\n");
log("\n");
}
- void execute(std::vector<std::string> args, Design *design) YS_OVERRIDE
+ void execute(std::vector<std::string> args, Design *design) override
{
log_header(design, "Executing EQUIV_PURGE pass.\n");
diff --git a/passes/equiv/equiv_remove.cc b/passes/equiv/equiv_remove.cc
index 6daa112b5..89442308b 100644
--- a/passes/equiv/equiv_remove.cc
+++ b/passes/equiv/equiv_remove.cc
@@ -24,7 +24,7 @@ PRIVATE_NAMESPACE_BEGIN
struct EquivRemovePass : public Pass {
EquivRemovePass() : Pass("equiv_remove", "remove $equiv cells") { }
- void help() YS_OVERRIDE
+ void help() override
{
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
log("\n");
@@ -40,7 +40,7 @@ struct EquivRemovePass : public Pass {
log(" keep gate circuit\n");
log("\n");
}
- void execute(std::vector<std::string> args, Design *design) YS_OVERRIDE
+ void execute(std::vector<std::string> args, Design *design) override
{
bool mode_gold = false;
bool mode_gate = false;
diff --git a/passes/equiv/equiv_simple.cc b/passes/equiv/equiv_simple.cc
index 4d2839f4d..408c5a793 100644
--- a/passes/equiv/equiv_simple.cc
+++ b/passes/equiv/equiv_simple.cc
@@ -273,7 +273,7 @@ struct EquivSimpleWorker
struct EquivSimplePass : public Pass {
EquivSimplePass() : Pass("equiv_simple", "try proving simple $equiv instances") { }
- void help() YS_OVERRIDE
+ void help() override
{
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
log("\n");
@@ -298,7 +298,7 @@ struct EquivSimplePass : public Pass {
log(" the max. number of time steps to be considered (default = 1)\n");
log("\n");
}
- void execute(std::vector<std::string> args, Design *design) YS_OVERRIDE
+ void execute(std::vector<std::string> args, Design *design) override
{
bool verbose = false, short_cones = false, model_undef = false, nogroup = false;
int success_counter = 0;
diff --git a/passes/equiv/equiv_status.cc b/passes/equiv/equiv_status.cc
index 258e2e45b..2db44ea90 100644
--- a/passes/equiv/equiv_status.cc
+++ b/passes/equiv/equiv_status.cc
@@ -24,7 +24,7 @@ PRIVATE_NAMESPACE_BEGIN
struct EquivStatusPass : public Pass {
EquivStatusPass() : Pass("equiv_status", "print status of equivalent checking module") { }
- void help() YS_OVERRIDE
+ void help() override
{
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
log("\n");
@@ -36,7 +36,7 @@ struct EquivStatusPass : public Pass {
log(" produce an error if any unproven $equiv cell is found\n");
log("\n");
}
- void execute(std::vector<std::string> args, Design *design) YS_OVERRIDE
+ void execute(std::vector<std::string> args, Design *design) override
{
bool assert_mode = false;
int unproven_count = 0;
diff --git a/passes/equiv/equiv_struct.cc b/passes/equiv/equiv_struct.cc
index 1b7bf96a8..9784225db 100644
--- a/passes/equiv/equiv_struct.cc
+++ b/passes/equiv/equiv_struct.cc
@@ -283,7 +283,7 @@ struct EquivStructWorker
struct EquivStructPass : public Pass {
EquivStructPass() : Pass("equiv_struct", "structural equivalence checking") { }
- void help() YS_OVERRIDE
+ void help() override
{
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
log("\n");
@@ -314,7 +314,7 @@ struct EquivStructPass : public Pass {
log(" maximum number of iterations to run before aborting\n");
log("\n");
}
- void execute(std::vector<std::string> args, Design *design) YS_OVERRIDE
+ void execute(std::vector<std::string> args, Design *design) override
{
pool<IdString> fwonly_cells({ ID($equiv) });
bool mode_icells = false;
diff --git a/passes/fsm/fsm.cc b/passes/fsm/fsm.cc
index c5cb338ab..21d352407 100644
--- a/passes/fsm/fsm.cc
+++ b/passes/fsm/fsm.cc
@@ -27,7 +27,7 @@ PRIVATE_NAMESPACE_BEGIN
struct FsmPass : public Pass {
FsmPass() : Pass("fsm", "extract and optimize finite state machines") { }
- void help() YS_OVERRIDE
+ void help() override
{
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
log("\n");
@@ -68,7 +68,7 @@ struct FsmPass : public Pass {
log(" passed through to fsm_recode pass\n");
log("\n");
}
- void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
+ void execute(std::vector<std::string> args, RTLIL::Design *design) override
{
bool flag_nomap = false;
bool flag_norecode = false;
diff --git a/passes/fsm/fsm_detect.cc b/passes/fsm/fsm_detect.cc
index 30e9e4dad..97c575ba7 100644
--- a/passes/fsm/fsm_detect.cc
+++ b/passes/fsm/fsm_detect.cc
@@ -257,7 +257,7 @@ static void detect_fsm(RTLIL::Wire *wire)
struct FsmDetectPass : public Pass {
FsmDetectPass() : Pass("fsm_detect", "finding FSMs in design") { }
- void help() YS_OVERRIDE
+ void help() override
{
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
log("\n");
@@ -273,7 +273,7 @@ struct FsmDetectPass : public Pass {
log("'fsm_encoding' attribute to \"none\".\n");
log("\n");
}
- void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
+ void execute(std::vector<std::string> args, RTLIL::Design *design) override
{
log_header(design, "Executing FSM_DETECT pass (finding FSMs in design).\n");
extra_args(args, 1, design);
diff --git a/passes/fsm/fsm_expand.cc b/passes/fsm/fsm_expand.cc
index ade6c17f5..d6b492af5 100644
--- a/passes/fsm/fsm_expand.cc
+++ b/passes/fsm/fsm_expand.cc
@@ -265,7 +265,7 @@ struct FsmExpand
struct FsmExpandPass : public Pass {
FsmExpandPass() : Pass("fsm_expand", "expand FSM cells by merging logic into it") { }
- void help() YS_OVERRIDE
+ void help() override
{
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
log("\n");
@@ -279,7 +279,7 @@ struct FsmExpandPass : public Pass {
log("word-wide cells. Call with -full to consider all cells for merging.\n");
log("\n");
}
- void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
+ void execute(std::vector<std::string> args, RTLIL::Design *design) override
{
bool full_mode = false;
diff --git a/passes/fsm/fsm_export.cc b/passes/fsm/fsm_export.cc
index c02a54ea2..be6702d7e 100644
--- a/passes/fsm/fsm_export.cc
+++ b/passes/fsm/fsm_export.cc
@@ -120,7 +120,7 @@ void write_kiss2(struct RTLIL::Module *module, struct RTLIL::Cell *cell, std::st
*/
struct FsmExportPass : public Pass {
FsmExportPass() : Pass("fsm_export", "exporting FSMs to KISS2 files") { }
- void help() YS_OVERRIDE
+ void help() override
{
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
log("\n");
@@ -143,7 +143,7 @@ struct FsmExportPass : public Pass {
log(" use binary state encoding as state names instead of s0, s1, ...\n");
log("\n");
}
- void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
+ void execute(std::vector<std::string> args, RTLIL::Design *design) override
{
dict<RTLIL::IdString, RTLIL::Const>::iterator attr_it;
std::string arg;
diff --git a/passes/fsm/fsm_extract.cc b/passes/fsm/fsm_extract.cc
index 3840aabc8..082973153 100644
--- a/passes/fsm/fsm_extract.cc
+++ b/passes/fsm/fsm_extract.cc
@@ -394,14 +394,14 @@ static void extract_fsm(RTLIL::Wire *wire)
RTLIL::Cell *cell = module->cells_.at(cellport.first);
RTLIL::SigSpec port_sig = assign_map(cell->getPort(cellport.second));
RTLIL::SigSpec unconn_sig = port_sig.extract(ctrl_out);
- RTLIL::Wire *unconn_wire = module->addWire(stringf("$fsm_unconnect$%s$%d", log_signal(unconn_sig), autoidx++), unconn_sig.size());
+ RTLIL::Wire *unconn_wire = module->addWire(stringf("$fsm_unconnect$%d", autoidx++), unconn_sig.size());
port_sig.replace(unconn_sig, RTLIL::SigSpec(unconn_wire), &cell->connections_[cellport.second]);
}
}
struct FsmExtractPass : public Pass {
FsmExtractPass() : Pass("fsm_extract", "extracting FSMs in design") { }
- void help() YS_OVERRIDE
+ void help() override
{
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
log("\n");
@@ -417,7 +417,7 @@ struct FsmExtractPass : public Pass {
log("'opt_clean' pass to eliminate this signal.\n");
log("\n");
}
- void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
+ void execute(std::vector<std::string> args, RTLIL::Design *design) override
{
log_header(design, "Executing FSM_EXTRACT pass (extracting FSM from design).\n");
extra_args(args, 1, design);
diff --git a/passes/fsm/fsm_info.cc b/passes/fsm/fsm_info.cc
index 90250f9b7..da0982bb9 100644
--- a/passes/fsm/fsm_info.cc
+++ b/passes/fsm/fsm_info.cc
@@ -30,7 +30,7 @@ PRIVATE_NAMESPACE_BEGIN
struct FsmInfoPass : public Pass {
FsmInfoPass() : Pass("fsm_info", "print information on finite state machines") { }
- void help() YS_OVERRIDE
+ void help() override
{
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
log("\n");
@@ -41,7 +41,7 @@ struct FsmInfoPass : public Pass {
log("pass so that this information is included in the synthesis log file.\n");
log("\n");
}
- void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
+ void execute(std::vector<std::string> args, RTLIL::Design *design) override
{
log_header(design, "Executing FSM_INFO pass (dumping all available information on FSM cells).\n");
extra_args(args, 1, design);
diff --git a/passes/fsm/fsm_map.cc b/passes/fsm/fsm_map.cc
index 1765df092..a30d407f0 100644
--- a/passes/fsm/fsm_map.cc
+++ b/passes/fsm/fsm_map.cc
@@ -322,7 +322,7 @@ static void map_fsm(RTLIL::Cell *fsm_cell, RTLIL::Module *module)
struct FsmMapPass : public Pass {
FsmMapPass() : Pass("fsm_map", "mapping FSMs to basic logic") { }
- void help() YS_OVERRIDE
+ void help() override
{
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
log("\n");
@@ -331,7 +331,7 @@ struct FsmMapPass : public Pass {
log("This pass translates FSM cells to flip-flops and logic.\n");
log("\n");
}
- void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
+ void execute(std::vector<std::string> args, RTLIL::Design *design) override
{
log_header(design, "Executing FSM_MAP pass (mapping FSMs to basic logic).\n");
extra_args(args, 1, design);
diff --git a/passes/fsm/fsm_opt.cc b/passes/fsm/fsm_opt.cc
index 89e8132d4..5fc1fb3bb 100644
--- a/passes/fsm/fsm_opt.cc
+++ b/passes/fsm/fsm_opt.cc
@@ -324,7 +324,7 @@ PRIVATE_NAMESPACE_BEGIN
struct FsmOptPass : public Pass {
FsmOptPass() : Pass("fsm_opt", "optimize finite state machines") { }
- void help() YS_OVERRIDE
+ void help() override
{
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
log("\n");
@@ -335,7 +335,7 @@ struct FsmOptPass : public Pass {
log("combination with the 'opt_clean' pass (see also 'help fsm').\n");
log("\n");
}
- void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
+ void execute(std::vector<std::string> args, RTLIL::Design *design) override
{
log_header(design, "Executing FSM_OPT pass (simple optimizations of FSMs).\n");
extra_args(args, 1, design);
diff --git a/passes/fsm/fsm_recode.cc b/passes/fsm/fsm_recode.cc
index 7edb923b9..d4a704270 100644
--- a/passes/fsm/fsm_recode.cc
+++ b/passes/fsm/fsm_recode.cc
@@ -126,7 +126,7 @@ static void fsm_recode(RTLIL::Cell *cell, RTLIL::Module *module, FILE *fm_set_fs
struct FsmRecodePass : public Pass {
FsmRecodePass() : Pass("fsm_recode", "recoding finite state machines") { }
- void help() YS_OVERRIDE
+ void help() override
{
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
log("\n");
@@ -151,7 +151,7 @@ struct FsmRecodePass : public Pass {
log(" .map <old_bitpattern> <new_bitpattern>\n");
log("\n");
}
- void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
+ void execute(std::vector<std::string> args, RTLIL::Design *design) override
{
FILE *fm_set_fsm_file = NULL;
FILE *encfile = NULL;
diff --git a/passes/hierarchy/hierarchy.cc b/passes/hierarchy/hierarchy.cc
index 95d74d1eb..a2a428d15 100644
--- a/passes/hierarchy/hierarchy.cc
+++ b/passes/hierarchy/hierarchy.cc
@@ -254,16 +254,6 @@ bool expand_module(RTLIL::Design *design, RTLIL::Module *module, bool flag_check
// some lists, so that the ports for sub-modules can be replaced further down:
for (auto &conn : cell->connections()) {
if(mod->wire(conn.first) != nullptr && mod->wire(conn.first)->get_bool_attribute(ID::is_interface)) { // Check if the connection is present as an interface in the sub-module's port list
- //const pool<string> &interface_type_pool = mod->wire(conn.first)->get_strpool_attribute(ID::interface_type);
- //for (auto &d : interface_type_pool) { // TODO: Compare interface type to type in parent module (not crucially important, but good for robustness)
- //}
-
- // Find if the sub-module has set a modport for the current interface connection:
- const pool<string> &interface_modport_pool = mod->wire(conn.first)->get_strpool_attribute(ID::interface_modport);
- std::string interface_modport = "";
- for (auto &d : interface_modport_pool) {
- interface_modport = "\\" + d;
- }
if(conn.second.bits().size() == 1 && conn.second.bits()[0].wire->get_bool_attribute(ID::is_interface)) { // Check if the connected wire is a potential interface in the parent module
std::string interface_name_str = conn.second.bits()[0].wire->name.str();
interface_name_str.replace(0,23,""); // Strip the prefix '$dummywireforinterface' from the dummy wire to get the name
@@ -297,9 +287,12 @@ bool expand_module(RTLIL::Design *design, RTLIL::Module *module, bool flag_check
connections_to_remove.push_back(conn.first);
interfaces_to_add_to_submodule[conn.first] = interfaces_in_module.at(interface_name2);
- // Add modports to a dict which will be passed to AstModule::derive
- if (interface_modport != "") {
- modports_used_in_submodule[conn.first] = interface_modport;
+ // Find if the sub-module has set a modport for the current
+ // interface connection. Add any modports to a dict which will
+ // be passed to AstModule::derive
+ string modport_name = mod->wire(conn.first)->get_string_attribute(ID::interface_modport);
+ if (!modport_name.empty()) {
+ modports_used_in_submodule[conn.first] = "\\" + modport_name;
}
}
else not_found_interface = true;
@@ -565,7 +558,7 @@ RTLIL::Wire *find_implicit_port_wire(Module *module, Cell *cell, const std::stri
struct HierarchyPass : public Pass {
HierarchyPass() : Pass("hierarchy", "check, expand and clean up design hierarchy") { }
- void help() YS_OVERRIDE
+ void help() override
{
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
log("\n");
@@ -574,9 +567,9 @@ struct HierarchyPass : public Pass {
log("\n");
log("In parametric designs, a module might exists in several variations with\n");
log("different parameter values. This pass looks at all modules in the current\n");
- log("design an re-runs the language frontends for the parametric modules as\n");
+ log("design and re-runs the language frontends for the parametric modules as\n");
log("needed. It also resolves assignments to wired logic data types (wand/wor),\n");
- log("resolves positional module parameters, unroll array instances, and more.\n");
+ log("resolves positional module parameters, unrolls array instances, and more.\n");
log("\n");
log(" -check\n");
log(" also check the design hierarchy. this generates an error when\n");
@@ -646,7 +639,7 @@ struct HierarchyPass : public Pass {
log("in the current design.\n");
log("\n");
}
- void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
+ void execute(std::vector<std::string> args, RTLIL::Design *design) override
{
log_header(design, "Executing HIERARCHY pass (managing design hierarchy).\n");
diff --git a/passes/hierarchy/submod.cc b/passes/hierarchy/submod.cc
index 2db7cf26b..b2826cbff 100644
--- a/passes/hierarchy/submod.cc
+++ b/passes/hierarchy/submod.cc
@@ -319,7 +319,7 @@ struct SubmodWorker
struct SubmodPass : public Pass {
SubmodPass() : Pass("submod", "moving part of a module to a new submodule") { }
- void help() YS_OVERRIDE
+ void help() override
{
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
log("\n");
@@ -351,7 +351,7 @@ struct SubmodPass : public Pass {
log(" original module with original public names.\n");
log("\n");
}
- void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
+ void execute(std::vector<std::string> args, RTLIL::Design *design) override
{
log_header(design, "Executing SUBMOD pass (moving cells to submodules as requested).\n");
log_push();
diff --git a/passes/hierarchy/uniquify.cc b/passes/hierarchy/uniquify.cc
index 5dbd15a7e..3f9443a63 100644
--- a/passes/hierarchy/uniquify.cc
+++ b/passes/hierarchy/uniquify.cc
@@ -24,7 +24,7 @@ PRIVATE_NAMESPACE_BEGIN
struct UniquifyPass : public Pass {
UniquifyPass() : Pass("uniquify", "create unique copies of modules") { }
- void help() YS_OVERRIDE
+ void help() override
{
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
log("\n");
@@ -41,7 +41,7 @@ struct UniquifyPass : public Pass {
log("attribute set (the 'top' module is unique implicitly).\n");
log("\n");
}
- void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
+ void execute(std::vector<std::string> args, RTLIL::Design *design) override
{
log_header(design, "Executing UNIQUIFY pass (creating unique copies of modules).\n");
diff --git a/passes/memory/memory.cc b/passes/memory/memory.cc
index cee63bdd8..282517992 100644
--- a/passes/memory/memory.cc
+++ b/passes/memory/memory.cc
@@ -27,7 +27,7 @@ PRIVATE_NAMESPACE_BEGIN
struct MemoryPass : public Pass {
MemoryPass() : Pass("memory", "translate memories to basic cells") { }
- void help() YS_OVERRIDE
+ void help() override
{
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
log("\n");
@@ -49,7 +49,7 @@ struct MemoryPass : public Pass {
log("or multiport memory blocks if called with the -nomap option.\n");
log("\n");
}
- void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
+ void execute(std::vector<std::string> args, RTLIL::Design *design) override
{
bool flag_nomap = false;
bool flag_nordff = false;
diff --git a/passes/memory/memory_bram.cc b/passes/memory/memory_bram.cc
index 0898ec288..3cb0728b7 100644
--- a/passes/memory/memory_bram.cc
+++ b/passes/memory/memory_bram.cc
@@ -1265,7 +1265,7 @@ void handle_cell(Cell *cell, const rules_t &rules)
struct MemoryBramPass : public Pass {
MemoryBramPass() : Pass("memory_bram", "map memories to block rams") { }
- void help() YS_OVERRIDE
+ void help() override
{
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
log("\n");
@@ -1367,7 +1367,7 @@ struct MemoryBramPass : public Pass {
log("the data bits to accommodate the enable pattern of port A.\n");
log("\n");
}
- void execute(vector<string> args, Design *design) YS_OVERRIDE
+ void execute(vector<string> args, Design *design) override
{
rules_t rules;
diff --git a/passes/memory/memory_collect.cc b/passes/memory/memory_collect.cc
index ef8b07811..7e82f47dc 100644
--- a/passes/memory/memory_collect.cc
+++ b/passes/memory/memory_collect.cc
@@ -245,7 +245,7 @@ static void handle_module(Design *design, Module *module)
struct MemoryCollectPass : public Pass {
MemoryCollectPass() : Pass("memory_collect", "creating multi-port memory cells") { }
- void help() YS_OVERRIDE
+ void help() override
{
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
log("\n");
@@ -255,7 +255,7 @@ struct MemoryCollectPass : public Pass {
log("memory cells.\n");
log("\n");
}
- void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE {
+ void execute(std::vector<std::string> args, RTLIL::Design *design) override {
log_header(design, "Executing MEMORY_COLLECT pass (generating $mem cells).\n");
extra_args(args, 1, design);
for (auto module : design->selected_modules())
diff --git a/passes/memory/memory_dff.cc b/passes/memory/memory_dff.cc
index 726a5c1ff..947cf7b35 100644
--- a/passes/memory/memory_dff.cc
+++ b/passes/memory/memory_dff.cc
@@ -291,7 +291,7 @@ struct MemoryDffWorker
struct MemoryDffPass : public Pass {
MemoryDffPass() : Pass("memory_dff", "merge input/output DFFs into memories") { }
- void help() YS_OVERRIDE
+ void help() override
{
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
log("\n");
@@ -305,7 +305,7 @@ struct MemoryDffPass : public Pass {
log(" do not merge registers on read ports\n");
log("\n");
}
- void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
+ void execute(std::vector<std::string> args, RTLIL::Design *design) override
{
bool flag_wr_only = false;
diff --git a/passes/memory/memory_map.cc b/passes/memory/memory_map.cc
index 9d455f55b..80dd3957d 100644
--- a/passes/memory/memory_map.cc
+++ b/passes/memory/memory_map.cc
@@ -403,7 +403,7 @@ struct MemoryMapWorker
struct MemoryMapPass : public Pass {
MemoryMapPass() : Pass("memory_map", "translate multiport memories to basic cells") { }
- void help() YS_OVERRIDE
+ void help() override
{
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
log("\n");
@@ -425,7 +425,7 @@ struct MemoryMapPass : public Pass {
log(" for -attr, ignore case of <value>.\n");
log("\n");
}
- void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
+ void execute(std::vector<std::string> args, RTLIL::Design *design) override
{
bool attr_icase = false;
dict<RTLIL::IdString, std::vector<RTLIL::Const>> attributes;
diff --git a/passes/memory/memory_memx.cc b/passes/memory/memory_memx.cc
index 5d5f61c7d..02e00cf30 100644
--- a/passes/memory/memory_memx.cc
+++ b/passes/memory/memory_memx.cc
@@ -28,7 +28,7 @@ PRIVATE_NAMESPACE_BEGIN
struct MemoryMemxPass : public Pass {
MemoryMemxPass() : Pass("memory_memx", "emulate vlog sim behavior for mem ports") { }
- void help() YS_OVERRIDE
+ void help() override
{
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
log("\n");
@@ -38,7 +38,7 @@ struct MemoryMemxPass : public Pass {
log("behavior for out-of-bounds memory reads and writes.\n");
log("\n");
}
- void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE {
+ void execute(std::vector<std::string> args, RTLIL::Design *design) override {
log_header(design, "Executing MEMORY_MEMX pass (converting $mem cells to logic and flip-flops).\n");
extra_args(args, 1, design);
diff --git a/passes/memory/memory_nordff.cc b/passes/memory/memory_nordff.cc
index 487785397..07bbd9fe8 100644
--- a/passes/memory/memory_nordff.cc
+++ b/passes/memory/memory_nordff.cc
@@ -25,7 +25,7 @@ PRIVATE_NAMESPACE_BEGIN
struct MemoryNordffPass : public Pass {
MemoryNordffPass() : Pass("memory_nordff", "extract read port FFs from memories") { }
- void help() YS_OVERRIDE
+ void help() override
{
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
log("\n");
@@ -35,7 +35,7 @@ struct MemoryNordffPass : public Pass {
log("similar to what one would get from calling memory_dff with -nordff.\n");
log("\n");
}
- void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
+ void execute(std::vector<std::string> args, RTLIL::Design *design) override
{
log_header(design, "Executing MEMORY_NORDFF pass (extracting $dff cells from $mem).\n");
diff --git a/passes/memory/memory_share.cc b/passes/memory/memory_share.cc
index 477246687..7315aeae1 100644
--- a/passes/memory/memory_share.cc
+++ b/passes/memory/memory_share.cc
@@ -715,6 +715,8 @@ struct MemoryShareWorker
cone_ct.cell_types.erase(ID($mul));
cone_ct.cell_types.erase(ID($mod));
cone_ct.cell_types.erase(ID($div));
+ cone_ct.cell_types.erase(ID($modfloor));
+ cone_ct.cell_types.erase(ID($divfloor));
cone_ct.cell_types.erase(ID($pow));
cone_ct.cell_types.erase(ID($shl));
cone_ct.cell_types.erase(ID($shr));
@@ -732,7 +734,7 @@ struct MemoryShareWorker
struct MemorySharePass : public Pass {
MemorySharePass() : Pass("memory_share", "consolidate memory ports") { }
- void help() YS_OVERRIDE
+ void help() override
{
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
log("\n");
@@ -758,7 +760,7 @@ struct MemorySharePass : public Pass {
log("optimizations) such as \"share\" and \"opt_merge\".\n");
log("\n");
}
- void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE {
+ void execute(std::vector<std::string> args, RTLIL::Design *design) override {
log_header(design, "Executing MEMORY_SHARE pass (consolidating $memrd/$memwr cells).\n");
extra_args(args, 1, design);
MemoryShareWorker msw(design);
diff --git a/passes/memory/memory_unpack.cc b/passes/memory/memory_unpack.cc
index 8d284edcd..d04d4ba7a 100644
--- a/passes/memory/memory_unpack.cc
+++ b/passes/memory/memory_unpack.cc
@@ -127,7 +127,7 @@ void handle_module(RTLIL::Design *design, RTLIL::Module *module)
struct MemoryUnpackPass : public Pass {
MemoryUnpackPass() : Pass("memory_unpack", "unpack multi-port memory cells") { }
- void help() YS_OVERRIDE
+ void help() override
{
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
log("\n");
@@ -137,7 +137,7 @@ struct MemoryUnpackPass : public Pass {
log("$memwr cells. It is the counterpart to the memory_collect pass.\n");
log("\n");
}
- void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE {
+ void execute(std::vector<std::string> args, RTLIL::Design *design) override {
log_header(design, "Executing MEMORY_UNPACK pass (generating $memrd/$memwr cells form $mem cells).\n");
extra_args(args, 1, design);
for (auto module : design->selected_modules())
diff --git a/passes/opt/muxpack.cc b/passes/opt/muxpack.cc
index 9df49ab3c..aa5f82437 100644
--- a/passes/opt/muxpack.cc
+++ b/passes/opt/muxpack.cc
@@ -326,7 +326,7 @@ struct MuxpackWorker
struct MuxpackPass : public Pass {
MuxpackPass() : Pass("muxpack", "$mux/$pmux cascades to $pmux") { }
- void help() YS_OVERRIDE
+ void help() override
{
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
log("\n");
@@ -341,7 +341,7 @@ struct MuxpackPass : public Pass {
log("certain that their select inputs are mutually exclusive.\n");
log("\n");
}
- void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
+ void execute(std::vector<std::string> args, RTLIL::Design *design) override
{
log_header(design, "Executing MUXPACK pass ($mux cell cascades to $pmux).\n");
diff --git a/passes/opt/opt.cc b/passes/opt/opt.cc
index 396819883..8be94e345 100644
--- a/passes/opt/opt.cc
+++ b/passes/opt/opt.cc
@@ -27,7 +27,7 @@ PRIVATE_NAMESPACE_BEGIN
struct OptPass : public Pass {
OptPass() : Pass("opt", "perform simple optimizations") { }
- void help() YS_OVERRIDE
+ void help() override
{
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
log("\n");
@@ -44,8 +44,8 @@ struct OptPass : public Pass {
log(" opt_muxtree\n");
log(" opt_reduce [-fine] [-full]\n");
log(" opt_merge [-share_all]\n");
- log(" opt_share (-full only)\n");
- log(" opt_rmdff [-keepdc] [-sat]\n");
+ log(" opt_share (-full only)\n");
+ log(" opt_rmdff [-keepdc] [-sat] (except when called with -noff)\n");
log(" opt_clean [-purge]\n");
log(" opt_expr [-mux_undef] [-mux_bool] [-undriven] [-clkinv] [-fine] [-full] [-keepdc]\n");
log(" while <changed design>\n");
@@ -55,7 +55,7 @@ struct OptPass : public Pass {
log(" do\n");
log(" opt_expr [-mux_undef] [-mux_bool] [-undriven] [-clkinv] [-fine] [-full] [-keepdc]\n");
log(" opt_merge [-share_all]\n");
- log(" opt_rmdff [-keepdc] [-sat]\n");
+ log(" opt_rmdff [-keepdc] [-sat] (except when called with -noff)\n");
log(" opt_clean [-purge]\n");
log(" while <changed design in opt_rmdff>\n");
log("\n");
@@ -64,7 +64,7 @@ struct OptPass : public Pass {
log("\n");
log("\n");
}
- void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
+ void execute(std::vector<std::string> args, RTLIL::Design *design) override
{
std::string opt_clean_args;
std::string opt_expr_args;
@@ -73,6 +73,7 @@ struct OptPass : public Pass {
std::string opt_rmdff_args;
bool opt_share = false;
bool fast_mode = false;
+ bool noff_mode = false;
log_header(design, "Executing OPT pass (performing simple optimizations).\n");
log_push();
@@ -127,6 +128,10 @@ struct OptPass : public Pass {
fast_mode = true;
continue;
}
+ if (args[argidx] == "-noff") {
+ noff_mode = true;
+ continue;
+ }
break;
}
extra_args(args, argidx, design);
@@ -137,7 +142,8 @@ struct OptPass : public Pass {
Pass::call(design, "opt_expr" + opt_expr_args);
Pass::call(design, "opt_merge" + opt_merge_args);
design->scratchpad_unset("opt.did_something");
- Pass::call(design, "opt_rmdff" + opt_rmdff_args);
+ if (!noff_mode)
+ Pass::call(design, "opt_rmdff" + opt_rmdff_args);
if (design->scratchpad_get_bool("opt.did_something") == false)
break;
Pass::call(design, "opt_clean" + opt_clean_args);
@@ -156,7 +162,8 @@ struct OptPass : public Pass {
Pass::call(design, "opt_merge" + opt_merge_args);
if (opt_share)
Pass::call(design, "opt_share");
- Pass::call(design, "opt_rmdff" + opt_rmdff_args);
+ if (!noff_mode)
+ Pass::call(design, "opt_rmdff" + opt_rmdff_args);
Pass::call(design, "opt_clean" + opt_clean_args);
Pass::call(design, "opt_expr" + opt_expr_args);
if (design->scratchpad_get_bool("opt.did_something") == false)
diff --git a/passes/opt/opt_clean.cc b/passes/opt/opt_clean.cc
index f7de02164..44de60b48 100644
--- a/passes/opt/opt_clean.cc
+++ b/passes/opt/opt_clean.cc
@@ -526,7 +526,7 @@ void rmunused_module(RTLIL::Module *module, bool purge_mode, bool verbose, bool
struct OptCleanPass : public Pass {
OptCleanPass() : Pass("opt_clean", "remove unused cells and wires") { }
- void help() YS_OVERRIDE
+ void help() override
{
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
log("\n");
@@ -543,7 +543,7 @@ struct OptCleanPass : public Pass {
log(" also remove internal nets if they have a public name\n");
log("\n");
}
- void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
+ void execute(std::vector<std::string> args, RTLIL::Design *design) override
{
bool purge_mode = false;
@@ -592,7 +592,7 @@ struct OptCleanPass : public Pass {
struct CleanPass : public Pass {
CleanPass() : Pass("clean", "remove unused cells and wires") { }
- void help() YS_OVERRIDE
+ void help() override
{
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
log("\n");
@@ -607,7 +607,7 @@ struct CleanPass : public Pass {
log("in -purge mode between the commands.\n");
log("\n");
}
- void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
+ void execute(std::vector<std::string> args, RTLIL::Design *design) override
{
bool purge_mode = false;
diff --git a/passes/opt/opt_demorgan.cc b/passes/opt/opt_demorgan.cc
index 4bc82815b..f0fa86f42 100644
--- a/passes/opt/opt_demorgan.cc
+++ b/passes/opt/opt_demorgan.cc
@@ -169,7 +169,7 @@ void demorgan_worker(
struct OptDemorganPass : public Pass {
OptDemorganPass() : Pass("opt_demorgan", "Optimize reductions with DeMorgan equivalents") { }
- void help() YS_OVERRIDE
+ void help() override
{
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
log("\n");
@@ -179,7 +179,7 @@ struct OptDemorganPass : public Pass {
log("overall gate count of the circuit\n");
log("\n");
}
- void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
+ void execute(std::vector<std::string> args, RTLIL::Design *design) override
{
log_header(design, "Executing OPT_DEMORGAN pass (push inverters through $reduce_* cells).\n");
diff --git a/passes/opt/opt_expr.cc b/passes/opt/opt_expr.cc
index 777a24777..1051a59f2 100644
--- a/passes/opt/opt_expr.cc
+++ b/passes/opt/opt_expr.cc
@@ -117,7 +117,7 @@ void replace_undriven(RTLIL::Module *module, const CellTypes &ct)
}
void replace_cell(SigMap &assign_map, RTLIL::Module *module, RTLIL::Cell *cell,
- const std::string &info YS_ATTRIBUTE(unused), IdString out_port, RTLIL::SigSpec out_val)
+ const std::string &info, IdString out_port, RTLIL::SigSpec out_val)
{
RTLIL::SigSpec Y = cell->getPort(out_port);
out_val.extend_u0(Y.size(), false);
@@ -467,15 +467,21 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons
if (clkinv)
{
- if (cell->type.in(ID($dff), ID($dffe), ID($dffsr), ID($adff), ID($fsm), ID($memrd), ID($memwr)))
+ if (cell->type.in(ID($dff), ID($dffe), ID($dffsr), ID($dffsre), ID($adff), ID($adffe), ID($sdff), ID($sdffe), ID($sdffce), ID($fsm), ID($memrd), ID($memwr)))
handle_polarity_inv(cell, ID::CLK, ID::CLK_POLARITY, assign_map, invert_map);
- if (cell->type.in(ID($sr), ID($dffsr), ID($dlatchsr))) {
+ if (cell->type.in(ID($sr), ID($dffsr), ID($dffsre), ID($dlatchsr))) {
handle_polarity_inv(cell, ID::SET, ID::SET_POLARITY, assign_map, invert_map);
handle_polarity_inv(cell, ID::CLR, ID::CLR_POLARITY, assign_map, invert_map);
}
- if (cell->type.in(ID($dffe), ID($dlatch), ID($dlatchsr)))
+ if (cell->type.in(ID($adff), ID($adffe), ID($adlatch)))
+ handle_polarity_inv(cell, ID::ARST, ID::ARST_POLARITY, assign_map, invert_map);
+
+ if (cell->type.in(ID($sdff), ID($sdffe), ID($sdffce)))
+ handle_polarity_inv(cell, ID::SRST, ID::SRST_POLARITY, assign_map, invert_map);
+
+ if (cell->type.in(ID($dffe), ID($adffe), ID($sdffe), ID($sdffce), ID($dffsre), ID($dlatch), ID($adlatch), ID($dlatchsr)))
handle_polarity_inv(cell, ID::EN, ID::EN_POLARITY, assign_map, invert_map);
handle_clkpol_celltype_swap(cell, "$_SR_N?_", "$_SR_P?_", ID::S, assign_map, invert_map);
@@ -489,12 +495,35 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons
handle_clkpol_celltype_swap(cell, "$_DFF_N??_", "$_DFF_P??_", ID::C, assign_map, invert_map);
handle_clkpol_celltype_swap(cell, "$_DFF_?N?_", "$_DFF_?P?_", ID::R, assign_map, invert_map);
+ handle_clkpol_celltype_swap(cell, "$_DFFE_N???_", "$_DFFE_P???_", ID::C, assign_map, invert_map);
+ handle_clkpol_celltype_swap(cell, "$_DFFE_?N??_", "$_DFFE_?P??_", ID::R, assign_map, invert_map);
+ handle_clkpol_celltype_swap(cell, "$_DFFE_???N_", "$_DFFE_???P_", ID::E, assign_map, invert_map);
+
+ handle_clkpol_celltype_swap(cell, "$_SDFF_N??_", "$_SDFF_P??_", ID::C, assign_map, invert_map);
+ handle_clkpol_celltype_swap(cell, "$_SDFF_?N?_", "$_SDFF_?P?_", ID::R, assign_map, invert_map);
+
+ handle_clkpol_celltype_swap(cell, "$_SDFFE_N???_", "$_SDFFE_P???_", ID::C, assign_map, invert_map);
+ handle_clkpol_celltype_swap(cell, "$_SDFFE_?N??_", "$_SDFFE_?P??_", ID::R, assign_map, invert_map);
+ handle_clkpol_celltype_swap(cell, "$_SDFFE_???N_", "$_SDFFE_???P_", ID::E, assign_map, invert_map);
+
+ handle_clkpol_celltype_swap(cell, "$_SDFFCE_N???_", "$_SDFFCE_P???_", ID::C, assign_map, invert_map);
+ handle_clkpol_celltype_swap(cell, "$_SDFFCE_?N??_", "$_SDFFCE_?P??_", ID::R, assign_map, invert_map);
+ handle_clkpol_celltype_swap(cell, "$_SDFFCE_???N_", "$_SDFFCE_???P_", ID::E, assign_map, invert_map);
+
handle_clkpol_celltype_swap(cell, "$_DFFSR_N??_", "$_DFFSR_P??_", ID::C, assign_map, invert_map);
handle_clkpol_celltype_swap(cell, "$_DFFSR_?N?_", "$_DFFSR_?P?_", ID::S, assign_map, invert_map);
handle_clkpol_celltype_swap(cell, "$_DFFSR_??N_", "$_DFFSR_??P_", ID::R, assign_map, invert_map);
+ handle_clkpol_celltype_swap(cell, "$_DFFSRE_N???_", "$_DFFSRE_P???_", ID::C, assign_map, invert_map);
+ handle_clkpol_celltype_swap(cell, "$_DFFSRE_?N??_", "$_DFFSRE_?P??_", ID::S, assign_map, invert_map);
+ handle_clkpol_celltype_swap(cell, "$_DFFSRE_??N?_", "$_DFFSRE_??P?_", ID::R, assign_map, invert_map);
+ handle_clkpol_celltype_swap(cell, "$_DFFSRE_???N_", "$_DFFSRE_???P_", ID::E, assign_map, invert_map);
+
handle_clkpol_celltype_swap(cell, "$_DLATCH_N_", "$_DLATCH_P_", ID::E, assign_map, invert_map);
+ handle_clkpol_celltype_swap(cell, "$_DLATCH_N??_", "$_DLATCH_P??_", ID::E, assign_map, invert_map);
+ handle_clkpol_celltype_swap(cell, "$_DLATCH_?N?_", "$_DLATCH_?P?_", ID::R, assign_map, invert_map);
+
handle_clkpol_celltype_swap(cell, "$_DLATCHSR_N??_", "$_DLATCHSR_P??_", ID::E, assign_map, invert_map);
handle_clkpol_celltype_swap(cell, "$_DLATCHSR_?N?_", "$_DLATCHSR_?P?_", ID::S, assign_map, invert_map);
handle_clkpol_celltype_swap(cell, "$_DLATCHSR_??N_", "$_DLATCHSR_??P_", ID::R, assign_map, invert_map);
@@ -864,7 +893,7 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons
skip_fine_alu:
if (cell->type.in(ID($reduce_xor), ID($reduce_xnor), ID($shift), ID($shiftx), ID($shl), ID($shr), ID($sshl), ID($sshr),
- ID($lt), ID($le), ID($ge), ID($gt), ID($neg), ID($add), ID($sub), ID($mul), ID($div), ID($mod), ID($pow)))
+ ID($lt), ID($le), ID($ge), ID($gt), ID($neg), ID($add), ID($sub), ID($mul), ID($div), ID($mod), ID($divfloor), ID($modfloor), ID($pow)))
{
RTLIL::SigSpec sig_a = assign_map(cell->getPort(ID::A));
RTLIL::SigSpec sig_b = cell->hasPort(ID::B) ? assign_map(cell->getPort(ID::B)) : RTLIL::SigSpec();
@@ -883,7 +912,7 @@ skip_fine_alu:
if (0) {
found_the_x_bit:
cover_list("opt.opt_expr.xbit", "$reduce_xor", "$reduce_xnor", "$shl", "$shr", "$sshl", "$sshr", "$shift", "$shiftx",
- "$lt", "$le", "$ge", "$gt", "$neg", "$add", "$sub", "$mul", "$div", "$mod", "$pow", cell->type.str());
+ "$lt", "$le", "$ge", "$gt", "$neg", "$add", "$sub", "$mul", "$div", "$mod", "$divfloor", "$modfloor", "$pow", cell->type.str());
if (cell->type.in(ID($reduce_xor), ID($reduce_xnor), ID($lt), ID($le), ID($ge), ID($gt)))
replace_cell(assign_map, module, cell, "x-bit in input", ID::Y, RTLIL::State::Sx);
else
@@ -1469,6 +1498,8 @@ skip_identity:
FOLD_2ARG_CELL(mul)
FOLD_2ARG_CELL(div)
FOLD_2ARG_CELL(mod)
+ FOLD_2ARG_CELL(divfloor)
+ FOLD_2ARG_CELL(modfloor)
FOLD_2ARG_CELL(pow)
FOLD_1ARG_CELL(pos)
@@ -1583,9 +1614,11 @@ skip_identity:
}
}
- if (!keepdc && cell->type.in(ID($div), ID($mod)))
+ if (!keepdc && cell->type.in(ID($div), ID($mod), ID($divfloor), ID($modfloor)))
{
+ bool a_signed = cell->parameters[ID::A_SIGNED].as_bool();
bool b_signed = cell->parameters[ID::B_SIGNED].as_bool();
+ SigSpec sig_a = assign_map(cell->getPort(ID::A));
SigSpec sig_b = assign_map(cell->getPort(ID::B));
SigSpec sig_y = assign_map(cell->getPort(ID::Y));
@@ -1610,11 +1643,13 @@ skip_identity:
for (int i = 1; i < (b_signed ? sig_b.size()-1 : sig_b.size()); i++)
if (b_val == (1 << i))
{
- if (cell->type == ID($div))
+ if (cell->type.in(ID($div), ID($divfloor)))
{
cover("opt.opt_expr.div_shift");
- log_debug("Replacing divide-by-%d cell `%s' in module `%s' with shift-by-%d.\n",
+ bool is_truncating = cell->type == ID($div);
+ log_debug("Replacing %s-divide-by-%d cell `%s' in module `%s' with shift-by-%d.\n",
+ is_truncating ? "truncating" : "flooring",
b_val, cell->name.c_str(), module->name.c_str(), i);
std::vector<RTLIL::SigBit> new_b = RTLIL::SigSpec(i, 6);
@@ -1622,17 +1657,35 @@ skip_identity:
while (GetSize(new_b) > 1 && new_b.back() == RTLIL::State::S0)
new_b.pop_back();
- cell->type = ID($shr);
+ cell->type = ID($sshr);
cell->parameters[ID::B_WIDTH] = GetSize(new_b);
cell->parameters[ID::B_SIGNED] = false;
cell->setPort(ID::B, new_b);
+
+ // Truncating division is the same as flooring division, except when
+ // the result is negative and there is a remainder - then trunc = floor + 1
+ if (is_truncating && a_signed) {
+ Wire *flooring = module->addWire(NEW_ID, sig_y.size());
+ cell->setPort(ID::Y, flooring);
+
+ Wire *result_neg = module->addWire(NEW_ID);
+ module->addXor(NEW_ID, sig_a[sig_a.size()-1], sig_b[sig_b.size()-1], result_neg);
+ Wire *rem_nonzero = module->addWire(NEW_ID);
+ module->addReduceOr(NEW_ID, sig_a.extract(0, i), rem_nonzero);
+ Wire *should_add = module->addWire(NEW_ID);
+ module->addAnd(NEW_ID, result_neg, rem_nonzero, should_add);
+ module->addAdd(NEW_ID, flooring, should_add, sig_y);
+ }
+
cell->check();
}
- else
+ else if (cell->type.in(ID($mod), ID($modfloor)))
{
cover("opt.opt_expr.mod_mask");
- log_debug("Replacing modulo-by-%d cell `%s' in module `%s' with bitmask.\n",
+ bool is_truncating = cell->type == ID($mod);
+ log_debug("Replacing %s-modulo-by-%d cell `%s' in module `%s' with bitmask.\n",
+ is_truncating ? "truncating" : "flooring",
b_val, cell->name.c_str(), module->name.c_str());
std::vector<RTLIL::SigBit> new_b = RTLIL::SigSpec(State::S1, i);
@@ -1643,6 +1696,24 @@ skip_identity:
cell->type = ID($and);
cell->parameters[ID::B_WIDTH] = GetSize(new_b);
cell->setPort(ID::B, new_b);
+
+ // truncating modulo has the same masked bits as flooring modulo, but
+ // the sign bits are those of A (except when R=0)
+ if (is_truncating && a_signed) {
+ Wire *flooring = module->addWire(NEW_ID, sig_y.size());
+ cell->setPort(ID::Y, flooring);
+ SigSpec truncating = SigSpec(flooring).extract(0, i);
+
+ Wire *rem_nonzero = module->addWire(NEW_ID);
+ module->addReduceOr(NEW_ID, truncating, rem_nonzero);
+ SigSpec a_sign = sig_a[sig_a.size()-1];
+ Wire *extend_bit = module->addWire(NEW_ID);
+ module->addAnd(NEW_ID, a_sign, rem_nonzero, extend_bit);
+
+ truncating.append(extend_bit);
+ module->addPos(NEW_ID, truncating, sig_y, true);
+ }
+
cell->check();
}
@@ -1967,7 +2038,7 @@ skip_alu_split:
struct OptExprPass : public Pass {
OptExprPass() : Pass("opt_expr", "perform const folding and simple expression rewriting") { }
- void help() YS_OVERRIDE
+ void help() override
{
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
log("\n");
@@ -2001,7 +2072,7 @@ struct OptExprPass : public Pass {
log(" replaced by 'a'. the -keepdc option disables all such optimizations.\n");
log("\n");
}
- void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
+ void execute(std::vector<std::string> args, RTLIL::Design *design) override
{
bool mux_undef = false;
bool mux_bool = false;
diff --git a/passes/opt/opt_lut.cc b/passes/opt/opt_lut.cc
index 12927d052..07a91af8a 100644
--- a/passes/opt/opt_lut.cc
+++ b/passes/opt/opt_lut.cc
@@ -520,7 +520,7 @@ static void split(std::vector<std::string> &tokens, const std::string &text, cha
struct OptLutPass : public Pass {
OptLutPass() : Pass("opt_lut", "optimize LUT cells") { }
- void help() YS_OVERRIDE
+ void help() override
{
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
log("\n");
@@ -538,7 +538,7 @@ struct OptLutPass : public Pass {
log(" only perform the first N combines, then stop. useful for debugging.\n");
log("\n");
}
- void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
+ void execute(std::vector<std::string> args, RTLIL::Design *design) override
{
log_header(design, "Executing OPT_LUT pass (optimize LUTs).\n");
diff --git a/passes/opt/opt_lut_ins.cc b/passes/opt/opt_lut_ins.cc
index 1d32e84bb..bb40e1e55 100644
--- a/passes/opt/opt_lut_ins.cc
+++ b/passes/opt/opt_lut_ins.cc
@@ -25,7 +25,7 @@ PRIVATE_NAMESPACE_BEGIN
struct OptLutInsPass : public Pass {
OptLutInsPass() : Pass("opt_lut_ins", "discard unused LUT inputs") { }
- void help() YS_OVERRIDE
+ void help() override
{
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
log("\n");
@@ -42,7 +42,7 @@ struct OptLutInsPass : public Pass {
log(" to the given technology. Valid values are: xilinx, ecp5, gowin.\n");
log("\n");
}
- void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
+ void execute(std::vector<std::string> args, RTLIL::Design *design) override
{
log_header(design, "Executing OPT_LUT_INS pass (discard unused LUT inputs).\n");
string techname;
diff --git a/passes/opt/opt_mem.cc b/passes/opt/opt_mem.cc
index ff9c06453..24df1356b 100644
--- a/passes/opt/opt_mem.cc
+++ b/passes/opt/opt_mem.cc
@@ -97,7 +97,7 @@ struct OptMemWorker
struct OptMemPass : public Pass {
OptMemPass() : Pass("opt_mem", "optimize memories") { }
- void help() YS_OVERRIDE
+ void help() override
{
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
log("\n");
@@ -106,7 +106,7 @@ struct OptMemPass : public Pass {
log("This pass performs various optimizations on memories in the design.\n");
log("\n");
}
- void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
+ void execute(std::vector<std::string> args, RTLIL::Design *design) override
{
log_header(design, "Executing OPT_MEM pass (optimize memories).\n");
diff --git a/passes/opt/opt_merge.cc b/passes/opt/opt_merge.cc
index d845926fc..f03faa9cf 100644
--- a/passes/opt/opt_merge.cc
+++ b/passes/opt/opt_merge.cc
@@ -298,9 +298,7 @@ struct OptMergeWorker
module->connect(RTLIL::SigSig(it.second, other_sig));
assign_map.add(it.second, other_sig);
- if (it.first == ID::Q && (cell->type.begins_with("$dff") || cell->type.begins_with("$dlatch") ||
- cell->type.begins_with("$_DFF") || cell->type.begins_with("$_DLATCH") || cell->type.begins_with("$_SR_") ||
- cell->type.in(ID($adff), ID($sr), ID($ff), ID($_FF_)))) {
+ if (it.first == ID::Q && RTLIL::builtin_ff_cell_types().count(cell->type)) {
for (auto c : it.second.chunks()) {
auto jt = c.wire->attributes.find(ID::init);
if (jt == c.wire->attributes.end())
@@ -326,7 +324,7 @@ struct OptMergeWorker
struct OptMergePass : public Pass {
OptMergePass() : Pass("opt_merge", "consolidate identical cells") { }
- void help() YS_OVERRIDE
+ void help() override
{
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
log("\n");
@@ -342,7 +340,7 @@ struct OptMergePass : public Pass {
log(" Operate on all cell types, not just built-in types.\n");
log("\n");
}
- void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
+ void execute(std::vector<std::string> args, RTLIL::Design *design) override
{
log_header(design, "Executing OPT_MERGE pass (detect identical cells).\n");
diff --git a/passes/opt/opt_muxtree.cc b/passes/opt/opt_muxtree.cc
index d076addae..67b283e11 100644
--- a/passes/opt/opt_muxtree.cc
+++ b/passes/opt/opt_muxtree.cc
@@ -473,7 +473,7 @@ struct OptMuxtreeWorker
struct OptMuxtreePass : public Pass {
OptMuxtreePass() : Pass("opt_muxtree", "eliminate dead trees in multiplexer trees") { }
- void help() YS_OVERRIDE
+ void help() override
{
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
log("\n");
@@ -486,7 +486,7 @@ struct OptMuxtreePass : public Pass {
log("This pass only operates on completely selected modules without processes.\n");
log("\n");
}
- void execute(vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
+ void execute(vector<std::string> args, RTLIL::Design *design) override
{
log_header(design, "Executing OPT_MUXTREE pass (detect dead branches in mux trees).\n");
extra_args(args, 1, design);
diff --git a/passes/opt/opt_reduce.cc b/passes/opt/opt_reduce.cc
index f640f50a0..28de9ceb6 100644
--- a/passes/opt/opt_reduce.cc
+++ b/passes/opt/opt_reduce.cc
@@ -332,7 +332,7 @@ struct OptReduceWorker
struct OptReducePass : public Pass {
OptReducePass() : Pass("opt_reduce", "simplify large MUXes and AND/OR gates") { }
- void help() YS_OVERRIDE
+ void help() override
{
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
log("\n");
@@ -353,7 +353,7 @@ struct OptReducePass : public Pass {
log(" alias for -fine\n");
log("\n");
}
- void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
+ void execute(std::vector<std::string> args, RTLIL::Design *design) override
{
bool do_fine = false;
diff --git a/passes/opt/opt_rmdff.cc b/passes/opt/opt_rmdff.cc
index 81326a417..8f7628a4a 100644
--- a/passes/opt/opt_rmdff.cc
+++ b/passes/opt/opt_rmdff.cc
@@ -540,7 +540,7 @@ delete_dff:
struct OptRmdffPass : public Pass {
OptRmdffPass() : Pass("opt_rmdff", "remove DFFs with constant inputs") { }
- void help() YS_OVERRIDE
+ void help() override
{
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
log("\n");
@@ -554,7 +554,7 @@ struct OptRmdffPass : public Pass {
log(" non-constant inputs) that can also be replaced with a constant driver\n");
log("\n");
}
- void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
+ void execute(std::vector<std::string> args, RTLIL::Design *design) override
{
int total_count = 0, total_initdrv = 0;
log_header(design, "Executing OPT_RMDFF pass (remove dff with constant values).\n");
diff --git a/passes/opt/opt_share.cc b/passes/opt/opt_share.cc
index 1f69c98f4..db21cef28 100644
--- a/passes/opt/opt_share.cc
+++ b/passes/opt/opt_share.cc
@@ -103,7 +103,7 @@ bool cell_supported(RTLIL::Cell *cell)
if (sig_bi.is_fully_const() && sig_ci.is_fully_const() && sig_bi == sig_ci)
return true;
- } else if (cell->type.in(LOGICAL_OPS, SHIFT_OPS, BITWISE_OPS, RELATIONAL_OPS, ID($add), ID($sub), ID($mul), ID($div), ID($mod), ID($concat))) {
+ } else if (cell->type.in(LOGICAL_OPS, SHIFT_OPS, BITWISE_OPS, RELATIONAL_OPS, ID($add), ID($sub), ID($mul), ID($div), ID($mod), ID($divfloor), ID($modfloor), ID($concat))) {
return true;
}
@@ -130,7 +130,7 @@ bool mergeable(RTLIL::Cell *a, RTLIL::Cell *b)
RTLIL::IdString decode_port_semantics(RTLIL::Cell *cell, RTLIL::IdString port_name)
{
- if (cell->type.in(ID($lt), ID($le), ID($ge), ID($gt), ID($div), ID($mod), ID($concat), SHIFT_OPS) && port_name == ID::B)
+ if (cell->type.in(ID($lt), ID($le), ID($ge), ID($gt), ID($div), ID($mod), ID($divfloor), ID($modfloor), ID($concat), SHIFT_OPS) && port_name == ID::B)
return port_name;
return "";
@@ -473,7 +473,7 @@ dict<RTLIL::SigSpec, OpMuxConn> find_valid_op_mux_conns(RTLIL::Module *module, d
struct OptSharePass : public Pass {
OptSharePass() : Pass("opt_share", "merge mutually exclusive cells of the same type that share an input signal") {}
- void help() YS_OVERRIDE
+ void help() override
{
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
log("\n");
@@ -488,7 +488,7 @@ struct OptSharePass : public Pass {
log("multiplexing its output to multiplexing the non-shared input signals.\n");
log("\n");
}
- void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
+ void execute(std::vector<std::string> args, RTLIL::Design *design) override
{
log_header(design, "Executing OPT_SHARE pass.\n");
diff --git a/passes/opt/pmux2shiftx.cc b/passes/opt/pmux2shiftx.cc
index 11b80b6b3..9f226e12d 100644
--- a/passes/opt/pmux2shiftx.cc
+++ b/passes/opt/pmux2shiftx.cc
@@ -63,11 +63,13 @@ struct OnehotDatabase
vector<SigSpec> inputs;
SigSpec output;
- if (cell->type.in(ID($adff), ID($dff), ID($dffe), ID($dlatch), ID($ff)))
+ if (cell->type.in(ID($adff), ID($adffe), ID($dff), ID($dffe), ID($sdff), ID($sdffe), ID($sdffce), ID($dlatch), ID($adlatch), ID($ff)))
{
output = cell->getPort(ID::Q);
- if (cell->type == ID($adff))
+ if (cell->type.in(ID($adff), ID($adffe), ID($adlatch)))
inputs.push_back(cell->getParam(ID::ARST_VALUE));
+ if (cell->type.in(ID($sdff), ID($sdffe), ID($sdffce)))
+ inputs.push_back(cell->getParam(ID::SRST_VALUE));
inputs.push_back(cell->getPort(ID::D));
}
@@ -198,7 +200,7 @@ struct OnehotDatabase
struct Pmux2ShiftxPass : public Pass {
Pmux2ShiftxPass() : Pass("pmux2shiftx", "transform $pmux cells to $shiftx cells") { }
- void help() YS_OVERRIDE
+ void help() override
{
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
log("\n");
@@ -225,7 +227,7 @@ struct Pmux2ShiftxPass : public Pass {
log(" disable $sub inference for \"range decoders\"\n");
log("\n");
}
- void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
+ void execute(std::vector<std::string> args, RTLIL::Design *design) override
{
int min_density = 50;
int min_choices = 3;
@@ -737,7 +739,7 @@ struct Pmux2ShiftxPass : public Pass {
struct OnehotPass : public Pass {
OnehotPass() : Pass("onehot", "optimize $eq cells for onehot signals") { }
- void help() YS_OVERRIDE
+ void help() override
{
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
log("\n");
@@ -749,7 +751,7 @@ struct OnehotPass : public Pass {
log(" verbose output\n");
log("\n");
}
- void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
+ void execute(std::vector<std::string> args, RTLIL::Design *design) override
{
bool verbose = false;
bool verbose_onehot = false;
diff --git a/passes/opt/rmports.cc b/passes/opt/rmports.cc
index 32363dd68..99a2a61c8 100644
--- a/passes/opt/rmports.cc
+++ b/passes/opt/rmports.cc
@@ -28,7 +28,7 @@ PRIVATE_NAMESPACE_BEGIN
struct RmportsPassPass : public Pass {
RmportsPassPass() : Pass("rmports", "remove module ports with no connections") { }
- void help() YS_OVERRIDE
+ void help() override
{
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
log("\n");
@@ -39,7 +39,7 @@ struct RmportsPassPass : public Pass {
log("\n");
}
- void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
+ void execute(std::vector<std::string> args, RTLIL::Design *design) override
{
log_header(design, "Executing RMPORTS pass (remove ports with no connections).\n");
diff --git a/passes/opt/share.cc b/passes/opt/share.cc
index 2839507b0..f7848e01d 100644
--- a/passes/opt/share.cc
+++ b/passes/opt/share.cc
@@ -376,7 +376,7 @@ struct ShareWorker
continue;
}
- if (cell->type.in(ID($mul), ID($div), ID($mod))) {
+ if (cell->type.in(ID($mul), ID($div), ID($mod), ID($divfloor), ID($modfloor))) {
if (config.opt_aggressive || cell->parameters.at(ID::Y_WIDTH).as_int() >= 4)
shareable_cells.insert(cell);
continue;
@@ -1133,6 +1133,8 @@ struct ShareWorker
cone_ct.cell_types.erase(ID($mul));
cone_ct.cell_types.erase(ID($mod));
cone_ct.cell_types.erase(ID($div));
+ cone_ct.cell_types.erase(ID($modfloor));
+ cone_ct.cell_types.erase(ID($divfloor));
cone_ct.cell_types.erase(ID($pow));
cone_ct.cell_types.erase(ID($shl));
cone_ct.cell_types.erase(ID($shr));
@@ -1442,7 +1444,7 @@ struct ShareWorker
struct SharePass : public Pass {
SharePass() : Pass("share", "perform sat-based resource sharing") { }
- void help() YS_OVERRIDE
+ void help() override
{
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
log("\n");
@@ -1474,7 +1476,7 @@ struct SharePass : public Pass {
log(" Only perform the first N merges, then stop. This is useful for debugging.\n");
log("\n");
}
- void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
+ void execute(std::vector<std::string> args, RTLIL::Design *design) override
{
ShareWorkerConfig config;
@@ -1512,6 +1514,8 @@ struct SharePass : public Pass {
config.generic_bin_ops.insert(ID($sub));
config.generic_bin_ops.insert(ID($div));
config.generic_bin_ops.insert(ID($mod));
+ config.generic_bin_ops.insert(ID($divfloor));
+ config.generic_bin_ops.insert(ID($modfloor));
// config.generic_bin_ops.insert(ID($pow));
config.generic_uni_ops.insert(ID($logic_not));
diff --git a/passes/opt/wreduce.cc b/passes/opt/wreduce.cc
index 195400bf0..78e2bcbea 100644
--- a/passes/opt/wreduce.cc
+++ b/passes/opt/wreduce.cc
@@ -37,9 +37,10 @@ struct WreduceConfig
ID($and), ID($or), ID($xor), ID($xnor),
ID($shl), ID($shr), ID($sshl), ID($sshr), ID($shift), ID($shiftx),
ID($lt), ID($le), ID($eq), ID($ne), ID($eqx), ID($nex), ID($ge), ID($gt),
- ID($add), ID($sub), ID($mul), // ID($div), ID($mod), ID($pow),
+ ID($add), ID($sub), ID($mul), // ID($div), ID($mod), ID($divfloor), ID($modfloor), ID($pow),
ID($mux), ID($pmux),
- ID($dff), ID($adff)
+ ID($dff), ID($dffe), ID($adff), ID($adffe), ID($sdff), ID($sdffe), ID($sdffce),
+ ID($dlatch), ID($adlatch),
});
}
};
@@ -143,8 +144,8 @@ struct WreduceWorker
SigSpec sig_d = mi.sigmap(cell->getPort(ID::D));
SigSpec sig_q = mi.sigmap(cell->getPort(ID::Q));
- bool is_adff = (cell->type == ID($adff));
- Const initval, arst_value;
+ bool has_reset = false;
+ Const initval, rst_value;
int width_before = GetSize(sig_q);
@@ -152,7 +153,11 @@ struct WreduceWorker
return;
if (cell->parameters.count(ID::ARST_VALUE)) {
- arst_value = cell->parameters[ID::ARST_VALUE];
+ rst_value = cell->parameters[ID::ARST_VALUE];
+ has_reset = true;
+ } else if (cell->parameters.count(ID::SRST_VALUE)) {
+ rst_value = cell->parameters[ID::SRST_VALUE];
+ has_reset = true;
}
bool zero_ext = sig_d[GetSize(sig_d)-1] == State::S0;
@@ -169,7 +174,7 @@ struct WreduceWorker
for (int i = GetSize(sig_q)-1; i >= 0; i--)
{
if (zero_ext && sig_d[i] == State::S0 && (initval[i] == State::S0 || initval[i] == State::Sx) &&
- (!is_adff || i >= GetSize(arst_value) || arst_value[i] == State::S0 || arst_value[i] == State::Sx)) {
+ (!has_reset || i >= GetSize(rst_value) || rst_value[i] == State::S0 || rst_value[i] == State::Sx)) {
module->connect(sig_q[i], State::S0);
remove_init_bits.insert(sig_q[i]);
sig_d.remove(i);
@@ -178,7 +183,7 @@ struct WreduceWorker
}
if (sign_ext && i > 0 && sig_d[i] == sig_d[i-1] && initval[i] == initval[i-1] &&
- (!is_adff || i >= GetSize(arst_value) || arst_value[i] == arst_value[i-1])) {
+ (!has_reset || i >= GetSize(rst_value) || rst_value[i] == rst_value[i-1])) {
module->connect(sig_q[i], sig_q[i-1]);
remove_init_bits.insert(sig_q[i]);
sig_d.remove(i);
@@ -221,8 +226,11 @@ struct WreduceWorker
// Narrow ARST_VALUE parameter to new size.
if (cell->parameters.count(ID::ARST_VALUE)) {
- arst_value.bits.resize(GetSize(sig_q));
- cell->setParam(ID::ARST_VALUE, arst_value);
+ rst_value.bits.resize(GetSize(sig_q));
+ cell->setParam(ID::ARST_VALUE, rst_value);
+ } else if (cell->parameters.count(ID::SRST_VALUE)) {
+ rst_value.bits.resize(GetSize(sig_q));
+ cell->setParam(ID::SRST_VALUE, rst_value);
}
cell->setPort(ID::D, sig_d);
@@ -272,7 +280,7 @@ struct WreduceWorker
if (cell->type.in(ID($mux), ID($pmux)))
return run_cell_mux(cell);
- if (cell->type.in(ID($dff), ID($adff)))
+ if (cell->type.in(ID($dff), ID($dffe), ID($adff), ID($adffe), ID($sdff), ID($sdffe), ID($sdffce), ID($dlatch), ID($adlatch)))
return run_cell_dff(cell);
SigSpec sig = mi.sigmap(cell->getPort(ID::Y));
@@ -482,7 +490,7 @@ struct WreduceWorker
struct WreducePass : public Pass {
WreducePass() : Pass("wreduce", "reduce the word size of operations if possible") { }
- void help() YS_OVERRIDE
+ void help() override
{
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
log("\n");
@@ -505,7 +513,7 @@ struct WreducePass : public Pass {
log(" Do not optimize explicit don't-care values.\n");
log("\n");
}
- void execute(std::vector<std::string> args, Design *design) YS_OVERRIDE
+ void execute(std::vector<std::string> args, Design *design) override
{
WreduceConfig config;
bool opt_memx = false;
@@ -545,7 +553,7 @@ struct WreducePass : public Pass {
}
}
- if (c->type.in(ID($div), ID($mod), ID($pow)))
+ if (c->type.in(ID($div), ID($mod), ID($divfloor), ID($modfloor), ID($pow)))
{
SigSpec A = c->getPort(ID::A);
int original_a_width = GetSize(A);
diff --git a/passes/pmgen/ice40_dsp.cc b/passes/pmgen/ice40_dsp.cc
index f16cc4a0b..fff04074b 100644
--- a/passes/pmgen/ice40_dsp.cc
+++ b/passes/pmgen/ice40_dsp.cc
@@ -275,7 +275,7 @@ void create_ice40_dsp(ice40_dsp_pm &pm)
struct Ice40DspPass : public Pass {
Ice40DspPass() : Pass("ice40_dsp", "iCE40: map multipliers") { }
- void help() YS_OVERRIDE
+ void help() override
{
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
log("\n");
@@ -294,7 +294,7 @@ struct Ice40DspPass : public Pass {
log("the accumulator to an arbitrary value can be inferred to use the {C,D} input.\n");
log("\n");
}
- void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
+ void execute(std::vector<std::string> args, RTLIL::Design *design) override
{
log_header(design, "Executing ICE40_DSP pass (map multipliers).\n");
diff --git a/passes/pmgen/ice40_wrapcarry.cc b/passes/pmgen/ice40_wrapcarry.cc
index 97d2008c2..e234906ad 100644
--- a/passes/pmgen/ice40_wrapcarry.cc
+++ b/passes/pmgen/ice40_wrapcarry.cc
@@ -72,7 +72,7 @@ void create_ice40_wrapcarry(ice40_wrapcarry_pm &pm)
struct Ice40WrapCarryPass : public Pass {
Ice40WrapCarryPass() : Pass("ice40_wrapcarry", "iCE40: wrap carries") { }
- void help() YS_OVERRIDE
+ void help() override
{
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
log("\n");
@@ -91,7 +91,7 @@ struct Ice40WrapCarryPass : public Pass {
log(" including restoring their attributes.\n");
log("\n");
}
- void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
+ void execute(std::vector<std::string> args, RTLIL::Design *design) override
{
bool unwrap = false;
diff --git a/passes/pmgen/peepopt.cc b/passes/pmgen/peepopt.cc
index 4379ce1e6..c16b4486d 100644
--- a/passes/pmgen/peepopt.cc
+++ b/passes/pmgen/peepopt.cc
@@ -32,7 +32,7 @@ pool<SigBit> rminitbits;
struct PeepoptPass : public Pass {
PeepoptPass() : Pass("peepopt", "collection of peephole optimizers") { }
- void help() YS_OVERRIDE
+ void help() override
{
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
log("\n");
@@ -41,7 +41,7 @@ struct PeepoptPass : public Pass {
log("This pass applies a collection of peephole optimizers to the current design.\n");
log("\n");
}
- void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
+ void execute(std::vector<std::string> args, RTLIL::Design *design) override
{
std::string genmode;
diff --git a/passes/pmgen/pmgen.py b/passes/pmgen/pmgen.py
index df0ffaff2..592a26fa6 100644
--- a/passes/pmgen/pmgen.py
+++ b/passes/pmgen/pmgen.py
@@ -589,7 +589,7 @@ with open(outfile, "w") as f:
if block["type"] in ("match", "code"):
print(" // {}".format(block["src"]), file=f)
- print(" void block_{}(int recursion YS_ATTRIBUTE(unused)) {{".format(index), file=f)
+ print(" void block_{}(int recursion YS_MAYBE_UNUSED) {{".format(index), file=f)
current_pattern, current_subpattern = block["pattern"]
if block["type"] == "final":
@@ -636,17 +636,17 @@ with open(outfile, "w") as f:
for s in sorted(const_st):
t = state_types[current_pattern][s]
if t.endswith("*"):
- print(" {} const &{} YS_ATTRIBUTE(unused) = st_{}.{};".format(t, s, current_pattern, s), file=f)
+ print(" {} const &{} YS_MAYBE_UNUSED = st_{}.{};".format(t, s, current_pattern, s), file=f)
else:
- print(" const {} &{} YS_ATTRIBUTE(unused) = st_{}.{};".format(t, s, current_pattern, s), file=f)
+ print(" const {} &{} YS_MAYBE_UNUSED = st_{}.{};".format(t, s, current_pattern, s), file=f)
for s in sorted(nonconst_st):
t = state_types[current_pattern][s]
- print(" {} &{} YS_ATTRIBUTE(unused) = st_{}.{};".format(t, s, current_pattern, s), file=f)
+ print(" {} &{} YS_MAYBE_UNUSED = st_{}.{};".format(t, s, current_pattern, s), file=f)
for u in sorted(udata_types[current_pattern].keys()):
t = udata_types[current_pattern][u]
- print(" {} &{} YS_ATTRIBUTE(unused) = ud_{}.{};".format(t, u, current_pattern, u), file=f)
+ print(" {} &{} YS_MAYBE_UNUSED = ud_{}.{};".format(t, u, current_pattern, u), file=f)
if len(restore_st):
print("", file=f)
@@ -676,7 +676,7 @@ with open(outfile, "w") as f:
print("", file=f)
print("rollback_label:", file=f)
- print(" YS_ATTRIBUTE(unused);", file=f)
+ print(" YS_MAYBE_UNUSED;", file=f)
if len(block["fcode"]):
print("#define accept do { accept_cnt++; on_accept(); } while(0)", file=f)
@@ -684,7 +684,7 @@ with open(outfile, "w") as f:
for line in block["fcode"]:
print(" " + line, file=f)
print("finish_label:", file=f)
- print(" YS_ATTRIBUTE(unused);", file=f)
+ print(" YS_MAYBE_UNUSED;", file=f)
print("#undef accept", file=f)
print("#undef finish", file=f)
@@ -733,13 +733,13 @@ with open(outfile, "w") as f:
valueidx = 1
for item in block["setup"]:
if item[0] == "slice":
- print(" const int &{} YS_ATTRIBUTE(unused) = std::get<{}>(cells[_pmg_idx]);".format(item[1], valueidx), file=f)
+ print(" const int &{} YS_MAYBE_UNUSED = std::get<{}>(cells[_pmg_idx]);".format(item[1], valueidx), file=f)
valueidx += 1
if item[0] == "choice":
- print(" const {} &{} YS_ATTRIBUTE(unused) = std::get<{}>(cells[_pmg_idx]);".format(item[1], item[2], valueidx), file=f)
+ print(" const {} &{} YS_MAYBE_UNUSED = std::get<{}>(cells[_pmg_idx]);".format(item[1], item[2], valueidx), file=f)
valueidx += 1
if item[0] == "define":
- print(" const {} &{} YS_ATTRIBUTE(unused) = std::get<{}>(cells[_pmg_idx]);".format(item[1], item[2], valueidx), file=f)
+ print(" const {} &{} YS_MAYBE_UNUSED = std::get<{}>(cells[_pmg_idx]);".format(item[1], item[2], valueidx), file=f)
valueidx += 1
print(" if (blacklist_cells.count({})) continue;".format(block["cell"]), file=f)
for expr in block["filter"]:
diff --git a/passes/pmgen/test_pmgen.cc b/passes/pmgen/test_pmgen.cc
index 9cfad03ef..7b2938ddf 100644
--- a/passes/pmgen/test_pmgen.cc
+++ b/passes/pmgen/test_pmgen.cc
@@ -118,7 +118,7 @@ void opt_eqpmux(test_pmgen_pm &pm)
struct TestPmgenPass : public Pass {
TestPmgenPass() : Pass("test_pmgen", "test pass for pmgen") { }
- void help() YS_OVERRIDE
+ void help() override
{
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
log("\n");
@@ -239,7 +239,7 @@ struct TestPmgenPass : public Pass {
log_cmd_error("Unknown pattern: %s\n", pattern.c_str());
}
- void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
+ void execute(std::vector<std::string> args, RTLIL::Design *design) override
{
if (GetSize(args) > 1)
{
diff --git a/passes/pmgen/xilinx_dsp.cc b/passes/pmgen/xilinx_dsp.cc
index f1f4b4206..d05157270 100644
--- a/passes/pmgen/xilinx_dsp.cc
+++ b/passes/pmgen/xilinx_dsp.cc
@@ -744,7 +744,7 @@ void xilinx_dsp_packC(xilinx_dsp_CREG_pm &pm)
struct XilinxDspPass : public Pass {
XilinxDspPass() : Pass("xilinx_dsp", "Xilinx: pack resources into DSPs") { }
- void help() YS_OVERRIDE
+ void help() override
{
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
log("\n");
@@ -785,7 +785,7 @@ struct XilinxDspPass : public Pass {
log(" default: xc7\n");
log("\n");
}
- void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
+ void execute(std::vector<std::string> args, RTLIL::Design *design) override
{
log_header(design, "Executing XILINX_DSP pass (pack resources into DSPs).\n");
diff --git a/passes/pmgen/xilinx_srl.cc b/passes/pmgen/xilinx_srl.cc
index b99653fb3..1410850c7 100644
--- a/passes/pmgen/xilinx_srl.cc
+++ b/passes/pmgen/xilinx_srl.cc
@@ -188,7 +188,7 @@ void run_variable(xilinx_srl_pm &pm)
struct XilinxSrlPass : public Pass {
XilinxSrlPass() : Pass("xilinx_srl", "Xilinx shift register extraction") { }
- void help() YS_OVERRIDE
+ void help() override
{
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
log("\n");
@@ -212,7 +212,7 @@ struct XilinxSrlPass : public Pass {
log("\n");
}
- void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
+ void execute(std::vector<std::string> args, RTLIL::Design *design) override
{
log_header(design, "Executing XILINX_SRL pass (Xilinx shift register extraction).\n");
diff --git a/passes/proc/proc.cc b/passes/proc/proc.cc
index a5b4a3112..f20a167b4 100644
--- a/passes/proc/proc.cc
+++ b/passes/proc/proc.cc
@@ -27,7 +27,7 @@ PRIVATE_NAMESPACE_BEGIN
struct ProcPass : public Pass {
ProcPass() : Pass("proc", "translate processes to netlists") { }
- void help() YS_OVERRIDE
+ void help() override
{
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
log("\n");
@@ -58,7 +58,7 @@ struct ProcPass : public Pass {
log(" executed in -ifx mode.\n");
log("\n");
}
- void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
+ void execute(std::vector<std::string> args, RTLIL::Design *design) override
{
std::string global_arst;
bool ifxmode = false;
diff --git a/passes/proc/proc_arst.cc b/passes/proc/proc_arst.cc
index e400fcb72..16db461b2 100644
--- a/passes/proc/proc_arst.cc
+++ b/passes/proc/proc_arst.cc
@@ -203,7 +203,7 @@ restart_proc_arst:
struct ProcArstPass : public Pass {
ProcArstPass() : Pass("proc_arst", "detect asynchronous resets") { }
- void help() YS_OVERRIDE
+ void help() override
{
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
log("\n");
@@ -221,7 +221,7 @@ struct ProcArstPass : public Pass {
log(" in the 'init' attribute on the net.\n");
log("\n");
}
- void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
+ void execute(std::vector<std::string> args, RTLIL::Design *design) override
{
std::string global_arst;
bool global_arst_neg = false;
diff --git a/passes/proc/proc_clean.cc b/passes/proc/proc_clean.cc
index 114c6ab03..5e78b7316 100644
--- a/passes/proc/proc_clean.cc
+++ b/passes/proc/proc_clean.cc
@@ -166,7 +166,7 @@ void proc_clean(RTLIL::Module *mod, RTLIL::Process *proc, int &total_count, bool
struct ProcCleanPass : public Pass {
ProcCleanPass() : Pass("proc_clean", "remove empty parts of processes") { }
- void help() YS_OVERRIDE
+ void help() override
{
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
log("\n");
@@ -179,7 +179,7 @@ struct ProcCleanPass : public Pass {
log("if it contains only empty structures.\n");
log("\n");
}
- void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
+ void execute(std::vector<std::string> args, RTLIL::Design *design) override
{
int total_count = 0;
bool quiet = false;
diff --git a/passes/proc/proc_dff.cc b/passes/proc/proc_dff.cc
index 59cc5bd65..e320a72a6 100644
--- a/passes/proc/proc_dff.cc
+++ b/passes/proc/proc_dff.cc
@@ -370,7 +370,7 @@ void proc_dff(RTLIL::Module *mod, RTLIL::Process *proc, ConstEval &ce)
struct ProcDffPass : public Pass {
ProcDffPass() : Pass("proc_dff", "extract flip-flops from processes") { }
- void help() YS_OVERRIDE
+ void help() override
{
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
log("\n");
@@ -380,7 +380,7 @@ struct ProcDffPass : public Pass {
log("d-type flip-flop cells.\n");
log("\n");
}
- void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
+ void execute(std::vector<std::string> args, RTLIL::Design *design) override
{
log_header(design, "Executing PROC_DFF pass (convert process syncs to FFs).\n");
diff --git a/passes/proc/proc_dlatch.cc b/passes/proc/proc_dlatch.cc
index c9da1d1e3..e7c8a80dd 100644
--- a/passes/proc/proc_dlatch.cc
+++ b/passes/proc/proc_dlatch.cc
@@ -434,7 +434,7 @@ void proc_dlatch(proc_dlatch_db_t &db, RTLIL::Process *proc)
struct ProcDlatchPass : public Pass {
ProcDlatchPass() : Pass("proc_dlatch", "extract latches from processes") { }
- void help() YS_OVERRIDE
+ void help() override
{
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
log("\n");
@@ -444,7 +444,7 @@ struct ProcDlatchPass : public Pass {
log("d-type latches.\n");
log("\n");
}
- void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
+ void execute(std::vector<std::string> args, RTLIL::Design *design) override
{
log_header(design, "Executing PROC_DLATCH pass (convert process syncs to latches).\n");
diff --git a/passes/proc/proc_init.cc b/passes/proc/proc_init.cc
index dc00019aa..eb323038d 100644
--- a/passes/proc/proc_init.cc
+++ b/passes/proc/proc_init.cc
@@ -86,7 +86,7 @@ void proc_init(RTLIL::Module *mod, SigMap &sigmap, RTLIL::Process *proc)
struct ProcInitPass : public Pass {
ProcInitPass() : Pass("proc_init", "convert initial block to init attributes") { }
- void help() YS_OVERRIDE
+ void help() override
{
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
log("\n");
@@ -97,7 +97,7 @@ struct ProcInitPass : public Pass {
log("respective wire.\n");
log("\n");
}
- void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
+ void execute(std::vector<std::string> args, RTLIL::Design *design) override
{
log_header(design, "Executing PROC_INIT pass (extract init attributes).\n");
diff --git a/passes/proc/proc_mux.cc b/passes/proc/proc_mux.cc
index 867ba1698..d20f34534 100644
--- a/passes/proc/proc_mux.cc
+++ b/passes/proc/proc_mux.cc
@@ -438,7 +438,7 @@ void proc_mux(RTLIL::Module *mod, RTLIL::Process *proc, bool ifxmode)
struct ProcMuxPass : public Pass {
ProcMuxPass() : Pass("proc_mux", "convert decision trees to multiplexers") { }
- void help() YS_OVERRIDE
+ void help() override
{
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
log("\n");
@@ -452,7 +452,7 @@ struct ProcMuxPass : public Pass {
log(" 'case' expressions and 'if' conditions.\n");
log("\n");
}
- void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
+ void execute(std::vector<std::string> args, RTLIL::Design *design) override
{
bool ifxmode = false;
log_header(design, "Executing PROC_MUX pass (convert decision trees to multiplexers).\n");
diff --git a/passes/proc/proc_prune.cc b/passes/proc/proc_prune.cc
index 8d11447f6..bd122b91f 100644
--- a/passes/proc/proc_prune.cc
+++ b/passes/proc/proc_prune.cc
@@ -125,7 +125,7 @@ struct PruneWorker
struct ProcPrunePass : public Pass {
ProcPrunePass() : Pass("proc_prune", "remove redundant assignments") { }
- void help() YS_OVERRIDE
+ void help() override
{
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
log("\n");
@@ -135,7 +135,7 @@ struct ProcPrunePass : public Pass {
log("a later assignment to the same signal and removes them.\n");
log("\n");
}
- void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
+ void execute(std::vector<std::string> args, RTLIL::Design *design) override
{
int total_removed_count = 0, total_promoted_count = 0;
log_header(design, "Executing PROC_PRUNE pass (remove redundant assignments in processes).\n");
diff --git a/passes/proc/proc_rmdead.cc b/passes/proc/proc_rmdead.cc
index 6afaf25d1..ee91637ca 100644
--- a/passes/proc/proc_rmdead.cc
+++ b/passes/proc/proc_rmdead.cc
@@ -70,7 +70,7 @@ void proc_rmdead(RTLIL::SwitchRule *sw, int &counter, int &full_case_counter)
struct ProcRmdeadPass : public Pass {
ProcRmdeadPass() : Pass("proc_rmdead", "eliminate dead trees in decision trees") { }
- void help() YS_OVERRIDE
+ void help() override
{
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
log("\n");
@@ -79,7 +79,7 @@ struct ProcRmdeadPass : public Pass {
log("This pass identifies unreachable branches in decision trees and removes them.\n");
log("\n");
}
- void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
+ void execute(std::vector<std::string> args, RTLIL::Design *design) override
{
log_header(design, "Executing PROC_RMDEAD pass (remove dead branches from decision trees).\n");
diff --git a/passes/sat/assertpmux.cc b/passes/sat/assertpmux.cc
index 5bf2296ab..e9a10465e 100644
--- a/passes/sat/assertpmux.cc
+++ b/passes/sat/assertpmux.cc
@@ -181,7 +181,7 @@ struct AssertpmuxWorker
struct AssertpmuxPass : public Pass {
AssertpmuxPass() : Pass("assertpmux", "adds asserts for parallel muxes") { }
- void help() YS_OVERRIDE
+ void help() override
{
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
log("\n");
@@ -199,7 +199,7 @@ struct AssertpmuxPass : public Pass {
log(" additional constraint and check the $pmux condition always.\n");
log("\n");
}
- void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
+ void execute(std::vector<std::string> args, RTLIL::Design *design) override
{
bool flag_noinit = false;
bool flag_always = false;
diff --git a/passes/sat/async2sync.cc b/passes/sat/async2sync.cc
index e344e2b5b..6fc480925 100644
--- a/passes/sat/async2sync.cc
+++ b/passes/sat/async2sync.cc
@@ -25,7 +25,7 @@ PRIVATE_NAMESPACE_BEGIN
struct Async2syncPass : public Pass {
Async2syncPass() : Pass("async2sync", "convert async FF inputs to sync circuits") { }
- void help() YS_OVERRIDE
+ void help() override
{
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
log("\n");
@@ -42,7 +42,7 @@ struct Async2syncPass : public Pass {
log("Currently only $adff, $dffsr, and $dlatch cells are supported by this pass.\n");
log("\n");
}
- void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
+ void execute(std::vector<std::string> args, RTLIL::Design *design) override
{
// bool flag_noinit = false;
diff --git a/passes/sat/clk2fflogic.cc b/passes/sat/clk2fflogic.cc
index 1e155e52c..e5c5d0486 100644
--- a/passes/sat/clk2fflogic.cc
+++ b/passes/sat/clk2fflogic.cc
@@ -25,7 +25,7 @@ PRIVATE_NAMESPACE_BEGIN
struct Clk2fflogicPass : public Pass {
Clk2fflogicPass() : Pass("clk2fflogic", "convert clocked FFs to generic $ff cells") { }
- void help() YS_OVERRIDE
+ void help() override
{
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
log("\n");
@@ -36,7 +36,7 @@ struct Clk2fflogicPass : public Pass {
log("multiple clocks.\n");
log("\n");
}
- void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
+ void execute(std::vector<std::string> args, RTLIL::Design *design) override
{
// bool flag_noinit = false;
diff --git a/passes/sat/cutpoint.cc b/passes/sat/cutpoint.cc
index 26cc69211..6fc267d51 100644
--- a/passes/sat/cutpoint.cc
+++ b/passes/sat/cutpoint.cc
@@ -25,7 +25,7 @@ PRIVATE_NAMESPACE_BEGIN
struct CutpointPass : public Pass {
CutpointPass() : Pass("cutpoint", "adds formal cut points to the design") { }
- void help() YS_OVERRIDE
+ void help() override
{
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
log("\n");
@@ -38,7 +38,7 @@ struct CutpointPass : public Pass {
log(" $anyseq cell and drive the cutpoint net from that\n");
log("\n");
}
- void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
+ void execute(std::vector<std::string> args, RTLIL::Design *design) override
{
bool flag_undef = false;
@@ -126,15 +126,16 @@ struct CutpointPass : public Pass {
}
vector<Wire*> rewrite_wires;
- for (auto wire : module->wires()) {
- if (!wire->port_input)
- continue;
- int bit_count = 0;
- for (auto &bit : sigmap(wire))
- if (cutpoint_bits.count(bit))
- bit_count++;
- if (bit_count)
- rewrite_wires.push_back(wire);
+ for (auto id : module->ports) {
+ RTLIL::Wire *wire = module->wire(id);
+ if (wire->port_input) {
+ int bit_count = 0;
+ for (auto &bit : sigmap(wire))
+ if (cutpoint_bits.count(bit))
+ bit_count++;
+ if (bit_count)
+ rewrite_wires.push_back(wire);
+ }
}
for (auto wire : rewrite_wires) {
diff --git a/passes/sat/eval.cc b/passes/sat/eval.cc
index f910ea80d..085e7c5b8 100644
--- a/passes/sat/eval.cc
+++ b/passes/sat/eval.cc
@@ -359,7 +359,7 @@ struct VlogHammerReporter
struct EvalPass : public Pass {
EvalPass() : Pass("eval", "evaluate the circuit given an input") { }
- void help() YS_OVERRIDE
+ void help() override
{
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
log("\n");
@@ -382,7 +382,7 @@ struct EvalPass : public Pass {
log(" then all output ports of the current module are used.\n");
log("\n");
}
- void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
+ void execute(std::vector<std::string> args, RTLIL::Design *design) override
{
std::vector<std::pair<std::string, std::string>> sets;
std::vector<std::string> shows, tables;
diff --git a/passes/sat/expose.cc b/passes/sat/expose.cc
index 80ab82cd5..2c65821cf 100644
--- a/passes/sat/expose.cc
+++ b/passes/sat/expose.cc
@@ -217,7 +217,7 @@ RTLIL::Wire *add_new_wire(RTLIL::Module *module, RTLIL::IdString name, int width
struct ExposePass : public Pass {
ExposePass() : Pass("expose", "convert internal signals to module ports") { }
- void help() YS_OVERRIDE
+ void help() override
{
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
log("\n");
@@ -254,7 +254,7 @@ struct ExposePass : public Pass {
log(" designator for the exposed signal.\n");
log("\n");
}
- void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
+ void execute(std::vector<std::string> args, RTLIL::Design *design) override
{
bool flag_shared = false;
bool flag_evert = false;
@@ -281,11 +281,15 @@ struct ExposePass : public Pass {
flag_dff = true;
continue;
}
- if (args[argidx] == "-cut" && !flag_input) {
+ if (args[argidx] == "-cut") {
+ if (flag_input)
+ log_cmd_error("Options -cut and -input are mutually exclusive.\n");
flag_cut = true;
continue;
}
- if (args[argidx] == "-input" && !flag_cut) {
+ if (args[argidx] == "-input") {
+ if (flag_cut)
+ log_cmd_error("Options -cut and -input are mutually exclusive.\n");
flag_input = true;
continue;
}
@@ -445,6 +449,8 @@ struct ExposePass : public Pass {
SigMap out_to_in_map;
+ std::map<RTLIL::Wire*, RTLIL::IdString> wire_map;
+
for (auto w : module->wires())
{
if (flag_shared) {
@@ -462,8 +468,7 @@ struct ExposePass : public Pass {
if (!w->port_input) {
w->port_input = true;
log("New module port: %s/%s\n", RTLIL::id2cstr(module->name), RTLIL::id2cstr(w->name));
- RTLIL::Wire *in_wire = module->addWire(NEW_ID, GetSize(w));
- out_to_in_map.add(w, in_wire);
+ wire_map[w] = NEW_ID;
}
}
else
@@ -474,15 +479,19 @@ struct ExposePass : public Pass {
}
if (flag_cut) {
- RTLIL::Wire *in_wire = add_new_wire(module, w->name.str() + sep + "i", w->width);
- in_wire->port_input = true;
- out_to_in_map.add(sigmap(w), in_wire);
+ wire_map[w] = w->name.str() + sep + "i";
}
}
}
if (flag_input)
{
+ for (auto &wm : wire_map)
+ {
+ RTLIL::Wire *in_wire = module->addWire(wm.second, GetSize(wm.first));
+ out_to_in_map.add(wm.first, in_wire);
+ }
+
for (auto cell : module->cells()) {
if (!ct.cell_known(cell->type))
continue;
@@ -497,6 +506,13 @@ struct ExposePass : public Pass {
if (flag_cut)
{
+ for (auto &wm : wire_map)
+ {
+ RTLIL::Wire *in_wire = add_new_wire(module, wm.second, wm.first->width);
+ in_wire->port_input = true;
+ out_to_in_map.add(sigmap(wm.first), in_wire);
+ }
+
for (auto cell : module->cells()) {
if (!ct.cell_known(cell->type))
continue;
diff --git a/passes/sat/fmcombine.cc b/passes/sat/fmcombine.cc
index 5066485aa..cb49edac3 100644
--- a/passes/sat/fmcombine.cc
+++ b/passes/sat/fmcombine.cc
@@ -114,8 +114,7 @@ struct FmcombineWorker
Cell *gold = import_prim_cell(cell, "_gold");
Cell *gate = import_prim_cell(cell, "_gate");
if (opts.initeq) {
- if (cell->type.in(ID($ff), ID($dff), ID($dffe),
- ID($dffsr), ID($adff), ID($dlatch), ID($dlatchsr))) {
+ if (RTLIL::builtin_ff_cell_types().count(cell->type)) {
SigSpec gold_q = gold->getPort(ID::Q);
SigSpec gate_q = gate->getPort(ID::Q);
SigSpec en = module->Initstate(NEW_ID);
@@ -235,7 +234,7 @@ struct FmcombineWorker
struct FmcombinePass : public Pass {
FmcombinePass() : Pass("fmcombine", "combine two instances of a cell into one") { }
- void help() YS_OVERRIDE
+ void help() override
{
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
log("\n");
@@ -272,7 +271,7 @@ struct FmcombinePass : public Pass {
log("If none of -fwd, -bwd, and -nop is given, then -fwd is used as default.\n");
log("\n");
}
- void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
+ void execute(std::vector<std::string> args, RTLIL::Design *design) override
{
opts_t opts;
Module *module = nullptr;
diff --git a/passes/sat/fminit.cc b/passes/sat/fminit.cc
index 555a28dc6..c72e62548 100644
--- a/passes/sat/fminit.cc
+++ b/passes/sat/fminit.cc
@@ -25,7 +25,7 @@ PRIVATE_NAMESPACE_BEGIN
struct FminitPass : public Pass {
FminitPass() : Pass("fminit", "set init values/sequences for formal") { }
- void help() YS_OVERRIDE
+ void help() override
{
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
log("\n");
@@ -47,7 +47,7 @@ struct FminitPass : public Pass {
log(" Set clock for init sequences\n");
log("\n");
}
- void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
+ void execute(std::vector<std::string> args, RTLIL::Design *design) override
{
vector<pair<string, vector<string>>> initdata;
vector<pair<string, string>> setdata;
diff --git a/passes/sat/freduce.cc b/passes/sat/freduce.cc
index 5dfd7bd3f..762edfdfb 100644
--- a/passes/sat/freduce.cc
+++ b/passes/sat/freduce.cc
@@ -760,7 +760,7 @@ struct FreduceWorker
struct FreducePass : public Pass {
FreducePass() : Pass("freduce", "perform functional reduction") { }
- void help() YS_OVERRIDE
+ void help() override
{
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
log("\n");
@@ -791,7 +791,7 @@ struct FreducePass : public Pass {
log("circuit that is analyzed.\n");
log("\n");
}
- void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
+ void execute(std::vector<std::string> args, RTLIL::Design *design) override
{
reduce_counter = 0;
reduce_stop_at = 0;
diff --git a/passes/sat/miter.cc b/passes/sat/miter.cc
index aeece9b94..fe4a819f3 100644
--- a/passes/sat/miter.cc
+++ b/passes/sat/miter.cc
@@ -354,7 +354,7 @@ void create_miter_assert(struct Pass *that, std::vector<std::string> args, RTLIL
struct MiterPass : public Pass {
MiterPass() : Pass("miter", "automatically create a miter circuit") { }
- void help() YS_OVERRIDE
+ void help() override
{
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
log("\n");
@@ -398,7 +398,7 @@ struct MiterPass : public Pass {
log(" call 'flatten -wb; opt_expr -keepdc -undriven;;' on the miter circuit.\n");
log("\n");
}
- void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
+ void execute(std::vector<std::string> args, RTLIL::Design *design) override
{
if (args.size() > 1 && args[1] == "-equiv") {
create_miter_equiv(this, args, design);
diff --git a/passes/sat/mutate.cc b/passes/sat/mutate.cc
index af8ffca9e..15abee73e 100644
--- a/passes/sat/mutate.cc
+++ b/passes/sat/mutate.cc
@@ -726,7 +726,7 @@ void mutate_cnot(Design *design, const mutate_opts_t &opts, bool one)
struct MutatePass : public Pass {
MutatePass() : Pass("mutate", "generate or apply design mutations") { }
- void help() YS_OVERRIDE
+ void help() override
{
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
log("\n");
@@ -790,7 +790,7 @@ struct MutatePass : public Pass {
log(" Ignored. (They are generated by -list for documentation purposes.)\n");
log("\n");
}
- void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
+ void execute(std::vector<std::string> args, RTLIL::Design *design) override
{
mutate_opts_t opts;
string filename;
diff --git a/passes/sat/qbfsat.cc b/passes/sat/qbfsat.cc
index d99ca1b53..46f7f5070 100644
--- a/passes/sat/qbfsat.cc
+++ b/passes/sat/qbfsat.cc
@@ -1,4 +1,4 @@
-/*
+/* -*- c++ -*-
* yosys -- Yosys Open SYnthesis Suite
*
* Copyright (C) 2020 Alberto Gonzalez <boqwxp@airmail.cc>
@@ -18,216 +18,149 @@
*/
#include "kernel/yosys.h"
-#include "kernel/celltypes.h"
-#include "kernel/log.h"
-#include "kernel/rtlil.h"
-#include "kernel/register.h"
-#include <cstdio>
-#include <algorithm>
-
-#if defined(_WIN32)
-# define WIFEXITED(x) 1
-# define WIFSIGNALED(x) 0
-# define WIFSTOPPED(x) 0
-# define WEXITSTATUS(x) ((x) & 0xff)
-# define WTERMSIG(x) SIGTERM
-#else
-# include <sys/wait.h>
-#endif
+#include "kernel/consteval.h"
+#include "qbfsat.h"
USING_YOSYS_NAMESPACE
PRIVATE_NAMESPACE_BEGIN
-struct QbfSolutionType {
- std::vector<std::string> stdout_lines;
- dict<std::string, std::string> hole_to_value;
- bool sat;
- bool unknown; //true if neither 'sat' nor 'unsat'
- bool success; //true if exit code 0
-
- QbfSolutionType() : sat(false), unknown(true), success(false) {}
-};
-
-struct QbfSolveOptions {
- bool specialize, specialize_from_file, write_solution, nocleanup, dump_final_smt2, assume_outputs, assume_neg;
- bool sat, unsat, show_smtbmc;
- std::string specialize_soln_file;
- std::string write_soln_soln_file;
- std::string dump_final_smt2_file;
- size_t argidx;
- QbfSolveOptions() : specialize(false), specialize_from_file(false), write_solution(false),
- nocleanup(false), dump_final_smt2(false), assume_outputs(false), assume_neg(false),
- sat(false), unsat(false), show_smtbmc(false), argidx(0) {};
-};
-
-void recover_solution(QbfSolutionType &sol) {
- YS_REGEX_TYPE sat_regex = YS_REGEX_COMPILE("Status: PASSED");
- YS_REGEX_TYPE unsat_regex = YS_REGEX_COMPILE("Solver Error.*model is not available");
- YS_REGEX_TYPE hole_value_regex = YS_REGEX_COMPILE_WITH_SUBS("Value for anyconst in [a-zA-Z0-9_]* \\(([^:]*:[^\\)]*)\\): (.*)");
-#ifndef NDEBUG
- YS_REGEX_TYPE hole_loc_regex = YS_REGEX_COMPILE("[^:]*:[0-9]+.[0-9]+-[0-9]+.[0-9]+");
- YS_REGEX_TYPE hole_val_regex = YS_REGEX_COMPILE("[0-9]+");
-#endif
- YS_REGEX_MATCH_TYPE m;
- bool sat_regex_found = false;
- bool unsat_regex_found = false;
- dict<std::string, bool> hole_value_recovered;
- for (const std::string &x : sol.stdout_lines) {
- if(YS_REGEX_NS::regex_search(x, m, hole_value_regex)) {
- std::string loc = m[1].str();
- std::string val = m[2].str();
-#ifndef NDEBUG
- log_assert(YS_REGEX_NS::regex_search(loc, hole_loc_regex));
- log_assert(YS_REGEX_NS::regex_search(val, hole_val_regex));
-#endif
- sol.hole_to_value[loc] = val;
- }
- else if (YS_REGEX_NS::regex_search(x, sat_regex))
- sat_regex_found = true;
- else if (YS_REGEX_NS::regex_search(x, unsat_regex))
- unsat_regex_found = true;
- }
-#ifndef NDEBUG
- log_assert(!sol.unknown && sol.sat? sat_regex_found : true);
- log_assert(!sol.unknown && !sol.sat? unsat_regex_found : true);
-#endif
+static inline unsigned int difference(unsigned int a, unsigned int b) {
+ if (a < b)
+ return b - a;
+ else
+ return a - b;
}
-dict<std::string, std::string> get_hole_loc_name_map(RTLIL::Module *module, const QbfSolutionType &sol) {
- dict<std::string, std::string> hole_loc_to_name;
- for (auto cell : module->cells()) {
- std::string cell_src = cell->get_src_attribute();
- auto pos = sol.hole_to_value.find(cell_src);
- if (pos != sol.hole_to_value.end() && cell->type.in("$anyconst", "$anyseq")) {
- log_assert(hole_loc_to_name.find(pos->first) == hole_loc_to_name.end());
- hole_loc_to_name[pos->first] = cell->getPort(ID::Y).as_wire()->name.str();
+pool<std::string> validate_design_and_get_inputs(RTLIL::Module *module, bool assume_outputs) {
+ bool found_input = false;
+ bool found_hole = false;
+ bool found_1bit_output = false;
+ bool found_assert_assume = false;
+ pool<std::string> input_wires;
+ for (auto wire : module->wires()) {
+ if (wire->port_input) {
+ found_input = true;
+ input_wires.insert(wire->name.str());
}
+ if (wire->port_output && wire->width == 1)
+ found_1bit_output = true;
}
+ for (auto cell : module->cells()) {
+ if (cell->type == "$allconst")
+ found_input = true;
+ if (cell->type == "$anyconst")
+ found_hole = true;
+ if (cell->type.in("$assert", "$assume"))
+ found_assert_assume = true;
+ }
+ if (!found_input)
+ log_cmd_error("Can't perform QBF-SAT on a miter with no inputs!\n");
+ if (!found_hole)
+ log_cmd_error("Did not find any existentially-quantified variables. Use 'sat' instead.\n");
+ if (!found_1bit_output && !found_assert_assume)
+ log_cmd_error("Did not find any single-bit outputs or $assert/$assume cells. Is this a miter circuit?\n");
+ if (!found_assert_assume && !assume_outputs)
+ log_cmd_error("Did not find any $assert/$assume cells. Single-bit outputs were found, but `-assume-outputs` was not specified.\n");
- return hole_loc_to_name;
+ return input_wires;
}
-void write_solution(RTLIL::Module *module, const QbfSolutionType &sol, const std::string &file) {
- std::ofstream fout(file.c_str());
- if (!fout)
- log_cmd_error("could not open solution file for writing.\n");
+void specialize_from_file(RTLIL::Module *module, const std::string &file) {
+ YS_REGEX_TYPE hole_bit_assn_regex = YS_REGEX_COMPILE_WITH_SUBS("^(.+) ([0-9]+) ([^ ]+) \\[([0-9]+)] = ([01])$");
+ YS_REGEX_TYPE hole_assn_regex = YS_REGEX_COMPILE_WITH_SUBS("^(.+) ([0-9]+) ([^ ]+) = ([01])$"); //if no index specified
+ YS_REGEX_MATCH_TYPE bit_m, m;
+ dict<pool<std::string>, RTLIL::Cell*> anyconst_loc_to_cell;
+ dict<RTLIL::SigBit, RTLIL::State> hole_assignments;
- dict<std::string, std::string> hole_loc_to_name = get_hole_loc_name_map(module, sol);
- for(auto &x : sol.hole_to_value)
- fout << hole_loc_to_name[x.first] << "=" << x.second << std::endl;
-}
+ for (auto cell : module->cells())
+ if (cell->type == "$anyconst")
+ anyconst_loc_to_cell[cell->get_strpool_attribute(ID::src)] = cell;
-void specialize_from_file(RTLIL::Module *module, const std::string &file) {
- YS_REGEX_TYPE hole_assn_regex = YS_REGEX_COMPILE_WITH_SUBS("^(.*)=([01]+)$");
- YS_REGEX_MATCH_TYPE m;
- pool<RTLIL::Cell *> anyconsts_to_remove;
- dict<std::string, std::string> hole_name_to_value;
std::ifstream fin(file.c_str());
if (!fin)
log_cmd_error("could not read solution file.\n");
std::string buf;
while (std::getline(fin, buf)) {
- log_assert(YS_REGEX_NS::regex_search(buf, m, hole_assn_regex));
- std::string hole_name = m[1].str();
- std::string hole_value = m[2].str();
- hole_name_to_value[hole_name] = hole_value;
- }
+ bool bit_assn = true;
+ if (!YS_REGEX_NS::regex_search(buf, bit_m, hole_bit_assn_regex)) {
+ bit_assn = false;
+ if (!YS_REGEX_NS::regex_search(buf, m, hole_assn_regex))
+ log_cmd_error("solution file is not formatted correctly: \"%s\"\n", buf.c_str());
+ }
- for (auto cell : module->cells())
- if (cell->type == "$anyconst") {
- auto anyconst_port_y = cell->getPort(ID::Y).as_wire();
- if (anyconst_port_y == nullptr)
- continue;
- if (hole_name_to_value.find(anyconst_port_y->name.str()) != hole_name_to_value.end())
- anyconsts_to_remove.insert(cell);
+ std::string hole_loc = bit_assn? bit_m[1].str() : m[1].str();
+ unsigned int hole_bit = bit_assn? atoi(bit_m[2].str().c_str()) : atoi(m[2].str().c_str());
+ std::string hole_name = bit_assn? bit_m[3].str() : m[3].str();
+ unsigned int hole_offset = bit_assn? atoi(bit_m[4].str().c_str()) : 0;
+ RTLIL::State hole_value = bit_assn? (atoi(bit_m[5].str().c_str()) == 1? RTLIL::State::S1 : RTLIL::State::S0)
+ : (atoi(m[4].str().c_str()) == 1? RTLIL::State::S1 : RTLIL::State::S0);
+
+ //We have two options to identify holes. First, try to match wire names. If we can't find a matching wire,
+ //then try to find a cell with a matching location.
+ RTLIL::SigBit hole_sigbit;
+ if (module->wire(hole_name) != nullptr) {
+ RTLIL::Wire *hole_wire = module->wire(hole_name);
+ hole_sigbit = RTLIL::SigSpec(hole_wire)[hole_offset];
+ } else {
+ auto locs = split_tokens(hole_loc, "|");
+ pool<std::string> hole_loc_pool(locs.begin(), locs.end());
+ auto hole_cell_it = anyconst_loc_to_cell.find(hole_loc_pool);
+ if (hole_cell_it == anyconst_loc_to_cell.end())
+ log_cmd_error("cannot find matching wire name or $anyconst cell location for hole spec \"%s\"\n", buf.c_str());
+
+ RTLIL::Cell *hole_cell = hole_cell_it->second;
+ hole_sigbit = hole_cell->getPort(ID::Y)[hole_bit];
}
- for (auto cell : anyconsts_to_remove)
- module->remove(cell);
+ hole_assignments[hole_sigbit] = hole_value;
+ }
- for (auto &it : hole_name_to_value) {
- std::string hole_name = it.first;
- std::string hole_value = it.second;
- RTLIL::Wire *wire = module->wire(hole_name);
-#ifndef NDEBUG
- log_assert(wire != nullptr);
- log_assert(wire->width > 0 && GetSize(hole_value) == wire->width);
-#endif
-
- log("Specializing %s from file with %s = %d'b%s.\n", module->name.c_str(), hole_name.c_str(), wire->width, hole_value.c_str());
- std::vector<RTLIL::SigBit> value_bv;
- value_bv.reserve(wire->width);
- for (char c : hole_value)
- value_bv.emplace_back(c == '1'? RTLIL::S1 : RTLIL::S0);
- std::reverse(value_bv.begin(), value_bv.end());
- module->connect(wire, value_bv);
+ for (auto &it : anyconst_loc_to_cell)
+ module->remove(it.second);
+
+ for (auto &it : hole_assignments) {
+ RTLIL::SigSpec lhs(it.first);
+ RTLIL::SigSpec rhs(it.second);
+ log("Specializing %s from file with %s = %d.\n", module->name.c_str(), log_signal(it.first), it.second == RTLIL::State::S1? 1 : 0);
+ module->connect(lhs, rhs);
}
}
-void specialize(RTLIL::Module *module, const QbfSolutionType &sol) {
- dict<std::string, std::string> hole_loc_to_name = get_hole_loc_name_map(module, sol);
+void specialize(RTLIL::Module *module, const QbfSolutionType &sol, bool quiet = false) {
+ auto hole_loc_idx_to_sigbit = sol.get_hole_loc_idx_sigbit_map(module);
pool<RTLIL::Cell *> anyconsts_to_remove;
for (auto cell : module->cells())
if (cell->type == "$anyconst")
- if (hole_loc_to_name.find(cell->get_src_attribute()) != hole_loc_to_name.end())
+ if (hole_loc_idx_to_sigbit.find(std::make_pair(cell->get_strpool_attribute(ID::src), 0)) != hole_loc_idx_to_sigbit.end())
anyconsts_to_remove.insert(cell);
for (auto cell : anyconsts_to_remove)
module->remove(cell);
for (auto &it : sol.hole_to_value) {
- std::string hole_loc = it.first;
- std::string hole_value = it.second;
-
-#ifndef NDEBUG
- auto pos = hole_loc_to_name.find(hole_loc);
- log_assert(pos != hole_loc_to_name.end());
-#endif
-
- std::string hole_name = hole_loc_to_name[hole_loc];
- RTLIL::Wire *wire = module->wire(hole_name);
-#ifndef NDEBUG
- log_assert(wire != nullptr);
- log_assert(wire->width > 0 && GetSize(hole_value) == wire->width);
-#endif
-
- log("Specializing %s with %s = %d'b%s.\n", module->name.c_str(), hole_name.c_str(), wire->width, hole_value.c_str());
- std::vector<RTLIL::SigBit> value_bv;
- value_bv.reserve(wire->width);
- for (char c : hole_value)
- value_bv.emplace_back(c == '1'? RTLIL::S1 : RTLIL::S0);
- std::reverse(value_bv.begin(), value_bv.end());
- module->connect(wire, value_bv);
- }
-}
-
-void dump_model(RTLIL::Module *module, const QbfSolutionType &sol) {
- log("Satisfiable model:\n");
- dict<std::string, std::string> hole_loc_to_name = get_hole_loc_name_map(module, sol);
- for (auto &it : sol.hole_to_value) {
- std::string hole_loc = it.first;
+ pool<std::string> hole_loc = it.first;
std::string hole_value = it.second;
-#ifndef NDEBUG
- auto pos = hole_loc_to_name.find(hole_loc);
- log_assert(pos != hole_loc_to_name.end());
-#endif
-
- std::string hole_name = hole_loc_to_name[hole_loc];
- log("\t%s = %lu'b%s\n", hole_name.c_str(), hole_value.size(), hole_value.c_str());
- std::vector<RTLIL::SigBit> value_bv;
- value_bv.reserve(hole_value.size());
- for (char c : hole_value)
- value_bv.emplace_back(c == '1'? RTLIL::S1 : RTLIL::S0);
- std::reverse(value_bv.begin(), value_bv.end());
+ for (unsigned int i = 0; i < hole_value.size(); ++i) {
+ int bit_idx = GetSize(hole_value) - 1 - i;
+ auto it = hole_loc_idx_to_sigbit.find(std::make_pair(hole_loc, i));
+ log_assert(it != hole_loc_idx_to_sigbit.end());
+
+ RTLIL::SigBit hole_sigbit = it->second;
+ log_assert(hole_sigbit.wire != nullptr);
+ log_assert(hole_value[bit_idx] == '0' || hole_value[bit_idx] == '1');
+ RTLIL::SigSpec lhs(hole_sigbit.wire, hole_sigbit.offset, 1);
+ RTLIL::State hole_bit_val = hole_value[bit_idx] == '1'? RTLIL::State::S1 : RTLIL::State::S0;
+ if (!quiet)
+ log("Specializing %s with %s = %d.\n", module->name.c_str(), log_signal(hole_sigbit), hole_bit_val == RTLIL::State::S0? 0 : 1)
+;
+ module->connect(lhs, hole_bit_val);
+ }
}
-
}
void allconstify_inputs(RTLIL::Module *module, const pool<std::string> &input_wires) {
for (auto &n : input_wires) {
RTLIL::Wire *input = module->wire(n);
-#ifndef NDEBUG
log_assert(input != nullptr);
-#endif
RTLIL::Cell *allconst = module->addCell("$allconst$" + n, "$allconst");
allconst->setParam(ID(WIDTH), input->width);
@@ -239,7 +172,7 @@ void allconstify_inputs(RTLIL::Module *module, const pool<std::string> &input_wi
module->fixup_ports();
}
-void assume_miter_outputs(RTLIL::Module *module, const QbfSolveOptions &opt) {
+void assume_miter_outputs(RTLIL::Module *module, bool assume_neg) {
std::vector<RTLIL::Wire *> wires_to_assume;
for (auto w : module->wires())
if (w->port_output && w->width == 1)
@@ -254,7 +187,7 @@ void assume_miter_outputs(RTLIL::Module *module, const QbfSolveOptions &opt) {
log("\n");
}
- if (opt.assume_neg) {
+ if (assume_neg) {
for (unsigned int i = 0; i < wires_to_assume.size(); ++i) {
RTLIL::SigSpec n_wire = module->LogicNot(wires_to_assume[i]->name.str() + "__n__qbfsat", wires_to_assume[i], false, wires_to_assume[i]->get_src_attribute());
wires_to_assume[i] = n_wire.as_wire();
@@ -274,90 +207,173 @@ void assume_miter_outputs(RTLIL::Module *module, const QbfSolveOptions &opt) {
wires_to_assume.swap(buf);
}
-#ifndef NDEBUG
log_assert(wires_to_assume.size() == 1);
-#endif
module->addAssume("$assume_qbfsat_miter_outputs", wires_to_assume[0], RTLIL::S1);
}
-QbfSolutionType qbf_solve(RTLIL::Module *mod, const QbfSolveOptions &opt) {
+QbfSolutionType call_qbf_solver(RTLIL::Module *mod, const QbfSolveOptions &opt, const std::string &tempdir_name, const bool quiet = false, const int iter_num = 0) {
+ //Execute and capture stdout from `yosys-smtbmc -s z3 -t 1 -g --binary [--dump-smt2 <file>]`
QbfSolutionType ret;
const std::string yosys_smtbmc_exe = proc_self_dirname() + "yosys-smtbmc";
+ const std::string smt2_command = stringf("write_smt2 -stbv -wires %s/problem%d.smt2", tempdir_name.c_str(), iter_num);
const std::string smtbmc_warning = "z3: WARNING:";
- const bool show_smtbmc = opt.show_smtbmc;
+ const std::string smtbmc_cmd = stringf("%s -s %s %s -t 1 -g --binary %s %s/problem%d.smt2 2>&1",
+ yosys_smtbmc_exe.c_str(), opt.get_solver_name().c_str(),
+ (opt.timeout != 0? stringf("--timeout %d", opt.timeout) : "").c_str(),
+ (opt.dump_final_smt2? "--dump-smt2 " + opt.dump_final_smt2_file : "").c_str(),
+ tempdir_name.c_str(), iter_num);
- const std::string tempdir_name = make_temp_dir("/tmp/yosys-z3-XXXXXX");
- const std::string smt2_command = "write_smt2 -stbv -wires " + tempdir_name + "/problem.smt2";
-#ifndef NDEBUG
- log_assert(mod->design != nullptr);
-#endif
Pass::call(mod->design, smt2_command);
+
+ auto process_line = [&ret, &smtbmc_warning, &opt, &quiet](const std::string &line) {
+ ret.stdout_lines.push_back(line.substr(0, line.size()-1)); //don't include trailing newline
+ auto warning_pos = line.find(smtbmc_warning);
+ if (warning_pos != std::string::npos)
+ log_warning("%s", line.substr(warning_pos + smtbmc_warning.size() + 1).c_str());
+ else
+ if (opt.show_smtbmc && !quiet)
+ log("smtbmc output: %s", line.c_str());
+ };
log_header(mod->design, "Solving QBF-SAT problem.\n");
+ if (!quiet) log("Launching \"%s\".\n", smtbmc_cmd.c_str());
+ int64_t begin = PerformanceTimer::query();
+ run_command(smtbmc_cmd, process_line);
+ int64_t end = PerformanceTimer::query();
+ ret.solver_time = (end - begin) / 1e9f;
+ if (!quiet) log("Solver finished in %.3f seconds.\n", ret.solver_time);
+
+ ret.recover_solution();
+ return ret;
+}
- //Execute and capture stdout from `yosys-smtbmc -s z3 -t 1 -g --binary [--dump-smt2 <file>]`
- {
- const std::string cmd = yosys_smtbmc_exe + " -s z3 -t 1 -g --binary " + (opt.dump_final_smt2? "--dump-smt2 " + opt.dump_final_smt2_file + " " : "") + tempdir_name + "/problem.smt2 2>&1";
- auto process_line = [&ret, &smtbmc_warning, &show_smtbmc](const std::string &line) {
- ret.stdout_lines.push_back(line.substr(0, line.size()-1)); //don't include trailing newline
- auto warning_pos = line.find(smtbmc_warning);
- if (warning_pos != std::string::npos)
- log_warning("%s", line.substr(warning_pos + smtbmc_warning.size() + 1).c_str());
- else
- if (show_smtbmc)
- log("smtbmc output: %s", line.c_str());
- };
-
- log("Launching \"%s\".\n", cmd.c_str());
- int retval = run_command(cmd, process_line);
- if (retval == 0) {
- ret.sat = true;
- ret.unknown = false;
- } else if (retval == 1) {
- ret.sat = false;
- ret.unknown = false;
+QbfSolutionType qbf_solve(RTLIL::Module *mod, const QbfSolveOptions &opt) {
+ QbfSolutionType ret, best_soln;
+ const std::string tempdir_name = make_temp_dir("/tmp/yosys-qbfsat-XXXXXX");
+ RTLIL::Module *module = mod;
+ RTLIL::Design *design = module->design;
+ std::string module_name = module->name.str();
+ RTLIL::IdString wire_to_optimize_name = "";
+ bool maximize = false;
+ log_assert(module->design != nullptr);
+
+ Pass::call(design, "design -push-copy");
+
+ //Replace input wires with wires assigned $allconst cells:
+ pool<std::string> input_wires = validate_design_and_get_inputs(module, opt.assume_outputs);
+ allconstify_inputs(module, input_wires);
+ if (opt.assume_outputs)
+ assume_miter_outputs(module, opt.assume_neg);
+
+ //Find the wire to be optimized, if any:
+ for (auto wire : module->wires()) {
+ if (wire->get_bool_attribute("\\maximize") || wire->get_bool_attribute("\\minimize")) {
+ wire_to_optimize_name = wire->name;
+ maximize = wire->get_bool_attribute("\\maximize");
+ if (opt.nooptimize) {
+ if (maximize)
+ wire->set_bool_attribute("\\maximize", false);
+ else
+ wire->set_bool_attribute("\\minimize", false);
+ }
}
}
- if(!opt.nocleanup)
- remove_directory(tempdir_name);
+ //If -O1 or -O2 was specified, use ABC to simplify the problem:
+ if (opt.oflag == opt.OptimizationLevel::O1)
+ Pass::call(module->design, "abc -g AND,NAND,OR,NOR,XOR,XNOR,MUX,NMUX -script +print_stats;strash;print_stats;drwsat;print_stats;fraig;print_stats;refactor,-N,10,-lz;print_stats;&get,-n;&dch,-pem;&nf;&put " + mod->name.str());
+ else if (opt.oflag == opt.OptimizationLevel::O2)
+ Pass::call(module->design, "abc -g AND,NAND,OR,NOR,XOR,XNOR,MUX,NMUX -script +print_stats;strash;print_stats;drwsat;print_stats;dch,-S,1000000,-C,100000,-p;print_stats;fraig;print_stats;refactor,-N,15,-lz;print_stats;dc2,-pbl;print_stats;drwsat;print_stats;&get,-n;&dch,-pem;&nf;&put " + mod->name.str());
+ if (opt.oflag != opt.OptimizationLevel::O0) {
+ Pass::call(module->design, "techmap");
+ Pass::call(module->design, "opt");
+ }
- recover_solution(ret);
+ if (opt.nobisection || opt.nooptimize || wire_to_optimize_name == "") {
+ ret = call_qbf_solver(module, opt, tempdir_name, false, 0);
+ } else {
+ //Do the iterated bisection method:
+ unsigned int iter_num = 1;
+ unsigned int success = 0;
+ unsigned int failure = 0;
+ unsigned int cur_thresh = 0;
+
+ log_assert(wire_to_optimize_name != "");
+ log_assert(module->wire(wire_to_optimize_name) != nullptr);
+ log("%s wire \"%s\".\n", (maximize? "Maximizing" : "Minimizing"), wire_to_optimize_name.c_str());
+
+ //If maximizing, grow until we get a failure. Then bisect success and failure.
+ while (failure == 0 || difference(success, failure) > 1) {
+ Pass::call(design, "design -push-copy");
+ log_header(design, "Preparing QBF-SAT problem.\n");
- return ret;
-}
+ if (cur_thresh != 0) {
+ //Add thresholding logic (but not on the initial run when we don't have a sense of where to start):
+ RTLIL::SigSpec comparator = maximize? module->Ge(NEW_ID, module->wire(wire_to_optimize_name), RTLIL::Const(cur_thresh), false)
+ : module->Le(NEW_ID, module->wire(wire_to_optimize_name), RTLIL::Const(cur_thresh), false);
-pool<std::string> validate_design_and_get_inputs(RTLIL::Module *module, const QbfSolveOptions &opt) {
- bool found_input = false;
- bool found_hole = false;
- bool found_1bit_output = false;
- bool found_assert_assume = false;
- pool<std::string> input_wires;
- for (auto wire : module->wires()) {
- if (wire->port_input) {
- found_input = true;
- input_wires.insert(wire->name.str());
+ module->addAssume(wire_to_optimize_name.str() + "__threshold", comparator, RTLIL::Const(1, 1));
+ log("Trying to solve with %s %s %d.\n", wire_to_optimize_name.c_str(), (maximize? ">=" : "<="), cur_thresh);
+ }
+
+ ret = call_qbf_solver(module, opt, tempdir_name, false, iter_num);
+ Pass::call(design, "design -pop");
+ module = design->module(module_name);
+
+ if (!ret.unknown && ret.sat) {
+ Pass::call(design, "design -push-copy");
+ specialize(module, ret, true);
+
+ RTLIL::SigSpec wire, value, undef;
+ RTLIL::SigSpec::parse_sel(wire, design, module, wire_to_optimize_name.str());
+
+ ConstEval ce(module);
+ value = wire;
+ if (!ce.eval(value, undef))
+ log_cmd_error("Failed to evaluate signal %s: Missing value for %s.\n", log_signal(wire), log_signal(undef));
+ log_assert(value.is_fully_const());
+ success = value.as_const().as_int();
+ best_soln = ret;
+ log("Problem is satisfiable with %s = %d.\n", wire_to_optimize_name.c_str(), success);
+ Pass::call(design, "design -pop");
+ module = design->module(module_name);
+
+ //sometimes this happens if we get an 'unknown' or timeout
+ if (!maximize && success < failure)
+ break;
+ else if (maximize && failure != 0 && success > failure)
+ break;
+
+ } else {
+ //Treat 'unknown' as UNSAT
+ failure = cur_thresh;
+ if (failure == 0) {
+ log("Problem is NOT satisfiable.\n");
+ break;
+ }
+ else
+ log("Problem is NOT satisfiable with %s %s %d.\n", wire_to_optimize_name.c_str(), (maximize? ">=" : "<="), failure);
+ }
+
+ iter_num++;
+ if (maximize && failure == 0 && success == 0)
+ cur_thresh = 2;
+ else if (maximize && failure == 0)
+ cur_thresh = 2 * success; //growth
+ else //if (!maximize || failure != 0)
+ cur_thresh = (success + failure) / 2; //bisection
+ }
+ if (success != 0 || failure != 0) {
+ log("Wire %s is %s at %d.\n", wire_to_optimize_name.c_str(), (maximize? "maximized" : "minimized"), success);
+ ret = best_soln;
}
- if (wire->port_output && wire->width == 1)
- found_1bit_output = true;
- }
- for (auto cell : module->cells()) {
- if (cell->type == "$allconst")
- found_input = true;
- if (cell->type == "$anyconst")
- found_hole = true;
- if (cell->type.in("$assert", "$assume"))
- found_assert_assume = true;
}
- if (!found_input)
- log_cmd_error("Can't perform QBF-SAT on a miter with no inputs!\n");
- if (!found_hole)
- log_cmd_error("Did not find any existentially-quantified variables. Use 'sat' instead.\n");
- if (!found_1bit_output && !found_assert_assume)
- log_cmd_error("Did not find any single-bit outputs or $assert/$assume cells. Is this a miter circuit?\n");
- if (!found_assert_assume && !opt.assume_outputs)
- log_cmd_error("Did not find any $assert/$assume cells. Single-bit outputs were found, but `-assume-outputs` was not specified.\n");
- return input_wires;
+ if(!opt.nocleanup)
+ remove_directory(tempdir_name);
+
+ Pass::call(design, "design -pop");
+
+ return ret;
}
QbfSolveOptions parse_args(const std::vector<std::string> &args) {
@@ -379,6 +395,59 @@ QbfSolveOptions parse_args(const std::vector<std::string> &args) {
opt.assume_neg = true;
continue;
}
+ else if (args[opt.argidx] == "-nooptimize") {
+ opt.nooptimize = true;
+ continue;
+ }
+ else if (args[opt.argidx] == "-nobisection") {
+ opt.nobisection = true;
+ continue;
+ }
+ else if (args[opt.argidx] == "-solver") {
+ if (args.size() <= opt.argidx + 1)
+ log_cmd_error("solver not specified.\n");
+ else {
+ if (args[opt.argidx+1] == "z3")
+ opt.solver = opt.Solver::Z3;
+ else if (args[opt.argidx+1] == "yices")
+ opt.solver = opt.Solver::Yices;
+ else if (args[opt.argidx+1] == "cvc4")
+ opt.solver = opt.Solver::CVC4;
+ else
+ log_cmd_error("Unknown solver \"%s\".\n", args[opt.argidx+1].c_str());
+ opt.argidx++;
+ }
+ continue;
+ }
+ else if (args[opt.argidx] == "-timeout") {
+ if (args.size() <= opt.argidx + 1)
+ log_cmd_error("timeout not specified.\n");
+ else {
+ int timeout = atoi(args[opt.argidx+1].c_str());
+ if (timeout > 0)
+ opt.timeout = timeout;
+ else
+ log_cmd_error("timeout must be greater than 0.\n");
+ opt.argidx++;
+ }
+ continue;
+ }
+ else if (args[opt.argidx].substr(0, 2) == "-O" && args[opt.argidx].size() == 3) {
+ switch (args[opt.argidx][2]) {
+ case '0':
+ opt.oflag = opt.OptimizationLevel::O0;
+ break;
+ case '1':
+ opt.oflag = opt.OptimizationLevel::O1;
+ break;
+ case '2':
+ opt.oflag = opt.OptimizationLevel::O2;
+ break;
+ default:
+ log_cmd_error("unknown argument %s\n", args[opt.argidx].c_str());
+ }
+ continue;
+ }
else if (args[opt.argidx] == "-sat") {
opt.sat = true;
continue;
@@ -421,62 +490,56 @@ QbfSolveOptions parse_args(const std::vector<std::string> &args) {
return opt;
}
-void print_proof_failed()
-{
- log("\n");
- log(" ______ ___ ___ _ _ _ _ \n");
- log(" (_____ \\ / __) / __) (_) | | | |\n");
- log(" _____) )___ ___ ___ _| |__ _| |__ _____ _| | _____ __| | |\n");
- log(" | ____/ ___) _ \\ / _ (_ __) (_ __|____ | | || ___ |/ _ |_|\n");
- log(" | | | | | |_| | |_| || | | | / ___ | | || ____( (_| |_ \n");
- log(" |_| |_| \\___/ \\___/ |_| |_| \\_____|_|\\_)_____)\\____|_|\n");
- log("\n");
-}
-
-void print_qed()
-{
- log("\n");
- log(" /$$$$$$ /$$$$$$$$ /$$$$$$$ \n");
- log(" /$$__ $$ | $$_____/ | $$__ $$ \n");
- log(" | $$ \\ $$ | $$ | $$ \\ $$ \n");
- log(" | $$ | $$ | $$$$$ | $$ | $$ \n");
- log(" | $$ | $$ | $$__/ | $$ | $$ \n");
- log(" | $$/$$ $$ | $$ | $$ | $$ \n");
- log(" | $$$$$$/ /$$| $$$$$$$$ /$$| $$$$$$$//$$\n");
- log(" \\____ $$$|__/|________/|__/|_______/|__/\n");
- log(" \\__/ \n");
- log("\n");
-}
-
struct QbfSatPass : public Pass {
QbfSatPass() : Pass("qbfsat", "solve a 2QBF-SAT problem in the circuit") { }
- void help() YS_OVERRIDE
+ void help() override
{
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
log("\n");
log(" qbfsat [options] [selection]\n");
log("\n");
- log("This command solves a 2QBF-SAT problem defined over the currently selected module.\n");
- log("Existentially-quantified variables are declared by assigning a wire \"$anyconst\".\n");
- log("Universally-quantified variables may be explicitly declared by assigning a wire\n");
- log("\"$allconst\", but module inputs will be treated as universally-quantified variables\n");
- log("by default.\n");
+ log("This command solves an \"exists-forall\" 2QBF-SAT problem defined over the currently\n");
+ log("selected module. Existentially-quantified variables are declared by assigning a wire\n");
+ log("\"$anyconst\". Universally-quantified variables may be explicitly declared by assigning\n");
+ log("a wire \"$allconst\", but module inputs will be treated as universally-quantified\n");
+ log("variables by default.\n");
log("\n");
log(" -nocleanup\n");
- log(" Do not delete temporary files and directories. Useful for\n");
- log(" debugging.\n");
+ log(" Do not delete temporary files and directories. Useful for debugging.\n");
log("\n");
log(" -dump-final-smt2 <file>\n");
log(" Pass the --dump-smt2 option to yosys-smtbmc.\n");
log("\n");
log(" -assume-outputs\n");
- log(" Add an $assume cell for the conjunction of all one-bit module output wires.\n");
+ log(" Add an \"$assume\" cell for the conjunction of all one-bit module output wires.\n");
log("\n");
log(" -assume-negative-polarity\n");
log(" When adding $assume cells for one-bit module output wires, assume they are\n");
log(" negative polarity signals and should always be low, for example like the\n");
log(" miters created with the `miter` command.\n");
log("\n");
+ log(" -nooptimize\n");
+ log(" Ignore \"\\minimize\" and \"\\maximize\" attributes, do not emit \"(maximize)\" or\n");
+ log(" \"(minimize)\" in the SMT-LIBv2, and generally make no attempt to optimize anything.\n");
+ log("\n");
+ log(" -nobisection\n");
+ log(" If a wire is marked with the \"\\minimize\" or \"\\maximize\" attribute, do not\n");
+ log(" attempt to optimize that value with the default iterated solving and threshold\n");
+ log(" bisection approach. Instead, have yosys-smtbmc emit a \"(minimize)\" or \"(maximize)\"\n");
+ log(" command in the SMT-LIBv2 output and hope that the solver supports optimizing\n");
+ log(" quantified bitvector problems.\n");
+ log("\n");
+ log(" -solver <solver>\n");
+ log(" Use a particular solver. Choose one of: \"z3\", \"yices\", and \"cvc4\".\n");
+ log(" (default: yices)\n");
+ log("\n");
+ log(" -timeout <value>\n");
+ log(" Set the per-iteration timeout in seconds.\n");
+ log(" (default: no timeout)\n");
+ log("\n");
+ log(" -O0, -O1, -O2\n");
+ log(" Control the use of ABC to simplify the QBF-SAT problem before solving.\n");
+ log("\n");
log(" -sat\n");
log(" Generate an error if the solver does not return \"sat\".\n");
log("\n");
@@ -487,20 +550,21 @@ struct QbfSatPass : public Pass {
log(" Print the output from yosys-smtbmc.\n");
log("\n");
log(" -specialize\n");
- log(" Replace all \"$anyconst\" cells with constant values determined by the solver.\n");
+ log(" If the problem is satisfiable, replace each \"$anyconst\" cell with its\n");
+ log(" corresponding constant value from the model produced by the solver.\n");
log("\n");
log(" -specialize-from-file <solution file>\n");
- log(" Do not run the solver, but instead only attempt to replace all \"$anyconst\"\n");
- log(" cells in the current module with values provided by the specified file.\n");
+ log(" Do not run the solver, but instead only attempt to replace each \"$anyconst\"\n");
+ log(" cell in the current module with a constant value provided by the specified file.\n");
log("\n");
log(" -write-solution <solution file>\n");
- log(" Write the assignments discovered by the solver for all \"$anyconst\" cells\n");
- log(" to the specified file.");
+ log(" If the problem is satisfiable, write the corresponding constant value for each\n");
+ log(" \"$anyconst\" cell from the model produced by the solver to the specified file.");
log("\n");
log("\n");
}
- void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
+ void execute(std::vector<std::string> args, RTLIL::Design *design) override
{
log_header(design, "Executing QBFSAT pass (solving QBF-SAT problems in the circuit).\n");
QbfSolveOptions opt = parse_args(args);
@@ -519,41 +583,31 @@ struct QbfSatPass : public Pass {
if (!opt.specialize_from_file) {
//Save the design to restore after modiyfing the current module.
std::string module_name = module->name.str();
- Pass::call(design, "design -push-copy");
-
- //Replace input wires with wires assigned $allconst cells.
- pool<std::string> input_wires = validate_design_and_get_inputs(module, opt);
- allconstify_inputs(module, input_wires);
- if (opt.assume_outputs)
- assume_miter_outputs(module, opt);
QbfSolutionType ret = qbf_solve(module, opt);
- Pass::call(design, "design -pop");
module = design->module(module_name);
-
- if (ret.unknown)
- log_warning("solver did not give an answer\n");
- else if (ret.sat)
+ if (ret.unknown) {
+ if (opt.sat || opt.unsat)
+ log_cmd_error("expected problem to be %s\n", opt.sat? "SAT" : "UNSAT");
+ }
+ else if (ret.sat) {
print_qed();
- else
- print_proof_failed();
-
- if(!ret.unknown && ret.sat) {
if (opt.write_solution) {
- write_solution(module, ret, opt.write_soln_soln_file);
+ ret.write_solution(module, opt.write_soln_soln_file);
}
if (opt.specialize) {
specialize(module, ret);
} else {
- dump_model(module, ret);
+ ret.dump_model(module);
}
if (opt.unsat)
log_cmd_error("expected problem to be UNSAT\n");
}
- else if (!ret.unknown && !ret.sat && opt.sat)
- log_cmd_error("expected problem to be SAT\n");
- else if (ret.unknown && (opt.sat || opt.unsat))
- log_cmd_error("expected problem to be %s\n", opt.sat? "SAT" : "UNSAT");
+ else {
+ print_proof_failed();
+ if (opt.sat)
+ log_cmd_error("expected problem to be SAT\n");
+ }
} else
specialize_from_file(module, opt.specialize_soln_file);
log_pop();
diff --git a/passes/sat/qbfsat.h b/passes/sat/qbfsat.h
new file mode 100644
index 000000000..401f9c7a6
--- /dev/null
+++ b/passes/sat/qbfsat.h
@@ -0,0 +1,252 @@
+/* -*- c++ -*-
+ * yosys -- Yosys Open SYnthesis Suite
+ *
+ * Copyright (C) 2020 Alberto Gonzalez <boqwxp@airmail.cc>
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ */
+
+#ifndef QBFSAT_H
+#define QBFSAT_H
+
+#include "kernel/yosys.h"
+#include <numeric>
+
+YOSYS_NAMESPACE_BEGIN
+
+struct QbfSolveOptions {
+ bool specialize = false, specialize_from_file = false, write_solution = false, nocleanup = false;
+ bool dump_final_smt2 = false, assume_outputs = false, assume_neg = false, nooptimize = false;
+ bool nobisection = false, sat = false, unsat = false, show_smtbmc = false;
+ enum Solver{Z3, Yices, CVC4} solver = Yices;
+ enum OptimizationLevel{O0, O1, O2} oflag = O0;
+ int timeout = 0;
+ std::string specialize_soln_file = "";
+ std::string write_soln_soln_file = "";
+ std::string dump_final_smt2_file = "";
+ size_t argidx = 0;
+
+ std::string get_solver_name() const {
+ if (solver == Solver::Z3)
+ return "z3";
+ else if (solver == Solver::Yices)
+ return "yices";
+ else if (solver == Solver::CVC4)
+ return "cvc4";
+
+ log_cmd_error("unknown solver specified.\n");
+ return "";
+ }
+};
+
+struct QbfSolutionType {
+ std::vector<std::string> stdout_lines = {};
+ dict<pool<std::string>, std::string> hole_to_value = {};
+ double solver_time = 0;
+ bool sat = false;
+ bool unknown = true; //true if neither 'sat' nor 'unsat'
+
+ dict<std::pair<pool<std::string>, int>, RTLIL::SigBit> get_hole_loc_idx_sigbit_map(RTLIL::Module *module) const {
+ dict<std::pair<pool<std::string>, int>, RTLIL::SigBit> hole_loc_idx_to_sigbit;
+ pool<RTLIL::SigBit> anyconst_sigbits;
+ dict<RTLIL::SigBit, RTLIL::SigBit> anyconst_sigbit_to_wire_sigbit;
+
+ for (auto cell : module->cells()) {
+ pool<std::string> cell_src = cell->get_strpool_attribute(ID::src);
+ auto pos = hole_to_value.find(cell_src);
+ if (pos != hole_to_value.end() && cell->type.in("$anyconst", "$anyseq")) {
+ RTLIL::SigSpec port_y = cell->getPort(ID::Y);
+ for (int i = GetSize(port_y) - 1; i >= 0; --i) {
+ hole_loc_idx_to_sigbit[std::make_pair(pos->first, i)] = port_y[i];
+ anyconst_sigbits.insert(port_y[i]);
+ }
+ }
+ }
+
+ for (auto &conn : module->connections()) {
+ auto lhs = conn.first;
+ auto rhs = conn.second;
+ for (auto i = 0; i < GetSize(rhs); ++i) {
+ if (anyconst_sigbits[rhs[i]]) {
+ auto pos = anyconst_sigbit_to_wire_sigbit.find(rhs[i]);
+ if (pos != anyconst_sigbit_to_wire_sigbit.end())
+ log_cmd_error("conflicting names for hole $anyconst sigbit %s\n", log_signal(rhs[i]));
+ anyconst_sigbit_to_wire_sigbit[rhs[i]] = lhs[i];
+ }
+ }
+ }
+
+ for (auto &it : hole_loc_idx_to_sigbit) {
+ auto pos = anyconst_sigbit_to_wire_sigbit.find(it.second);
+ if (pos != anyconst_sigbit_to_wire_sigbit.end())
+ it.second = pos->second;
+ }
+
+ return hole_loc_idx_to_sigbit;
+ }
+
+ void dump_model(RTLIL::Module *module) const {
+ log("Satisfiable model:\n");
+ auto hole_loc_idx_to_sigbit = get_hole_loc_idx_sigbit_map(module);
+ for (auto &it : hole_to_value) {
+ pool<std::string> hole_loc = it.first;
+ std::string hole_value = it.second;
+
+ for (unsigned int i = 0; i < hole_value.size(); ++i) {
+ int bit_idx = GetSize(hole_value) - 1 - i;
+ auto it = hole_loc_idx_to_sigbit.find(std::make_pair(hole_loc, i));
+ log_assert(it != hole_loc_idx_to_sigbit.end());
+
+ RTLIL::SigBit hole_sigbit = it->second;
+ log("\t%s = 1'b%c\n", log_signal(hole_sigbit), hole_value[bit_idx]);
+ }
+ }
+ }
+
+ void write_solution(RTLIL::Module *module, const std::string &file) const {
+ std::ofstream fout(file.c_str());
+ if (!fout)
+ log_cmd_error("could not open solution file for writing.\n");
+
+ //There is a question here: How exactly shall we identify holes?
+ //There are at least two reasonable options:
+ //1. By the source location of the $anyconst cells
+ //2. By the name(s) of the wire(s) connected to each SigBit of the $anyconst cell->getPort(ID::Y) SigSpec.
+ //
+ //Option 1 has the benefit of being very precise. There is very limited potential for confusion, as long
+ //as the source attribute has been set. However, if the source attribute is not set, this won't work.
+ //More importantly, we want to have the ability to port hole assignments to other modules with compatible
+ //hole names and widths. Obviously in those cases source locations of the $anyconst cells will not match.
+ //
+ //Option 2 has the benefits previously described, but wire names can be changed automatically by
+ //optimization or techmapping passes, especially when (ex/im)porting from BLIF for optimization with ABC.
+ //
+ //The approach taken here is to allow both options. We write the assignment information for each bit of
+ //the solution on a separate line. Each line is of one of two forms:
+ //
+ //location bit name = value
+ //location bit name [offset] = value
+ //
+ //where '[', ']', and '=' are literal symbols, "location" is the $anyconst cell source location attribute,
+ //"bit" is the index of the $anyconst cell, "name" is the `wire->name` field of the SigBit corresponding
+ //to the current bit of the $anyconst cell->getPort(ID::Y), "offset" is the `offset` field of that same
+ //SigBit, and "value", which is either '0' or '1', represents the assignment for that bit.
+ auto hole_loc_idx_to_sigbit = get_hole_loc_idx_sigbit_map(module);
+ for (auto &x : hole_to_value) {
+ std::string src_as_str = std::accumulate(x.first.begin(), x.first.end(), std::string(), [](const std::string &a, const std::string &b){return a + "|" + b;});
+ for (auto i = 0; i < GetSize(x.second); ++i)
+ fout << src_as_str.c_str() << " " << i << " " << log_signal(hole_loc_idx_to_sigbit[std::make_pair(x.first, i)]) << " = " << x.second[GetSize(x.second) - 1 - i] << std::endl;
+ }
+ }
+
+ void recover_solution() {
+ YS_REGEX_TYPE sat_regex = YS_REGEX_COMPILE("Status: PASSED");
+ YS_REGEX_TYPE unsat_regex = YS_REGEX_COMPILE("Solver Error.*model is not available");
+ YS_REGEX_TYPE unsat_regex2 = YS_REGEX_COMPILE("Status: FAILED");
+ YS_REGEX_TYPE timeout_regex = YS_REGEX_COMPILE("No solution found! \\(timeout\\)");
+ YS_REGEX_TYPE timeout_regex2 = YS_REGEX_COMPILE("No solution found! \\(interrupted\\)");
+ YS_REGEX_TYPE unknown_regex = YS_REGEX_COMPILE("No solution found! \\(unknown\\)");
+ YS_REGEX_TYPE unknown_regex2 = YS_REGEX_COMPILE("Unexpected EOF response from solver");
+ YS_REGEX_TYPE memout_regex = YS_REGEX_COMPILE("Solver Error:.*error \"out of memory\"");
+ YS_REGEX_TYPE hole_value_regex = YS_REGEX_COMPILE_WITH_SUBS("Value for anyconst in [a-zA-Z0-9_]* \\(([^:]*:[^\\)]*)\\): (.*)");
+#ifndef NDEBUG
+ YS_REGEX_TYPE hole_loc_regex = YS_REGEX_COMPILE("[^:]*:[0-9]+.[0-9]+-[0-9]+.[0-9]+");
+ YS_REGEX_TYPE hole_val_regex = YS_REGEX_COMPILE("[0-9]+");
+#endif
+ YS_REGEX_MATCH_TYPE m;
+ bool sat_regex_found = false;
+ bool unsat_regex_found = false;
+ dict<std::string, bool> hole_value_recovered;
+ for (const std::string &x : stdout_lines) {
+ if(YS_REGEX_NS::regex_search(x, m, hole_value_regex)) {
+ std::string loc = m[1].str();
+ std::string val = m[2].str();
+#ifndef NDEBUG
+ log_assert(YS_REGEX_NS::regex_search(loc, hole_loc_regex));
+ log_assert(YS_REGEX_NS::regex_search(val, hole_val_regex));
+#endif
+ auto locs = split_tokens(loc, "|");
+ pool<std::string> loc_pool(locs.begin(), locs.end());
+ hole_to_value[loc_pool] = val;
+ }
+ else if (YS_REGEX_NS::regex_search(x, sat_regex)) {
+ sat_regex_found = true;
+ sat = true;
+ unknown = false;
+ }
+ else if (YS_REGEX_NS::regex_search(x, unsat_regex)) {
+ unsat_regex_found = true;
+ sat = false;
+ unknown = false;
+ }
+ else if (YS_REGEX_NS::regex_search(x, memout_regex)) {
+ unknown = true;
+ log_warning("solver ran out of memory\n");
+ }
+ else if (YS_REGEX_NS::regex_search(x, timeout_regex)) {
+ unknown = true;
+ log_warning("solver timed out\n");
+ }
+ else if (YS_REGEX_NS::regex_search(x, timeout_regex2)) {
+ unknown = true;
+ log_warning("solver timed out\n");
+ }
+ else if (YS_REGEX_NS::regex_search(x, unknown_regex)) {
+ unknown = true;
+ log_warning("solver returned \"unknown\"\n");
+ }
+ else if (YS_REGEX_NS::regex_search(x, unsat_regex2)) {
+ unsat_regex_found = true;
+ sat = false;
+ unknown = false;
+ }
+ else if (YS_REGEX_NS::regex_search(x, unknown_regex2)) {
+ unknown = true;
+ }
+ }
+ log_assert(!unknown && sat? sat_regex_found : true);
+ log_assert(!unknown && !sat? unsat_regex_found : true);
+ }
+};
+
+void print_proof_failed()
+{
+ log("\n");
+ log(" ______ ___ ___ _ _ _ _ \n");
+ log(" (_____ \\ / __) / __) (_) | | | |\n");
+ log(" _____) )___ ___ ___ _| |__ _| |__ _____ _| | _____ __| | |\n");
+ log(" | ____/ ___) _ \\ / _ (_ __) (_ __|____ | | || ___ |/ _ |_|\n");
+ log(" | | | | | |_| | |_| || | | | / ___ | | || ____( (_| |_ \n");
+ log(" |_| |_| \\___/ \\___/ |_| |_| \\_____|_|\\_)_____)\\____|_|\n");
+ log("\n");
+}
+
+void print_qed()
+{
+ log("\n");
+ log(" /$$$$$$ /$$$$$$$$ /$$$$$$$ \n");
+ log(" /$$__ $$ | $$_____/ | $$__ $$ \n");
+ log(" | $$ \\ $$ | $$ | $$ \\ $$ \n");
+ log(" | $$ | $$ | $$$$$ | $$ | $$ \n");
+ log(" | $$ | $$ | $$__/ | $$ | $$ \n");
+ log(" | $$/$$ $$ | $$ | $$ | $$ \n");
+ log(" | $$$$$$/ /$$| $$$$$$$$ /$$| $$$$$$$//$$\n");
+ log(" \\____ $$$|__/|________/|__/|_______/|__/\n");
+ log(" \\__/ \n");
+ log("\n");
+}
+
+YOSYS_NAMESPACE_END
+
+#endif
diff --git a/passes/sat/sat.cc b/passes/sat/sat.cc
index 6acdbc800..d7bf125d1 100644
--- a/passes/sat/sat.cc
+++ b/passes/sat/sat.cc
@@ -256,13 +256,13 @@ struct SatHelper
{
RTLIL::SigSpec big_lhs, big_rhs;
- for (auto &it : module->wires_)
+ for (auto wire : module->wires())
{
- if (it.second->attributes.count(ID::init) == 0)
+ if (wire->attributes.count(ID::init) == 0)
continue;
- RTLIL::SigSpec lhs = sigmap(it.second);
- RTLIL::SigSpec rhs = it.second->attributes.at(ID::init);
+ RTLIL::SigSpec lhs = sigmap(wire);
+ RTLIL::SigSpec rhs = wire->attributes.at(ID::init);
log_assert(lhs.size() == rhs.size());
RTLIL::SigSpec removed_bits;
@@ -893,7 +893,7 @@ void print_qed()
struct SatPass : public Pass {
SatPass() : Pass("sat", "solve a SAT problem in the circuit") { }
- void help() YS_OVERRIDE
+ void help() override
{
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
log("\n");
@@ -1060,7 +1060,7 @@ struct SatPass : public Pass {
log(" Like -falsify but do not return an error for timeouts.\n");
log("\n");
}
- void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
+ void execute(std::vector<std::string> args, RTLIL::Design *design) override
{
std::vector<std::pair<std::string, std::string>> sets, sets_init, prove, prove_x;
std::map<int, std::vector<std::pair<std::string, std::string>>> sets_at;
diff --git a/passes/sat/sim.cc b/passes/sat/sim.cc
index 03ca42cf3..fb496ff87 100644
--- a/passes/sat/sim.cc
+++ b/passes/sat/sim.cc
@@ -163,7 +163,10 @@ struct SimInstance
mem_database[cell] = mem;
}
-
+ if (cell->type.in(ID($memwr),ID($memrd)))
+ {
+ log_error("$memrd and $memwr cells have to be merged to stand-alone $mem cells (execute memory_collect pass)\n");
+ }
if (cell->type.in(ID($assert), ID($cover), ID($assume))) {
formal_database.insert(cell);
}
@@ -751,7 +754,7 @@ struct SimWorker : SimShared
struct SimPass : public Pass {
SimPass() : Pass("sim", "simulate the circuit") { }
- void help() YS_OVERRIDE
+ void help() override
{
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
log("\n");
@@ -793,7 +796,7 @@ struct SimPass : public Pass {
log(" enable debug output\n");
log("\n");
}
- void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
+ void execute(std::vector<std::string> args, RTLIL::Design *design) override
{
SimWorker worker;
int numcycles = 20;
diff --git a/passes/sat/supercover.cc b/passes/sat/supercover.cc
index ba44f02d8..aacc044fb 100644
--- a/passes/sat/supercover.cc
+++ b/passes/sat/supercover.cc
@@ -25,7 +25,7 @@ PRIVATE_NAMESPACE_BEGIN
struct SupercoverPass : public Pass {
SupercoverPass() : Pass("supercover", "add hi/lo cover cells for each wire bit") { }
- void help() YS_OVERRIDE
+ void help() override
{
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
log("\n");
@@ -35,7 +35,7 @@ struct SupercoverPass : public Pass {
log("checking for a hi signal level and one checking for lo level.\n");
log("\n");
}
- void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
+ void execute(std::vector<std::string> args, RTLIL::Design *design) override
{
// bool flag_noinit = false;
diff --git a/passes/techmap/.gitignore b/passes/techmap/.gitignore
deleted file mode 100644
index e6dcc6bc0..000000000
--- a/passes/techmap/.gitignore
+++ /dev/null
@@ -1 +0,0 @@
-techmap.inc
diff --git a/passes/techmap/Makefile.inc b/passes/techmap/Makefile.inc
index 1802ba0de..e3b3d8dea 100644
--- a/passes/techmap/Makefile.inc
+++ b/passes/techmap/Makefile.inc
@@ -1,4 +1,5 @@
+OBJS += passes/techmap/flatten.o
OBJS += passes/techmap/techmap.o
OBJS += passes/techmap/simplemap.o
OBJS += passes/techmap/dfflibmap.o
@@ -40,23 +41,12 @@ OBJS += passes/techmap/insbuf.o
OBJS += passes/techmap/attrmvcp.o
OBJS += passes/techmap/attrmap.o
OBJS += passes/techmap/zinit.o
+OBJS += passes/techmap/dfflegalize.o
OBJS += passes/techmap/dff2dffs.o
OBJS += passes/techmap/flowmap.o
OBJS += passes/techmap/extractinv.o
endif
-GENFILES += passes/techmap/techmap.inc
-
-passes/techmap/techmap.inc: techlibs/common/techmap.v
- $(Q) mkdir -p $(dir $@)
- $(P) echo "// autogenerated from $<" > $@.new
- $(Q) echo "static char stdcells_code[] = {" >> $@.new
- $(Q) od -v -td1 -An $< | $(SED) -e 's/[0-9][0-9]*/&,/g' >> $@.new
- $(Q) echo "0};" >> $@.new
- $(Q) mv $@.new $@
-
-passes/techmap/techmap.o: passes/techmap/techmap.inc
-
ifeq ($(DISABLE_SPAWN),0)
TARGETS += $(PROGRAM_PREFIX)yosys-filterlib$(EXE)
EXTRA_OBJS += passes/techmap/filterlib.o
diff --git a/passes/techmap/abc.cc b/passes/techmap/abc.cc
index fae8b2426..0a58fdcc0 100644
--- a/passes/techmap/abc.cc
+++ b/passes/techmap/abc.cc
@@ -1276,7 +1276,7 @@ void abc_module(RTLIL::Design *design, RTLIL::Module *current_module, std::strin
struct AbcPass : public Pass {
AbcPass() : Pass("abc", "use ABC for technology mapping") { }
- void help() YS_OVERRIDE
+ void help() override
{
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
log("\n");
@@ -1460,7 +1460,7 @@ struct AbcPass : public Pass {
log("[1] http://www.eecs.berkeley.edu/~alanmi/abc/\n");
log("\n");
}
- void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
+ void execute(std::vector<std::string> args, RTLIL::Design *design) override
{
log_header(design, "Executing ABC pass (technology mapping using ABC).\n");
log_push();
diff --git a/passes/techmap/abc9.cc b/passes/techmap/abc9.cc
index 1b3d5ff06..127f8934e 100644
--- a/passes/techmap/abc9.cc
+++ b/passes/techmap/abc9.cc
@@ -36,7 +36,7 @@ PRIVATE_NAMESPACE_BEGIN
struct Abc9Pass : public ScriptPass
{
Abc9Pass() : ScriptPass("abc9", "use ABC9 for technology mapping") { }
- void on_register() YS_OVERRIDE
+ void on_register() override
{
RTLIL::constpad["abc9.script.default"] = "+&scorr; &sweep; &dc2; &dch -f; &ps; &if {C} {W} {D} {R} -v; &mfs";
RTLIL::constpad["abc9.script.default.area"] = "+&scorr; &sweep; &dc2; &dch -f; &ps; &if {C} {W} {D} {R} -a -v; &mfs";
@@ -81,7 +81,7 @@ struct Abc9Pass : public ScriptPass
"&st; &if {C} -g -K 6; &synch2; &if {C} {W} {D} {R} -v; &save; &load;"\
"&mfs";
}
- void help() YS_OVERRIDE
+ void help() override
{
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
log("\n");
@@ -151,8 +151,8 @@ struct Abc9Pass : public ScriptPass
log(" specified).\n");
log("\n");
log(" -dff\n");
- log(" also pass $_ABC9_FF_ cells through to ABC. modules with many clock\n");
- log(" domains are marked as such and automatically partitioned by ABC.\n");
+ log(" also pass $_DFF_[NP]_ cells through to ABC. modules with many clock\n");
+ log(" domains are supported and automatically partitioned by ABC.\n");
log("\n");
log(" -nocleanup\n");
log(" when this option is used, the temporary files created by this pass\n");
@@ -184,7 +184,7 @@ struct Abc9Pass : public ScriptPass
int maxlut;
std::string box_file;
- void clear_flags() YS_OVERRIDE
+ void clear_flags() override
{
exe_cmd.str("");
exe_cmd << "abc9_exe";
@@ -195,7 +195,7 @@ struct Abc9Pass : public ScriptPass
box_file = "";
}
- void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
+ void execute(std::vector<std::string> args, RTLIL::Design *design) override
{
std::string run_from, run_to;
clear_flags();
@@ -272,42 +272,108 @@ struct Abc9Pass : public ScriptPass
log_pop();
}
- void script() YS_OVERRIDE
+ void script() override
{
+ if (check_label("check")) {
+ if (help_mode)
+ run("abc9_ops -check [-dff]", "(option if -dff)");
+ else
+ run(stringf("abc9_ops -check %s", dff_mode ? "-dff" : ""));
+ }
+
+ if (check_label("map")) {
+ if (help_mode)
+ run("abc9_ops -prep_hier -prep_bypass [-prep_dff -dff]", "(option if -dff)");
+ else
+ run(stringf("abc9_ops -prep_hier -prep_bypass %s", dff_mode ? "-prep_dff -dff" : ""));
+ if (dff_mode) {
+ run("design -copy-to $abc9_map @$abc9_flops", "(only if -dff)");
+ run("select -unset $abc9_flops", " (only if -dff)");
+ }
+ run("design -stash $abc9");
+ run("design -load $abc9_map");
+ run("proc");
+ run("wbflip");
+ run("techmap");
+ run("opt");
+ if (dff_mode || help_mode) {
+ if (!help_mode)
+ active_design->scratchpad_unset("abc9_ops.prep_dff_submod.did_something");
+ run("abc9_ops -prep_dff_submod", " (only if -dff)"); // rewrite specify
+ bool did_something = help_mode || active_design->scratchpad_get_bool("abc9_ops.prep_dff_submod.did_something");
+ if (did_something) {
+ // select all $_DFF_[NP]_
+ // then select all its fanins
+ // then select all fanouts of all that
+ // lastly remove $_DFF_[NP]_ cells
+ run("setattr -set submod \"$abc9_flop\" t:$_DFF_?_ %ci* %co* t:$_DFF_?_ %d", " (only if -dff)");
+ run("submod", " (only if -dff)");
+ run("setattr -mod -set whitebox 1 -set abc9_flop 1 -set abc9_box 1 *_$abc9_flop", "(only if -dff)");
+ if (help_mode) {
+ run("foreach module in design");
+ run(" rename <module-name>_$abc9_flop _TECHMAP_REPLACE_", " (only if -dff)");
+ }
+ else {
+ // Rename all submod-s to _TECHMAP_REPLACE_ to inherit name + attrs
+ for (auto module : active_design->selected_modules()) {
+ active_design->selected_active_module = module->name.str();
+ if (module->cell(stringf("%s_$abc9_flop", module->name.c_str())))
+ run(stringf("rename %s_$abc9_flop _TECHMAP_REPLACE_", module->name.c_str()));
+ }
+ active_design->selected_active_module.clear();
+ }
+ run("abc9_ops -prep_dff_unmap", " (only if -dff)");
+ run("design -copy-to $abc9 =*_$abc9_flop", " (only if -dff)"); // copy submod out
+ run("delete =*_$abc9_flop", " (only if -dff)");
+ }
+ }
+ run("design -stash $abc9_map");
+ run("design -load $abc9");
+ run("design -delete $abc9");
+ if (help_mode)
+ run("techmap -wb -max_iter 1 -map %$abc9_map -map +/abc9_map.v [-D DFF]", "(option if -dff)");
+ else
+ run(stringf("techmap -wb -max_iter 1 -map %%$abc9_map -map +/abc9_map.v %s", dff_mode ? "-D DFF" : ""));
+ run("design -delete $abc9_map");
+ }
+
if (check_label("pre")) {
- run("abc9_ops -check");
+ run("read_verilog -icells -lib -specify +/abc9_model.v");
run("scc -set_attr abc9_scc_id {}");
if (help_mode)
run("abc9_ops -mark_scc -prep_delays -prep_xaiger [-dff]", "(option for -dff)");
else
- run("abc9_ops -mark_scc -prep_delays -prep_xaiger" + std::string(dff_mode ? " -dff" : ""), "(option for -dff)");
+ run("abc9_ops -mark_scc -prep_delays -prep_xaiger" + std::string(dff_mode ? " -dff" : ""));
if (help_mode)
run("abc9_ops -prep_lut <maxlut>", "(skip if -lut or -luts)");
else if (!lut_mode)
run(stringf("abc9_ops -prep_lut %d", maxlut));
if (help_mode)
- run("abc9_ops -prep_box [-dff]", "(skip if -box)");
+ run("abc9_ops -prep_box", "(skip if -box)");
else if (box_file.empty())
- run(stringf("abc9_ops -prep_box %s", dff_mode ? "-dff" : ""));
- run("select -set abc9_holes A:abc9_holes");
- run("flatten -wb @abc9_holes");
- run("techmap @abc9_holes");
- if (dff_mode || help_mode)
- run("abc9_ops -prep_dff", "(only if -dff)");
- run("opt -purge @abc9_holes");
- run("aigmap");
- run("wbflip @abc9_holes");
+ run("abc9_ops -prep_box");
+ if (saved_designs.count("$abc9_holes") || help_mode) {
+ run("design -stash $abc9");
+ run("design -load $abc9_holes");
+ run("techmap -wb -map %$abc9 -map +/techmap.v");
+ run("opt -purge");
+ run("aigmap");
+ run("design -stash $abc9_holes");
+ run("design -load $abc9");
+ run("design -delete $abc9");
+ }
}
- if (check_label("map")) {
+ if (check_label("exe")) {
+ run("aigmap");
if (help_mode) {
run("foreach module in selection");
run(" abc9_ops -write_lut <abc-temp-dir>/input.lut", "(skip if '-lut' or '-luts')");
- run(" abc9_ops -write_box <abc-temp-dir>/input.box");
- run(" write_xaiger -map <abc-temp-dir>/input.sym <abc-temp-dir>/input.xaig");
- run(" abc9_exe [options] -cwd <abc-temp-dir> [-lut <abc-temp-dir>/input.lut] -box <abc-temp-dir>/input.box");
+ run(" abc9_ops -write_box <abc-temp-dir>/input.box", "(skip if '-box')");
+ run(" write_xaiger -map <abc-temp-dir>/input.sym [-dff] <abc-temp-dir>/input.xaig");
+ run(" abc9_exe [options] -cwd <abc-temp-dir> -lut [<abc-temp-dir>/input.lut] -box [<abc-temp-dir>/input.box]");
run(" read_aiger -xaiger -wideports -module_name <module-name>$abc9 -map <abc-temp-dir>/input.sym <abc-temp-dir>/output.aig");
- run(" abc9_ops -reintegrate");
+ run(" abc9_ops -reintegrate [-dff]");
}
else {
auto selected_modules = active_design->selected_modules();
@@ -318,7 +384,6 @@ struct Abc9Pass : public ScriptPass
log("Skipping module %s as it contains processes.\n", log_id(mod));
continue;
}
- log_assert(!mod->attributes.count(ID::abc9_box_id));
log_push();
active_design->selection().select(mod);
@@ -333,8 +398,9 @@ struct Abc9Pass : public ScriptPass
if (!lut_mode)
run_nocheck(stringf("abc9_ops -write_lut %s/input.lut", tempdir_name.c_str()));
- run_nocheck(stringf("abc9_ops -write_box %s/input.box", tempdir_name.c_str()));
- run_nocheck(stringf("write_xaiger -map %s/input.sym %s/input.xaig", tempdir_name.c_str(), tempdir_name.c_str()));
+ if (box_file.empty())
+ run_nocheck(stringf("abc9_ops -write_box %s/input.box", tempdir_name.c_str()));
+ run_nocheck(stringf("write_xaiger -map %s/input.sym %s %s/input.xaig", tempdir_name.c_str(), dff_mode ? "-dff" : "", tempdir_name.c_str()));
int num_outputs = active_design->scratchpad_get_int("write_xaiger.num_outputs");
@@ -349,10 +415,13 @@ struct Abc9Pass : public ScriptPass
abc9_exe_cmd += stringf("%s -cwd %s", exe_cmd.str().c_str(), tempdir_name.c_str());
if (!lut_mode)
abc9_exe_cmd += stringf(" -lut %s/input.lut", tempdir_name.c_str());
- abc9_exe_cmd += stringf(" -box %s/input.box", tempdir_name.c_str());
+ if (box_file.empty())
+ abc9_exe_cmd += stringf(" -box %s/input.box", tempdir_name.c_str());
+ else
+ abc9_exe_cmd += stringf(" -box %s", box_file.c_str());
run_nocheck(abc9_exe_cmd);
run_nocheck(stringf("read_aiger -xaiger -wideports -module_name %s$abc9 -map %s/input.sym %s/output.aig", log_id(mod), tempdir_name.c_str(), tempdir_name.c_str()));
- run_nocheck("abc9_ops -reintegrate");
+ run_nocheck(stringf("abc9_ops -reintegrate %s", dff_mode ? "-dff" : ""));
}
else
log("Don't call ABC as there is nothing to map.\n");
@@ -369,6 +438,14 @@ struct Abc9Pass : public ScriptPass
active_design->selection_stack.pop_back();
}
}
+
+ if (check_label("unmap")) {
+ run("techmap -wb -map %$abc9_unmap -map +/abc9_unmap.v"); // techmap user design from submod back to original cell
+ // ($_DFF_[NP]_ already shorted by -reintegrate)
+ run("design -delete $abc9_unmap");
+ if (saved_designs.count("$abc9_holes") || help_mode)
+ run("design -delete $abc9_holes");
+ }
}
} Abc9Pass;
diff --git a/passes/techmap/abc9_exe.cc b/passes/techmap/abc9_exe.cc
index 0bf547921..7355840aa 100644
--- a/passes/techmap/abc9_exe.cc
+++ b/passes/techmap/abc9_exe.cc
@@ -293,7 +293,7 @@ void abc9_module(RTLIL::Design *design, std::string script_file, std::string exe
struct Abc9ExePass : public Pass {
Abc9ExePass() : Pass("abc9_exe", "use ABC9 for technology mapping") { }
- void help() YS_OVERRIDE
+ void help() override
{
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
log("\n");
@@ -375,7 +375,7 @@ struct Abc9ExePass : public Pass {
log("[1] http://www.eecs.berkeley.edu/~alanmi/abc/\n");
log("\n");
}
- void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
+ void execute(std::vector<std::string> args, RTLIL::Design *design) override
{
log_header(design, "Executing ABC9_EXE pass (technology mapping using ABC9).\n");
diff --git a/passes/techmap/abc9_ops.cc b/passes/techmap/abc9_ops.cc
index 1345188a4..98d0207c4 100644
--- a/passes/techmap/abc9_ops.cc
+++ b/passes/techmap/abc9_ops.cc
@@ -34,13 +34,10 @@ inline std::string remap_name(RTLIL::IdString abc9_name)
return stringf("$abc$%d$%s", map_autoidx, abc9_name.c_str()+1);
}
-void check(RTLIL::Design *design)
+void check(RTLIL::Design *design, bool dff_mode)
{
dict<IdString,IdString> box_lookup;
for (auto m : design->modules()) {
- if (m->name.begins_with("$paramod"))
- continue;
-
auto flop = m->get_bool_attribute(ID::abc9_flop);
auto it = m->attributes.find(ID::abc9_box_id);
if (!flop) {
@@ -88,6 +85,463 @@ void check(RTLIL::Design *design)
log_error("Module '%s' with (* abc9_flop *) has %d outputs (expect 1).\n", log_id(m), num_outputs);
}
}
+
+ if (dff_mode) {
+ static pool<IdString> unsupported{
+ ID($adff), ID($dlatch), ID($dlatchsr), ID($sr),
+ ID($_DFF_NN0_), ID($_DFF_NN1_), ID($_DFF_NP0_), ID($_DFF_NP1_),
+ ID($_DFF_PN0_), ID($_DFF_PN1_), ID($_DFF_PP0_), ID($_DFF_PP1_),
+ ID($_DLATCH_N_), ID($_DLATCH_P_),
+ ID($_DLATCHSR_NNN_), ID($_DLATCHSR_NNP_), ID($_DLATCHSR_NPN_), ID($_DLATCHSR_NPP_),
+ ID($_DLATCHSR_PNN_), ID($_DLATCHSR_PNP_), ID($_DLATCHSR_PPN_), ID($_DLATCHSR_PPP_),
+ ID($_SR_NN_), ID($_SR_NP_), ID($_SR_PN_), ID($_SR_PP_)
+ };
+ pool<IdString> processed;
+ for (auto module : design->selected_modules())
+ for (auto cell : module->cells()) {
+ auto inst_module = design->module(cell->type);
+ if (!inst_module)
+ continue;
+ IdString derived_type;
+ Module *derived_module;
+ if (cell->parameters.empty()) {
+ derived_type = cell->type;
+ derived_module = inst_module;
+ }
+ else {
+ // Check potential (since its value may depend on a parameter,
+ // but not its existence)
+ if (!inst_module->has_attribute(ID::abc9_flop))
+ continue;
+ derived_type = inst_module->derive(design, cell->parameters);
+ derived_module = design->module(derived_type);
+ log_assert(derived_module);
+ }
+ if (!derived_module->get_bool_attribute(ID::abc9_flop))
+ continue;
+ if (derived_module->get_blackbox_attribute(true /* ignore_wb */))
+ log_error("Module '%s' with (* abc9_flop *) is a blackbox.\n", log_id(derived_type));
+
+ if (derived_module->has_processes())
+ Pass::call_on_module(design, derived_module, "proc");
+
+ bool found = false;
+ for (auto derived_cell : derived_module->cells()) {
+ if (derived_cell->type.in(ID($dff), ID($_DFF_N_), ID($_DFF_P_))) {
+ if (found)
+ log_error("Whitebox '%s' with (* abc9_flop *) contains more than one $_DFF_[NP]_ cell.\n", log_id(derived_module));
+ found = true;
+
+ SigBit Q = derived_cell->getPort(ID::Q);
+ log_assert(GetSize(Q.wire) == 1);
+
+ if (!Q.wire->port_output)
+ log_error("Whitebox '%s' with (* abc9_flop *) contains a %s cell where its 'Q' port does not drive a module output.\n", log_id(derived_module), log_id(derived_cell->type));
+
+ Const init = Q.wire->attributes.at(ID::init, State::Sx);
+ log_assert(GetSize(init) == 1);
+ }
+ else if (unsupported.count(derived_cell->type))
+ log_error("Whitebox '%s' with (* abc9_flop *) contains a %s cell, which is not supported for sequential synthesis.\n", log_id(derived_module), log_id(derived_cell->type));
+ }
+ }
+ }
+}
+
+void prep_hier(RTLIL::Design *design, bool dff_mode)
+{
+ auto r = saved_designs.emplace("$abc9_unmap", nullptr);
+ if (r.second)
+ r.first->second = new Design;
+ Design *unmap_design = r.first->second;
+
+ static const pool<IdString> seq_types{
+ ID($dff), ID($dffsr), ID($adff),
+ ID($dlatch), ID($dlatchsr), ID($sr),
+ ID($mem),
+ ID($_DFF_N_), ID($_DFF_P_),
+ ID($_DFFSR_NNN_), ID($_DFFSR_NNP_), ID($_DFFSR_NPN_), ID($_DFFSR_NPP_),
+ ID($_DFFSR_PNN_), ID($_DFFSR_PNP_), ID($_DFFSR_PPN_), ID($_DFFSR_PPP_),
+ ID($_DFF_N_), ID($_DFF_NN0_), ID($_DFF_NN1_), ID($_DFF_NP0_), ID($_DFF_NP1_),
+ ID($_DFF_P_), ID($_DFF_PN0_), ID($_DFF_PN1_), ID($_DFF_PP0_), ID($_DFF_PP1_),
+ ID($_DLATCH_N_), ID($_DLATCH_P_),
+ ID($_DLATCHSR_NNN_), ID($_DLATCHSR_NNP_), ID($_DLATCHSR_NPN_), ID($_DLATCHSR_NPP_),
+ ID($_DLATCHSR_PNN_), ID($_DLATCHSR_PNP_), ID($_DLATCHSR_PPN_), ID($_DLATCHSR_PPP_),
+ ID($_SR_NN_), ID($_SR_NP_), ID($_SR_PN_), ID($_SR_PP_)
+ };
+
+ for (auto module : design->selected_modules())
+ for (auto cell : module->cells()) {
+ auto inst_module = design->module(cell->type);
+ if (!inst_module)
+ continue;
+ IdString derived_type;
+ Module *derived_module;
+ if (cell->parameters.empty()) {
+ derived_type = cell->type;
+ derived_module = inst_module;
+ }
+ else {
+ // Check potential for any one of those three
+ // (since its value may depend on a parameter, but not its existence)
+ if (!inst_module->has_attribute(ID::abc9_flop) && !inst_module->has_attribute(ID::abc9_box) && !inst_module->get_bool_attribute(ID::abc9_bypass))
+ continue;
+ derived_type = inst_module->derive(design, cell->parameters);
+ derived_module = design->module(derived_type);
+ }
+ if (derived_module->get_blackbox_attribute(true /* ignore_wb */))
+ continue;
+
+ if (derived_module->get_bool_attribute(ID::abc9_flop)) {
+ if (!dff_mode)
+ continue;
+ }
+ else {
+ if (!derived_module->get_bool_attribute(ID::abc9_box) && !derived_module->get_bool_attribute(ID::abc9_bypass))
+ continue;
+ }
+
+ if (!unmap_design->module(derived_type)) {
+ if (derived_module->has_processes())
+ Pass::call_on_module(design, derived_module, "proc");
+
+ if (derived_module->get_bool_attribute(ID::abc9_flop)) {
+ for (auto derived_cell : derived_module->cells())
+ if (derived_cell->type.in(ID($dff), ID($_DFF_N_), ID($_DFF_P_))) {
+ SigBit Q = derived_cell->getPort(ID::Q);
+ Const init = Q.wire->attributes.at(ID::init, State::Sx);
+ log_assert(GetSize(init) == 1);
+
+ // Block sequential synthesis on cells with (* init *) != 1'b0
+ // because ABC9 doesn't support them
+ if (init != State::S0) {
+ log_warning("Whitebox '%s' with (* abc9_flop *) contains a %s cell with non-zero initial state -- this is not supported for ABC9 sequential synthesis. Treating as a blackbox.\n", log_id(derived_module), log_id(derived_cell->type));
+ derived_module->set_bool_attribute(ID::abc9_flop, false);
+ }
+ break;
+ }
+ }
+ else if (derived_module->get_bool_attribute(ID::abc9_box)) {
+ for (auto derived_cell : derived_module->cells())
+ if (seq_types.count(derived_cell->type)) {
+ derived_module->set_bool_attribute(ID::abc9_box, false);
+ derived_module->set_bool_attribute(ID::abc9_bypass);
+ break;
+ }
+ }
+
+ if (derived_type != cell->type) {
+ auto unmap_module = unmap_design->addModule(derived_type);
+ for (auto port : derived_module->ports) {
+ auto w = unmap_module->addWire(port, derived_module->wire(port));
+ // Do not propagate (* init *) values into the box,
+ // in fact, remove it from outside too
+ if (w->port_output)
+ w->attributes.erase(ID::init);
+ }
+ unmap_module->ports = derived_module->ports;
+ unmap_module->check();
+
+ auto replace_cell = unmap_module->addCell(ID::_TECHMAP_REPLACE_, cell->type);
+ for (const auto &conn : cell->connections()) {
+ auto w = unmap_module->wire(conn.first);
+ log_assert(w);
+ replace_cell->setPort(conn.first, w);
+ }
+ replace_cell->parameters = cell->parameters;
+ }
+ }
+
+ cell->type = derived_type;
+ cell->parameters.clear();
+ }
+}
+
+void prep_bypass(RTLIL::Design *design)
+{
+ auto r = saved_designs.emplace("$abc9_map", nullptr);
+ if (r.second)
+ r.first->second = new Design;
+ Design *map_design = r.first->second;
+
+ r = saved_designs.emplace("$abc9_unmap", nullptr);
+ if (r.second)
+ r.first->second = new Design;
+ Design *unmap_design = r.first->second;
+
+ pool<IdString> processed;
+ for (auto module : design->selected_modules())
+ for (auto cell : module->cells()) {
+ if (!processed.insert(cell->type).second)
+ continue;
+ auto inst_module = design->module(cell->type);
+ if (!inst_module)
+ continue;
+ if (!inst_module->get_bool_attribute(ID::abc9_bypass))
+ continue;
+ log_assert(!inst_module->get_blackbox_attribute(true /* ignore_wb */));
+ log_assert(cell->parameters.empty());
+
+
+ // The idea is to create two techmap designs, one which maps:
+ //
+ // box u0 (.i(i), .o(o));
+ //
+ // to
+ //
+ // wire $abc9$o;
+ // box u0 (.i(i), .o($abc9_byp$o));
+ // box_$abc9_byp (.i(i), .$abc9_byp$o($abc9_byp$o), .o(o));
+ //
+ // the purpose being to move the (* abc9_box *) status from 'box'
+ // (which is stateful) to 'box_$abc9_byp' (which becomes a new
+ // combinatorial black- (not white-) box with all state elements
+ // removed). This has the effect of preserving any combinatorial
+ // paths through an otherwise sequential primitive -- e.g. LUTRAMs.
+ //
+ // The unmap design performs the reverse:
+ //
+ // wire $abc9$o;
+ // box u0 (.i(i), .o($abc9_byp$o));
+ // box_$abc9_byp (.i(i), .$abc9_byp$o($abc9_byp$o), .o(o));
+ //
+ // to:
+ //
+ // wire $abc9$o;
+ // box u0 (.i(i), .o($abc9_byp$o));
+ // assign o = $abc9_byp$o;
+
+
+ // Copy inst_module into map_design, with the same interface
+ // and duplicate $abc9$* wires for its output ports
+ auto map_module = map_design->addModule(cell->type);
+ for (auto port_name : inst_module->ports) {
+ auto w = map_module->addWire(port_name, inst_module->wire(port_name));
+ if (w->port_output)
+ w->attributes.erase(ID::init);
+ }
+ map_module->ports = inst_module->ports;
+ map_module->check();
+ map_module->set_bool_attribute(ID::whitebox);
+
+ // Create the bypass module in the user design, which has the same
+ // interface as the derived module but with additional input
+ // ports driven by the outputs of the replaced cell
+ auto bypass_module = design->addModule(cell->type.str() + "_$abc9_byp");
+ for (auto port_name : inst_module->ports) {
+ auto port = inst_module->wire(port_name);
+ if (!port->port_output)
+ continue;
+ auto dst = bypass_module->addWire(port_name, port);
+ auto src = bypass_module->addWire("$abc9byp$" + port_name.str(), GetSize(port));
+ src->port_input = true;
+ // For these new input ports driven by the replaced
+ // cell, then create a new simple-path specify entry:
+ // (input => output) = 0
+ auto specify = bypass_module->addCell(NEW_ID, ID($specify2));
+ specify->setPort(ID::EN, State::S1);
+ specify->setPort(ID::SRC, src);
+ specify->setPort(ID::DST, dst);
+ specify->setParam(ID::FULL, 0);
+ specify->setParam(ID::SRC_WIDTH, GetSize(src));
+ specify->setParam(ID::DST_WIDTH, GetSize(dst));
+ specify->setParam(ID::SRC_DST_PEN, 0);
+ specify->setParam(ID::SRC_DST_POL, 0);
+ specify->setParam(ID::T_RISE_MIN, 0);
+ specify->setParam(ID::T_RISE_TYP, 0);
+ specify->setParam(ID::T_RISE_MAX, 0);
+ specify->setParam(ID::T_FALL_MIN, 0);
+ specify->setParam(ID::T_FALL_TYP, 0);
+ specify->setParam(ID::T_FALL_MAX, 0);
+ }
+ bypass_module->set_bool_attribute(ID::blackbox);
+ bypass_module->set_bool_attribute(ID::abc9_box);
+
+ // Copy any 'simple' (combinatorial) specify paths from
+ // the derived module into the bypass module, if EN
+ // is not false and SRC/DST are driven only by
+ // module ports; create new input port if one doesn't
+ // already exist
+ for (auto cell : inst_module->cells()) {
+ if (cell->type != ID($specify2))
+ continue;
+ auto EN = cell->getPort(ID::EN).as_bit();
+ SigBit newEN;
+ if (!EN.wire && EN != State::S1)
+ continue;
+ auto SRC = cell->getPort(ID::SRC);
+ for (const auto &c : SRC.chunks())
+ if (c.wire && !c.wire->port_input) {
+ SRC = SigSpec();
+ break;
+ }
+ if (SRC.empty())
+ continue;
+ auto DST = cell->getPort(ID::DST);
+ for (const auto &c : DST.chunks())
+ if (c.wire && !c.wire->port_output) {
+ DST = SigSpec();
+ break;
+ }
+ if (DST.empty())
+ continue;
+ auto rw = [bypass_module](RTLIL::SigSpec &sig)
+ {
+ SigSpec new_sig;
+ for (auto c : sig.chunks()) {
+ if (c.wire) {
+ auto port = bypass_module->wire(c.wire->name);
+ if (!port)
+ port = bypass_module->addWire(c.wire->name, c.wire);
+ c.wire = port;
+ }
+ new_sig.append(std::move(c));
+ }
+ sig = std::move(new_sig);
+ };
+ auto specify = bypass_module->addCell(NEW_ID, cell);
+ specify->rewrite_sigspecs(rw);
+ }
+ bypass_module->fixup_ports();
+
+ // Create an _TECHMAP_REPLACE_ cell identical to the original cell,
+ // and a bypass cell that has the same inputs/outputs as the
+ // original cell, but with additional inputs taken from the
+ // replaced cell
+ auto replace_cell = map_module->addCell(ID::_TECHMAP_REPLACE_, cell->type);
+ auto bypass_cell = map_module->addCell(NEW_ID, cell->type.str() + "_$abc9_byp");
+ for (const auto &conn : cell->connections()) {
+ auto port = map_module->wire(conn.first);
+ if (cell->input(conn.first)) {
+ replace_cell->setPort(conn.first, port);
+ if (bypass_module->wire(conn.first))
+ bypass_cell->setPort(conn.first, port);
+ }
+ if (cell->output(conn.first)) {
+ bypass_cell->setPort(conn.first, port);
+ auto n = "$abc9byp$" + conn.first.str();
+ auto w = map_module->addWire(n, GetSize(conn.second));
+ replace_cell->setPort(conn.first, w);
+ bypass_cell->setPort(n, w);
+ }
+ }
+
+
+ // Lastly, create a new module in the unmap_design that shorts
+ // out the bypass cell back to leave the replace cell behind
+ // driving the outputs
+ auto unmap_module = unmap_design->addModule(cell->type.str() + "_$abc9_byp");
+ for (auto port_name : inst_module->ports) {
+ auto w = unmap_module->addWire(port_name, inst_module->wire(port_name));
+ if (w->port_output) {
+ w->attributes.erase(ID::init);
+ auto w2 = unmap_module->addWire("$abc9byp$" + port_name.str(), GetSize(w));
+ w2->port_input = true;
+ unmap_module->connect(w, w2);
+ }
+ }
+ unmap_module->fixup_ports();
+ }
+}
+
+void prep_dff(RTLIL::Design *design)
+{
+ auto r = design->selection_vars.insert(std::make_pair(ID($abc9_flops), RTLIL::Selection(false)));
+ auto &modules_sel = r.first->second;
+
+ for (auto module : design->selected_modules())
+ for (auto cell : module->cells()) {
+ if (modules_sel.selected_whole_module(cell->type))
+ continue;
+ auto inst_module = design->module(cell->type);
+ if (!inst_module)
+ continue;
+ if (!inst_module->get_bool_attribute(ID::abc9_flop))
+ continue;
+ log_assert(!inst_module->get_blackbox_attribute(true /* ignore_wb */));
+ log_assert(cell->parameters.empty());
+ modules_sel.select(inst_module);
+ }
+}
+
+void prep_dff_submod(RTLIL::Design *design)
+{
+ for (auto module : design->modules()) {
+ vector<Cell*> specify_cells;
+ SigBit Q;
+ Cell* dff_cell = nullptr;
+
+ if (!module->get_bool_attribute(ID::abc9_flop))
+ continue;
+
+ for (auto cell : module->cells())
+ if (cell->type.in(ID($_DFF_N_), ID($_DFF_P_))) {
+ log_assert(!dff_cell);
+ dff_cell = cell;
+ Q = cell->getPort(ID::Q);
+ log_assert(GetSize(Q.wire) == 1);
+ }
+ else if (cell->type.in(ID($specify3), ID($specrule)))
+ specify_cells.emplace_back(cell);
+ log_assert(dff_cell);
+
+ // Add an always-enabled CE mux that drives $_DFF_[NP]_.D so that:
+ // (a) flop box will have an output
+ // (b) $_DFF_[NP]_.Q will be present as an input
+ SigBit D = module->addWire(NEW_ID);
+ module->addMuxGate(NEW_ID, dff_cell->getPort(ID::D), Q, State::S0, D);
+ dff_cell->setPort(ID::D, D);
+
+ // Rewrite $specify cells that end with $_DFF_[NP]_.Q
+ // to $_DFF_[NP]_.D since it will be moved into
+ // the submodule
+ for (auto cell : specify_cells) {
+ auto DST = cell->getPort(ID::DST);
+ DST.replace(Q, D);
+ cell->setPort(ID::DST, DST);
+ }
+
+ design->scratchpad_set_bool("abc9_ops.prep_dff_submod.did_something", true);
+ }
+}
+
+void prep_dff_unmap(RTLIL::Design *design)
+{
+ Design *unmap_design = saved_designs.at("$abc9_unmap");
+
+ for (auto module : design->modules()) {
+ if (!module->get_bool_attribute(ID::abc9_flop) || module->get_bool_attribute(ID::abc9_box))
+ continue;
+
+ // Make sure the box module has all the same ports present on flop cell
+ auto replace_cell = module->cell(ID::_TECHMAP_REPLACE_);
+ log_assert(replace_cell);
+ auto box_module = design->module(module->name.str() + "_$abc9_flop");
+ log_assert(box_module);
+ for (auto port_name : module->ports) {
+ auto port = module->wire(port_name);
+ auto box_port = box_module->wire(port_name);
+ if (box_port) {
+ // Do not propagate init -- already captured by box
+ box_port->attributes.erase(ID::init);
+ continue;
+ }
+ log_assert(port->port_input);
+ box_module->addWire(port_name, port);
+ replace_cell->setPort(port_name, port);
+ }
+ box_module->fixup_ports();
+
+ auto unmap_module = unmap_design->addModule(box_module->name);
+ replace_cell = unmap_module->addCell(ID::_TECHMAP_REPLACE_, module->name);
+ for (auto port_name : box_module->ports) {
+ auto w = unmap_module->addWire(port_name, box_module->wire(port_name));
+ if (module->wire(port_name))
+ replace_cell->setPort(port_name, w);
+ }
+ unmap_module->ports = box_module->ports;
+ unmap_module->check();
+ }
}
void mark_scc(RTLIL::Module *module)
@@ -95,7 +549,7 @@ void mark_scc(RTLIL::Module *module)
// For every unique SCC found, (arbitrarily) find the first
// cell in the component, and replace its output connections
// with a new wire driven by the old connection but with a
- // special (* abc9_scc *) attribute set (which is used by
+ // special (* abc9_keep *) attribute set (which is used by
// write_xaiger to break this wire into PI and POs)
pool<RTLIL::Const> ids_seen;
for (auto cell : module->cells()) {
@@ -111,7 +565,7 @@ void mark_scc(RTLIL::Module *module)
if (c.second.is_fully_const()) continue;
if (cell->output(c.first)) {
Wire *w = module->addWire(NEW_ID, GetSize(c.second));
- w->set_bool_attribute(ID::abc9_scc);
+ w->set_bool_attribute(ID::abc9_keep);
module->connect(w, c.second);
c.second = w;
}
@@ -119,80 +573,94 @@ void mark_scc(RTLIL::Module *module)
}
}
-void prep_dff(RTLIL::Module *module)
+void prep_delays(RTLIL::Design *design, bool dff_mode)
{
- auto design = module->design;
- log_assert(design);
+ TimingInfo timing;
- SigMap assign_map(module);
+ // Derive all Yosys blackbox modules that are not combinatorial abc9 boxes
+ // (e.g. DSPs, RAMs, etc.) nor abc9 flops and collect all such instantiations
+ std::vector<Cell*> cells;
+ for (auto module : design->selected_modules()) {
+ if (module->processes.size() > 0) {
+ log("Skipping module %s as it contains processes.\n", log_id(module));
+ continue;
+ }
- typedef SigSpec clkdomain_t;
- dict<clkdomain_t, int> clk_to_mergeability;
+ for (auto cell : module->cells()) {
+ if (cell->type.in(ID($_AND_), ID($_NOT_), ID($_DFF_N_), ID($_DFF_P_)))
+ continue;
+ log_assert(!cell->type.begins_with("$paramod$__ABC9_DELAY\\DELAY="));
- for (auto cell : module->cells()) {
- if (cell->type != ID($__ABC9_FF_))
- continue;
+ RTLIL::Module* inst_module = design->module(cell->type);
+ if (!inst_module)
+ continue;
+ if (!inst_module->get_blackbox_attribute())
+ continue;
+ if (!cell->parameters.empty())
+ continue;
- Wire *abc9_clock_wire = module->wire(stringf("%s.clock", cell->name.c_str()));
- if (abc9_clock_wire == NULL)
- log_error("'%s.clock' is not a wire present in module '%s'.\n", cell->name.c_str(), log_id(module));
- SigSpec abc9_clock = assign_map(abc9_clock_wire);
+ if (inst_module->get_bool_attribute(ID::abc9_box))
+ continue;
+ if (inst_module->get_bool_attribute(ID::abc9_bypass))
+ continue;
- clkdomain_t key(abc9_clock);
+ if (dff_mode && inst_module->get_bool_attribute(ID::abc9_flop)) {
+ continue; // do not add $__ABC9_DELAY boxes to flops
+ // as delays will be captured in the flop box
+ }
+
+ if (!timing.count(cell->type))
+ timing.setup_module(inst_module);
- auto r = clk_to_mergeability.insert(std::make_pair(abc9_clock, clk_to_mergeability.size() + 1));
- auto r2 = cell->attributes.insert(ID::abc9_mergeability);
- log_assert(r2.second);
- r2.first->second = r.first->second;
+ cells.emplace_back(cell);
+ }
}
- RTLIL::Module *holes_module = design->module(stringf("%s$holes", module->name.c_str()));
- if (holes_module) {
- SigMap sigmap(holes_module);
+ // Insert $__ABC9_DELAY cells on all cells that instantiate blackboxes
+ // (or bypassed white-boxes with required times)
+ dict<int, IdString> box_cache;
+ Module *delay_module = design->module(ID($__ABC9_DELAY));
+ log_assert(delay_module);
+ for (auto cell : cells) {
+ auto module = cell->module;
+ auto inst_module = design->module(cell->type);
+ log_assert(inst_module);
- dict<SigSpec, SigSpec> replace;
- for (auto cell : holes_module->cells().to_vector()) {
- if (!cell->type.in(ID($_DFF_N_), ID($_DFF_NN0_), ID($_DFF_NN1_), ID($_DFF_NP0_), ID($_DFF_NP1_),
- ID($_DFF_P_), ID($_DFF_PN0_), ID($_DFF_PN1), ID($_DFF_PP0_), ID($_DFF_PP1_)))
+ auto &t = timing.at(cell->type).required;
+ for (auto &conn : cell->connections_) {
+ auto port_wire = inst_module->wire(conn.first);
+ if (!port_wire)
+ log_error("Port %s in cell %s (type %s) from module %s does not actually exist",
+ log_id(conn.first), log_id(cell), log_id(cell->type), log_id(module));
+ if (!port_wire->port_input)
+ continue;
+ if (conn.second.is_fully_const())
continue;
- SigBit D = cell->getPort(ID::D);
- SigBit Q = cell->getPort(ID::Q);
- // Emulate async control embedded inside $_DFF_* cell with mux in front of D
- if (cell->type.in(ID($_DFF_NN0_), ID($_DFF_PN0_)))
- D = holes_module->MuxGate(NEW_ID, State::S0, D, cell->getPort(ID::R));
- else if (cell->type.in(ID($_DFF_NN1_), ID($_DFF_PN1_)))
- D = holes_module->MuxGate(NEW_ID, State::S1, D, cell->getPort(ID::R));
- else if (cell->type.in(ID($_DFF_NP0_), ID($_DFF_PP0_)))
- D = holes_module->MuxGate(NEW_ID, D, State::S0, cell->getPort(ID::R));
- else if (cell->type.in(ID($_DFF_NP1_), ID($_DFF_PP1_)))
- D = holes_module->MuxGate(NEW_ID, D, State::S1, cell->getPort(ID::R));
- // Remove the $_DFF_* cell from what needs to be a combinatorial box
- holes_module->remove(cell);
- Wire *port;
- if (GetSize(Q.wire) == 1)
- port = holes_module->wire(stringf("$abc%s", Q.wire->name.c_str()));
- else
- port = holes_module->wire(stringf("$abc%s[%d]", Q.wire->name.c_str(), Q.offset));
- log_assert(port);
- // Prepare to replace "assign <port> = $_DFF_*.Q;" with "assign <port> = $_DFF_*.D;"
- // in order to extract just the combinatorial control logic that feeds the box
- // (i.e. clock enable, synchronous reset, etc.)
- replace.insert(std::make_pair(Q,D));
- // Since `flatten` above would have created wires named "<cell>.Q",
- // extract the pre-techmap cell name
- auto pos = Q.wire->name.str().rfind(".");
- log_assert(pos != std::string::npos);
- IdString driver = Q.wire->name.substr(0, pos);
- // And drive the signal that was previously driven by "DFF.Q" (typically
- // used to implement clock-enable functionality) with the "<cell>.$abc9_currQ"
- // wire (which itself is driven an by input port) we inserted above
- Wire *currQ = holes_module->wire(stringf("%s.abc9_ff.Q", driver.c_str()));
- log_assert(currQ);
- holes_module->connect(Q, currQ);
- }
- for (auto &conn : holes_module->connections_)
- conn.second = replace.at(sigmap(conn.second), conn.second);
+ SigSpec O = module->addWire(NEW_ID, GetSize(conn.second));
+ for (int i = 0; i < GetSize(conn.second); i++) {
+ auto d = t.at(TimingInfo::NameBit(conn.first,i), 0);
+ if (d == 0)
+ continue;
+
+#ifndef NDEBUG
+ if (ys_debug(1)) {
+ static std::set<std::tuple<IdString,IdString,int>> seen;
+ if (seen.emplace(cell->type, conn.first, i).second) log("%s.%s[%d] abc9_required = %d\n",
+ log_id(cell->type), log_id(conn.first), i, d);
+ }
+#endif
+ auto r = box_cache.insert(d);
+ if (r.second) {
+ r.first->second = delay_module->derive(design, {{ID::DELAY, d}});
+ log_assert(r.first->second.begins_with("$paramod$__ABC9_DELAY\\DELAY="));
+ }
+ auto box = module->addCell(NEW_ID, r.first->second);
+ box->setPort(ID::I, conn.second[i]);
+ box->setPort(ID::O, O[i]);
+ conn.second[i] = O[i];
+ }
+ }
}
}
@@ -208,17 +676,17 @@ void prep_xaiger(RTLIL::Module *module, bool dff)
dict<IdString, std::vector<IdString>> box_ports;
for (auto cell : module->cells()) {
- if (cell->type == ID($__ABC9_FF_))
+ if (cell->type.in(ID($_DFF_N_), ID($_DFF_P_)))
continue;
if (cell->has_keep_attr())
continue;
- auto inst_module = module->design->module(cell->type);
+ auto inst_module = design->module(cell->type);
bool abc9_flop = inst_module && inst_module->get_bool_attribute(ID::abc9_flop);
if (abc9_flop && !dff)
continue;
- if ((inst_module && inst_module->get_bool_attribute(ID::abc9_box)) || abc9_flop) {
+ if (inst_module && inst_module->get_bool_attribute(ID::abc9_box)) {
auto r = box_ports.insert(cell->type);
if (r.second) {
// Make carry in the last PI, and carry out the last PO
@@ -253,8 +721,10 @@ void prep_xaiger(RTLIL::Module *module, bool dff)
bit_users[bit].insert(cell->name);
if (cell->output(conn.first) && !abc9_flop)
- for (auto bit : sigmap(conn.second))
- bit_drivers[bit].insert(cell->name);
+ for (const auto &chunk : conn.second.chunks())
+ if (!chunk.wire->get_bool_attribute(ID::abc9_keep))
+ for (auto b : sigmap(SigSpec(chunk)))
+ bit_drivers[b].insert(cell->name);
}
toposort.node(cell->name);
}
@@ -271,7 +741,7 @@ void prep_xaiger(RTLIL::Module *module, bool dff)
if (ys_debug(1))
toposort.analyze_loops = true;
- bool no_loops YS_ATTRIBUTE(unused) = toposort.sort();
+ bool no_loops = toposort.sort();
if (ys_debug(1)) {
unsigned i = 0;
@@ -287,9 +757,13 @@ void prep_xaiger(RTLIL::Module *module, bool dff)
log_assert(no_loops);
- RTLIL::Module *holes_module = design->addModule(stringf("%s$holes", module->name.c_str()));
+ auto r = saved_designs.emplace("$abc9_holes", nullptr);
+ if (r.second)
+ r.first->second = new Design;
+ RTLIL::Design *holes_design = r.first->second;
+ log_assert(holes_design);
+ RTLIL::Module *holes_module = holes_design->addModule(module->name);
log_assert(holes_module);
- holes_module->set_bool_attribute(ID::abc9_holes);
dict<IdString, Cell*> cell_cache;
TimingInfo timing;
@@ -300,22 +774,20 @@ void prep_xaiger(RTLIL::Module *module, bool dff)
log_assert(cell);
RTLIL::Module* box_module = design->module(cell->type);
- if (!box_module || (!box_module->get_bool_attribute(ID::abc9_box) && !box_module->get_bool_attribute(ID::abc9_flop)))
+ if (!box_module)
+ continue;
+ if (!box_module->get_bool_attribute(ID::abc9_box))
continue;
+ log_assert(cell->parameters.empty());
+ log_assert(box_module->get_blackbox_attribute());
cell->attributes[ID::abc9_box_seq] = box_count++;
- IdString derived_type = box_module->derive(design, cell->parameters);
- box_module = design->module(derived_type);
-
- auto r = cell_cache.insert(derived_type);
+ auto r = cell_cache.insert(cell->type);
auto &holes_cell = r.first->second;
if (r.second) {
- if (box_module->has_processes())
- Pass::call_on_module(design, box_module, "proc");
-
if (box_module->get_bool_attribute(ID::whitebox)) {
- holes_cell = holes_module->addCell(cell->name, derived_type);
+ holes_cell = holes_module->addCell(cell->name, cell->type);
if (box_module->has_processes())
Pass::call_on_module(design, box_module, "proc");
@@ -340,22 +812,7 @@ void prep_xaiger(RTLIL::Module *module, bool dff)
}
}
else if (w->port_output)
- conn = holes_module->addWire(stringf("%s.%s", derived_type.c_str(), log_id(port_name)), GetSize(w));
- }
-
- // For flops only, create an extra 1-bit input that drives a new wire
- // called "<cell>.abc9_ff.Q" that is used below
- if (box_module->get_bool_attribute(ID::abc9_flop)) {
- box_inputs++;
- Wire *holes_wire = holes_module->wire(stringf("\\i%d", box_inputs));
- if (!holes_wire) {
- holes_wire = holes_module->addWire(stringf("\\i%d", box_inputs));
- holes_wire->port_input = true;
- holes_wire->port_id = port_id++;
- holes_module->ports.push_back(holes_wire->name);
- }
- Wire *Q = holes_module->addWire(stringf("%s.abc9_ff.Q", cell->name.c_str()));
- holes_module->connect(Q, holes_wire);
+ conn = holes_module->addWire(stringf("%s.%s", cell->type.c_str(), log_id(port_name)), GetSize(w));
}
}
else // box_module is a blackbox
@@ -379,90 +836,6 @@ void prep_xaiger(RTLIL::Module *module, bool dff)
}
}
-void prep_delays(RTLIL::Design *design, bool dff_mode)
-{
- TimingInfo timing;
-
- // Derive all Yosys blackbox modules that are not combinatorial abc9 boxes
- // (e.g. DSPs, RAMs, etc.) nor abc9 flops and collect all such instantiations
- pool<Module*> flops;
- std::vector<Cell*> cells;
- for (auto module : design->selected_modules()) {
- if (module->processes.size() > 0) {
- log("Skipping module %s as it contains processes.\n", log_id(module));
- continue;
- }
-
- for (auto cell : module->cells()) {
- if (cell->type.in(ID($_AND_), ID($_NOT_), ID($__ABC9_FF_), ID($__ABC9_DELAY)))
- continue;
-
- RTLIL::Module* inst_module = module->design->module(cell->type);
- if (!inst_module)
- continue;
- if (!inst_module->get_blackbox_attribute())
- continue;
- if (inst_module->attributes.count(ID::abc9_box))
- continue;
- IdString derived_type = inst_module->derive(design, cell->parameters);
- inst_module = design->module(derived_type);
- log_assert(inst_module);
-
- if (dff_mode && inst_module->get_bool_attribute(ID::abc9_flop)) {
- flops.insert(inst_module);
- continue; // do not add $__ABC9_DELAY boxes to flops
- // as delays will be captured in the flop box
- }
-
- if (!timing.count(derived_type))
- timing.setup_module(inst_module);
-
- cells.emplace_back(cell);
- }
- }
-
- // Insert $__ABC9_DELAY cells on all cells that instantiate blackboxes
- // with required times
- for (auto cell : cells) {
- auto module = cell->module;
- RTLIL::Module* inst_module = module->design->module(cell->type);
- log_assert(inst_module);
- IdString derived_type = inst_module->derive(design, cell->parameters);
- inst_module = design->module(derived_type);
- log_assert(inst_module);
-
- auto &t = timing.at(derived_type).required;
- for (auto &conn : cell->connections_) {
- auto port_wire = inst_module->wire(conn.first);
- if (!port_wire)
- log_error("Port %s in cell %s (type %s) of module %s does not actually exist",
- log_id(conn.first), log_id(cell->name), log_id(cell->type), log_id(module->name));
- if (!port_wire->port_input)
- continue;
-
- SigSpec O = module->addWire(NEW_ID, GetSize(conn.second));
- for (int i = 0; i < GetSize(conn.second); i++) {
- auto d = t.at(TimingInfo::NameBit(conn.first,i), 0);
- if (d == 0)
- continue;
-
-#ifndef NDEBUG
- if (ys_debug(1)) {
- static std::set<std::tuple<IdString,IdString,int>> seen;
- if (seen.emplace(derived_type, conn.first, i).second) log("%s.%s[%d] abc9_required = %d\n",
- log_id(cell->type), log_id(conn.first), i, d);
- }
-#endif
- auto box = module->addCell(NEW_ID, ID($__ABC9_DELAY));
- box->setPort(ID::I, conn.second[i]);
- box->setPort(ID::O, O[i]);
- box->setParam(ID::DELAY, d);
- conn.second[i] = O[i];
- }
- }
- }
-}
-
void prep_lut(RTLIL::Design *design, int maxlut)
{
TimingInfo timing;
@@ -540,7 +913,7 @@ void write_lut(RTLIL::Module *module, const std::string &dst) {
ofs.close();
}
-void prep_box(RTLIL::Design *design, bool dff_mode)
+void prep_box(RTLIL::Design *design)
{
TimingInfo timing;
@@ -555,165 +928,162 @@ void prep_box(RTLIL::Design *design, bool dff_mode)
dict<IdString,std::vector<IdString>> box_ports;
for (auto module : design->modules()) {
- auto abc9_flop = module->get_bool_attribute(ID::abc9_flop);
- if (abc9_flop) {
- auto r = module->attributes.insert(ID::abc9_box_id);
- if (!r.second)
- continue;
- r.first->second = abc9_box_id++;
-
- if (dff_mode) {
- int num_inputs = 0, num_outputs = 0;
- for (auto port_name : module->ports) {
- auto wire = module->wire(port_name);
- log_assert(GetSize(wire) == 1);
- if (wire->port_input) num_inputs++;
- if (wire->port_output) num_outputs++;
- }
- log_assert(num_outputs == 1);
+ auto it = module->attributes.find(ID::abc9_box);
+ if (it == module->attributes.end())
+ continue;
+ bool box = it->second.as_bool();
+ module->attributes.erase(it);
+ if (!box)
+ continue;
- ss << log_id(module) << " " << r.first->second.as_int();
- ss << " " << (module->get_bool_attribute(ID::whitebox) ? "1" : "0");
- ss << " " << num_inputs+1 << " " << num_outputs << std::endl;
+ auto r = module->attributes.insert(ID::abc9_box_id);
+ if (!r.second)
+ continue;
+ r.first->second = abc9_box_id++;
+
+ if (module->get_bool_attribute(ID::abc9_flop)) {
+ int num_inputs = 0, num_outputs = 0;
+ for (auto port_name : module->ports) {
+ auto wire = module->wire(port_name);
+ log_assert(GetSize(wire) == 1);
+ if (wire->port_input) num_inputs++;
+ if (wire->port_output) num_outputs++;
+ }
+ log_assert(num_outputs == 1);
+
+ ss << log_id(module) << " " << r.first->second.as_int();
+ log_assert(module->get_bool_attribute(ID::whitebox));
+ ss << " " << "1";
+ ss << " " << num_inputs << " " << num_outputs << std::endl;
+
+ ss << "#";
+ bool first = true;
+ for (auto port_name : module->ports) {
+ auto wire = module->wire(port_name);
+ if (!wire->port_input)
+ continue;
+ if (first)
+ first = false;
+ else
+ ss << " ";
+ ss << log_id(wire);
+ }
+ ss << std::endl;
- ss << "#";
- bool first = true;
- for (auto port_name : module->ports) {
- auto wire = module->wire(port_name);
- if (!wire->port_input)
- continue;
- if (first)
- first = false;
- else
- ss << " ";
- ss << log_id(wire);
- }
- ss << " abc9_ff.Q" << std::endl;
+ auto &t = timing.setup_module(module).required;
+ if (t.empty())
+ log_error("Module '%s' with (* abc9_flop *) has no clk-to-q timing (and thus no connectivity) information.\n", log_id(module));
- auto &t = timing.setup_module(module).required;
- first = true;
- for (auto port_name : module->ports) {
- auto wire = module->wire(port_name);
- if (!wire->port_input)
- continue;
- if (first)
- first = false;
- else
- ss << " ";
- log_assert(GetSize(wire) == 1);
- auto it = t.find(TimingInfo::NameBit(port_name,0));
- if (it == t.end())
- // Assume that no setup time means zero
- ss << 0;
- else {
- ss << it->second;
+ first = true;
+ for (auto port_name : module->ports) {
+ auto wire = module->wire(port_name);
+ if (!wire->port_input)
+ continue;
+ if (first)
+ first = false;
+ else
+ ss << " ";
+ log_assert(GetSize(wire) == 1);
+ auto it = t.find(TimingInfo::NameBit(port_name,0));
+ if (it == t.end())
+ // Assume no connectivity if no setup time
+ ss << "-";
+ else {
+ ss << it->second;
#ifndef NDEBUG
- if (ys_debug(1)) {
- static std::set<std::pair<IdString,IdString>> seen;
- if (seen.emplace(module->name, port_name).second) log("%s.%s abc9_required = %d\n", log_id(module),
- log_id(port_name), it->second);
- }
-#endif
+ if (ys_debug(1)) {
+ static std::set<std::pair<IdString,IdString>> seen;
+ if (seen.emplace(module->name, port_name).second) log("%s.%s abc9_required = %d\n", log_id(module),
+ log_id(port_name), it->second);
}
-
+#endif
}
- // Last input is 'abc9_ff.Q'
- ss << " 0" << std::endl << std::endl;
- continue;
}
+ ss << " # $_DFF_[NP]_.D" << std::endl;
+ ss << std::endl;
}
else {
- if (!module->attributes.erase(ID::abc9_box))
- continue;
-
- auto r = module->attributes.insert(ID::abc9_box_id);
- if (!r.second)
- continue;
- r.first->second = abc9_box_id++;
- }
+ auto r2 = box_ports.insert(module->name);
+ if (r2.second) {
+ // Make carry in the last PI, and carry out the last PO
+ // since ABC requires it this way
+ IdString carry_in, carry_out;
+ for (const auto &port_name : module->ports) {
+ auto w = module->wire(port_name);
+ log_assert(w);
+ if (w->get_bool_attribute(ID::abc9_carry)) {
+ log_assert(w->port_input != w->port_output);
+ if (w->port_input)
+ carry_in = port_name;
+ else if (w->port_output)
+ carry_out = port_name;
+ }
+ else
+ r2.first->second.push_back(port_name);
+ }
- auto r = box_ports.insert(module->name);
- if (r.second) {
- // Make carry in the last PI, and carry out the last PO
- // since ABC requires it this way
- IdString carry_in, carry_out;
- for (const auto &port_name : module->ports) {
- auto w = module->wire(port_name);
- log_assert(w);
- if (w->get_bool_attribute(ID::abc9_carry)) {
- log_assert(w->port_input != w->port_output);
- if (w->port_input)
- carry_in = port_name;
- else if (w->port_output)
- carry_out = port_name;
+ if (carry_in != IdString()) {
+ r2.first->second.push_back(carry_in);
+ r2.first->second.push_back(carry_out);
}
- else
- r.first->second.push_back(port_name);
}
- if (carry_in != IdString()) {
- r.first->second.push_back(carry_in);
- r.first->second.push_back(carry_out);
+ std::vector<SigBit> inputs, outputs;
+ for (auto port_name : r2.first->second) {
+ auto wire = module->wire(port_name);
+ if (wire->port_input)
+ for (int i = 0; i < GetSize(wire); i++)
+ inputs.emplace_back(wire, i);
+ if (wire->port_output)
+ for (int i = 0; i < GetSize(wire); i++)
+ outputs.emplace_back(wire, i);
}
- }
-
- std::vector<SigBit> inputs;
- std::vector<SigBit> outputs;
- for (auto port_name : r.first->second) {
- auto wire = module->wire(port_name);
- if (wire->port_input)
- for (int i = 0; i < GetSize(wire); i++)
- inputs.emplace_back(wire, i);
- if (wire->port_output)
- for (int i = 0; i < GetSize(wire); i++)
- outputs.emplace_back(wire, i);
- }
- ss << log_id(module) << " " << module->attributes.at(ID::abc9_box_id).as_int();
- ss << " " << (module->get_bool_attribute(ID::whitebox) ? "1" : "0");
- ss << " " << GetSize(inputs) << " " << GetSize(outputs) << std::endl;
+ ss << log_id(module) << " " << module->attributes.at(ID::abc9_box_id).as_int();
+ ss << " " << (module->get_bool_attribute(ID::whitebox) ? "1" : "0");
+ ss << " " << GetSize(inputs) << " " << GetSize(outputs) << std::endl;
- bool first = true;
- ss << "#";
- for (const auto &i : inputs) {
- if (first)
- first = false;
- else
- ss << " ";
- if (GetSize(i.wire) == 1)
- ss << log_id(i.wire);
- else
- ss << log_id(i.wire) << "[" << i.offset << "]";
- }
- ss << std::endl;
-
- auto &t = timing.setup_module(module).comb;
- if (!abc9_flop && t.empty())
- log_warning("(* abc9_box *) module '%s' has no timing (and thus no connectivity) information.\n", log_id(module));
-
- for (const auto &o : outputs) {
- first = true;
+ bool first = true;
+ ss << "#";
for (const auto &i : inputs) {
if (first)
first = false;
else
ss << " ";
- auto jt = t.find(TimingInfo::BitBit(i,o));
- if (jt == t.end())
- ss << "-";
+ if (GetSize(i.wire) == 1)
+ ss << log_id(i.wire);
else
- ss << jt->second;
+ ss << log_id(i.wire) << "[" << i.offset << "]";
}
- ss << " # ";
- if (GetSize(o.wire) == 1)
- ss << log_id(o.wire);
- else
- ss << log_id(o.wire) << "[" << o.offset << "]";
ss << std::endl;
+ auto &t = timing.setup_module(module);
+ if (t.comb.empty())
+ log_error("Module '%s' with (* abc9_box *) has no timing (and thus no connectivity) information.\n", log_id(module));
+
+ for (const auto &o : outputs) {
+ first = true;
+ for (const auto &i : inputs) {
+ if (first)
+ first = false;
+ else
+ ss << " ";
+ auto jt = t.comb.find(TimingInfo::BitBit(i,o));
+ if (jt == t.comb.end())
+ ss << "-";
+ else
+ ss << jt->second;
+ }
+ ss << " # ";
+ if (GetSize(o.wire) == 1)
+ ss << log_id(o.wire);
+ else
+ ss << log_id(o.wire) << "[" << o.offset << "]";
+ ss << std::endl;
+ }
+ ss << std::endl;
}
- ss << std::endl;
}
// ABC expects at least one box
@@ -730,7 +1100,7 @@ void write_box(RTLIL::Module *module, const std::string &dst) {
ofs.close();
}
-void reintegrate(RTLIL::Module *module)
+void reintegrate(RTLIL::Module *module, bool dff_mode)
{
auto design = module->design;
log_assert(design);
@@ -744,6 +1114,8 @@ void reintegrate(RTLIL::Module *module)
for (auto w : mapped_mod->wires()) {
auto nw = module->addWire(remap_name(w->name), GetSize(w));
nw->start_offset = w->start_offset;
+ // Remove all (* init *) since they only exist on $_DFF_[NP]_
+ w->attributes.erase(ID::init);
}
dict<IdString,std::vector<IdString>> box_ports;
@@ -779,11 +1151,38 @@ void reintegrate(RTLIL::Module *module)
}
}
+ SigMap initmap;
+ if (dff_mode) {
+ // Build a sigmap prioritising bits with (* init *)
+ initmap.set(module);
+ for (auto w : module->wires()) {
+ auto it = w->attributes.find(ID::init);
+ if (it == w->attributes.end())
+ continue;
+ for (auto i = 0; i < GetSize(w); i++)
+ if (it->second[i] == State::S0 || it->second[i] == State::S1)
+ initmap.add(w);
+ }
+ }
+
std::vector<Cell*> boxes;
for (auto cell : module->cells().to_vector()) {
if (cell->has_keep_attr())
continue;
- if (cell->type.in(ID($_AND_), ID($_NOT_), ID($__ABC9_FF_)))
+
+ // Short out (so that existing name can be preserved) and remove
+ // $_DFF_[NP]_ cells since flop box already has all the information
+ // we need to reconstruct them
+ if (dff_mode && cell->type.in(ID($_DFF_N_), ID($_DFF_P_)) && !cell->get_bool_attribute(ID::abc9_keep)) {
+ SigBit Q = cell->getPort(ID::Q);
+ module->connect(Q, cell->getPort(ID::D));
+ module->remove(cell);
+ auto Qi = initmap(Q);
+ auto it = Qi.wire->attributes.find(ID::init);
+ if (it != Qi.wire->attributes.end())
+ it->second[Qi.offset] = State::Sx;
+ }
+ else if (cell->type.in(ID($_AND_), ID($_NOT_)))
module->remove(cell);
else if (cell->attributes.erase(ID::abc9_box_seq))
boxes.emplace_back(cell);
@@ -797,6 +1196,18 @@ void reintegrate(RTLIL::Module *module)
std::map<IdString, int> cell_stats;
for (auto mapped_cell : mapped_mod->cells())
{
+ // Short out $_FF_ cells since the flop box already has
+ // all the information we need to reconstruct cell
+ if (dff_mode && mapped_cell->type == ID($_FF_)) {
+ SigBit D = mapped_cell->getPort(ID::D);
+ SigBit Q = mapped_cell->getPort(ID::Q);
+ if (D.wire)
+ D.wire = module->wires_.at(remap_name(D.wire->name));
+ Q.wire = module->wires_.at(remap_name(Q.wire->name));
+ module->connect(Q, D);
+ continue;
+ }
+
// TODO: Speed up toposort -- we care about NOT ordering only
toposort.node(mapped_cell->name);
@@ -846,7 +1257,7 @@ void reintegrate(RTLIL::Module *module)
continue;
}
- if (mapped_cell->type.in(ID($lut), ID($__ABC9_FF_))) {
+ if (mapped_cell->type == ID($lut)) {
RTLIL::Cell *cell = module->addCell(remap_name(mapped_cell->name), mapped_cell->type);
cell->parameters = mapped_cell->parameters;
cell->attributes = mapped_cell->attributes;
@@ -881,7 +1292,7 @@ void reintegrate(RTLIL::Module *module)
if (!existing_cell)
log_error("Cannot find existing box cell with name '%s' in original design.\n", log_id(mapped_cell));
- if (existing_cell->type == ID($__ABC9_DELAY)) {
+ if (existing_cell->type.begins_with("$paramod$__ABC9_DELAY\\DELAY=")) {
SigBit I = mapped_cell->getPort(ID(i));
SigBit O = mapped_cell->getPort(ID(o));
if (I.wire)
@@ -893,10 +1304,8 @@ void reintegrate(RTLIL::Module *module)
}
RTLIL::Module* box_module = design->module(existing_cell->type);
- IdString derived_type = box_module->derive(design, existing_cell->parameters);
- RTLIL::Module* derived_module = design->module(derived_type);
- log_assert(derived_module);
- log_assert(mapped_cell->type == stringf("$__boxid%d", derived_module->attributes.at(ID::abc9_box_id).as_int()));
+ log_assert(existing_cell->parameters.empty());
+ log_assert(mapped_cell->type == stringf("$__boxid%d", box_module->attributes.at(ID::abc9_box_id).as_int()));
mapped_cell->type = existing_cell->type;
RTLIL::Cell *cell = module->addCell(remap_name(mapped_cell->name), mapped_cell->type);
@@ -913,8 +1322,26 @@ void reintegrate(RTLIL::Module *module)
SigSpec outputs = std::move(jt->second);
mapped_cell->connections_.erase(jt);
- auto abc9_flop = box_module->attributes.count(ID::abc9_flop);
- if (!abc9_flop) {
+ auto abc9_flop = box_module->get_bool_attribute(ID::abc9_flop);
+ if (abc9_flop) {
+ // Link this sole flop box output to the output of the existing
+ // flop box, so that any (public) signal it drives will be
+ // preserved
+ SigBit old_q;
+ for (const auto &port_name : box_ports.at(existing_cell->type)) {
+ RTLIL::Wire *w = box_module->wire(port_name);
+ log_assert(w);
+ if (!w->port_output)
+ continue;
+ log_assert(old_q == SigBit());
+ log_assert(GetSize(w) == 1);
+ old_q = existing_cell->getPort(port_name);
+ }
+ auto new_q = outputs[0];
+ new_q.wire = module->wires_.at(remap_name(new_q.wire->name));
+ module->connect(old_q, new_q);
+ }
+ else {
for (const auto &i : inputs)
bit_users[i].insert(mapped_cell->name);
for (const auto &i : outputs)
@@ -924,7 +1351,7 @@ void reintegrate(RTLIL::Module *module)
}
int input_count = 0, output_count = 0;
- for (const auto &port_name : box_ports.at(derived_type)) {
+ for (const auto &port_name : box_ports.at(existing_cell->type)) {
RTLIL::Wire *w = box_module->wire(port_name);
log_assert(w);
@@ -947,11 +1374,12 @@ void reintegrate(RTLIL::Module *module)
c.wire = module->wires_.at(remap_name(c.wire->name));
newsig.append(c);
}
- cell->setPort(port_name, newsig);
if (w->port_input && !abc9_flop)
for (const auto &i : newsig)
bit2sinks[i].push_back(cell);
+
+ cell->setPort(port_name, std::move(newsig));
}
}
@@ -988,7 +1416,7 @@ void reintegrate(RTLIL::Module *module)
RTLIL::Wire *mapped_wire = mapped_mod->wire(port);
RTLIL::Wire *wire = module->wire(port);
log_assert(wire);
- wire->attributes.erase(ID::abc9_scc);
+ wire->attributes.erase(ID::abc9_keep);
RTLIL::Wire *remap_wire = module->wire(remap_name(port));
RTLIL::SigSpec signal(wire, remap_wire->start_offset-wire->start_offset, GetSize(remap_wire));
@@ -1013,7 +1441,7 @@ void reintegrate(RTLIL::Module *module)
// treated as being "free"), in particular driving primary
// outputs (real primary outputs, or cells treated as blackboxes)
// or driving box inputs.
- // Instead of just mapping those $_NOT_ gates into 2-input $lut-s
+ // Instead of just mapping those $_NOT_ gates into 1-input $lut-s
// at an area and delay cost, see if it is possible to push
// this $_NOT_ into the driving LUT, or into all sink LUTs.
// When this is not possible, (i.e. this signal drives two primary
@@ -1025,7 +1453,7 @@ void reintegrate(RTLIL::Module *module)
for (auto driver_cell : bit_drivers.at(it.first))
for (auto user_cell : it.second)
toposort.edge(driver_cell, user_cell);
- bool no_loops YS_ATTRIBUTE(unused) = toposort.sort();
+ bool no_loops = toposort.sort();
log_assert(no_loops);
for (auto ii = toposort.sorted.rbegin(); ii != toposort.sorted.rend(); ii++) {
@@ -1102,7 +1530,7 @@ clone_lut:
struct Abc9OpsPass : public Pass {
Abc9OpsPass() : Pass("abc9_ops", "helper functions for ABC9") { }
- void help() YS_OVERRIDE
+ void help() override
{
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
log("\n");
@@ -1116,6 +1544,37 @@ struct Abc9OpsPass : public Pass {
log(" check that the design is valid, e.g. (* abc9_box_id *) values are unique,\n");
log(" (* abc9_carry *) is only given for one input/output port, etc.\n");
log("\n");
+ log(" -prep_hier\n");
+ log(" derive all used (* abc9_box *) or (* abc9_flop *) (if -dff option)\n");
+ log(" whitebox modules. with (* abc9_flop *) modules, only those containing\n");
+ log(" $dff/$_DFF_[NP]_ cells with zero initial state -- due to an ABC limitation\n");
+ log(" -- will be derived.\n");
+ log("\n");
+ log(" -prep_bypass\n");
+ log(" create techmap rules in the '$abc9_map' and '$abc9_unmap' designs for\n");
+ log(" bypassing sequential (* abc9_box *) modules using a combinatorial box\n");
+ log(" (named *_$abc9_byp). bypassing is necessary if sequential elements (e.g.\n");
+ log(" $dff, $mem, etc.) are discovered inside so that any combinatorial paths\n");
+ log(" will be correctly captured. this bypass box will only contain ports that\n");
+ log(" are referenced by a simple path declaration ($specify2 cell) inside a\n");
+ log(" specify block.\n");
+ log("\n");
+ log(" -prep_dff\n");
+ log(" select all (* abc9_flop *) modules instantiated in the design and store\n");
+ log(" in the named selection '$abc9_flops'.\n");
+ log("\n");
+ log(" -prep_dff_submod\n");
+ log(" within (* abc9_flop *) modules, rewrite all edge-sensitive path\n");
+ log(" declarations and $setup() timing checks ($specify3 and $specrule cells)\n");
+ log(" that share a 'DST' port with the $_DFF_[NP]_.Q port from this 'Q' port to\n");
+ log(" the DFF's 'D' port. this is to prepare such specify cells to be moved\n");
+ log(" into the flop box.\n");
+ log("\n");
+ log(" -prep_dff_unmap\n");
+ log(" populate the '$abc9_unmap' design with techmap rules for mapping *_$abc9_flop\n");
+ log(" cells back into their derived cell types (where the rules created by\n");
+ log(" -prep_hier will then map back to the original cell with parameters).\n");
+ log("\n");
log(" -prep_delays\n");
log(" insert `$__ABC9_DELAY' blackbox cells into the design to account for\n");
log(" certain required times.\n");
@@ -1128,18 +1587,13 @@ struct Abc9OpsPass : public Pass {
log("\n");
log(" -prep_xaiger\n");
log(" prepare the design for XAIGER output. this includes computing the\n");
- log(" topological ordering of ABC9 boxes, as well as preparing the\n");
- log(" '<module-name>$holes' module that contains the logic behaviour of ABC9\n");
- log(" whiteboxes.\n");
+ log(" topological ordering of ABC9 boxes, as well as preparing the '$abc9_holes'\n");
+ log(" design that contains the logic behaviour of ABC9 whiteboxes.\n");
log("\n");
log(" -dff\n");
log(" consider flop cells (those instantiating modules marked with (* abc9_flop *))\n");
log(" during -prep_{delays,xaiger,box}.\n");
log("\n");
- log(" -prep_dff\n");
- log(" compute the clock domain and initial value of each flop in the design.\n");
- log(" process the '$holes' module to support clock-enable functionality.\n");
- log("\n");
log(" -prep_lut <maxlut>\n");
log(" pre-compute the lut library by analysing all modules marked with\n");
log(" (* abc9_lut=<area> *).\n");
@@ -1160,14 +1614,16 @@ struct Abc9OpsPass : public Pass {
log(" inputs and outputs.\n");
log("\n");
}
- void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
+ void execute(std::vector<std::string> args, RTLIL::Design *design) override
{
log_header(design, "Executing ABC9_OPS pass (helper functions for ABC9).\n");
bool check_mode = false;
bool prep_delays_mode = false;
bool mark_scc_mode = false;
- bool prep_dff_mode = false;
+ bool prep_hier_mode = false;
+ bool prep_bypass_mode = false;
+ bool prep_dff_mode = false, prep_dff_submod_mode = false, prep_dff_unmap_mode = false;
bool prep_xaiger_mode = false;
bool prep_lut_mode = false;
bool prep_box_mode = false;
@@ -1177,53 +1633,81 @@ struct Abc9OpsPass : public Pass {
int maxlut = 0;
std::string write_box_dst;
+ bool valid = false;
size_t argidx;
for (argidx = 1; argidx < args.size(); argidx++) {
std::string arg = args[argidx];
if (arg == "-check") {
check_mode = true;
+ valid = true;
continue;
}
if (arg == "-mark_scc") {
mark_scc_mode = true;
+ valid = true;
+ continue;
+ }
+ if (arg == "-prep_hier") {
+ prep_hier_mode = true;
+ valid = true;
+ continue;
+ }
+ if (arg == "-prep_bypass") {
+ prep_bypass_mode = true;
+ valid = true;
continue;
}
if (arg == "-prep_dff") {
prep_dff_mode = true;
+ valid = true;
+ continue;
+ }
+ if (arg == "-prep_dff_submod") {
+ prep_dff_submod_mode = true;
+ valid = true;
+ continue;
+ }
+ if (arg == "-prep_dff_unmap") {
+ prep_dff_unmap_mode = true;
+ valid = true;
continue;
}
if (arg == "-prep_xaiger") {
prep_xaiger_mode = true;
+ valid = true;
continue;
}
if (arg == "-prep_delays") {
prep_delays_mode = true;
+ valid = true;
continue;
}
if (arg == "-prep_lut" && argidx+1 < args.size()) {
prep_lut_mode = true;
maxlut = atoi(args[++argidx].c_str());
- continue;
- }
- if (arg == "-maxlut" && argidx+1 < args.size()) {
+ valid = true;
continue;
}
if (arg == "-write_lut" && argidx+1 < args.size()) {
write_lut_dst = args[++argidx];
rewrite_filename(write_lut_dst);
+ valid = true;
continue;
}
if (arg == "-prep_box") {
prep_box_mode = true;
+ valid = true;
continue;
}
if (arg == "-write_box" && argidx+1 < args.size()) {
write_box_dst = args[++argidx];
rewrite_filename(write_box_dst);
+ valid = true;
continue;
}
if (arg == "-reintegrate") {
reintegrate_mode = true;
+ valid = true;
continue;
}
if (arg == "-dff") {
@@ -1234,25 +1718,32 @@ struct Abc9OpsPass : public Pass {
}
extra_args(args, argidx, design);
- if (!(check_mode || mark_scc_mode || prep_delays_mode || prep_xaiger_mode || prep_dff_mode || prep_lut_mode || prep_box_mode || !write_lut_dst.empty() || !write_box_dst.empty() || reintegrate_mode))
- log_cmd_error("At least one of -check, -mark_scc, -prep_{delays,xaiger,dff,lut,box}, -write_{lut,box}, -reintegrate must be specified.\n");
+ if (!valid)
+ log_cmd_error("At least one of -check, -mark_scc, -prep_{delays,xaiger,dff[123],lut,box}, -write_{lut,box}, -reintegrate must be specified.\n");
- if (dff_mode && !prep_delays_mode && !prep_xaiger_mode && !prep_box_mode)
- log_cmd_error("'-dff' option is only relevant for -prep_{delay,xaiger,box}.\n");
+ if (dff_mode && !check_mode && !prep_hier_mode && !prep_delays_mode && !prep_xaiger_mode && !reintegrate_mode)
+ log_cmd_error("'-dff' option is only relevant for -prep_{hier,delay,xaiger} or -reintegrate.\n");
if (check_mode)
- check(design);
+ check(design, dff_mode);
+ if (prep_hier_mode)
+ prep_hier(design, dff_mode);
+ if (prep_bypass_mode)
+ prep_bypass(design);
+ if (prep_dff_mode)
+ prep_dff(design);
+ if (prep_dff_submod_mode)
+ prep_dff_submod(design);
+ if (prep_dff_unmap_mode)
+ prep_dff_unmap(design);
if (prep_delays_mode)
prep_delays(design, dff_mode);
if (prep_lut_mode)
prep_lut(design, maxlut);
if (prep_box_mode)
- prep_box(design, dff_mode);
+ prep_box(design);
for (auto mod : design->selected_modules()) {
- if (mod->get_bool_attribute(ID::abc9_holes))
- continue;
-
if (mod->processes.size() > 0) {
log("Skipping module %s as it contains processes.\n", log_id(mod));
continue;
@@ -1267,12 +1758,10 @@ struct Abc9OpsPass : public Pass {
write_box(mod, write_box_dst);
if (mark_scc_mode)
mark_scc(mod);
- if (prep_dff_mode)
- prep_dff(mod);
if (prep_xaiger_mode)
prep_xaiger(mod, dff_mode);
if (reintegrate_mode)
- reintegrate(mod);
+ reintegrate(mod, dff_mode);
}
}
} Abc9OpsPass;
diff --git a/passes/techmap/aigmap.cc b/passes/techmap/aigmap.cc
index 2ecb2f35a..ce151c7f3 100644
--- a/passes/techmap/aigmap.cc
+++ b/passes/techmap/aigmap.cc
@@ -25,7 +25,7 @@ PRIVATE_NAMESPACE_BEGIN
struct AigmapPass : public Pass {
AigmapPass() : Pass("aigmap", "map logic to and-inverter-graph circuit") { }
- void help() YS_OVERRIDE
+ void help() override
{
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
log("\n");
@@ -43,7 +43,7 @@ struct AigmapPass : public Pass {
log("\n");
}
- void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
+ void execute(std::vector<std::string> args, RTLIL::Design *design) override
{
bool nand_mode = false, select_mode = false;
diff --git a/passes/techmap/alumacc.cc b/passes/techmap/alumacc.cc
index 1925145d3..b16e9750e 100644
--- a/passes/techmap/alumacc.cc
+++ b/passes/techmap/alumacc.cc
@@ -550,7 +550,7 @@ struct AlumaccWorker
struct AlumaccPass : public Pass {
AlumaccPass() : Pass("alumacc", "extract ALU and MACC cells") { }
- void help() YS_OVERRIDE
+ void help() override
{
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
log("\n");
@@ -560,7 +560,7 @@ struct AlumaccPass : public Pass {
log("and $macc cells.\n");
log("\n");
}
- void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
+ void execute(std::vector<std::string> args, RTLIL::Design *design) override
{
log_header(design, "Executing ALUMACC pass (create $alu and $macc cells).\n");
diff --git a/passes/techmap/attrmap.cc b/passes/techmap/attrmap.cc
index 5f30817d4..8643543c8 100644
--- a/passes/techmap/attrmap.cc
+++ b/passes/techmap/attrmap.cc
@@ -81,7 +81,7 @@ struct AttrmapAction {
struct AttrmapTocase : AttrmapAction {
string name;
- bool apply(IdString &id, Const&) YS_OVERRIDE {
+ bool apply(IdString &id, Const&) override {
if (match_name(name, id, true))
id = RTLIL::escape_id(name);
return true;
@@ -90,7 +90,7 @@ struct AttrmapTocase : AttrmapAction {
struct AttrmapRename : AttrmapAction {
string old_name, new_name;
- bool apply(IdString &id, Const&) YS_OVERRIDE {
+ bool apply(IdString &id, Const&) override {
if (match_name(old_name, id))
id = RTLIL::escape_id(new_name);
return true;
@@ -101,7 +101,7 @@ struct AttrmapMap : AttrmapAction {
bool imap;
string old_name, new_name;
string old_value, new_value;
- bool apply(IdString &id, Const &val) YS_OVERRIDE {
+ bool apply(IdString &id, Const &val) override {
if (match_name(old_name, id) && match_value(old_value, val, true)) {
id = RTLIL::escape_id(new_name);
val = make_value(new_value);
@@ -113,7 +113,7 @@ struct AttrmapMap : AttrmapAction {
struct AttrmapRemove : AttrmapAction {
bool has_value;
string name, value;
- bool apply(IdString &id, Const &val) YS_OVERRIDE {
+ bool apply(IdString &id, Const &val) override {
return !(match_name(name, id) && (!has_value || match_value(value, val)));
}
};
@@ -221,7 +221,7 @@ bool parse_attrmap_paramap_options(size_t &argidx, std::vector<std::string> &arg
struct AttrmapPass : public Pass {
AttrmapPass() : Pass("attrmap", "renaming attributes") { }
- void help() YS_OVERRIDE
+ void help() override
{
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
log("\n");
@@ -241,7 +241,7 @@ struct AttrmapPass : public Pass {
log(" -imap keep=\"false\" keep=0 -remove keep=0\n");
log("\n");
}
- void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
+ void execute(std::vector<std::string> args, RTLIL::Design *design) override
{
log_header(design, "Executing ATTRMAP pass (move or copy attributes).\n");
@@ -301,7 +301,7 @@ struct AttrmapPass : public Pass {
struct ParamapPass : public Pass {
ParamapPass() : Pass("paramap", "renaming cell parameters") { }
- void help() YS_OVERRIDE
+ void help() override
{
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
log("\n");
@@ -317,7 +317,7 @@ struct ParamapPass : public Pass {
log(" paramap -tocase INIT t:LUT4\n");
log("\n");
}
- void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
+ void execute(std::vector<std::string> args, RTLIL::Design *design) override
{
log_header(design, "Executing PARAMAP pass (move or copy cell parameters).\n");
diff --git a/passes/techmap/attrmvcp.cc b/passes/techmap/attrmvcp.cc
index e59aa6518..b3202c587 100644
--- a/passes/techmap/attrmvcp.cc
+++ b/passes/techmap/attrmvcp.cc
@@ -25,7 +25,7 @@ PRIVATE_NAMESPACE_BEGIN
struct AttrmvcpPass : public Pass {
AttrmvcpPass() : Pass("attrmvcp", "move or copy attributes from wires to driving cells") { }
- void help() YS_OVERRIDE
+ void help() override
{
log("\n");
log(" attrmvcp [options] [selection]\n");
@@ -53,7 +53,7 @@ struct AttrmvcpPass : public Pass {
log(" multiple times.\n");
log("\n");
}
- void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
+ void execute(std::vector<std::string> args, RTLIL::Design *design) override
{
log_header(design, "Executing ATTRMVCP pass (move or copy attributes).\n");
diff --git a/passes/techmap/clkbufmap.cc b/passes/techmap/clkbufmap.cc
index 3f4b6aa66..451325fee 100644
--- a/passes/techmap/clkbufmap.cc
+++ b/passes/techmap/clkbufmap.cc
@@ -35,7 +35,7 @@ void split_portname_pair(std::string &port1, std::string &port2)
struct ClkbufmapPass : public Pass {
ClkbufmapPass() : Pass("clkbufmap", "insert global buffers on clock networks") { }
- void help() YS_OVERRIDE
+ void help() override
{
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
log("\n");
@@ -76,7 +76,7 @@ struct ClkbufmapPass : public Pass {
modules_processed.insert(module);
}
- void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
+ void execute(std::vector<std::string> args, RTLIL::Design *design) override
{
log_header(design, "Executing CLKBUFMAP pass (inserting global clock buffers).\n");
diff --git a/passes/techmap/deminout.cc b/passes/techmap/deminout.cc
index a7dce9c81..9a23cb90e 100644
--- a/passes/techmap/deminout.cc
+++ b/passes/techmap/deminout.cc
@@ -25,7 +25,7 @@ PRIVATE_NAMESPACE_BEGIN
struct DeminoutPass : public Pass {
DeminoutPass() : Pass("deminout", "demote inout ports to input or output") { }
- void help() YS_OVERRIDE
+ void help() override
{
log("\n");
log(" deminout [options] [selection]\n");
@@ -33,7 +33,7 @@ struct DeminoutPass : public Pass {
log("\"Demote\" inout ports to input or output ports, if possible.\n");
log("\n");
}
- void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
+ void execute(std::vector<std::string> args, RTLIL::Design *design) override
{
log_header(design, "Executing DEMINOUT pass (demote inout ports to input or output).\n");
diff --git a/passes/techmap/dff2dffe.cc b/passes/techmap/dff2dffe.cc
index aa9bbfe17..62ee3fea6 100644
--- a/passes/techmap/dff2dffe.cc
+++ b/passes/techmap/dff2dffe.cc
@@ -253,7 +253,7 @@ struct Dff2dffeWorker
struct Dff2dffePass : public Pass {
Dff2dffePass() : Pass("dff2dffe", "transform $dff cells to $dffe cells") { }
- void help() YS_OVERRIDE
+ void help() override
{
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
log("\n");
@@ -282,13 +282,13 @@ struct Dff2dffePass : public Pass {
log("\n");
log(" -direct-match <pattern>\n");
log(" like -direct for all DFF cell types matching the expression.\n");
- log(" this will use $__DFFE_* as <external_gate_type> matching the\n");
- log(" internal gate type $_DFF_*_, and $__DFFSE_* for those matching\n");
- log(" $_DFFS_*_, except for $_DFF_[NP]_, which is converted to \n");
+ log(" this will use $_DFFE_* as <external_gate_type> matching the\n");
+ log(" internal gate type $_DFF_*_, and $_SDFFE_* for those matching\n");
+ log(" $_SDFF_*_, except for $_DFF_[NP]_, which is converted to \n");
log(" $_DFFE_[NP]_.\n");
log("\n");
}
- void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
+ void execute(std::vector<std::string> args, RTLIL::Design *design) override
{
log_header(design, "Executing DFF2DFFE pass (transform $dff to $dffe where applicable).\n");
@@ -318,23 +318,23 @@ struct Dff2dffePass : public Pass {
const char *pattern = args[++argidx].c_str();
if (patmatch(pattern, "$_DFF_P_" )) found_match = true, direct_dict[ID($_DFF_P_) ] = ID($_DFFE_PP_);
if (patmatch(pattern, "$_DFF_N_" )) found_match = true, direct_dict[ID($_DFF_N_) ] = ID($_DFFE_NP_);
- if (patmatch(pattern, "$_DFF_NN0_")) found_match = true, direct_dict[ID($_DFF_NN0_)] = ID($__DFFE_NN0);
- if (patmatch(pattern, "$_DFF_NN1_")) found_match = true, direct_dict[ID($_DFF_NN1_)] = ID($__DFFE_NN1);
- if (patmatch(pattern, "$_DFF_NP0_")) found_match = true, direct_dict[ID($_DFF_NP0_)] = ID($__DFFE_NP0);
- if (patmatch(pattern, "$_DFF_NP1_")) found_match = true, direct_dict[ID($_DFF_NP1_)] = ID($__DFFE_NP1);
- if (patmatch(pattern, "$_DFF_PN0_")) found_match = true, direct_dict[ID($_DFF_PN0_)] = ID($__DFFE_PN0);
- if (patmatch(pattern, "$_DFF_PN1_")) found_match = true, direct_dict[ID($_DFF_PN1_)] = ID($__DFFE_PN1);
- if (patmatch(pattern, "$_DFF_PP0_")) found_match = true, direct_dict[ID($_DFF_PP0_)] = ID($__DFFE_PP0);
- if (patmatch(pattern, "$_DFF_PP1_")) found_match = true, direct_dict[ID($_DFF_PP1_)] = ID($__DFFE_PP1);
-
- if (patmatch(pattern, "$__DFFS_NN0_")) found_match = true, direct_dict[ID($__DFFS_NN0_)] = ID($__DFFSE_NN0);
- if (patmatch(pattern, "$__DFFS_NN1_")) found_match = true, direct_dict[ID($__DFFS_NN1_)] = ID($__DFFSE_NN1);
- if (patmatch(pattern, "$__DFFS_NP0_")) found_match = true, direct_dict[ID($__DFFS_NP0_)] = ID($__DFFSE_NP0);
- if (patmatch(pattern, "$__DFFS_NP1_")) found_match = true, direct_dict[ID($__DFFS_NP1_)] = ID($__DFFSE_NP1);
- if (patmatch(pattern, "$__DFFS_PN0_")) found_match = true, direct_dict[ID($__DFFS_PN0_)] = ID($__DFFSE_PN0);
- if (patmatch(pattern, "$__DFFS_PN1_")) found_match = true, direct_dict[ID($__DFFS_PN1_)] = ID($__DFFSE_PN1);
- if (patmatch(pattern, "$__DFFS_PP0_")) found_match = true, direct_dict[ID($__DFFS_PP0_)] = ID($__DFFSE_PP0);
- if (patmatch(pattern, "$__DFFS_PP1_")) found_match = true, direct_dict[ID($__DFFS_PP1_)] = ID($__DFFSE_PP1);
+ if (patmatch(pattern, "$_DFF_NN0_")) found_match = true, direct_dict[ID($_DFF_NN0_)] = ID($_DFFE_NN0P_);
+ if (patmatch(pattern, "$_DFF_NN1_")) found_match = true, direct_dict[ID($_DFF_NN1_)] = ID($_DFFE_NN1P_);
+ if (patmatch(pattern, "$_DFF_NP0_")) found_match = true, direct_dict[ID($_DFF_NP0_)] = ID($_DFFE_NP0P_);
+ if (patmatch(pattern, "$_DFF_NP1_")) found_match = true, direct_dict[ID($_DFF_NP1_)] = ID($_DFFE_NP1P_);
+ if (patmatch(pattern, "$_DFF_PN0_")) found_match = true, direct_dict[ID($_DFF_PN0_)] = ID($_DFFE_PN0P_);
+ if (patmatch(pattern, "$_DFF_PN1_")) found_match = true, direct_dict[ID($_DFF_PN1_)] = ID($_DFFE_PN1P_);
+ if (patmatch(pattern, "$_DFF_PP0_")) found_match = true, direct_dict[ID($_DFF_PP0_)] = ID($_DFFE_PP0P_);
+ if (patmatch(pattern, "$_DFF_PP1_")) found_match = true, direct_dict[ID($_DFF_PP1_)] = ID($_DFFE_PP1P_);
+
+ if (patmatch(pattern, "$_SDFF_NN0_")) found_match = true, direct_dict[ID($_SDFF_NN0_)] = ID($_SDFFE_NN0P_);
+ if (patmatch(pattern, "$_SDFF_NN1_")) found_match = true, direct_dict[ID($_SDFF_NN1_)] = ID($_SDFFE_NN1P_);
+ if (patmatch(pattern, "$_SDFF_NP0_")) found_match = true, direct_dict[ID($_SDFF_NP0_)] = ID($_SDFFE_NP0P_);
+ if (patmatch(pattern, "$_SDFF_NP1_")) found_match = true, direct_dict[ID($_SDFF_NP1_)] = ID($_SDFFE_NP1P_);
+ if (patmatch(pattern, "$_SDFF_PN0_")) found_match = true, direct_dict[ID($_SDFF_PN0_)] = ID($_SDFFE_PN0P_);
+ if (patmatch(pattern, "$_SDFF_PN1_")) found_match = true, direct_dict[ID($_SDFF_PN1_)] = ID($_SDFFE_PN1P_);
+ if (patmatch(pattern, "$_SDFF_PP0_")) found_match = true, direct_dict[ID($_SDFF_PP0_)] = ID($_SDFFE_PP0P_);
+ if (patmatch(pattern, "$_SDFF_PP1_")) found_match = true, direct_dict[ID($_SDFF_PP1_)] = ID($_SDFFE_PP1P_);
if (!found_match)
log_cmd_error("No cell types matched pattern '%s'.\n", pattern);
continue;
diff --git a/passes/techmap/dff2dffs.cc b/passes/techmap/dff2dffs.cc
index c155297d9..6c2cca4bc 100644
--- a/passes/techmap/dff2dffs.cc
+++ b/passes/techmap/dff2dffs.cc
@@ -26,12 +26,12 @@ PRIVATE_NAMESPACE_BEGIN
struct Dff2dffsPass : public Pass {
Dff2dffsPass() : Pass("dff2dffs", "process sync set/reset with SR over CE priority") { }
- void help() YS_OVERRIDE
+ void help() override
{
log("\n");
log(" dff2dffs [options] [selection]\n");
log("\n");
- log("Merge synchronous set/reset $_MUX_ cells to create $__DFFS_[NP][NP][01], to be run before\n");
+ log("Merge synchronous set/reset $_MUX_ cells to create $_SDFF_[NP][NP][01]_, to be run before\n");
log("dff2dffe for SR over CE priority.\n");
log("\n");
log(" -match-init\n");
@@ -39,7 +39,7 @@ struct Dff2dffsPass : public Pass {
log(" output wire's init attribute (if any).\n");
log("\n");
}
- void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
+ void execute(std::vector<std::string> args, RTLIL::Design *design) override
{
log_header(design, "Executing dff2dffs pass (merge synchronous set/reset into FF cells).\n");
@@ -138,21 +138,21 @@ struct Dff2dffsPass : public Pass {
if (sr_val == State::S1) {
if (cell->type == ID($_DFF_N_)) {
- if (invert_sr) cell->type = ID($__DFFS_NN1_);
- else cell->type = ID($__DFFS_NP1_);
+ if (invert_sr) cell->type = ID($_SDFF_NN1_);
+ else cell->type = ID($_SDFF_NP1_);
} else {
log_assert(cell->type == ID($_DFF_P_));
- if (invert_sr) cell->type = ID($__DFFS_PN1_);
- else cell->type = ID($__DFFS_PP1_);
+ if (invert_sr) cell->type = ID($_SDFF_PN1_);
+ else cell->type = ID($_SDFF_PP1_);
}
} else {
if (cell->type == ID($_DFF_N_)) {
- if (invert_sr) cell->type = ID($__DFFS_NN0_);
- else cell->type = ID($__DFFS_NP0_);
+ if (invert_sr) cell->type = ID($_SDFF_NN0_);
+ else cell->type = ID($_SDFF_NP0_);
} else {
log_assert(cell->type == ID($_DFF_P_));
- if (invert_sr) cell->type = ID($__DFFS_PN0_);
- else cell->type = ID($__DFFS_PP0_);
+ if (invert_sr) cell->type = ID($_SDFF_PN0_);
+ else cell->type = ID($_SDFF_PP0_);
}
}
cell->setPort(ID::R, sr_sig);
diff --git a/passes/techmap/dffinit.cc b/passes/techmap/dffinit.cc
index 35645582b..c60a901c1 100644
--- a/passes/techmap/dffinit.cc
+++ b/passes/techmap/dffinit.cc
@@ -25,7 +25,7 @@ PRIVATE_NAMESPACE_BEGIN
struct DffinitPass : public Pass {
DffinitPass() : Pass("dffinit", "set INIT param on FF cells") { }
- void help() YS_OVERRIDE
+ void help() override
{
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
log("\n");
@@ -54,7 +54,7 @@ struct DffinitPass : public Pass {
log(" the already defined initial value.\n");
log("\n");
}
- void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
+ void execute(std::vector<std::string> args, RTLIL::Design *design) override
{
log_header(design, "Executing DFFINIT pass (set INIT param on FF cells).\n");
diff --git a/passes/techmap/dfflegalize.cc b/passes/techmap/dfflegalize.cc
new file mode 100644
index 000000000..013f2d974
--- /dev/null
+++ b/passes/techmap/dfflegalize.cc
@@ -0,0 +1,1356 @@
+/*
+ * yosys -- Yosys Open SYnthesis Suite
+ *
+ * Copyright (C) 2020 Marcelina Kościelnicka <mwk@0x04.net>
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ */
+
+#include "kernel/yosys.h"
+#include "kernel/sigtools.h"
+
+USING_YOSYS_NAMESPACE
+PRIVATE_NAMESPACE_BEGIN
+
+enum FfType {
+ FF_DFF,
+ FF_DFFE,
+ FF_ADFF0,
+ FF_ADFF1,
+ FF_ADFFE0,
+ FF_ADFFE1,
+ FF_DFFSR,
+ FF_DFFSRE,
+ FF_SDFF0,
+ FF_SDFF1,
+ FF_SDFFE0,
+ FF_SDFFE1,
+ FF_SDFFCE0,
+ FF_SDFFCE1,
+ FF_SR,
+ FF_DLATCH,
+ FF_ADLATCH0,
+ FF_ADLATCH1,
+ FF_DLATCHSR,
+ NUM_FFTYPES,
+};
+
+enum FfNeg {
+ NEG_R = 0x1,
+ NEG_S = 0x2,
+ NEG_E = 0x4,
+ NEG_C = 0x8,
+ NUM_NEG = 0x10,
+};
+
+enum FfInit {
+ INIT_X = 0x1,
+ INIT_0 = 0x2,
+ INIT_1 = 0x4,
+};
+
+struct DffLegalizePass : public Pass {
+ DffLegalizePass() : Pass("dfflegalize", "convert FFs to types supported by the target") { }
+ void help() override
+ {
+ // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
+ log("\n");
+ log(" dfflegalize [options] [selection]\n");
+ log("\n");
+ log("Converts FFs to types supported by the target.\n");
+ log("\n");
+ log(" -cell <cell_type_pattern> <init_values>\n");
+ log(" specifies a supported group of FF cells. <cell_type_pattern>\n");
+ log(" is a yosys internal fine cell name, where ? characters can be\n");
+ log(" as a wildcard matching any character. <init_values> specifies\n");
+ log(" which initialization values these FF cells can support, and can\n");
+ log(" be one of:\n");
+ log("\n");
+ log(" - x (no init value supported)\n");
+ log(" - 0\n");
+ log(" - 1\n");
+ log(" - r (init value has to match reset value, only for some FF types)\n");
+ log(" - 01 (both 0 and 1 supported).\n");
+ log("\n");
+ log(" -mince <num>\n");
+ log(" specifies a minimum number of FFs that should be using any given\n");
+ log(" clock enable signal. If a clock enable signal doesn't meet this\n");
+ log(" threshold, it is unmapped into soft logic.\n");
+ log("\n");
+ log(" -minsrst <num>\n");
+ log(" specifies a minimum number of FFs that should be using any given\n");
+ log(" sync set/reset signal. If a sync set/reset signal doesn't meet this\n");
+ log(" threshold, it is unmapped into soft logic.\n");
+ log("\n");
+ log("The following cells are supported by this pass (ie. will be ingested,\n");
+ log("and can be specified as allowed targets):\n");
+ log("\n");
+ log("- $_DFF_[NP]_\n");
+ log("- $_DFFE_[NP][NP]_\n");
+ log("- $_DFF_[NP][NP][01]_\n");
+ log("- $_DFFE_[NP][NP][01][NP]_\n");
+ log("- $_DFFSR_[NP][NP][NP]_\n");
+ log("- $_DFFSRE_[NP][NP][NP][NP]_\n");
+ log("- $_SDFF_[NP][NP][01]_\n");
+ log("- $_SDFFE_[NP][NP][01][NP]_\n");
+ log("- $_SDFFCE_[NP][NP][01][NP]_\n");
+ log("- $_SR_[NP][NP]_\n");
+ log("- $_DLATCH_[NP]_\n");
+ log("- $_DLATCH_[NP][NP][01]_\n");
+ log("- $_DLATCHSR_[NP][NP][NP]_\n");
+ log("\n");
+ log("The following transformations are performed by this pass:");
+ log("");
+ log("- upconversion from a less capable cell to a more capable cell, if the less");
+ log(" capable cell is not supported (eg. dff -> dffe, or adff -> dffsr)");
+ log("");
+ log("- unmapping FFs with clock enable (due to unsupported cell type or -mince)");
+ log("");
+ log("- unmapping FFs with sync reset (due to unsupported cell type or -minsrst)");
+ log("");
+ log("- adding inverters on the control pins (due to unsupported polarity)");
+ log("");
+ log("- adding inverters on the D and Q pins and inverting the init/reset values\n");
+ log(" (due to unsupported init or reset value)");
+ log("");
+ log("- converting sr into adlatch (by tying D to 1 and using E as set input)");
+ log("");
+ log("- emulating unsupported dffsr cell by adff + adff + sr + mux");
+ log("");
+ log("- emulating unsupported dlatchsr cell by adlatch + adlatch + sr + mux");
+ log("");
+ log("- emulating adff when the (reset, init) value combination is unsupported by\n");
+ log(" dff + adff + dlatch + mux");
+ log("");
+ log("- emulating adlatch when the (reset, init) value combination is unsupported by\n");
+ log("- dlatch + adlatch + dlatch + mux");
+ log("");
+ log("If the pass is unable to realize a given cell type (eg. adff when only plain dff");
+ log("is available), an error is raised.");
+ }
+
+ // Table of all supported cell types.
+ // First index in the array is one of the FF_* values, second
+ // index is the set of negative-polarity inputs (OR of NEG_*
+ // values), and the value is the set of supported init values
+ // (OR of INIT_* values).
+ int supported_cells_neg[NUM_FFTYPES][NUM_NEG];
+ // Aggregated table ignoring signal polarity.
+ int supported_cells[NUM_FFTYPES];
+ // Aggregated for all *dff* cells.
+ int supported_dff;
+ // Aggregated for all dffsr* cells.
+ int supported_dffsr;
+ // Aggregated for all adff* cells.
+ int supported_adff0;
+ int supported_adff1;
+ // Aggregated for all sdff* cells.
+ int supported_sdff0;
+ int supported_sdff1;
+ // Aggregated for all ways to obtain a SR latch.
+ int supported_sr;
+ // Aggregated for all *dlatch* cells.
+ int supported_dlatch;
+
+ int mince;
+ int minsrst;
+
+ dict<SigBit, int> ce_used;
+ dict<SigBit, int> srst_used;
+
+ SigMap sigmap;
+ dict<SigBit, std::pair<State,SigBit>> initbits;
+
+ int flip_initmask(int mask) {
+ int res = mask & INIT_X;
+ if (mask & INIT_0)
+ res |= INIT_1;
+ if (mask & INIT_1)
+ res |= INIT_0;
+ return res;
+ }
+
+ void handle_ff(Cell *cell) {
+ std::string type_str = cell->type.str();
+
+ FfType ff_type;
+ int ff_neg = 0;
+ SigSpec sig_d;
+ SigSpec sig_q;
+ SigSpec sig_c;
+ SigSpec sig_e;
+ SigSpec sig_r;
+ SigSpec sig_s;
+ bool has_srst = false;
+
+ if (cell->hasPort(ID::D))
+ sig_d = cell->getPort(ID::D);
+ if (cell->hasPort(ID::Q))
+ sig_q = cell->getPort(ID::Q);
+ if (cell->hasPort(ID::C))
+ sig_c = cell->getPort(ID::C);
+ if (cell->hasPort(ID::E))
+ sig_e = cell->getPort(ID::E);
+ if (cell->hasPort(ID::R))
+ sig_r = cell->getPort(ID::R);
+ if (cell->hasPort(ID::S))
+ sig_s = cell->getPort(ID::S);
+
+ if (type_str.substr(0, 5) == "$_SR_") {
+ ff_type = FF_SR;
+ if (type_str[5] == 'N')
+ ff_neg |= NEG_S;
+ if (type_str[6] == 'N')
+ ff_neg |= NEG_R;
+ } else if (type_str.substr(0, 6) == "$_DFF_" && type_str.size() == 8) {
+ ff_type = FF_DFF;
+ if (type_str[6] == 'N')
+ ff_neg |= NEG_C;
+ } else if (type_str.substr(0, 7) == "$_DFFE_" && type_str.size() == 10) {
+ ff_type = FF_DFFE;
+ if (type_str[7] == 'N')
+ ff_neg |= NEG_C;
+ if (type_str[8] == 'N')
+ ff_neg |= NEG_E;
+ } else if (type_str.substr(0, 6) == "$_DFF_" && type_str.size() == 10) {
+ ff_type = type_str[8] == '1' ? FF_ADFF1 : FF_ADFF0;
+ if (type_str[6] == 'N')
+ ff_neg |= NEG_C;
+ if (type_str[7] == 'N')
+ ff_neg |= NEG_R;
+ } else if (type_str.substr(0, 7) == "$_DFFE_" && type_str.size() == 12) {
+ ff_type = type_str[9] == '1' ? FF_ADFFE1 : FF_ADFFE0;
+ if (type_str[7] == 'N')
+ ff_neg |= NEG_C;
+ if (type_str[8] == 'N')
+ ff_neg |= NEG_R;
+ if (type_str[10] == 'N')
+ ff_neg |= NEG_E;
+ } else if (type_str.substr(0, 8) == "$_DFFSR_" && type_str.size() == 12) {
+ ff_type = FF_DFFSR;
+ if (type_str[8] == 'N')
+ ff_neg |= NEG_C;
+ if (type_str[9] == 'N')
+ ff_neg |= NEG_S;
+ if (type_str[10] == 'N')
+ ff_neg |= NEG_R;
+ } else if (type_str.substr(0, 9) == "$_DFFSRE_" && type_str.size() == 14) {
+ ff_type = FF_DFFSRE;
+ if (type_str[9] == 'N')
+ ff_neg |= NEG_C;
+ if (type_str[10] == 'N')
+ ff_neg |= NEG_S;
+ if (type_str[11] == 'N')
+ ff_neg |= NEG_R;
+ if (type_str[12] == 'N')
+ ff_neg |= NEG_E;
+ } else if (type_str.substr(0, 7) == "$_SDFF_" && type_str.size() == 11) {
+ ff_type = type_str[9] == '1' ? FF_SDFF1 : FF_SDFF0;
+ if (type_str[7] == 'N')
+ ff_neg |= NEG_C;
+ if (type_str[8] == 'N')
+ ff_neg |= NEG_R;
+ has_srst = true;
+ } else if (type_str.substr(0, 8) == "$_SDFFE_" && type_str.size() == 13) {
+ ff_type = type_str[10] == '1' ? FF_SDFFE1 : FF_SDFFE0;
+ if (type_str[8] == 'N')
+ ff_neg |= NEG_C;
+ if (type_str[9] == 'N')
+ ff_neg |= NEG_R;
+ if (type_str[11] == 'N')
+ ff_neg |= NEG_E;
+ has_srst = true;
+ } else if (type_str.substr(0, 9) == "$_SDFFCE_" && type_str.size() == 14) {
+ ff_type = type_str[11] == '1' ? FF_SDFFCE1 : FF_SDFFCE0;
+ if (type_str[9] == 'N')
+ ff_neg |= NEG_C;
+ if (type_str[10] == 'N')
+ ff_neg |= NEG_R;
+ if (type_str[12] == 'N')
+ ff_neg |= NEG_E;
+ has_srst = true;
+ } else if (type_str.substr(0, 9) == "$_DLATCH_" && type_str.size() == 11) {
+ ff_type = FF_DLATCH;
+ if (type_str[9] == 'N')
+ ff_neg |= NEG_E;
+ } else if (type_str.substr(0, 9) == "$_DLATCH_" && type_str.size() == 13) {
+ ff_type = type_str[11] == '1' ? FF_ADLATCH1 : FF_ADLATCH0;
+ if (type_str[9] == 'N')
+ ff_neg |= NEG_E;
+ if (type_str[10] == 'N')
+ ff_neg |= NEG_R;
+ } else if (type_str.substr(0, 11) == "$_DLATCHSR_" && type_str.size() == 15) {
+ ff_type = FF_DLATCHSR;
+ if (type_str[11] == 'N')
+ ff_neg |= NEG_E;
+ if (type_str[12] == 'N')
+ ff_neg |= NEG_S;
+ if (type_str[13] == 'N')
+ ff_neg |= NEG_R;
+ } else {
+ log_warning("Ignoring unknown ff type %s [%s.%s].\n", log_id(cell->type), log_id(cell->module->name), log_id(cell->name));
+ return;
+ }
+
+ State initval = State::Sx;
+ SigBit initbit;
+ if (GetSize(sig_q) > 0 && initbits.count(sigmap(sig_q[0]))) {
+ const auto &d = initbits.at(sigmap(sig_q[0]));
+ initval = d.first;
+ initbit = d.second;
+ }
+
+ FfInit initmask = INIT_X;
+ if (initval == State::S0)
+ initmask = INIT_0;
+ else if (initval == State::S1)
+ initmask = INIT_1;
+ const char *reason;
+
+ bool kill_ce = mince && GetSize(sig_c) && GetSize(sig_e) && sig_e[0].wire && ce_used[sig_e[0]] < mince;
+ bool kill_srst = minsrst && has_srst && sig_r[0].wire && srst_used[sig_r[0]] < minsrst;
+
+ while (!(supported_cells[ff_type] & initmask) || kill_ce || kill_srst) {
+ // Well, cell is not directly supported. Decide how to deal with it.
+
+ if (ff_type == FF_DFF || ff_type == FF_DFFE) {
+ if (kill_ce) {
+ ff_type = FF_DFF;
+ goto unmap_enable;
+ }
+ if (!(supported_dff & initmask)) {
+ // This init value is not supported at all...
+ if (supported_dff & flip_initmask(initmask)) {
+ // The other one is, though. Negate D, Q, and init.
+flip_dqi:
+ if (initval == State::S0) {
+ initval = State::S1;
+ initmask = INIT_1;
+ } else if (initval == State::S1) {
+ initval = State::S0;
+ initmask = INIT_0;
+ }
+ if (ff_type != FF_SR)
+ sig_d = cell->module->NotGate(NEW_ID, sig_d[0]);
+ SigBit new_q = SigSpec(cell->module->addWire(NEW_ID))[0];
+ cell->module->addNotGate(NEW_ID, new_q, sig_q[0]);
+ if (initbit.wire) {
+ initbit.wire->attributes.at(ID::init)[initbit.offset] = State::Sx;
+ initbit = new_q;
+ new_q.wire->attributes[ID::init] = initval;
+ initbits[new_q] = std::make_pair(initval, new_q);
+ }
+ sig_q = new_q;
+ continue;
+ }
+ if (!supported_dff)
+ reason = "dffs are not supported";
+ else
+ reason = "initialized dffs are not supported";
+ goto error;
+ }
+
+ // Some DFF is supported with this init val. Just pick a type.
+ if (ff_type == FF_DFF) {
+ // Try adding a set or reset pin.
+ for (auto new_type: {FF_ADFF0, FF_ADFF1, FF_SDFF0, FF_SDFF1})
+ if (supported_cells[new_type] & initmask) {
+ ff_type = new_type;
+ sig_r = State::S0;
+ goto cell_ok;
+ }
+ // Try adding both.
+ if (supported_cells[FF_DFFSR] & initmask) {
+ ff_type = FF_DFFSR;
+ sig_r = State::S0;
+ sig_s = State::S0;
+ break;
+ }
+ // Nope. Will need to add enable and go the DFFE route.
+ sig_e = State::S1;
+ if (supported_cells[FF_DFFE] & initmask) {
+ ff_type = FF_DFFE;
+ break;
+ }
+ }
+ // Try adding a set or reset pin.
+ for (auto new_type: {FF_SDFFE0, FF_SDFFE1, FF_SDFFCE0, FF_SDFFCE1, FF_ADFFE0, FF_ADFFE1})
+ if (supported_cells[new_type] & initmask) {
+ ff_type = new_type;
+ sig_r = State::S0;
+ goto cell_ok;
+ }
+ // Try adding both.
+ if (supported_cells[FF_DFFSRE] & initmask) {
+ ff_type = FF_DFFSRE;
+ sig_r = State::S0;
+ sig_s = State::S0;
+ break;
+ }
+
+ // Seems that no DFFs with enable are supported.
+ // The enable input needs to be unmapped.
+ // This should not be reached if we started from plain DFF.
+ log_assert(ff_type == FF_DFFE);
+ ff_type = FF_DFF;
+unmap_enable:
+ if (ff_neg & NEG_E)
+ sig_d = cell->module->MuxGate(NEW_ID, sig_d[0], sig_q[0], sig_e[0]);
+ else
+ sig_d = cell->module->MuxGate(NEW_ID, sig_q[0], sig_d[0], sig_e[0]);
+ ff_neg &= ~NEG_E;
+ sig_e = SigSpec();
+ kill_ce = false;
+ // Now try again as plain DFF.
+ continue;
+ } else if (ff_type == FF_ADFF0 || ff_type == FF_ADFF1 || ff_type == FF_ADFFE0 || ff_type == FF_ADFFE1) {
+ bool has_set = ff_type == FF_ADFF1 || ff_type == FF_ADFFE1;
+ bool has_en = ff_type == FF_ADFFE0 || ff_type == FF_ADFFE1;
+ if (kill_ce) {
+ ff_type = has_set ? FF_ADFF1 : FF_ADFF0;
+ goto unmap_enable;
+ }
+ if (!has_en && (supported_cells[has_set ? FF_ADFFE1 : FF_ADFFE0] & initmask)) {
+ // Just add enable.
+ sig_e = State::S1;
+ ff_type = has_set ? FF_ADFFE1 : FF_ADFFE0;
+ break;
+ }
+ if (supported_dffsr & initmask) {
+ // Throw in a set/reset, retry in DFFSR/DFFSRE branch.
+ if (has_set) {
+ sig_s = sig_r;
+ sig_r = State::S0;
+ if (ff_neg & NEG_R) {
+ ff_neg &= ~NEG_R;
+ ff_neg |= NEG_S;
+ }
+ } else {
+ sig_s = State::S0;
+ }
+ if (has_en)
+ ff_type = FF_DFFSRE;
+ else
+ ff_type = FF_DFFSR;
+ continue;
+ }
+ if (has_en && (supported_cells[has_set ? FF_ADFF1 : FF_ADFF0] & initmask)) {
+ // Unmap enable.
+ ff_type = has_set ? FF_ADFF1 : FF_ADFF0;
+ goto unmap_enable;
+ }
+ log_assert(!((has_set ? supported_adff1 : supported_adff0) & initmask));
+ // Alright, so this particular combination of initval and
+ // resetval is not natively supported. First, try flipping
+ // them both to see whether this helps.
+ int flipmask = flip_initmask(initmask);
+ if ((has_set ? supported_adff0 : supported_adff1) & flipmask) {
+ // Checks out, do it.
+ ff_type = has_en ? (has_set ? FF_ADFFE0 : FF_ADFFE1) : (has_set ? FF_ADFF0 : FF_ADFF1);
+ goto flip_dqi;
+ }
+
+ if (!supported_adff0 && !supported_adff1) {
+ reason = "dffs with async set or reset are not supported";
+ goto error;
+ }
+ if (!(supported_dff & ~INIT_X)) {
+ reason = "initialized dffs are not supported";
+ goto error;
+ }
+ // If we got here, initialized dff is supported, but not this
+ // particular reset+init combination (nor its negation).
+ // The only hope left is breaking down to adff + dff + dlatch + mux.
+ if (!(supported_dlatch & ~INIT_X)) {
+ reason = "unsupported initial value and async reset value combination";
+ goto error;
+ }
+
+ // If we have to unmap enable anyway, do it before breakdown.
+ if (has_en && !supported_cells[FF_ADFFE0] && !supported_cells[FF_ADFFE1]) {
+ ff_type = has_set ? FF_ADFF1 : FF_ADFF0;
+ goto unmap_enable;
+ }
+
+ log_warning("Emulating mismatched async reset and init with several FFs and a mux for %s.%s\n", log_id(cell->module->name), log_id(cell->name));
+ if (initbit.wire)
+ initbit.wire->attributes.at(ID::init)[initbit.offset] = State::Sx;
+ Wire *adff_q = cell->module->addWire(NEW_ID);
+ Wire *dff_q = cell->module->addWire(NEW_ID);
+ Wire *sel_q = cell->module->addWire(NEW_ID);
+ dff_q->attributes[ID::init] = initval;
+ initbits[SigBit(dff_q, 0)] = std::make_pair(initval, SigBit(dff_q, 0));
+ sel_q->attributes[ID::init] = State::S0;
+ initbits[SigBit(sel_q, 0)] = std::make_pair(State::S0, SigBit(sel_q, 0));
+ Cell *cell_dff;
+ Cell *cell_adff;
+ Cell *cell_sel;
+ if (!has_en) {
+ cell_dff = cell->module->addDffGate(NEW_ID, sig_c, sig_d, dff_q, !(ff_neg & NEG_C));
+ cell_adff = cell->module->addAdffGate(NEW_ID, sig_c, sig_r, sig_d, adff_q, has_set, !(ff_neg & NEG_C), !(ff_neg & NEG_R));
+ } else {
+ cell_dff = cell->module->addDffeGate(NEW_ID, sig_c, sig_e, sig_d, dff_q, !(ff_neg & NEG_C), !(ff_neg & NEG_E));
+ cell_adff = cell->module->addAdffeGate(NEW_ID, sig_c, sig_e, sig_r, sig_d, adff_q, has_set, !(ff_neg & NEG_C), !(ff_neg & NEG_E), !(ff_neg & NEG_R));
+ }
+ cell_sel = cell->module->addDlatchGate(NEW_ID, sig_r, State::S1, sel_q, !(ff_neg & NEG_R));
+ cell->module->addMuxGate(NEW_ID, dff_q, adff_q, sel_q, sig_q);
+
+ // Bye, cell.
+ cell->module->remove(cell);
+ handle_ff(cell_dff);
+ handle_ff(cell_adff);
+ handle_ff(cell_sel);
+ return;
+ } else if (ff_type == FF_DFFSR || ff_type == FF_DFFSRE) {
+ if (kill_ce) {
+ ff_type = FF_DFFSR;
+ goto unmap_enable;
+ }
+ // First, see if mapping/unmapping enable will help.
+ if (supported_cells[FF_DFFSRE] & initmask) {
+ ff_type = FF_DFFSRE;
+ sig_e = State::S1;
+ break;
+ }
+ if (supported_cells[FF_DFFSR] & initmask) {
+ ff_type = FF_DFFSR;
+ goto unmap_enable;
+ }
+ if (supported_dffsr & flip_initmask(initmask)) {
+flip_dqisr:;
+ log_warning("Flipping D/Q/init and inseerting set/reset fixup to handle init value on %s.%s [%s]\n", log_id(cell->module->name), log_id(cell->name), log_id(cell->type));
+ SigSpec new_r;
+ bool neg_r = (ff_neg & NEG_R);
+ bool neg_s = (ff_neg & NEG_S);
+ if (!(ff_neg & NEG_S)) {
+ if (!(ff_neg & NEG_R))
+ new_r = cell->module->AndnotGate(NEW_ID, sig_s, sig_r);
+ else
+ new_r = cell->module->AndGate(NEW_ID, sig_s, sig_r);
+ } else {
+ if (!(ff_neg & NEG_R))
+ new_r = cell->module->OrGate(NEW_ID, sig_s, sig_r);
+ else
+ new_r = cell->module->OrnotGate(NEW_ID, sig_s, sig_r);
+ }
+ ff_neg &= ~(NEG_R | NEG_S);
+ if (neg_r)
+ ff_neg |= NEG_S;
+ if (neg_s)
+ ff_neg |= NEG_R;
+ sig_s = sig_r;
+ sig_r = new_r;
+ goto flip_dqi;
+ }
+ // No native DFFSR. However, if we can conjure
+ // a SR latch and ADFF, it can still be emulated.
+ int flipmask = flip_initmask(initmask);
+ bool init0 = true;
+ bool init1 = true;
+ State initsel = State::Sx;
+ if (((supported_adff0 & initmask) || (supported_adff1 & flipmask)) && ((supported_adff1 & initmask) || (supported_adff0 & flipmask)) && supported_sr) {
+ // OK
+ } else if (((supported_adff0 & initmask) || (supported_adff1 & flipmask)) && (supported_sr & INIT_0)) {
+ init1 = false;
+ initsel = State::S0;
+ } else if (((supported_adff1 & initmask) || (supported_adff0 & flipmask)) && (supported_sr & INIT_1)) {
+ init0 = false;
+ initsel = State::S1;
+ } else if (((supported_adff0 & initmask) || (supported_adff1 & flipmask)) && (supported_sr & INIT_1)) {
+ init1 = false;
+ initsel = State::S0;
+ } else if (((supported_adff1 & initmask) || (supported_adff0 & flipmask)) && (supported_sr & INIT_0)) {
+ init0 = false;
+ initsel = State::S1;
+ } else {
+ if (!supported_dffsr)
+ reason = "dffs with async set and reset are not supported";
+ else
+ reason = "initialized dffs with async set and reset are not supported";
+ goto error;
+ }
+
+ // If we have to unmap enable anyway, do it before breakdown.
+ if (ff_type == FF_DFFSRE && !supported_cells[FF_ADFFE0] && !supported_cells[FF_ADFFE1]) {
+ ff_type = FF_DFFSR;
+ goto unmap_enable;
+ }
+
+ log_warning("Emulating async set + reset with several FFs and a mux for %s.%s\n", log_id(cell->module->name), log_id(cell->name));
+ if (initbit.wire)
+ initbit.wire->attributes.at(ID::init)[initbit.offset] = State::Sx;
+ Wire *adff0_q = cell->module->addWire(NEW_ID);
+ Wire *adff1_q = cell->module->addWire(NEW_ID);
+ Wire *sel_q = cell->module->addWire(NEW_ID);
+ if (init0) {
+ adff0_q->attributes[ID::init] = initval;
+ initbits[SigBit(adff0_q, 0)] = std::make_pair(initval, SigBit(adff0_q, 0));
+ }
+ if (init1) {
+ adff1_q->attributes[ID::init] = initval;
+ initbits[SigBit(adff1_q, 0)] = std::make_pair(initval, SigBit(adff1_q, 0));
+ }
+ sel_q->attributes[ID::init] = initsel;
+ initbits[SigBit(sel_q, 0)] = std::make_pair(initsel, SigBit(sel_q, 0));
+ Cell *cell_adff0;
+ Cell *cell_adff1;
+ Cell *cell_sel;
+ if (ff_type == FF_DFFSR) {
+ cell_adff0 = cell->module->addAdffGate(NEW_ID, sig_c, sig_r, sig_d, adff0_q, false, !(ff_neg & NEG_C), !(ff_neg & NEG_R));
+ cell_adff1 = cell->module->addAdffGate(NEW_ID, sig_c, sig_s, sig_d, adff1_q, true, !(ff_neg & NEG_C), !(ff_neg & NEG_S));
+ } else {
+ cell_adff0 = cell->module->addAdffeGate(NEW_ID, sig_c, sig_e, sig_r, sig_d, adff0_q, false, !(ff_neg & NEG_C), !(ff_neg & NEG_E), !(ff_neg & NEG_R));
+ cell_adff1 = cell->module->addAdffeGate(NEW_ID, sig_c, sig_e, sig_s, sig_d, adff1_q, true, !(ff_neg & NEG_C), !(ff_neg & NEG_E), !(ff_neg & NEG_S));
+ }
+ cell_sel = cell->module->addSrGate(NEW_ID, sig_s, sig_r, sel_q, !(ff_neg & NEG_S), !(ff_neg & NEG_R));
+ cell->module->addMuxGate(NEW_ID, adff0_q, adff1_q, sel_q, sig_q);
+
+ // Bye, cell.
+ cell->module->remove(cell);
+ handle_ff(cell_adff0);
+ handle_ff(cell_adff1);
+ handle_ff(cell_sel);
+ return;
+ } else if (ff_type == FF_SR) {
+ if (supported_cells[FF_ADLATCH0] & initmask || supported_cells[FF_ADLATCH1] & flip_initmask(initmask)) {
+ // Convert to ADLATCH0. May get converted to ADLATCH1.
+ ff_type = FF_ADLATCH0;
+ sig_e = sig_s;
+ sig_d = State::S1;
+ if (ff_neg & NEG_S) {
+ ff_neg &= ~NEG_S;
+ ff_neg |= NEG_E;
+ }
+ continue;
+ } else if (supported_cells[FF_DLATCHSR] & initmask) {
+ // Upgrade to DLATCHSR.
+ ff_type = FF_DLATCHSR;
+ sig_e = State::S0;
+ sig_d = State::Sx;
+ break;
+ } else if (supported_dffsr & initmask) {
+ // Upgrade to DFFSR. May get further upgraded to DFFSRE.
+ ff_type = FF_DFFSR;
+ sig_c = State::S0;
+ sig_d = State::Sx;
+ continue;
+ } else if (supported_sr & flip_initmask(initmask)) {
+ goto flip_dqisr;
+ } else {
+ if (!supported_sr)
+ reason = "sr latches are not supported";
+ else
+ reason = "initialized sr latches are not supported";
+ goto error;
+ }
+ } else if (ff_type == FF_DLATCH) {
+ if (!(supported_dlatch & initmask)) {
+ // This init value is not supported at all...
+ if (supported_dlatch & flip_initmask(initmask))
+ goto flip_dqi;
+ if (!supported_dlatch)
+ reason = "dlatch are not supported";
+ else
+ reason = "initialized dlatch are not supported";
+ goto error;
+ }
+
+ // Some DLATCH is supported with this init val. Just pick a type.
+ if (supported_cells[FF_ADLATCH0] & initmask) {
+ ff_type = FF_ADLATCH0;
+ sig_r = State::S0;
+ break;
+ }
+ if (supported_cells[FF_ADLATCH1] & initmask) {
+ ff_type = FF_ADLATCH1;
+ sig_r = State::S0;
+ break;
+ }
+ if (supported_cells[FF_DLATCHSR] & initmask) {
+ ff_type = FF_DLATCHSR;
+ sig_r = State::S0;
+ sig_s = State::S0;
+ break;
+ }
+ log_assert(0);
+ } else if (ff_type == FF_ADLATCH0 || ff_type == FF_ADLATCH1) {
+ if (supported_cells[FF_DLATCHSR] & initmask) {
+ if (ff_type == FF_ADLATCH1) {
+ sig_s = sig_r;
+ sig_r = State::S0;
+ if (ff_neg & NEG_R) {
+ ff_neg &= ~NEG_R;
+ ff_neg |= NEG_S;
+ }
+ } else {
+ sig_s = State::S0;
+ }
+ ff_type = FF_DLATCHSR;
+ break;
+ }
+ FfType flip_type = ff_type == FF_ADLATCH0 ? FF_ADLATCH1 : FF_ADLATCH0;
+ if ((supported_cells[flip_type] | supported_cells[FF_DLATCHSR]) & flip_initmask(initmask)) {
+ ff_type = flip_type;
+ goto flip_dqi;
+ }
+
+ if (!supported_cells[FF_ADLATCH0] && !supported_cells[FF_ADLATCH1] && !supported_cells[FF_DLATCHSR]) {
+ reason = "dlatch with async set or reset are not supported";
+ goto error;
+ }
+ if (!(supported_dlatch & ~INIT_X)) {
+ reason = "initialized dlatch are not supported";
+ goto error;
+ }
+
+ if (!(supported_dlatch & ~INIT_X)) {
+ reason = "initialized dlatch are not supported";
+ goto error;
+ }
+ // If we got here, initialized dlatch is supported, but not this
+ // particular reset+init combination (nor its negation).
+ // The only hope left is breaking down to adff + dff + dlatch + mux.
+
+ log_warning("Emulating mismatched async reset and init with several latches and a mux for %s.%s\n", log_id(cell->module->name), log_id(cell->name));
+ if (initbit.wire)
+ initbit.wire->attributes.at(ID::init)[initbit.offset] = State::Sx;
+ Wire *adlatch_q = cell->module->addWire(NEW_ID);
+ Wire *dlatch_q = cell->module->addWire(NEW_ID);
+ Wire *sel_q = cell->module->addWire(NEW_ID);
+ dlatch_q->attributes[ID::init] = initval;
+ initbits[SigBit(dlatch_q, 0)] = std::make_pair(initval, SigBit(dlatch_q, 0));
+ sel_q->attributes[ID::init] = State::S0;
+ initbits[SigBit(sel_q, 0)] = std::make_pair(State::S0, SigBit(sel_q, 0));
+ Cell *cell_dlatch;
+ Cell *cell_adlatch;
+ Cell *cell_sel;
+ cell_dlatch = cell->module->addDlatchGate(NEW_ID, sig_e, sig_d, dlatch_q, !(ff_neg & NEG_E));
+ cell_adlatch = cell->module->addAdlatchGate(NEW_ID, sig_e, sig_r, sig_d, adlatch_q, ff_type == FF_ADLATCH1, !(ff_neg & NEG_E), !(ff_neg & NEG_R));
+ cell_sel = cell->module->addDlatchGate(NEW_ID, sig_r, State::S1, sel_q, !(ff_neg & NEG_R));
+ cell->module->addMuxGate(NEW_ID, dlatch_q, adlatch_q, sel_q, sig_q);
+
+ // Bye, cell.
+ cell->module->remove(cell);
+ handle_ff(cell_dlatch);
+ handle_ff(cell_adlatch);
+ handle_ff(cell_sel);
+ return;
+ } else if (ff_type == FF_DLATCHSR) {
+ if (supported_cells[FF_DLATCHSR] & flip_initmask(initmask)) {
+ goto flip_dqisr;
+ }
+ // No native DFFSR. However, if we can conjure
+ // a SR latch and ADFF, it can still be emulated.
+ int flipmask = flip_initmask(initmask);
+ bool init0 = true;
+ bool init1 = true;
+ State initsel = State::Sx;
+ if (((supported_cells[FF_ADLATCH0] & initmask) || (supported_cells[FF_ADLATCH1] & flipmask)) && ((supported_cells[FF_ADLATCH1] & initmask) || (supported_cells[FF_ADLATCH0] & flipmask)) && supported_sr) {
+ // OK
+ } else if (((supported_cells[FF_ADLATCH0] & initmask) || (supported_cells[FF_ADLATCH1] & flipmask)) && (supported_sr & INIT_0)) {
+ init1 = false;
+ initsel = State::S0;
+ } else if (((supported_cells[FF_ADLATCH1] & initmask) || (supported_cells[FF_ADLATCH0] & flipmask)) && (supported_sr & INIT_1)) {
+ init0 = false;
+ initsel = State::S1;
+ } else if (((supported_cells[FF_ADLATCH0] & initmask) || (supported_cells[FF_ADLATCH1] & flipmask)) && (supported_sr & INIT_1)) {
+ init1 = false;
+ initsel = State::S0;
+ } else if (((supported_cells[FF_ADLATCH1] & initmask) || (supported_cells[FF_ADLATCH0] & flipmask)) && (supported_sr & INIT_0)) {
+ init0 = false;
+ initsel = State::S1;
+ } else {
+ if (!supported_cells[FF_DLATCHSR])
+ reason = "dlatch with async set and reset are not supported";
+ else
+ reason = "initialized dlatch with async set and reset are not supported";
+ goto error;
+ }
+
+ log_warning("Emulating async set + reset with several latches and a mux for %s.%s\n", log_id(cell->module->name), log_id(cell->name));
+ if (initbit.wire)
+ initbit.wire->attributes.at(ID::init)[initbit.offset] = State::Sx;
+ Wire *adlatch0_q = cell->module->addWire(NEW_ID);
+ Wire *adlatch1_q = cell->module->addWire(NEW_ID);
+ Wire *sel_q = cell->module->addWire(NEW_ID);
+ if (init0) {
+ adlatch0_q->attributes[ID::init] = initval;
+ initbits[SigBit(adlatch0_q, 0)] = std::make_pair(initval, SigBit(adlatch0_q, 0));
+ }
+ if (init1) {
+ adlatch1_q->attributes[ID::init] = initval;
+ initbits[SigBit(adlatch1_q, 0)] = std::make_pair(initval, SigBit(adlatch1_q, 0));
+ }
+ sel_q->attributes[ID::init] = initsel;
+ initbits[SigBit(sel_q, 0)] = std::make_pair(initsel, SigBit(sel_q, 0));
+ Cell *cell_adlatch0;
+ Cell *cell_adlatch1;
+ Cell *cell_sel;
+ cell_adlatch0 = cell->module->addAdlatchGate(NEW_ID, sig_e, sig_r, sig_d, adlatch0_q, false, !(ff_neg & NEG_E), !(ff_neg & NEG_R));
+ cell_adlatch1 = cell->module->addAdlatchGate(NEW_ID, sig_e, sig_s, sig_d, adlatch1_q, true, !(ff_neg & NEG_E), !(ff_neg & NEG_S));
+ cell_sel = cell->module->addSrGate(NEW_ID, sig_s, sig_r, sel_q, !(ff_neg & NEG_S), !(ff_neg & NEG_R));
+ cell->module->addMuxGate(NEW_ID, adlatch0_q, adlatch1_q, sel_q, sig_q);
+
+ // Bye, cell.
+ cell->module->remove(cell);
+ handle_ff(cell_adlatch0);
+ handle_ff(cell_adlatch1);
+ handle_ff(cell_sel);
+ return;
+ } else if (ff_type == FF_SDFF0 || ff_type == FF_SDFF1 || ff_type == FF_SDFFE0 || ff_type == FF_SDFFE1 || ff_type == FF_SDFFCE0 || ff_type == FF_SDFFCE1) {
+ bool has_set = ff_type == FF_SDFF1 || ff_type == FF_SDFFE1 || ff_type == FF_SDFFCE1;
+ bool has_en = ff_type == FF_SDFFE0 || ff_type == FF_SDFFE1;
+ bool has_ce = ff_type == FF_SDFFCE0 || ff_type == FF_SDFFCE1;
+
+ if (has_en) {
+ if (kill_ce || kill_srst) {
+ ff_type = has_set ? FF_SDFF1 : FF_SDFF0;
+ goto unmap_enable;
+ }
+ } else if (has_ce) {
+ if (kill_ce || kill_srst)
+ goto unmap_srst;
+ } else {
+ log_assert(!kill_ce);
+ if (kill_srst)
+ goto unmap_srst;
+ }
+
+ if (!has_ce) {
+ if (!has_en && (supported_cells[has_set ? FF_SDFFE1 : FF_SDFFE0] & initmask)) {
+ // Just add enable.
+ sig_e = State::S1;
+ ff_type = has_set ? FF_SDFFE1 : FF_SDFFE0;
+ break;
+ }
+ if (!has_en && (supported_cells[has_set ? FF_SDFFCE1 : FF_SDFFCE0] & initmask)) {
+ // Just add enable.
+ sig_e = State::S1;
+ ff_type = has_set ? FF_SDFFCE1 : FF_SDFFCE0;
+ break;
+ }
+ if (has_en && (supported_cells[has_set ? FF_SDFFCE1 : FF_SDFFCE0] & initmask)) {
+ // Convert sdffe to sdffce
+ if (!(ff_neg & NEG_E)) {
+ if (!(ff_neg & NEG_R))
+ sig_e = cell->module->OrGate(NEW_ID, sig_e, sig_r);
+ else
+ sig_e = cell->module->OrnotGate(NEW_ID, sig_e, sig_r);
+ } else {
+ if (!(ff_neg & NEG_R))
+ sig_e = cell->module->AndnotGate(NEW_ID, sig_e, sig_r);
+ else
+ sig_e = cell->module->AndGate(NEW_ID, sig_e, sig_r);
+ }
+ ff_type = has_set ? FF_SDFFCE1 : FF_SDFFCE0;
+ break;
+ }
+ if (has_en && (supported_cells[has_set ? FF_SDFF1 : FF_SDFF0] & initmask)) {
+ // Unmap enable.
+ ff_type = has_set ? FF_SDFF1 : FF_SDFF0;
+ goto unmap_enable;
+ }
+ log_assert(!((has_set ? supported_sdff1 : supported_sdff0) & initmask));
+ } else {
+ if ((has_set ? supported_sdff1 : supported_sdff0) & initmask) {
+ // Convert sdffce to sdffe, which may be further converted to sdff.
+ if (!(ff_neg & NEG_R)) {
+ if (!(ff_neg & NEG_E))
+ sig_r = cell->module->AndGate(NEW_ID, sig_r, sig_e);
+ else
+ sig_r = cell->module->AndnotGate(NEW_ID, sig_r, sig_e);
+ } else {
+ if (!(ff_neg & NEG_E))
+ sig_r = cell->module->OrnotGate(NEW_ID, sig_r, sig_e);
+ else
+ sig_r = cell->module->OrGate(NEW_ID, sig_r, sig_e);
+ }
+ ff_type = has_set ? FF_SDFFE1 : FF_SDFFE0;
+ continue;
+ }
+ }
+ // Alright, so this particular combination of initval and
+ // resetval is not natively supported. First, try flipping
+ // them both to see whether this helps.
+ if ((has_set ? supported_sdff0 : supported_sdff1) & flip_initmask(initmask)) {
+ // Checks out, do it.
+ ff_type = has_ce ? (has_set ? FF_SDFFCE0 : FF_SDFFCE1) : has_en ? (has_set ? FF_SDFFE0 : FF_SDFFE1) : (has_set ? FF_SDFF0 : FF_SDFF1);
+ goto flip_dqi;
+ }
+
+ // Nope. No way to get SDFF* of the right kind, so unmap it.
+ // For SDFFE, the enable has to be unmapped first.
+ if (has_en) {
+ ff_type = has_set ? FF_SDFF1 : FF_SDFF0;
+ goto unmap_enable;
+ }
+unmap_srst:
+ if (has_ce)
+ ff_type = FF_DFFE;
+ else
+ ff_type = FF_DFF;
+ if (ff_neg & NEG_R)
+ sig_d = cell->module->MuxGate(NEW_ID, has_set ? State::S1 : State::S0, sig_d[0], sig_r[0]);
+ else
+ sig_d = cell->module->MuxGate(NEW_ID, sig_d[0], has_set ? State::S1 : State::S0, sig_r[0]);
+ ff_neg &= ~NEG_R;
+ sig_r = SigSpec();
+ kill_srst = false;
+ continue;
+ } else {
+ log_assert(0);
+ }
+ }
+cell_ok:
+
+ if (!(supported_cells_neg[ff_type][ff_neg] & initmask)) {
+ // Cell is supported, but not with those polarities.
+ // Will need to add some inverters.
+
+ // Find the smallest value that xored with the neg mask
+ // results in a supported one — this results in preferentially
+ // inverting resets before clocks, etc.
+ int xneg;
+ for (xneg = 0; xneg < NUM_NEG; xneg++)
+ if (supported_cells_neg[ff_type][ff_neg ^ xneg] & initmask)
+ break;
+ log_assert(xneg < NUM_NEG);
+ if (xneg & NEG_R)
+ sig_r = cell->module->NotGate(NEW_ID, sig_r[0]);
+ if (xneg & NEG_S)
+ sig_s = cell->module->NotGate(NEW_ID, sig_s[0]);
+ if (xneg & NEG_E)
+ sig_e = cell->module->NotGate(NEW_ID, sig_e[0]);
+ if (xneg & NEG_C)
+ sig_c = cell->module->NotGate(NEW_ID, sig_c[0]);
+ ff_neg ^= xneg;
+ }
+
+ cell->unsetPort(ID::D);
+ cell->unsetPort(ID::Q);
+ cell->unsetPort(ID::C);
+ cell->unsetPort(ID::E);
+ cell->unsetPort(ID::S);
+ cell->unsetPort(ID::R);
+ switch (ff_type) {
+ case FF_DFF:
+ cell->type = IdString(stringf("$_DFF_%c_",
+ (ff_neg & NEG_C) ? 'N' : 'P'
+ ));
+ cell->setPort(ID::D, sig_d);
+ cell->setPort(ID::Q, sig_q);
+ cell->setPort(ID::C, sig_c);
+ break;
+ case FF_DFFE:
+ cell->type = IdString(stringf("$_DFFE_%c%c_",
+ (ff_neg & NEG_C) ? 'N' : 'P',
+ (ff_neg & NEG_E) ? 'N' : 'P'
+ ));
+ cell->setPort(ID::D, sig_d);
+ cell->setPort(ID::Q, sig_q);
+ cell->setPort(ID::C, sig_c);
+ cell->setPort(ID::E, sig_e);
+ break;
+ case FF_ADFF0:
+ case FF_ADFF1:
+ cell->type = IdString(stringf("$_DFF_%c%c%c_",
+ (ff_neg & NEG_C) ? 'N' : 'P',
+ (ff_neg & NEG_R) ? 'N' : 'P',
+ (ff_type == FF_ADFF1) ? '1' : '0'
+ ));
+ cell->setPort(ID::D, sig_d);
+ cell->setPort(ID::Q, sig_q);
+ cell->setPort(ID::C, sig_c);
+ cell->setPort(ID::R, sig_r);
+ break;
+ case FF_ADFFE0:
+ case FF_ADFFE1:
+ cell->type = IdString(stringf("$_DFFE_%c%c%c%c_",
+ (ff_neg & NEG_C) ? 'N' : 'P',
+ (ff_neg & NEG_R) ? 'N' : 'P',
+ (ff_type == FF_ADFFE1) ? '1' : '0',
+ (ff_neg & NEG_E) ? 'N' : 'P'
+ ));
+ cell->setPort(ID::D, sig_d);
+ cell->setPort(ID::Q, sig_q);
+ cell->setPort(ID::C, sig_c);
+ cell->setPort(ID::E, sig_e);
+ cell->setPort(ID::R, sig_r);
+ break;
+ case FF_DFFSR:
+ cell->type = IdString(stringf("$_DFFSR_%c%c%c_",
+ (ff_neg & NEG_C) ? 'N' : 'P',
+ (ff_neg & NEG_S) ? 'N' : 'P',
+ (ff_neg & NEG_R) ? 'N' : 'P'
+ ));
+ cell->setPort(ID::D, sig_d);
+ cell->setPort(ID::Q, sig_q);
+ cell->setPort(ID::C, sig_c);
+ cell->setPort(ID::S, sig_s);
+ cell->setPort(ID::R, sig_r);
+ break;
+ case FF_DFFSRE:
+ cell->type = IdString(stringf("$_DFFSRE_%c%c%c%c_",
+ (ff_neg & NEG_C) ? 'N' : 'P',
+ (ff_neg & NEG_S) ? 'N' : 'P',
+ (ff_neg & NEG_R) ? 'N' : 'P',
+ (ff_neg & NEG_E) ? 'N' : 'P'
+ ));
+ cell->setPort(ID::D, sig_d);
+ cell->setPort(ID::Q, sig_q);
+ cell->setPort(ID::C, sig_c);
+ cell->setPort(ID::E, sig_e);
+ cell->setPort(ID::S, sig_s);
+ cell->setPort(ID::R, sig_r);
+ break;
+ case FF_SDFF0:
+ case FF_SDFF1:
+ cell->type = IdString(stringf("$_SDFF_%c%c%c_",
+ (ff_neg & NEG_C) ? 'N' : 'P',
+ (ff_neg & NEG_R) ? 'N' : 'P',
+ (ff_type == FF_SDFF1) ? '1' : '0'
+ ));
+ cell->setPort(ID::D, sig_d);
+ cell->setPort(ID::Q, sig_q);
+ cell->setPort(ID::C, sig_c);
+ cell->setPort(ID::R, sig_r);
+ break;
+ case FF_SDFFE0:
+ case FF_SDFFE1:
+ cell->type = IdString(stringf("$_SDFFE_%c%c%c%c_",
+ (ff_neg & NEG_C) ? 'N' : 'P',
+ (ff_neg & NEG_R) ? 'N' : 'P',
+ (ff_type == FF_SDFFE1) ? '1' : '0',
+ (ff_neg & NEG_E) ? 'N' : 'P'
+ ));
+ cell->setPort(ID::D, sig_d);
+ cell->setPort(ID::Q, sig_q);
+ cell->setPort(ID::C, sig_c);
+ cell->setPort(ID::E, sig_e);
+ cell->setPort(ID::R, sig_r);
+ break;
+ case FF_SDFFCE0:
+ case FF_SDFFCE1:
+ cell->type = IdString(stringf("$_SDFFCE_%c%c%c%c_",
+ (ff_neg & NEG_C) ? 'N' : 'P',
+ (ff_neg & NEG_R) ? 'N' : 'P',
+ (ff_type == FF_SDFFCE1) ? '1' : '0',
+ (ff_neg & NEG_E) ? 'N' : 'P'
+ ));
+ cell->setPort(ID::D, sig_d);
+ cell->setPort(ID::Q, sig_q);
+ cell->setPort(ID::C, sig_c);
+ cell->setPort(ID::E, sig_e);
+ cell->setPort(ID::R, sig_r);
+ break;
+ case FF_DLATCH:
+ cell->type = IdString(stringf("$_DLATCH_%c_",
+ (ff_neg & NEG_E) ? 'N' : 'P'
+ ));
+ cell->setPort(ID::D, sig_d);
+ cell->setPort(ID::Q, sig_q);
+ cell->setPort(ID::E, sig_e);
+ break;
+ case FF_ADLATCH0:
+ case FF_ADLATCH1:
+ cell->type = IdString(stringf("$_DLATCH_%c%c%c_",
+ (ff_neg & NEG_E) ? 'N' : 'P',
+ (ff_neg & NEG_R) ? 'N' : 'P',
+ (ff_type == FF_ADLATCH1) ? '1' : '0'
+ ));
+ cell->setPort(ID::D, sig_d);
+ cell->setPort(ID::Q, sig_q);
+ cell->setPort(ID::E, sig_e);
+ cell->setPort(ID::R, sig_r);
+ break;
+ case FF_DLATCHSR:
+ cell->type = IdString(stringf("$_DLATCHSR_%c%c%c_",
+ (ff_neg & NEG_E) ? 'N' : 'P',
+ (ff_neg & NEG_S) ? 'N' : 'P',
+ (ff_neg & NEG_R) ? 'N' : 'P'
+ ));
+ cell->setPort(ID::D, sig_d);
+ cell->setPort(ID::Q, sig_q);
+ cell->setPort(ID::E, sig_e);
+ cell->setPort(ID::S, sig_s);
+ cell->setPort(ID::R, sig_r);
+ break;
+ case FF_SR:
+ cell->type = IdString(stringf("$_SR_%c%c_",
+ (ff_neg & NEG_S) ? 'N' : 'P',
+ (ff_neg & NEG_R) ? 'N' : 'P'
+ ));
+ cell->setPort(ID::Q, sig_q);
+ cell->setPort(ID::S, sig_s);
+ cell->setPort(ID::R, sig_r);
+ break;
+ default:
+ log_assert(0);
+ }
+ return;
+
+error:
+ log_error("FF %s.%s (type %s) cannot be legalized: %s\n", log_id(cell->module->name), log_id(cell->name), log_id(cell->type), reason);
+ }
+
+ void execute(std::vector<std::string> args, RTLIL::Design *design) override
+ {
+
+ log_header(design, "Executing DFFLEGALIZE pass (convert FFs to types supported by the target).\n");
+
+ for (int i = 0; i < NUM_FFTYPES; i++) {
+ for (int j = 0; j < NUM_NEG; j++)
+ supported_cells_neg[i][j] = 0;
+ supported_cells[i] = 0;
+ }
+ mince = 0;
+ minsrst = 0;
+
+ size_t argidx;
+ for (argidx = 1; argidx < args.size(); argidx++)
+ {
+ if (args[argidx] == "-cell" && argidx + 2 < args.size()) {
+ std::string celltype = args[++argidx];
+ std::string inittype = args[++argidx];
+ enum FfType ff_type[2] = {NUM_FFTYPES, NUM_FFTYPES};
+ char pol_c = 0;
+ char pol_e = 0;
+ char pol_s = 0;
+ char pol_r = 0;
+ char srval = 0;
+ if (celltype.substr(0, 5) == "$_SR_" && celltype.size() == 8 && celltype[7] == '_') {
+ ff_type[0] = FF_SR;
+ pol_s = celltype[5];
+ pol_r = celltype[6];
+ } else if (celltype.substr(0, 6) == "$_DFF_" && celltype.size() == 8 && celltype[7] == '_') {
+ ff_type[0] = FF_DFF;
+ pol_c = celltype[6];
+ } else if (celltype.substr(0, 7) == "$_DFFE_" && celltype.size() == 10 && celltype[9] == '_') {
+ ff_type[0] = FF_DFFE;
+ pol_c = celltype[7];
+ pol_e = celltype[8];
+ } else if (celltype.substr(0, 6) == "$_DFF_" && celltype.size() == 10 && celltype[9] == '_') {
+ ff_type[0] = FF_ADFF0;
+ ff_type[1] = FF_ADFF1;
+ pol_c = celltype[6];
+ pol_r = celltype[7];
+ srval = celltype[8];
+ } else if (celltype.substr(0, 7) == "$_DFFE_" && celltype.size() == 12 && celltype[11] == '_') {
+ ff_type[0] = FF_ADFFE0;
+ ff_type[1] = FF_ADFFE1;
+ pol_c = celltype[7];
+ pol_r = celltype[8];
+ srval = celltype[9];
+ pol_e = celltype[10];
+ } else if (celltype.substr(0, 8) == "$_DFFSR_" && celltype.size() == 12 && celltype[11] == '_') {
+ ff_type[0] = FF_DFFSR;
+ pol_c = celltype[8];
+ pol_s = celltype[9];
+ pol_r = celltype[10];
+ } else if (celltype.substr(0, 9) == "$_DFFSRE_" && celltype.size() == 14 && celltype[13] == '_') {
+ ff_type[0] = FF_DFFSRE;
+ pol_c = celltype[9];
+ pol_s = celltype[10];
+ pol_r = celltype[11];
+ pol_e = celltype[12];
+ } else if (celltype.substr(0, 7) == "$_SDFF_" && celltype.size() == 11 && celltype[10] == '_') {
+ ff_type[0] = FF_SDFF0;
+ ff_type[1] = FF_SDFF1;
+ pol_c = celltype[7];
+ pol_r = celltype[8];
+ srval = celltype[9];
+ } else if (celltype.substr(0, 8) == "$_SDFFE_" && celltype.size() == 13 && celltype[12] == '_') {
+ ff_type[0] = FF_SDFFE0;
+ ff_type[1] = FF_SDFFE1;
+ pol_c = celltype[8];
+ pol_r = celltype[9];
+ srval = celltype[10];
+ pol_e = celltype[11];
+ } else if (celltype.substr(0, 9) == "$_SDFFCE_" && celltype.size() == 14 && celltype[13] == '_') {
+ ff_type[0] = FF_SDFFCE0;
+ ff_type[1] = FF_SDFFCE1;
+ pol_c = celltype[9];
+ pol_r = celltype[10];
+ srval = celltype[11];
+ pol_e = celltype[12];
+ } else if (celltype.substr(0, 9) == "$_DLATCH_" && celltype.size() == 11 && celltype[10] == '_') {
+ ff_type[0] = FF_DLATCH;
+ pol_e = celltype[9];
+ } else if (celltype.substr(0, 9) == "$_DLATCH_" && celltype.size() == 13 && celltype[12] == '_') {
+ ff_type[0] = FF_ADLATCH0;
+ ff_type[1] = FF_ADLATCH1;
+ pol_e = celltype[9];
+ pol_r = celltype[10];
+ srval = celltype[11];
+ } else if (celltype.substr(0, 11) == "$_DLATCHSR_" && celltype.size() == 15 && celltype[14] == '_') {
+ ff_type[0] = FF_DLATCHSR;
+ pol_e = celltype[11];
+ pol_s = celltype[12];
+ pol_r = celltype[13];
+ } else {
+unrecognized:
+ log_error("unrecognized cell type %s.\n", celltype.c_str());
+ }
+ int mask = 0;
+ int match = 0;
+ for (auto pair : {
+ std::make_pair(pol_c, NEG_C),
+ std::make_pair(pol_e, NEG_E),
+ std::make_pair(pol_s, NEG_S),
+ std::make_pair(pol_r, NEG_R),
+ }) {
+ if (pair.first == 'N') {
+ mask |= pair.second;
+ match |= pair.second;
+ } else if (pair.first == 'P' || pair.first == 0) {
+ mask |= pair.second;
+ } else if (pair.first != '?') {
+ goto unrecognized;
+ }
+ }
+ if (srval == '0') {
+ ff_type[1] = NUM_FFTYPES;
+ } else if (srval == '1') {
+ ff_type[0] = NUM_FFTYPES;
+ } else if (srval != 0 && srval != '?') {
+ goto unrecognized;
+ }
+ for (int i = 0; i < 2; i++) {
+ if (ff_type[i] == NUM_FFTYPES)
+ continue;
+ int initmask;
+ if (inittype == "x") {
+ initmask = INIT_X;
+ } else if (inittype == "0") {
+ initmask = INIT_X | INIT_0;
+ } else if (inittype == "1") {
+ initmask = INIT_X | INIT_1;
+ } else if (inittype == "r") {
+ if (srval == 0)
+ log_error("init type r not valid for cell type %s.\n", celltype.c_str());
+ if (i == 0)
+ initmask = INIT_X | INIT_0;
+ else
+ initmask = INIT_X | INIT_1;
+ } else if (inittype == "01") {
+ initmask = INIT_X | INIT_0 | INIT_1;
+ } else {
+ log_error("unrecognized init type %s for cell type %s.\n", inittype.c_str(), celltype.c_str());
+ }
+ for (int neg = 0; neg < NUM_NEG; neg++)
+ if ((neg & mask) == match)
+ supported_cells_neg[ff_type[i]][neg] |= initmask;
+ supported_cells[ff_type[i]] |= initmask;
+ }
+ continue;
+ } else if (args[argidx] == "-mince" && argidx + 1 < args.size()) {
+ mince = atoi(args[++argidx].c_str());
+ continue;
+ } else if (args[argidx] == "-minsrst" && argidx + 1 < args.size()) {
+ minsrst = atoi(args[++argidx].c_str());
+ continue;
+ }
+ break;
+ }
+ extra_args(args, argidx, design);
+ supported_dffsr = supported_cells[FF_DFFSR] | supported_cells[FF_DFFSRE];
+ supported_adff0 = supported_cells[FF_ADFF0] | supported_cells[FF_ADFFE0] | supported_dffsr;
+ supported_adff1 = supported_cells[FF_ADFF1] | supported_cells[FF_ADFFE1] | supported_dffsr;
+ supported_sdff0 = supported_cells[FF_SDFF0] | supported_cells[FF_SDFFE0] | supported_cells[FF_SDFFCE0];
+ supported_sdff1 = supported_cells[FF_SDFF1] | supported_cells[FF_SDFFE1] | supported_cells[FF_SDFFCE1];
+ supported_dff = supported_cells[FF_DFF] | supported_cells[FF_DFFE] | supported_dffsr | supported_adff0 | supported_adff1 | supported_sdff0 | supported_sdff1;
+ supported_sr = supported_dffsr | supported_cells[FF_DLATCHSR] | supported_cells[FF_SR] | supported_cells[FF_ADLATCH0] | flip_initmask(supported_cells[FF_ADLATCH1]);
+ supported_dlatch = supported_cells[FF_DLATCH] | supported_cells[FF_ADLATCH0] | supported_cells[FF_ADLATCH1] | supported_cells[FF_DLATCHSR];
+
+ for (auto module : design->selected_modules())
+ {
+ sigmap.set(module);
+ initbits.clear();
+
+ for (auto wire : module->selected_wires())
+ {
+ if (wire->attributes.count(ID::init) == 0)
+ continue;
+
+ SigSpec wirebits = sigmap(wire);
+ Const initval = wire->attributes.at(ID::init);
+
+ for (int i = 0; i < GetSize(wirebits) && i < GetSize(initval); i++)
+ {
+ SigBit bit = wirebits[i];
+ State val = initval[i];
+
+ if (val != State::S0 && val != State::S1 && bit.wire != nullptr)
+ continue;
+
+ if (initbits.count(bit)) {
+ if (initbits.at(bit).first != val)
+ log_error("Conflicting init values for signal %s (%s = %s != %s).\n",
+ log_signal(bit), log_signal(SigBit(wire, i)),
+ log_signal(val), log_signal(initbits.at(bit).first));
+ continue;
+ }
+
+ initbits[bit] = std::make_pair(val,SigBit(wire,i));
+ }
+ }
+
+ if (mince || minsrst) {
+ ce_used.clear();
+ srst_used.clear();
+
+ for (auto cell : module->cells()) {
+ if (!RTLIL::builtin_ff_cell_types().count(cell->type))
+ continue;
+
+ if (cell->hasPort(ID::C) && cell->hasPort(ID::E)) {
+ SigSpec sig = cell->getPort(ID::E);
+ // Do not count const enable signals.
+ if (GetSize(sig) == 1 && sig[0].wire)
+ ce_used[sig[0]]++;
+ }
+ if (cell->type.str().substr(0, 6) == "$_SDFF") {
+ SigSpec sig = cell->getPort(ID::R);
+ // Do not count const srst signals.
+ if (GetSize(sig) == 1 && sig[0].wire)
+ srst_used[sig[0]]++;
+ }
+ }
+ }
+
+ // First gather FF cells, then iterate over them later.
+ // We may need to split an FF into several cells.
+ std::vector<Cell *> ff_cells;
+
+ for (auto cell : module->selected_cells())
+ {
+ // Early exit for non-FFs.
+ if (!RTLIL::builtin_ff_cell_types().count(cell->type))
+ continue;
+
+ ff_cells.push_back(cell);
+ }
+
+ for (auto cell: ff_cells)
+ handle_ff(cell);
+ }
+
+ sigmap.clear();
+ initbits.clear();
+ ce_used.clear();
+ srst_used.clear();
+ }
+} DffLegalizePass;
+
+PRIVATE_NAMESPACE_END
diff --git a/passes/techmap/dfflibmap.cc b/passes/techmap/dfflibmap.cc
index aa344cf8a..c189d649b 100644
--- a/passes/techmap/dfflibmap.cc
+++ b/passes/techmap/dfflibmap.cc
@@ -409,11 +409,11 @@ static void map_sr_to_arst(IdString from, IdString to)
if (!cell_mappings.count(from) || cell_mappings.count(to) > 0)
return;
- char from_clk_pol YS_ATTRIBUTE(unused) = from[8];
+ char from_clk_pol = from[8];
char from_set_pol = from[9];
char from_clr_pol = from[10];
- char to_clk_pol YS_ATTRIBUTE(unused) = to[6];
- char to_rst_pol YS_ATTRIBUTE(unused) = to[7];
+ char to_clk_pol = to[6];
+ char to_rst_pol = to[7];
char to_rst_val = to[8];
log_assert(from_clk_pol == to_clk_pol);
@@ -455,9 +455,9 @@ static void map_adff_to_dff(IdString from, IdString to)
if (!cell_mappings.count(from) || cell_mappings.count(to) > 0)
return;
- char from_clk_pol YS_ATTRIBUTE(unused) = from[6];
+ char from_clk_pol = from[6];
char from_rst_pol = from[7];
- char to_clk_pol YS_ATTRIBUTE(unused) = to[6];
+ char to_clk_pol = to[6];
log_assert(from_clk_pol == to_clk_pol);
@@ -549,7 +549,7 @@ static void dfflibmap(RTLIL::Design *design, RTLIL::Module *module, bool prepare
struct DfflibmapPass : public Pass {
DfflibmapPass() : Pass("dfflibmap", "technology mapping of flip-flops") { }
- void help() YS_OVERRIDE
+ void help() override
{
log("\n");
log(" dfflibmap [-prepare] -liberty <file> [selection]\n");
@@ -565,7 +565,7 @@ struct DfflibmapPass : public Pass {
log("liberty file.\n");
log("\n");
}
- void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
+ void execute(std::vector<std::string> args, RTLIL::Design *design) override
{
log_header(design, "Executing DFFLIBMAP pass (mapping DFF cells to sequential cells from liberty file).\n");
diff --git a/passes/techmap/extract.cc b/passes/techmap/extract.cc
index f29044790..7278cb680 100644
--- a/passes/techmap/extract.cc
+++ b/passes/techmap/extract.cc
@@ -345,7 +345,7 @@ bool compareSortNeedleList(RTLIL::Module *left, RTLIL::Module *right)
struct ExtractPass : public Pass {
ExtractPass() : Pass("extract", "find subcircuits and replace them with cells") { }
- void help() YS_OVERRIDE
+ void help() override
{
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
log("\n");
@@ -433,7 +433,7 @@ struct ExtractPass : public Pass {
log("See 'help techmap' for a pass that does the opposite thing.\n");
log("\n");
}
- void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
+ void execute(std::vector<std::string> args, RTLIL::Design *design) override
{
log_header(design, "Executing EXTRACT pass (map subcircuits to cells).\n");
log_push();
diff --git a/passes/techmap/extract_counter.cc b/passes/techmap/extract_counter.cc
index 68b338143..56b2ea584 100644
--- a/passes/techmap/extract_counter.cc
+++ b/passes/techmap/extract_counter.cc
@@ -760,7 +760,7 @@ void counter_worker(
struct ExtractCounterPass : public Pass {
ExtractCounterPass() : Pass("extract_counter", "Extract GreenPak4 counter cells") { }
- void help() YS_OVERRIDE
+ void help() override
{
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
log("\n");
@@ -788,18 +788,18 @@ struct ExtractCounterPass : public Pass {
log("\n");
log("\n");
}
- void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
+ void execute(std::vector<std::string> args, RTLIL::Design *design) override
{
log_header(design, "Executing EXTRACT_COUNTER pass (find counters in netlist).\n");
pool<RTLIL::IdString> _parallel_cells;
CounterExtractionSettings settings
{
- .parallel_cells = _parallel_cells,
- .maxwidth = 64,
- .minwidth = 2,
- .allow_arst = true,
- .allowed_dirs = 0,
+ _parallel_cells, // parallel_cells
+ 64, // maxwidth
+ 2, // minwidth
+ true, // allow_arst
+ 0, // allowed_dirs
};
size_t argidx;
diff --git a/passes/techmap/extract_fa.cc b/passes/techmap/extract_fa.cc
index 9023d8687..3fcff01c3 100644
--- a/passes/techmap/extract_fa.cc
+++ b/passes/techmap/extract_fa.cc
@@ -539,7 +539,7 @@ struct ExtractFaWorker
struct ExtractFaPass : public Pass {
ExtractFaPass() : Pass("extract_fa", "find and extract full/half adders") { }
- void help() YS_OVERRIDE
+ void help() override
{
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
log("\n");
@@ -561,7 +561,7 @@ struct ExtractFaPass : public Pass {
log(" Verbose output\n");
log("\n");
}
- void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
+ void execute(std::vector<std::string> args, RTLIL::Design *design) override
{
ExtractFaConfig config;
diff --git a/passes/techmap/extract_reduce.cc b/passes/techmap/extract_reduce.cc
index 2d63e413f..07b4200cc 100644
--- a/passes/techmap/extract_reduce.cc
+++ b/passes/techmap/extract_reduce.cc
@@ -34,7 +34,7 @@ struct ExtractReducePass : public Pass
ExtractReducePass() : Pass("extract_reduce", "converts gate chains into $reduce_* cells") { }
- void help() YS_OVERRIDE
+ void help() override
{
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
log("\n");
@@ -63,7 +63,7 @@ struct ExtractReducePass : public Pass
(cell->type == ID($_XOR_) && gt == GateType::Xor);
}
- void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
+ void execute(std::vector<std::string> args, RTLIL::Design *design) override
{
log_header(design, "Executing EXTRACT_REDUCE pass.\n");
log_push();
diff --git a/passes/techmap/extractinv.cc b/passes/techmap/extractinv.cc
index 269fe5c6c..9b350456f 100644
--- a/passes/techmap/extractinv.cc
+++ b/passes/techmap/extractinv.cc
@@ -35,7 +35,7 @@ void split_portname_pair(std::string &port1, std::string &port2)
struct ExtractinvPass : public Pass {
ExtractinvPass() : Pass("extractinv", "extract explicit inverter cells for invertible cell pins") { }
- void help() YS_OVERRIDE
+ void help() override
{
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
log("\n");
@@ -57,7 +57,7 @@ struct ExtractinvPass : public Pass {
log("\n");
}
- void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
+ void execute(std::vector<std::string> args, RTLIL::Design *design) override
{
log_header(design, "Executing EXTRACTINV pass (extracting pin inverters).\n");
diff --git a/passes/techmap/flatten.cc b/passes/techmap/flatten.cc
new file mode 100644
index 000000000..b5f55cffa
--- /dev/null
+++ b/passes/techmap/flatten.cc
@@ -0,0 +1,333 @@
+/*
+ * yosys -- Yosys Open SYnthesis Suite
+ *
+ * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ */
+
+#include "kernel/yosys.h"
+#include "kernel/utils.h"
+#include "kernel/sigtools.h"
+
+#include <stdlib.h>
+#include <stdio.h>
+#include <string.h>
+
+USING_YOSYS_NAMESPACE
+PRIVATE_NAMESPACE_BEGIN
+
+IdString concat_name(RTLIL::Cell *cell, IdString object_name)
+{
+ if (object_name[0] == '\\')
+ return stringf("%s.%s", cell->name.c_str(), object_name.c_str() + 1);
+ else {
+ std::string object_name_str = object_name.str();
+ if (object_name_str.substr(0, 8) == "$flatten")
+ object_name_str.erase(0, 8);
+ return stringf("$flatten%s.%s", cell->name.c_str(), object_name_str.c_str());
+ }
+}
+
+template<class T>
+IdString map_name(RTLIL::Cell *cell, T *object)
+{
+ return cell->module->uniquify(concat_name(cell, object->name));
+}
+
+template<class T>
+void map_attributes(RTLIL::Cell *cell, T *object, IdString orig_object_name)
+{
+ if (object->has_attribute(ID::src))
+ object->add_strpool_attribute(ID::src, cell->get_strpool_attribute(ID::src));
+
+ // Preserve original names via the hdlname attribute, but only for objects with a fully public name.
+ if (cell->name[0] == '\\' && (object->has_attribute(ID::hdlname) || orig_object_name[0] == '\\')) {
+ std::vector<std::string> hierarchy;
+ if (object->has_attribute(ID::hdlname))
+ hierarchy = object->get_hdlname_attribute();
+ else
+ hierarchy.push_back(orig_object_name.str().substr(1));
+ hierarchy.insert(hierarchy.begin(), cell->name.str().substr(1));
+ object->set_hdlname_attribute(hierarchy);
+ }
+}
+
+void map_sigspec(const dict<RTLIL::Wire*, RTLIL::Wire*> &map, RTLIL::SigSpec &sig, RTLIL::Module *into = nullptr)
+{
+ vector<SigChunk> chunks = sig;
+ for (auto &chunk : chunks)
+ if (chunk.wire != nullptr && chunk.wire->module != into)
+ chunk.wire = map.at(chunk.wire);
+ sig = chunks;
+}
+
+struct FlattenWorker
+{
+ bool ignore_wb = false;
+
+ void flatten_cell(RTLIL::Design *design, RTLIL::Module *module, RTLIL::Cell *cell, RTLIL::Module *tpl, std::vector<RTLIL::Cell*> &new_cells)
+ {
+ // Copy the contents of the flattened cell
+
+ dict<IdString, IdString> memory_map;
+ for (auto &tpl_memory_it : tpl->memories) {
+ RTLIL::Memory *new_memory = module->addMemory(map_name(cell, tpl_memory_it.second), tpl_memory_it.second);
+ map_attributes(cell, new_memory, tpl_memory_it.second->name);
+ memory_map[tpl_memory_it.first] = new_memory->name;
+ design->select(module, new_memory);
+ }
+
+ dict<RTLIL::Wire*, RTLIL::Wire*> wire_map;
+ dict<IdString, IdString> positional_ports;
+ for (auto tpl_wire : tpl->wires()) {
+ if (tpl_wire->port_id > 0)
+ positional_ports.emplace(stringf("$%d", tpl_wire->port_id), tpl_wire->name);
+
+ RTLIL::Wire *new_wire = nullptr;
+ if (tpl_wire->name[0] == '\\') {
+ RTLIL::Wire *hier_wire = module->wire(concat_name(cell, tpl_wire->name));
+ if (hier_wire != nullptr && hier_wire->get_bool_attribute(ID::hierconn)) {
+ hier_wire->attributes.erase(ID::hierconn);
+ if (GetSize(hier_wire) < GetSize(tpl_wire)) {
+ log_warning("Widening signal %s.%s to match size of %s.%s (via %s.%s).\n",
+ log_id(module), log_id(hier_wire), log_id(tpl), log_id(tpl_wire), log_id(module), log_id(cell));
+ hier_wire->width = GetSize(tpl_wire);
+ }
+ new_wire = hier_wire;
+ }
+ }
+ if (new_wire == nullptr) {
+ new_wire = module->addWire(map_name(cell, tpl_wire), tpl_wire);
+ new_wire->port_input = new_wire->port_output = false;
+ new_wire->port_id = false;
+ }
+
+ map_attributes(cell, new_wire, tpl_wire->name);
+ wire_map[tpl_wire] = new_wire;
+ design->select(module, new_wire);
+ }
+
+ for (auto &tpl_proc_it : tpl->processes) {
+ RTLIL::Process *new_proc = module->addProcess(map_name(cell, tpl_proc_it.second), tpl_proc_it.second);
+ map_attributes(cell, new_proc, tpl_proc_it.second->name);
+ auto rewriter = [&](RTLIL::SigSpec &sig) { map_sigspec(wire_map, sig); };
+ new_proc->rewrite_sigspecs(rewriter);
+ design->select(module, new_proc);
+ }
+
+ for (auto tpl_cell : tpl->cells()) {
+ RTLIL::Cell *new_cell = module->addCell(map_name(cell, tpl_cell), tpl_cell);
+ map_attributes(cell, new_cell, tpl_cell->name);
+ if (new_cell->type.in(ID($memrd), ID($memwr), ID($meminit))) {
+ IdString memid = new_cell->getParam(ID::MEMID).decode_string();
+ new_cell->setParam(ID::MEMID, Const(memory_map.at(memid).str()));
+ } else if (new_cell->type == ID($mem)) {
+ IdString memid = new_cell->getParam(ID::MEMID).decode_string();
+ new_cell->setParam(ID::MEMID, Const(concat_name(cell, memid).str()));
+ }
+ auto rewriter = [&](RTLIL::SigSpec &sig) { map_sigspec(wire_map, sig); };
+ new_cell->rewrite_sigspecs(rewriter);
+ design->select(module, new_cell);
+ new_cells.push_back(new_cell);
+ }
+
+ for (auto &tpl_conn_it : tpl->connections()) {
+ RTLIL::SigSig new_conn = tpl_conn_it;
+ map_sigspec(wire_map, new_conn.first);
+ map_sigspec(wire_map, new_conn.second);
+ module->connect(new_conn);
+ }
+
+ // Attach port connections of the flattened cell
+
+ SigMap tpl_sigmap(tpl);
+ pool<SigBit> tpl_driven;
+ for (auto tpl_cell : tpl->cells())
+ for (auto &tpl_conn : tpl_cell->connections())
+ if (tpl_cell->output(tpl_conn.first))
+ for (auto bit : tpl_sigmap(tpl_conn.second))
+ tpl_driven.insert(bit);
+ for (auto &tpl_conn : tpl->connections())
+ for (auto bit : tpl_sigmap(tpl_conn.first))
+ tpl_driven.insert(bit);
+
+ SigMap sigmap(module);
+ for (auto &port_it : cell->connections())
+ {
+ IdString port_name = port_it.first;
+ if (positional_ports.count(port_name) > 0)
+ port_name = positional_ports.at(port_name);
+ if (tpl->wire(port_name) == nullptr || tpl->wire(port_name)->port_id == 0) {
+ if (port_name.begins_with("$"))
+ log_error("Can't map port `%s' of cell `%s' to template `%s'!\n",
+ port_name.c_str(), cell->name.c_str(), tpl->name.c_str());
+ continue;
+ }
+
+ if (GetSize(port_it.second) == 0)
+ continue;
+
+ RTLIL::Wire *tpl_wire = tpl->wire(port_name);
+ RTLIL::SigSig new_conn;
+ if (tpl_wire->port_output && !tpl_wire->port_input) {
+ new_conn.first = port_it.second;
+ new_conn.second = tpl_wire;
+ } else if (!tpl_wire->port_output && tpl_wire->port_input) {
+ new_conn.first = tpl_wire;
+ new_conn.second = port_it.second;
+ } else {
+ SigSpec sig_tpl = tpl_wire, sig_mod = port_it.second;
+ for (int i = 0; i < GetSize(sig_tpl) && i < GetSize(sig_mod); i++) {
+ if (tpl_driven.count(tpl_sigmap(sig_tpl[i]))) {
+ new_conn.first.append(sig_mod[i]);
+ new_conn.second.append(sig_tpl[i]);
+ } else {
+ new_conn.first.append(sig_tpl[i]);
+ new_conn.second.append(sig_mod[i]);
+ }
+ }
+ }
+ map_sigspec(wire_map, new_conn.first, module);
+ map_sigspec(wire_map, new_conn.second, module);
+
+ if (new_conn.second.size() > new_conn.first.size())
+ new_conn.second.remove(new_conn.first.size(), new_conn.second.size() - new_conn.first.size());
+ if (new_conn.second.size() < new_conn.first.size())
+ new_conn.second.append(RTLIL::SigSpec(RTLIL::State::S0, new_conn.first.size() - new_conn.second.size()));
+ log_assert(new_conn.first.size() == new_conn.second.size());
+
+ if (sigmap(new_conn.first).has_const())
+ log_error("Mismatch in directionality for cell port %s.%s.%s: %s <= %s\n",
+ log_id(module), log_id(cell), log_id(port_it.first), log_signal(new_conn.first), log_signal(new_conn.second));
+
+ module->connect(new_conn);
+ }
+
+ module->remove(cell);
+ }
+
+ void flatten_module(RTLIL::Design *design, RTLIL::Module *module, pool<RTLIL::Module*> &used_modules)
+ {
+ if (!design->selected(module) || module->get_blackbox_attribute(ignore_wb))
+ return;
+
+ std::vector<RTLIL::Cell*> worklist = module->selected_cells();
+ while (!worklist.empty())
+ {
+ RTLIL::Cell *cell = worklist.back();
+ worklist.pop_back();
+
+ if (!design->has(cell->type))
+ continue;
+
+ RTLIL::Module *tpl = design->module(cell->type);
+ if (tpl->get_blackbox_attribute(ignore_wb))
+ continue;
+
+ if (cell->get_bool_attribute(ID::keep_hierarchy) || tpl->get_bool_attribute(ID::keep_hierarchy)) {
+ log("Keeping %s.%s (found keep_hierarchy attribute).\n", log_id(module), log_id(cell));
+ used_modules.insert(tpl);
+ continue;
+ }
+
+ log_debug("Flattening %s.%s (%s).\n", log_id(module), log_id(cell), log_id(cell->type));
+ // If a design is fully selected and has a top module defined, topological sorting ensures that all cells
+ // added during flattening are black boxes, and flattening is finished in one pass. However, when flattening
+ // individual modules, this isn't the case, and the newly added cells might have to be flattened further.
+ flatten_cell(design, module, cell, tpl, worklist);
+ }
+ }
+};
+
+struct FlattenPass : public Pass {
+ FlattenPass() : Pass("flatten", "flatten design") { }
+ void help() override
+ {
+ // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
+ log("\n");
+ log(" flatten [options] [selection]\n");
+ log("\n");
+ log("This pass flattens the design by replacing cells by their implementation. This\n");
+ log("pass is very similar to the 'techmap' pass. The only difference is that this\n");
+ log("pass is using the current design as mapping library.\n");
+ log("\n");
+ log("Cells and/or modules with the 'keep_hierarchy' attribute set will not be\n");
+ log("flattened by this command.\n");
+ log("\n");
+ log(" -wb\n");
+ log(" Ignore the 'whitebox' attribute on cell implementations.\n");
+ log("\n");
+ }
+ void execute(std::vector<std::string> args, RTLIL::Design *design) override
+ {
+ log_header(design, "Executing FLATTEN pass (flatten design).\n");
+ log_push();
+
+ FlattenWorker worker;
+
+ size_t argidx;
+ for (argidx = 1; argidx < args.size(); argidx++) {
+ if (args[argidx] == "-wb") {
+ worker.ignore_wb = true;
+ continue;
+ }
+ break;
+ }
+ extra_args(args, argidx, design);
+
+ RTLIL::Module *top = nullptr;
+ if (design->full_selection())
+ for (auto module : design->modules())
+ if (module->get_bool_attribute(ID::top))
+ top = module;
+
+ pool<RTLIL::Module*> used_modules;
+ if (top == nullptr)
+ used_modules = design->modules();
+ else
+ used_modules.insert(top);
+
+ TopoSort<RTLIL::Module*, IdString::compare_ptr_by_name<RTLIL::Module>> topo_modules;
+ pool<RTLIL::Module*> worklist = used_modules;
+ while (!worklist.empty()) {
+ RTLIL::Module *module = worklist.pop();
+ for (auto cell : module->selected_cells()) {
+ RTLIL::Module *tpl = design->module(cell->type);
+ if (tpl != nullptr) {
+ if (topo_modules.database.count(tpl) == 0)
+ worklist.insert(tpl);
+ topo_modules.edge(tpl, module);
+ }
+ }
+ }
+
+ if (!topo_modules.sort())
+ log_error("Cannot flatten a design containing recursive instantiations.\n");
+
+ for (auto module : topo_modules.sorted)
+ worker.flatten_module(design, module, used_modules);
+
+ if (top != nullptr)
+ for (auto module : design->modules().to_vector())
+ if (!used_modules[module] && !module->get_blackbox_attribute(worker.ignore_wb)) {
+ log("Deleting now unused module %s.\n", log_id(module));
+ design->remove(module);
+ }
+
+ log_pop();
+ }
+} FlattenPass;
+
+PRIVATE_NAMESPACE_END
diff --git a/passes/techmap/flowmap.cc b/passes/techmap/flowmap.cc
index 72947237b..dfdbe6b88 100644
--- a/passes/techmap/flowmap.cc
+++ b/passes/techmap/flowmap.cc
@@ -1470,7 +1470,7 @@ static void split(std::vector<std::string> &tokens, const std::string &text, cha
struct FlowmapPass : public Pass {
FlowmapPass() : Pass("flowmap", "pack LUTs with FlowMap") { }
- void help() YS_OVERRIDE
+ void help() override
{
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
log("\n");
@@ -1511,7 +1511,7 @@ struct FlowmapPass : public Pass {
log(" explain decisions performed during depth relaxation.\n");
log("\n");
}
- void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
+ void execute(std::vector<std::string> args, RTLIL::Design *design) override
{
int order = 3;
int minlut = 1;
diff --git a/passes/techmap/hilomap.cc b/passes/techmap/hilomap.cc
index 5aeb5ea79..b808a8d8e 100644
--- a/passes/techmap/hilomap.cc
+++ b/passes/techmap/hilomap.cc
@@ -55,7 +55,7 @@ void hilomap_worker(RTLIL::SigSpec &sig)
struct HilomapPass : public Pass {
HilomapPass() : Pass("hilomap", "technology mapping of constant hi- and/or lo-drivers") { }
- void help() YS_OVERRIDE
+ void help() override
{
log("\n");
log(" hilomap [options] [selection]\n");
@@ -74,7 +74,7 @@ struct HilomapPass : public Pass {
log(" each constant bit.\n");
log("\n");
}
- void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
+ void execute(std::vector<std::string> args, RTLIL::Design *design) override
{
log_header(design, "Executing HILOMAP pass (mapping to constant drivers).\n");
diff --git a/passes/techmap/insbuf.cc b/passes/techmap/insbuf.cc
index 0686c0f2b..a3b5b698d 100644
--- a/passes/techmap/insbuf.cc
+++ b/passes/techmap/insbuf.cc
@@ -25,7 +25,7 @@ PRIVATE_NAMESPACE_BEGIN
struct InsbufPass : public Pass {
InsbufPass() : Pass("insbuf", "insert buffer cells for connected wires") { }
- void help() YS_OVERRIDE
+ void help() override
{
log("\n");
log(" insbuf [options] [selection]\n");
@@ -37,7 +37,7 @@ struct InsbufPass : public Pass {
log(" call to \"clean\" will remove all $_BUF_ in the design.)\n");
log("\n");
}
- void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
+ void execute(std::vector<std::string> args, RTLIL::Design *design) override
{
log_header(design, "Executing INSBUF pass (insert buffer cells for connected wires).\n");
diff --git a/passes/techmap/iopadmap.cc b/passes/techmap/iopadmap.cc
index a18d02652..e8530a034 100644
--- a/passes/techmap/iopadmap.cc
+++ b/passes/techmap/iopadmap.cc
@@ -34,7 +34,7 @@ void split_portname_pair(std::string &port1, std::string &port2)
struct IopadmapPass : public Pass {
IopadmapPass() : Pass("iopadmap", "technology mapping of i/o pads (or buffers)") { }
- void help() YS_OVERRIDE
+ void help() override
{
log("\n");
log(" iopadmap [options] [selection]\n");
@@ -97,7 +97,7 @@ struct IopadmapPass : public Pass {
modules_processed.insert(module);
}
- void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
+ void execute(std::vector<std::string> args, RTLIL::Design *design) override
{
log_header(design, "Executing IOPADMAP pass (mapping inputs/outputs to IO-PAD cells).\n");
diff --git a/passes/techmap/lut2mux.cc b/passes/techmap/lut2mux.cc
index 703bf6ff6..f56eff3e5 100644
--- a/passes/techmap/lut2mux.cc
+++ b/passes/techmap/lut2mux.cc
@@ -56,7 +56,7 @@ int lut2mux(Cell *cell)
struct Lut2muxPass : public Pass {
Lut2muxPass() : Pass("lut2mux", "convert $lut to $_MUX_") { }
- void help() YS_OVERRIDE
+ void help() override
{
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
log("\n");
@@ -65,7 +65,7 @@ struct Lut2muxPass : public Pass {
log("This pass converts $lut cells to $_MUX_ gates.\n");
log("\n");
}
- void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
+ void execute(std::vector<std::string> args, RTLIL::Design *design) override
{
log_header(design, "Executing LUT2MUX pass (convert $lut to $_MUX_).\n");
diff --git a/passes/techmap/maccmap.cc b/passes/techmap/maccmap.cc
index 3bb929009..43f2d97f5 100644
--- a/passes/techmap/maccmap.cc
+++ b/passes/techmap/maccmap.cc
@@ -365,7 +365,7 @@ PRIVATE_NAMESPACE_BEGIN
struct MaccmapPass : public Pass {
MaccmapPass() : Pass("maccmap", "mapping macc cells") { }
- void help() YS_OVERRIDE
+ void help() override
{
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
log("\n");
@@ -375,7 +375,7 @@ struct MaccmapPass : public Pass {
log("is used then the $macc cell is mapped to $add, $sub, etc. cells instead.\n");
log("\n");
}
- void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
+ void execute(std::vector<std::string> args, RTLIL::Design *design) override
{
bool unmap_mode = false;
diff --git a/passes/techmap/muxcover.cc b/passes/techmap/muxcover.cc
index bd049d86d..24109b579 100644
--- a/passes/techmap/muxcover.cc
+++ b/passes/techmap/muxcover.cc
@@ -623,7 +623,7 @@ struct MuxcoverWorker
struct MuxcoverPass : public Pass {
MuxcoverPass() : Pass("muxcover", "cover trees of MUX cells with wider MUXes") { }
- void help() YS_OVERRIDE
+ void help() override
{
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
log("\n");
@@ -656,7 +656,7 @@ struct MuxcoverPass : public Pass {
log(" than <N> different signals.\n");
log("\n");
}
- void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
+ void execute(std::vector<std::string> args, RTLIL::Design *design) override
{
log_header(design, "Executing MUXCOVER pass (mapping to wider MUXes).\n");
diff --git a/passes/techmap/nlutmap.cc b/passes/techmap/nlutmap.cc
index 798d82248..e1ebfcad8 100644
--- a/passes/techmap/nlutmap.cc
+++ b/passes/techmap/nlutmap.cc
@@ -129,7 +129,7 @@ struct NlutmapWorker
struct NlutmapPass : public Pass {
NlutmapPass() : Pass("nlutmap", "map to LUTs of different sizes") { }
- void help() YS_OVERRIDE
+ void help() override
{
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
log("\n");
@@ -149,7 +149,7 @@ struct NlutmapPass : public Pass {
log("to generic logic gates ($_AND_, etc.).\n");
log("\n");
}
- void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
+ void execute(std::vector<std::string> args, RTLIL::Design *design) override
{
NlutmapConfig config;
diff --git a/passes/techmap/pmuxtree.cc b/passes/techmap/pmuxtree.cc
index 2810b7f2d..b937d3fb0 100644
--- a/passes/techmap/pmuxtree.cc
+++ b/passes/techmap/pmuxtree.cc
@@ -67,7 +67,7 @@ static SigSpec recursive_mux_generator(Module *module, const SigSpec &sig_data,
struct PmuxtreePass : public Pass {
PmuxtreePass() : Pass("pmuxtree", "transform $pmux cells to trees of $mux cells") { }
- void help() YS_OVERRIDE
+ void help() override
{
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
log("\n");
@@ -76,7 +76,7 @@ struct PmuxtreePass : public Pass {
log("This pass transforms $pmux cells to trees of $mux cells.\n");
log("\n");
}
- void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
+ void execute(std::vector<std::string> args, RTLIL::Design *design) override
{
log_header(design, "Executing PMUXTREE pass.\n");
diff --git a/passes/techmap/shregmap.cc b/passes/techmap/shregmap.cc
index d7a381e0a..237c261ae 100644
--- a/passes/techmap/shregmap.cc
+++ b/passes/techmap/shregmap.cc
@@ -403,7 +403,7 @@ struct ShregmapWorker
struct ShregmapPass : public Pass {
ShregmapPass() : Pass("shregmap", "map shift registers") { }
- void help() YS_OVERRIDE
+ void help() override
{
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
log("\n");
@@ -461,7 +461,7 @@ struct ShregmapPass : public Pass {
log(" map to greenpak4 shift registers.\n");
log("\n");
}
- void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
+ void execute(std::vector<std::string> args, RTLIL::Design *design) override
{
ShregmapOptions opts;
string clkpol, enpol;
diff --git a/passes/techmap/simplemap.cc b/passes/techmap/simplemap.cc
index b65b3e972..b9d337da4 100644
--- a/passes/techmap/simplemap.cc
+++ b/passes/techmap/simplemap.cc
@@ -474,29 +474,93 @@ void simplemap_dffsr(RTLIL::Module *module, RTLIL::Cell *cell)
}
}
-void simplemap_adff(RTLIL::Module *module, RTLIL::Cell *cell)
+void simplemap_dffsre(RTLIL::Module *module, RTLIL::Cell *cell)
{
int width = cell->parameters.at(ID::WIDTH).as_int();
char clk_pol = cell->parameters.at(ID::CLK_POLARITY).as_bool() ? 'P' : 'N';
- char rst_pol = cell->parameters.at(ID::ARST_POLARITY).as_bool() ? 'P' : 'N';
+ char set_pol = cell->parameters.at(ID::SET_POLARITY).as_bool() ? 'P' : 'N';
+ char clr_pol = cell->parameters.at(ID::CLR_POLARITY).as_bool() ? 'P' : 'N';
+ char en_pol = cell->parameters.at(ID::EN_POLARITY).as_bool() ? 'P' : 'N';
- std::vector<RTLIL::State> rst_val = cell->parameters.at(ID::ARST_VALUE).bits;
+ RTLIL::SigSpec sig_clk = cell->getPort(ID::CLK);
+ RTLIL::SigSpec sig_s = cell->getPort(ID::SET);
+ RTLIL::SigSpec sig_r = cell->getPort(ID::CLR);
+ RTLIL::SigSpec sig_e = cell->getPort(ID::EN);
+ RTLIL::SigSpec sig_d = cell->getPort(ID::D);
+ RTLIL::SigSpec sig_q = cell->getPort(ID::Q);
+
+ IdString gate_type = stringf("$_DFFSRE_%c%c%c%c_", clk_pol, set_pol, clr_pol, en_pol);
+
+ for (int i = 0; i < width; i++) {
+ RTLIL::Cell *gate = module->addCell(NEW_ID, gate_type);
+ gate->add_strpool_attribute(ID::src, cell->get_strpool_attribute(ID::src));
+ gate->setPort(ID::C, sig_clk);
+ gate->setPort(ID::S, sig_s[i]);
+ gate->setPort(ID::R, sig_r[i]);
+ gate->setPort(ID::E, sig_e);
+ gate->setPort(ID::D, sig_d[i]);
+ gate->setPort(ID::Q, sig_q[i]);
+ }
+}
+
+void simplemap_adff_sdff(RTLIL::Module *module, RTLIL::Cell *cell)
+{
+ int width = cell->parameters.at(ID::WIDTH).as_int();
+ bool is_async = cell->type == ID($adff);
+ char clk_pol = cell->parameters.at(ID::CLK_POLARITY).as_bool() ? 'P' : 'N';
+ char rst_pol = cell->parameters.at(is_async ? ID::ARST_POLARITY : ID::SRST_POLARITY).as_bool() ? 'P' : 'N';
+ const char *type = is_async ? "DFF" : "SDFF";
+
+ std::vector<RTLIL::State> rst_val = cell->parameters.at(is_async ? ID::ARST_VALUE : ID::SRST_VALUE).bits;
while (int(rst_val.size()) < width)
rst_val.push_back(RTLIL::State::S0);
RTLIL::SigSpec sig_clk = cell->getPort(ID::CLK);
- RTLIL::SigSpec sig_rst = cell->getPort(ID::ARST);
+ RTLIL::SigSpec sig_rst = cell->getPort(is_async ? ID::ARST : ID::SRST);
+ RTLIL::SigSpec sig_d = cell->getPort(ID::D);
+ RTLIL::SigSpec sig_q = cell->getPort(ID::Q);
+
+ IdString gate_type_0 = stringf("$_%s_%c%c0_", type, clk_pol, rst_pol);
+ IdString gate_type_1 = stringf("$_%s_%c%c1_", type, clk_pol, rst_pol);
+
+ for (int i = 0; i < width; i++) {
+ RTLIL::Cell *gate = module->addCell(NEW_ID, rst_val.at(i) == RTLIL::State::S1 ? gate_type_1 : gate_type_0);
+ gate->add_strpool_attribute(ID::src, cell->get_strpool_attribute(ID::src));
+ gate->setPort(ID::C, sig_clk);
+ gate->setPort(ID::R, sig_rst);
+ gate->setPort(ID::D, sig_d[i]);
+ gate->setPort(ID::Q, sig_q[i]);
+ }
+}
+
+void simplemap_adffe_sdffe_sdffce(RTLIL::Module *module, RTLIL::Cell *cell)
+{
+ int width = cell->parameters.at(ID::WIDTH).as_int();
+ bool is_async = cell->type == ID($adffe);
+ char clk_pol = cell->parameters.at(ID::CLK_POLARITY).as_bool() ? 'P' : 'N';
+ char rst_pol = cell->parameters.at(is_async ? ID::ARST_POLARITY : ID::SRST_POLARITY).as_bool() ? 'P' : 'N';
+ char en_pol = cell->parameters.at(ID::EN_POLARITY).as_bool() ? 'P' : 'N';
+ const char *type = is_async ? "DFFE" : cell->type == ID($sdffe) ? "SDFFE" : "SDFFCE";
+
+ std::vector<RTLIL::State> rst_val = cell->parameters.at(is_async ? ID::ARST_VALUE : ID::SRST_VALUE).bits;
+ while (int(rst_val.size()) < width)
+ rst_val.push_back(RTLIL::State::S0);
+
+ RTLIL::SigSpec sig_clk = cell->getPort(ID::CLK);
+ RTLIL::SigSpec sig_rst = cell->getPort(is_async ? ID::ARST : ID::SRST);
+ RTLIL::SigSpec sig_e = cell->getPort(ID::EN);
RTLIL::SigSpec sig_d = cell->getPort(ID::D);
RTLIL::SigSpec sig_q = cell->getPort(ID::Q);
- IdString gate_type_0 = stringf("$_DFF_%c%c0_", clk_pol, rst_pol);
- IdString gate_type_1 = stringf("$_DFF_%c%c1_", clk_pol, rst_pol);
+ IdString gate_type_0 = stringf("$_%s_%c%c0%c_", type, clk_pol, rst_pol, en_pol);
+ IdString gate_type_1 = stringf("$_%s_%c%c1%c_", type, clk_pol, rst_pol, en_pol);
for (int i = 0; i < width; i++) {
RTLIL::Cell *gate = module->addCell(NEW_ID, rst_val.at(i) == RTLIL::State::S1 ? gate_type_1 : gate_type_0);
gate->add_strpool_attribute(ID::src, cell->get_strpool_attribute(ID::src));
gate->setPort(ID::C, sig_clk);
gate->setPort(ID::R, sig_rst);
+ gate->setPort(ID::E, sig_e);
gate->setPort(ID::D, sig_d[i]);
gate->setPort(ID::Q, sig_q[i]);
}
@@ -522,7 +586,61 @@ void simplemap_dlatch(RTLIL::Module *module, RTLIL::Cell *cell)
}
}
-void simplemap_get_mappers(std::map<RTLIL::IdString, void(*)(RTLIL::Module*, RTLIL::Cell*)> &mappers)
+void simplemap_adlatch(RTLIL::Module *module, RTLIL::Cell *cell)
+{
+ int width = cell->parameters.at(ID::WIDTH).as_int();
+ char en_pol = cell->parameters.at(ID::EN_POLARITY).as_bool() ? 'P' : 'N';
+ char rst_pol = cell->parameters.at(ID::ARST_POLARITY).as_bool() ? 'P' : 'N';
+
+ std::vector<RTLIL::State> rst_val = cell->parameters.at(ID::ARST_VALUE).bits;
+ while (int(rst_val.size()) < width)
+ rst_val.push_back(RTLIL::State::S0);
+
+ RTLIL::SigSpec sig_en = cell->getPort(ID::EN);
+ RTLIL::SigSpec sig_rst = cell->getPort(ID::ARST);
+ RTLIL::SigSpec sig_d = cell->getPort(ID::D);
+ RTLIL::SigSpec sig_q = cell->getPort(ID::Q);
+
+ IdString gate_type_0 = stringf("$_DLATCH_%c%c0_", en_pol, rst_pol);
+ IdString gate_type_1 = stringf("$_DLATCH_%c%c1_", en_pol, rst_pol);
+
+ for (int i = 0; i < width; i++) {
+ RTLIL::Cell *gate = module->addCell(NEW_ID, rst_val.at(i) == RTLIL::State::S1 ? gate_type_1 : gate_type_0);
+ gate->add_strpool_attribute(ID::src, cell->get_strpool_attribute(ID::src));
+ gate->setPort(ID::E, sig_en);
+ gate->setPort(ID::R, sig_rst);
+ gate->setPort(ID::D, sig_d[i]);
+ gate->setPort(ID::Q, sig_q[i]);
+ }
+}
+
+void simplemap_dlatchsr(RTLIL::Module *module, RTLIL::Cell *cell)
+{
+ int width = cell->parameters.at(ID::WIDTH).as_int();
+ char en_pol = cell->parameters.at(ID::EN_POLARITY).as_bool() ? 'P' : 'N';
+ char set_pol = cell->parameters.at(ID::SET_POLARITY).as_bool() ? 'P' : 'N';
+ char clr_pol = cell->parameters.at(ID::CLR_POLARITY).as_bool() ? 'P' : 'N';
+
+ RTLIL::SigSpec sig_en = cell->getPort(ID::EN);
+ RTLIL::SigSpec sig_s = cell->getPort(ID::SET);
+ RTLIL::SigSpec sig_r = cell->getPort(ID::CLR);
+ RTLIL::SigSpec sig_d = cell->getPort(ID::D);
+ RTLIL::SigSpec sig_q = cell->getPort(ID::Q);
+
+ IdString gate_type = stringf("$_DLATCHSR_%c%c%c_", en_pol, set_pol, clr_pol);
+
+ for (int i = 0; i < width; i++) {
+ RTLIL::Cell *gate = module->addCell(NEW_ID, gate_type);
+ gate->add_strpool_attribute(ID::src, cell->get_strpool_attribute(ID::src));
+ gate->setPort(ID::E, sig_en);
+ gate->setPort(ID::S, sig_s[i]);
+ gate->setPort(ID::R, sig_r[i]);
+ gate->setPort(ID::D, sig_d[i]);
+ gate->setPort(ID::Q, sig_q[i]);
+ }
+}
+
+void simplemap_get_mappers(dict<IdString, void(*)(RTLIL::Module*, RTLIL::Cell*)> &mappers)
{
mappers[ID($not)] = simplemap_not;
mappers[ID($pos)] = simplemap_pos;
@@ -553,13 +671,20 @@ void simplemap_get_mappers(std::map<RTLIL::IdString, void(*)(RTLIL::Module*, RTL
mappers[ID($dff)] = simplemap_dff;
mappers[ID($dffe)] = simplemap_dffe;
mappers[ID($dffsr)] = simplemap_dffsr;
- mappers[ID($adff)] = simplemap_adff;
+ mappers[ID($dffsre)] = simplemap_dffsre;
+ mappers[ID($adff)] = simplemap_adff_sdff;
+ mappers[ID($sdff)] = simplemap_adff_sdff;
+ mappers[ID($adffe)] = simplemap_adffe_sdffe_sdffce;
+ mappers[ID($sdffe)] = simplemap_adffe_sdffe_sdffce;
+ mappers[ID($sdffce)] = simplemap_adffe_sdffe_sdffce;
mappers[ID($dlatch)] = simplemap_dlatch;
+ mappers[ID($adlatch)] = simplemap_adlatch;
+ mappers[ID($dlatchsr)] = simplemap_dlatchsr;
}
void simplemap(RTLIL::Module *module, RTLIL::Cell *cell)
{
- static std::map<RTLIL::IdString, void(*)(RTLIL::Module*, RTLIL::Cell*)> mappers;
+ static dict<IdString, void(*)(RTLIL::Module*, RTLIL::Cell*)> mappers;
static bool initialized_mappers = false;
if (!initialized_mappers) {
@@ -575,7 +700,7 @@ PRIVATE_NAMESPACE_BEGIN
struct SimplemapPass : public Pass {
SimplemapPass() : Pass("simplemap", "mapping simple coarse-grain cells") { }
- void help() YS_OVERRIDE
+ void help() override
{
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
log("\n");
@@ -587,15 +712,15 @@ struct SimplemapPass : public Pass {
log(" $not, $pos, $and, $or, $xor, $xnor\n");
log(" $reduce_and, $reduce_or, $reduce_xor, $reduce_xnor, $reduce_bool\n");
log(" $logic_not, $logic_and, $logic_or, $mux, $tribuf\n");
- log(" $sr, $ff, $dff, $dffsr, $adff, $dlatch\n");
+ log(" $sr, $ff, $dff, $dffe, $dffsr, $dffsre, $adff, $adffe, $sdff, $sdffe, $sdffce, $dlatch, $adlatch, $dlatchsr\n");
log("\n");
}
- void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
+ void execute(std::vector<std::string> args, RTLIL::Design *design) override
{
log_header(design, "Executing SIMPLEMAP pass (map simple cells to gate primitives).\n");
extra_args(args, 1, design);
- std::map<RTLIL::IdString, void(*)(RTLIL::Module*, RTLIL::Cell*)> mappers;
+ dict<IdString, void(*)(RTLIL::Module*, RTLIL::Cell*)> mappers;
simplemap_get_mappers(mappers);
for (auto mod : design->modules()) {
diff --git a/passes/techmap/simplemap.h b/passes/techmap/simplemap.h
index c2d73ea79..5091050a1 100644
--- a/passes/techmap/simplemap.h
+++ b/passes/techmap/simplemap.h
@@ -42,7 +42,7 @@ extern void simplemap_adff(RTLIL::Module *module, RTLIL::Cell *cell);
extern void simplemap_dlatch(RTLIL::Module *module, RTLIL::Cell *cell);
extern void simplemap(RTLIL::Module *module, RTLIL::Cell *cell);
-extern void simplemap_get_mappers(std::map<RTLIL::IdString, void(*)(RTLIL::Module*, RTLIL::Cell*)> &mappers);
+extern void simplemap_get_mappers(dict<RTLIL::IdString, void(*)(RTLIL::Module*, RTLIL::Cell*)> &mappers);
YOSYS_NAMESPACE_END
diff --git a/passes/techmap/techmap.cc b/passes/techmap/techmap.cc
index a554be257..f98d1564a 100644
--- a/passes/techmap/techmap.cc
+++ b/passes/techmap/techmap.cc
@@ -27,7 +27,6 @@
#include <string.h>
#include "simplemap.h"
-#include "passes/techmap/techmap.inc"
YOSYS_NAMESPACE_BEGIN
@@ -51,27 +50,23 @@ void apply_prefix(IdString prefix, RTLIL::SigSpec &sig, RTLIL::Module *module)
{
vector<SigChunk> chunks = sig;
for (auto &chunk : chunks)
- if (chunk.wire != NULL) {
+ if (chunk.wire != nullptr) {
IdString wire_name = chunk.wire->name;
apply_prefix(prefix, wire_name);
- log_assert(module->wires_.count(wire_name) > 0);
- chunk.wire = module->wires_[wire_name];
+ log_assert(module->wire(wire_name) != nullptr);
+ chunk.wire = module->wire(wire_name);
}
sig = chunks;
}
struct TechmapWorker
{
- std::map<RTLIL::IdString, void(*)(RTLIL::Module*, RTLIL::Cell*)> simplemap_mappers;
- std::map<std::pair<RTLIL::IdString, std::map<RTLIL::IdString, RTLIL::Const>>, RTLIL::Module*> techmap_cache;
- std::map<RTLIL::Module*, bool> techmap_do_cache;
- std::set<RTLIL::Module*, RTLIL::IdString::compare_ptr_by_name<RTLIL::Module>> module_queue;
+ dict<IdString, void(*)(RTLIL::Module*, RTLIL::Cell*)> simplemap_mappers;
+ dict<std::pair<IdString, dict<IdString, RTLIL::Const>>, RTLIL::Module*> techmap_cache;
+ dict<RTLIL::Module*, bool> techmap_do_cache;
+ pool<RTLIL::Module*> module_queue;
dict<Module*, SigMap> sigmaps;
- pool<IdString> flatten_do_list;
- pool<IdString> flatten_done_list;
- pool<Cell*> flatten_keep_list;
-
pool<string> log_msg_cache;
struct TechmapWireData {
@@ -79,31 +74,20 @@ struct TechmapWorker
RTLIL::SigSpec value;
};
- typedef std::map<std::string, std::vector<TechmapWireData>> TechmapWires;
+ typedef dict<IdString, std::vector<TechmapWireData>> TechmapWires;
- bool extern_mode;
- bool assert_mode;
- bool flatten_mode;
- bool recursive_mode;
- bool autoproc_mode;
- bool ignore_wb;
-
- TechmapWorker()
- {
- extern_mode = false;
- assert_mode = false;
- flatten_mode = false;
- recursive_mode = false;
- autoproc_mode = false;
- ignore_wb = false;
- }
+ bool extern_mode = false;
+ bool assert_mode = false;
+ bool recursive_mode = false;
+ bool autoproc_mode = false;
+ bool ignore_wb = false;
std::string constmap_tpl_name(SigMap &sigmap, RTLIL::Module *tpl, RTLIL::Cell *cell, bool verbose)
{
std::string constmap_info;
- std::map<RTLIL::SigBit, std::pair<RTLIL::IdString, int>> connbits_map;
+ dict<RTLIL::SigBit, std::pair<IdString, int>> connbits_map;
- for (auto conn : cell->connections())
+ for (auto &conn : cell->connections())
for (int i = 0; i < GetSize(conn.second); i++) {
RTLIL::SigBit bit = sigmap(conn.second[i]);
if (bit.wire == nullptr) {
@@ -117,7 +101,7 @@ struct TechmapWorker
constmap_info += stringf("|%s %d %s %d", log_id(conn.first), i,
log_id(connbits_map.at(bit).first), connbits_map.at(bit).second);
} else {
- connbits_map[bit] = std::pair<RTLIL::IdString, int>(conn.first, i);
+ connbits_map.emplace(bit, std::make_pair(conn.first, i));
constmap_info += stringf("|%s %d", log_id(conn.first), i);
}
}
@@ -129,24 +113,25 @@ struct TechmapWorker
{
TechmapWires result;
- if (module == NULL)
+ if (module == nullptr)
return result;
- for (auto &it : module->wires_) {
- const char *p = it.first.c_str();
+ for (auto w : module->wires()) {
+ const char *p = w->name.c_str();
if (*p == '$')
continue;
const char *q = strrchr(p+1, '.');
- p = q ? q+1 : p+1;
+ if (q)
+ p = q;
- if (!strncmp(p, "_TECHMAP_", 9)) {
+ if (!strncmp(p, "\\_TECHMAP_", 10)) {
TechmapWireData record;
- record.wire = it.second;
- record.value = it.second;
+ record.wire = w;
+ record.value = w;
result[p].push_back(record);
- it.second->attributes[ID::keep] = RTLIL::Const(1);
- it.second->attributes[ID::_techmap_special_] = RTLIL::Const(1);
+ w->set_bool_attribute(ID::keep);
+ w->set_bool_attribute(ID::_techmap_special_);
}
}
@@ -165,7 +150,7 @@ struct TechmapWorker
if (tpl->processes.size() != 0) {
log("Technology map yielded processes:");
for (auto &it : tpl->processes)
- log(" %s",RTLIL::id2cstr(it.first));
+ log(" %s",log_id(it.first));
log("\n");
if (autoproc_mode) {
Pass::call_on_module(tpl->design, tpl, "proc");
@@ -178,89 +163,71 @@ struct TechmapWorker
pool<string> extra_src_attrs = cell->get_strpool_attribute(ID::src);
orig_cell_name = cell->name.str();
- if (!flatten_mode) {
- for (auto &it : tpl->cells_)
- if (it.first == ID::_TECHMAP_REPLACE_) {
- module->rename(cell, stringf("$techmap%d", autoidx++) + cell->name.str());
- break;
- }
- }
+ for (auto tpl_cell : tpl->cells())
+ if (tpl_cell->name == ID::_TECHMAP_REPLACE_) {
+ module->rename(cell, stringf("$techmap%d", autoidx++) + cell->name.str());
+ break;
+ }
dict<IdString, IdString> memory_renames;
for (auto &it : tpl->memories) {
IdString m_name = it.first;
apply_prefix(cell->name, m_name);
- RTLIL::Memory *m = new RTLIL::Memory;
- m->name = m_name;
- m->width = it.second->width;
- m->start_offset = it.second->start_offset;
- m->size = it.second->size;
- m->attributes = it.second->attributes;
+ RTLIL::Memory *m = module->addMemory(m_name, it.second);
if (m->attributes.count(ID::src))
m->add_strpool_attribute(ID::src, extra_src_attrs);
- module->memories[m->name] = m;
memory_renames[it.first] = m->name;
design->select(module, m);
}
- std::map<RTLIL::IdString, RTLIL::IdString> positional_ports;
+ dict<IdString, IdString> positional_ports;
dict<Wire*, IdString> temp_renamed_wires;
pool<SigBit> autopurge_tpl_bits;
- for (auto &it : tpl->wires_)
+ for (auto tpl_w : tpl->wires())
{
- if (it.second->port_id > 0)
+ if (tpl_w->port_id > 0)
{
- IdString posportname = stringf("$%d", it.second->port_id);
- positional_ports[posportname] = it.first;
+ IdString posportname = stringf("$%d", tpl_w->port_id);
+ positional_ports.emplace(posportname, tpl_w->name);
- if (!flatten_mode && it.second->get_bool_attribute(ID::techmap_autopurge) &&
- (!cell->hasPort(it.second->name) || !GetSize(cell->getPort(it.second->name))) &&
+ if (tpl_w->get_bool_attribute(ID::techmap_autopurge) &&
+ (!cell->hasPort(tpl_w->name) || !GetSize(cell->getPort(tpl_w->name))) &&
(!cell->hasPort(posportname) || !GetSize(cell->getPort(posportname))))
{
if (sigmaps.count(tpl) == 0)
sigmaps[tpl].set(tpl);
- for (auto bit : sigmaps.at(tpl)(it.second))
+ for (auto bit : sigmaps.at(tpl)(tpl_w))
if (bit.wire != nullptr)
autopurge_tpl_bits.insert(bit);
}
}
- IdString w_name = it.second->name;
+ IdString w_name = tpl_w->name;
apply_prefix(cell->name, w_name);
RTLIL::Wire *w = module->wire(w_name);
if (w != nullptr) {
- if (!flatten_mode || !w->get_bool_attribute(ID::hierconn)) {
- temp_renamed_wires[w] = w->name;
- module->rename(w, NEW_ID);
- w = nullptr;
- } else {
- w->attributes.erase(ID::hierconn);
- if (GetSize(w) < GetSize(it.second)) {
- log_warning("Widening signal %s.%s to match size of %s.%s (via %s.%s).\n", log_id(module), log_id(w),
- log_id(tpl), log_id(it.second), log_id(module), log_id(cell));
- w->width = GetSize(it.second);
- }
- }
+ temp_renamed_wires[w] = w->name;
+ module->rename(w, NEW_ID);
+ w = nullptr;
}
if (w == nullptr) {
- w = module->addWire(w_name, it.second);
+ w = module->addWire(w_name, tpl_w);
w->port_input = false;
w->port_output = false;
w->port_id = 0;
- if (!flatten_mode)
- w->attributes.erase(ID::techmap_autopurge);
- if (it.second->get_bool_attribute(ID::_techmap_special_))
+ w->attributes.erase(ID::techmap_autopurge);
+ if (tpl_w->get_bool_attribute(ID::_techmap_special_))
w->attributes.clear();
if (w->attributes.count(ID::src))
w->add_strpool_attribute(ID::src, extra_src_attrs);
}
design->select(module, w);
- if (it.second->name.begins_with("\\_TECHMAP_REPLACE_.")) {
- IdString replace_name = stringf("%s%s", orig_cell_name.c_str(), it.second->name.c_str() + strlen("\\_TECHMAP_REPLACE_"));
- Wire *replace_w = module->addWire(replace_name, it.second);
+ if (tpl_w->name.begins_with("\\_TECHMAP_REPLACE_.")) {
+ IdString replace_name = stringf("%s%s", orig_cell_name.c_str(), tpl_w->name.c_str() + strlen("\\_TECHMAP_REPLACE_"));
+ Wire *replace_w = module->addWire(replace_name, tpl_w);
module->connect(replace_w, w);
}
}
@@ -268,24 +235,23 @@ struct TechmapWorker
SigMap tpl_sigmap(tpl);
pool<SigBit> tpl_written_bits;
- for (auto &it1 : tpl->cells_)
- for (auto &it2 : it1.second->connections_)
- if (it1.second->output(it2.first))
- for (auto bit : tpl_sigmap(it2.second))
+ for (auto tpl_cell : tpl->cells())
+ for (auto &conn : tpl_cell->connections())
+ if (tpl_cell->output(conn.first))
+ for (auto bit : tpl_sigmap(conn.second))
tpl_written_bits.insert(bit);
- for (auto &it1 : tpl->connections_)
- for (auto bit : tpl_sigmap(it1.first))
+ for (auto &conn : tpl->connections())
+ for (auto bit : tpl_sigmap(conn.first))
tpl_written_bits.insert(bit);
SigMap port_signal_map;
- SigSig port_signal_assign;
for (auto &it : cell->connections())
{
- RTLIL::IdString portname = it.first;
+ IdString portname = it.first;
if (positional_ports.count(portname) > 0)
portname = positional_ports.at(portname);
- if (tpl->wires_.count(portname) == 0 || tpl->wires_.at(portname)->port_id == 0) {
+ if (tpl->wire(portname) == nullptr || tpl->wire(portname)->port_id == 0) {
if (portname.begins_with("$"))
log_error("Can't map port `%s' of cell `%s' to template `%s'!\n", portname.c_str(), cell->name.c_str(), tpl->name.c_str());
continue;
@@ -294,7 +260,7 @@ struct TechmapWorker
if (GetSize(it.second) == 0)
continue;
- RTLIL::Wire *w = tpl->wires_.at(portname);
+ RTLIL::Wire *w = tpl->wire(portname);
RTLIL::SigSig c, extra_connect;
if (w->port_output && !w->port_input) {
@@ -333,76 +299,58 @@ struct TechmapWorker
log_assert(c.first.size() == c.second.size());
- if (flatten_mode)
- {
- // more conservative approach:
- // connect internal and external wires
-
- if (sigmaps.count(module) == 0)
- sigmaps[module].set(module);
-
- if (sigmaps.at(module)(c.first).has_const())
- log_error("Mismatch in directionality for cell port %s.%s.%s: %s <= %s\n",
- log_id(module), log_id(cell), log_id(it.first), log_signal(c.first), log_signal(c.second));
+ // replace internal wires that are connected to external wires
+ if (w->port_output && !w->port_input) {
+ port_signal_map.add(c.second, c.first);
+ } else
+ if (!w->port_output && w->port_input) {
+ port_signal_map.add(c.first, c.second);
+ } else {
module->connect(c);
+ extra_connect = SigSig();
}
- else
- {
- // approach that yields nicer outputs:
- // replace internal wires that are connected to external wires
-
- if (w->port_output && !w->port_input) {
- port_signal_map.add(c.second, c.first);
- } else
- if (!w->port_output && w->port_input) {
- port_signal_map.add(c.first, c.second);
- } else {
- module->connect(c);
- extra_connect = SigSig();
- }
- for (auto &attr : w->attributes) {
- if (attr.first == ID::src)
- continue;
- auto lhs = GetSize(extra_connect.first);
- auto rhs = GetSize(extra_connect.second);
- if (lhs > rhs)
- extra_connect.first.remove(rhs, lhs-rhs);
- else if (rhs > lhs)
- extra_connect.second.remove(lhs, rhs-lhs);
- module->connect(extra_connect);
- break;
- }
+ for (auto &attr : w->attributes) {
+ if (attr.first == ID::src)
+ continue;
+ auto lhs = GetSize(extra_connect.first);
+ auto rhs = GetSize(extra_connect.second);
+ if (lhs > rhs)
+ extra_connect.first.remove(rhs, lhs-rhs);
+ else if (rhs > lhs)
+ extra_connect.second.remove(lhs, rhs-lhs);
+ module->connect(extra_connect);
+ break;
}
}
- for (auto &it : tpl->cells_)
+ for (auto tpl_cell : tpl->cells())
{
- IdString c_name = it.second->name.str();
- bool techmap_replace_cell = (!flatten_mode) && (c_name == ID::_TECHMAP_REPLACE_);
+ IdString c_name = tpl_cell->name;
+ bool techmap_replace_cell = (c_name == ID::_TECHMAP_REPLACE_);
if (techmap_replace_cell)
c_name = orig_cell_name;
- else if (it.second->name.begins_with("\\_TECHMAP_REPLACE_."))
+ else if (tpl_cell->name.begins_with("\\_TECHMAP_REPLACE_."))
c_name = stringf("%s%s", orig_cell_name.c_str(), c_name.c_str() + strlen("\\_TECHMAP_REPLACE_"));
else
apply_prefix(cell->name, c_name);
- RTLIL::Cell *c = module->addCell(c_name, it.second);
+ RTLIL::Cell *c = module->addCell(c_name, tpl_cell);
design->select(module, c);
- if (!flatten_mode && c->type.begins_with("\\$"))
+ if (c->type.begins_with("\\$"))
c->type = c->type.substr(1);
vector<IdString> autopurge_ports;
- for (auto &it2 : c->connections_)
+ for (auto &conn : c->connections())
{
bool autopurge = false;
if (!autopurge_tpl_bits.empty()) {
- autopurge = GetSize(it2.second) != 0;
- for (auto &bit : sigmaps.at(tpl)(it2.second))
+ autopurge = GetSize(conn.second) != 0;
+ for (auto &bit : sigmaps.at(tpl)(conn.second))
if (!autopurge_tpl_bits.count(bit)) {
autopurge = false;
break;
@@ -410,10 +358,12 @@ struct TechmapWorker
}
if (autopurge) {
- autopurge_ports.push_back(it2.first);
+ autopurge_ports.push_back(conn.first);
} else {
- apply_prefix(cell->name, it2.second, module);
- port_signal_map.apply(it2.second);
+ RTLIL::SigSpec new_conn = conn.second;
+ apply_prefix(cell->name, new_conn, module);
+ port_signal_map.apply(new_conn);
+ c->setPort(conn.first, std::move(new_conn));
}
}
@@ -463,8 +413,8 @@ struct TechmapWorker
}
}
- bool techmap_module(RTLIL::Design *design, RTLIL::Module *module, RTLIL::Design *map, std::set<RTLIL::Cell*> &handled_cells,
- const std::map<RTLIL::IdString, std::set<RTLIL::IdString, RTLIL::sort_by_id_str>> &celltypeMap, bool in_recursion)
+ bool techmap_module(RTLIL::Design *design, RTLIL::Module *module, RTLIL::Design *map, pool<RTLIL::Cell*> &handled_cells,
+ const dict<IdString, pool<IdString>> &celltypeMap, bool in_recursion)
{
std::string mapmsg_prefix = in_recursion ? "Recursively mapping" : "Mapping";
@@ -489,13 +439,13 @@ struct TechmapWorker
}
}
- TopoSort<RTLIL::Cell*, RTLIL::IdString::compare_ptr_by_name<RTLIL::Cell>> cells;
- std::map<RTLIL::Cell*, std::set<RTLIL::SigBit>> cell_to_inbit;
- std::map<RTLIL::SigBit, std::set<RTLIL::Cell*>> outbit_to_cell;
+ TopoSort<RTLIL::Cell*, IdString::compare_ptr_by_name<RTLIL::Cell>> cells;
+ dict<RTLIL::Cell*, pool<RTLIL::SigBit>> cell_to_inbit;
+ dict<RTLIL::SigBit, pool<RTLIL::Cell*>> outbit_to_cell;
- for (auto cell : module->cells())
+ for (auto cell : module->selected_cells())
{
- if (!design->selected(module, cell) || handled_cells.count(cell) > 0)
+ if (handled_cells.count(cell) > 0)
continue;
std::string cell_type = cell->type.str();
@@ -508,22 +458,6 @@ struct TechmapWorker
continue;
}
- if (flatten_mode) {
- bool keepit = cell->get_bool_attribute(ID::keep_hierarchy);
- for (auto &tpl_name : celltypeMap.at(cell_type))
- if (map->modules_[tpl_name]->get_bool_attribute(ID::keep_hierarchy))
- keepit = true;
- if (keepit) {
- if (!flatten_keep_list[cell]) {
- log("Keeping %s.%s (found keep_hierarchy property).\n", log_id(module), log_id(cell));
- flatten_keep_list.insert(cell);
- }
- if (!flatten_done_list[cell->type])
- flatten_do_list.insert(cell->type);
- continue;
- }
- }
-
for (auto &conn : cell->connections())
{
RTLIL::SigSpec sig = sigmap(conn.second);
@@ -533,7 +467,7 @@ struct TechmapWorker
continue;
for (auto &tpl_name : celltypeMap.at(cell_type)) {
- RTLIL::Module *tpl = map->modules_[tpl_name];
+ RTLIL::Module *tpl = map->module(tpl_name);
RTLIL::Wire *port = tpl->wire(conn.first);
if (port && port->port_input)
cell_to_inbit[cell].insert(sig.begin(), sig.end());
@@ -566,189 +500,188 @@ struct TechmapWorker
for (auto &tpl_name : celltypeMap.at(cell_type))
{
- RTLIL::IdString derived_name = tpl_name;
- RTLIL::Module *tpl = map->modules_[tpl_name];
- std::map<RTLIL::IdString, RTLIL::Const> parameters(cell->parameters.begin(), cell->parameters.end());
+ IdString derived_name = tpl_name;
+ RTLIL::Module *tpl = map->module(tpl_name);
+ dict<IdString, RTLIL::Const> parameters(cell->parameters);
if (tpl->get_blackbox_attribute(ignore_wb))
continue;
- if (!flatten_mode)
- {
- std::string extmapper_name;
+ std::string extmapper_name;
- if (tpl->get_bool_attribute(ID::techmap_simplemap))
- extmapper_name = "simplemap";
+ if (tpl->get_bool_attribute(ID::techmap_simplemap))
+ extmapper_name = "simplemap";
- if (tpl->get_bool_attribute(ID::techmap_maccmap))
- extmapper_name = "maccmap";
+ if (tpl->get_bool_attribute(ID::techmap_maccmap))
+ extmapper_name = "maccmap";
- if (tpl->attributes.count(ID::techmap_wrap))
- extmapper_name = "wrap";
+ if (tpl->attributes.count(ID::techmap_wrap))
+ extmapper_name = "wrap";
- if (!extmapper_name.empty())
- {
- cell->type = cell_type;
-
- if ((extern_mode && !in_recursion) || extmapper_name == "wrap")
- {
- std::string m_name = stringf("$extern:%s:%s", extmapper_name.c_str(), log_id(cell->type));
-
- for (auto &c : cell->parameters)
- m_name += stringf(":%s=%s", log_id(c.first), log_signal(c.second));
-
- if (extmapper_name == "wrap")
- m_name += ":" + sha1(tpl->attributes.at(ID::techmap_wrap).decode_string());
-
- RTLIL::Design *extmapper_design = extern_mode && !in_recursion ? design : tpl->design;
- RTLIL::Module *extmapper_module = extmapper_design->module(m_name);
+ if (!extmapper_name.empty())
+ {
+ cell->type = cell_type;
- if (extmapper_module == nullptr)
- {
- extmapper_module = extmapper_design->addModule(m_name);
- RTLIL::Cell *extmapper_cell = extmapper_module->addCell(cell->type, cell);
-
- extmapper_cell->set_src_attribute(cell->get_src_attribute());
-
- int port_counter = 1;
- for (auto &c : extmapper_cell->connections_) {
- RTLIL::Wire *w = extmapper_module->addWire(c.first, GetSize(c.second));
- if (w->name.in(ID::Y, ID::Q))
- w->port_output = true;
- else
- w->port_input = true;
- w->port_id = port_counter++;
- c.second = w;
- }
+ if ((extern_mode && !in_recursion) || extmapper_name == "wrap")
+ {
+ std::string m_name = stringf("$extern:%s:%s", extmapper_name.c_str(), log_id(cell->type));
- extmapper_module->fixup_ports();
- extmapper_module->check();
+ for (auto &c : cell->parameters)
+ m_name += stringf(":%s=%s", log_id(c.first), log_signal(c.second));
- if (extmapper_name == "simplemap") {
- log("Creating %s with simplemap.\n", log_id(extmapper_module));
- if (simplemap_mappers.count(extmapper_cell->type) == 0)
- log_error("No simplemap mapper for cell type %s found!\n", log_id(extmapper_cell->type));
- simplemap_mappers.at(extmapper_cell->type)(extmapper_module, extmapper_cell);
- extmapper_module->remove(extmapper_cell);
- }
+ if (extmapper_name == "wrap")
+ m_name += ":" + sha1(tpl->attributes.at(ID::techmap_wrap).decode_string());
- if (extmapper_name == "maccmap") {
- log("Creating %s with maccmap.\n", log_id(extmapper_module));
- if (extmapper_cell->type != ID($macc))
- log_error("The maccmap mapper can only map $macc (not %s) cells!\n", log_id(extmapper_cell->type));
- maccmap(extmapper_module, extmapper_cell);
- extmapper_module->remove(extmapper_cell);
- }
+ RTLIL::Design *extmapper_design = extern_mode && !in_recursion ? design : tpl->design;
+ RTLIL::Module *extmapper_module = extmapper_design->module(m_name);
- if (extmapper_name == "wrap") {
- std::string cmd_string = tpl->attributes.at(ID::techmap_wrap).decode_string();
- log("Running \"%s\" on wrapper %s.\n", cmd_string.c_str(), log_id(extmapper_module));
- mkdebug.on();
- Pass::call_on_module(extmapper_design, extmapper_module, cmd_string);
- log_continue = true;
- }
+ if (extmapper_module == nullptr)
+ {
+ extmapper_module = extmapper_design->addModule(m_name);
+ RTLIL::Cell *extmapper_cell = extmapper_module->addCell(cell->type, cell);
+
+ extmapper_cell->set_src_attribute(cell->get_src_attribute());
+
+ int port_counter = 1;
+ for (auto &c : extmapper_cell->connections_) {
+ RTLIL::Wire *w = extmapper_module->addWire(c.first, GetSize(c.second));
+ if (w->name.in(ID::Y, ID::Q))
+ w->port_output = true;
+ else
+ w->port_input = true;
+ w->port_id = port_counter++;
+ c.second = w;
}
- cell->type = extmapper_module->name;
- cell->parameters.clear();
+ extmapper_module->fixup_ports();
+ extmapper_module->check();
- if (!extern_mode || in_recursion) {
- tpl = extmapper_module;
- goto use_wrapper_tpl;
+ if (extmapper_name == "simplemap") {
+ log("Creating %s with simplemap.\n", log_id(extmapper_module));
+ if (simplemap_mappers.count(extmapper_cell->type) == 0)
+ log_error("No simplemap mapper for cell type %s found!\n", log_id(extmapper_cell->type));
+ simplemap_mappers.at(extmapper_cell->type)(extmapper_module, extmapper_cell);
+ extmapper_module->remove(extmapper_cell);
}
- auto msg = stringf("Using extmapper %s for cells of type %s.", log_id(extmapper_module), log_id(cell->type));
- if (!log_msg_cache.count(msg)) {
- log_msg_cache.insert(msg);
- log("%s\n", msg.c_str());
- }
- log_debug("%s %s.%s (%s) to %s.\n", mapmsg_prefix.c_str(), log_id(module), log_id(cell), log_id(cell->type), log_id(extmapper_module));
- }
- else
- {
- auto msg = stringf("Using extmapper %s for cells of type %s.", extmapper_name.c_str(), log_id(cell->type));
- if (!log_msg_cache.count(msg)) {
- log_msg_cache.insert(msg);
- log("%s\n", msg.c_str());
+ if (extmapper_name == "maccmap") {
+ log("Creating %s with maccmap.\n", log_id(extmapper_module));
+ if (extmapper_cell->type != ID($macc))
+ log_error("The maccmap mapper can only map $macc (not %s) cells!\n", log_id(extmapper_cell->type));
+ maccmap(extmapper_module, extmapper_cell);
+ extmapper_module->remove(extmapper_cell);
}
- log_debug("%s %s.%s (%s) with %s.\n", mapmsg_prefix.c_str(), log_id(module), log_id(cell), log_id(cell->type), extmapper_name.c_str());
- if (extmapper_name == "simplemap") {
- if (simplemap_mappers.count(cell->type) == 0)
- log_error("No simplemap mapper for cell type %s found!\n", RTLIL::id2cstr(cell->type));
- simplemap_mappers.at(cell->type)(module, cell);
+ if (extmapper_name == "wrap") {
+ std::string cmd_string = tpl->attributes.at(ID::techmap_wrap).decode_string();
+ log("Running \"%s\" on wrapper %s.\n", cmd_string.c_str(), log_id(extmapper_module));
+ mkdebug.on();
+ Pass::call_on_module(extmapper_design, extmapper_module, cmd_string);
+ log_continue = true;
}
+ }
- if (extmapper_name == "maccmap") {
- if (cell->type != ID($macc))
- log_error("The maccmap mapper can only map $macc (not %s) cells!\n", log_id(cell->type));
- maccmap(module, cell);
- }
+ cell->type = extmapper_module->name;
+ cell->parameters.clear();
- module->remove(cell);
- cell = NULL;
+ if (!extern_mode || in_recursion) {
+ tpl = extmapper_module;
+ goto use_wrapper_tpl;
}
- did_something = true;
- mapped_cell = true;
- break;
+ auto msg = stringf("Using extmapper %s for cells of type %s.", log_id(extmapper_module), log_id(cell->type));
+ if (!log_msg_cache.count(msg)) {
+ log_msg_cache.insert(msg);
+ log("%s\n", msg.c_str());
+ }
+ log_debug("%s %s.%s (%s) to %s.\n", mapmsg_prefix.c_str(), log_id(module), log_id(cell), log_id(cell->type), log_id(extmapper_module));
}
+ else
+ {
+ auto msg = stringf("Using extmapper %s for cells of type %s.", extmapper_name.c_str(), log_id(cell->type));
+ if (!log_msg_cache.count(msg)) {
+ log_msg_cache.insert(msg);
+ log("%s\n", msg.c_str());
+ }
+ log_debug("%s %s.%s (%s) with %s.\n", mapmsg_prefix.c_str(), log_id(module), log_id(cell), log_id(cell->type), extmapper_name.c_str());
+
+ if (extmapper_name == "simplemap") {
+ if (simplemap_mappers.count(cell->type) == 0)
+ log_error("No simplemap mapper for cell type %s found!\n", log_id(cell->type));
+ simplemap_mappers.at(cell->type)(module, cell);
+ }
- for (auto conn : cell->connections()) {
- if (conn.first.begins_with("$"))
- continue;
- if (tpl->wires_.count(conn.first) > 0 && tpl->wires_.at(conn.first)->port_id > 0)
- continue;
- if (!conn.second.is_fully_const() || parameters.count(conn.first) > 0 || tpl->avail_parameters.count(conn.first) == 0)
- goto next_tpl;
- parameters[conn.first] = conn.second.as_const();
+ if (extmapper_name == "maccmap") {
+ if (cell->type != ID($macc))
+ log_error("The maccmap mapper can only map $macc (not %s) cells!\n", log_id(cell->type));
+ maccmap(module, cell);
+ }
+
+ module->remove(cell);
+ cell = nullptr;
}
- if (0) {
- next_tpl:
+ did_something = true;
+ mapped_cell = true;
+ break;
+ }
+
+ for (auto &conn : cell->connections()) {
+ if (conn.first.begins_with("$"))
continue;
- }
+ if (tpl->wire(conn.first) != nullptr && tpl->wire(conn.first)->port_id > 0)
+ continue;
+ if (!conn.second.is_fully_const() || parameters.count(conn.first) > 0 || tpl->avail_parameters.count(conn.first) == 0)
+ goto next_tpl;
+ parameters[conn.first] = conn.second.as_const();
+ }
+
+ if (0) {
+ next_tpl:
+ continue;
+ }
- if (tpl->avail_parameters.count(ID::_TECHMAP_CELLTYPE_) != 0)
- parameters[ID::_TECHMAP_CELLTYPE_] = RTLIL::unescape_id(cell->type);
+ if (tpl->avail_parameters.count(ID::_TECHMAP_CELLTYPE_) != 0)
+ parameters.emplace(ID::_TECHMAP_CELLTYPE_, RTLIL::unescape_id(cell->type));
- for (auto conn : cell->connections()) {
- if (tpl->avail_parameters.count(stringf("\\_TECHMAP_CONSTMSK_%s_", RTLIL::id2cstr(conn.first))) != 0) {
- std::vector<RTLIL::SigBit> v = sigmap(conn.second).to_sigbit_vector();
- for (auto &bit : v)
- bit = RTLIL::SigBit(bit.wire == NULL ? RTLIL::State::S1 : RTLIL::State::S0);
- parameters[stringf("\\_TECHMAP_CONSTMSK_%s_", RTLIL::id2cstr(conn.first))] = RTLIL::SigSpec(v).as_const();
- }
- if (tpl->avail_parameters.count(stringf("\\_TECHMAP_CONSTVAL_%s_", RTLIL::id2cstr(conn.first))) != 0) {
- std::vector<RTLIL::SigBit> v = sigmap(conn.second).to_sigbit_vector();
- for (auto &bit : v)
- if (bit.wire != NULL)
- bit = RTLIL::SigBit(RTLIL::State::Sx);
- parameters[stringf("\\_TECHMAP_CONSTVAL_%s_", RTLIL::id2cstr(conn.first))] = RTLIL::SigSpec(v).as_const();
- }
- if (tpl->avail_parameters.count(stringf("\\_TECHMAP_WIREINIT_%s_", RTLIL::id2cstr(conn.first))) != 0) {
- auto sig = sigmap(conn.second);
- RTLIL::Const value(State::Sx, sig.size());
- for (int i = 0; i < sig.size(); i++) {
- auto it = init_bits.find(sig[i]);
- if (it != init_bits.end()) {
- value[i] = it->second;
- }
+ for (auto &conn : cell->connections()) {
+ if (tpl->avail_parameters.count(stringf("\\_TECHMAP_CONSTMSK_%s_", log_id(conn.first))) != 0) {
+ std::vector<RTLIL::SigBit> v = sigmap(conn.second).to_sigbit_vector();
+ for (auto &bit : v)
+ bit = RTLIL::SigBit(bit.wire == nullptr ? RTLIL::State::S1 : RTLIL::State::S0);
+ parameters.emplace(stringf("\\_TECHMAP_CONSTMSK_%s_", log_id(conn.first)), RTLIL::SigSpec(v).as_const());
+ }
+ if (tpl->avail_parameters.count(stringf("\\_TECHMAP_CONSTVAL_%s_", log_id(conn.first))) != 0) {
+ std::vector<RTLIL::SigBit> v = sigmap(conn.second).to_sigbit_vector();
+ for (auto &bit : v)
+ if (bit.wire != nullptr)
+ bit = RTLIL::SigBit(RTLIL::State::Sx);
+ parameters.emplace(stringf("\\_TECHMAP_CONSTVAL_%s_", log_id(conn.first)), RTLIL::SigSpec(v).as_const());
+ }
+ if (tpl->avail_parameters.count(stringf("\\_TECHMAP_WIREINIT_%s_", log_id(conn.first))) != 0) {
+ auto sig = sigmap(conn.second);
+ RTLIL::Const value(State::Sx, sig.size());
+ for (int i = 0; i < sig.size(); i++) {
+ auto it = init_bits.find(sig[i]);
+ if (it != init_bits.end()) {
+ value[i] = it->second;
}
- parameters[stringf("\\_TECHMAP_WIREINIT_%s_", RTLIL::id2cstr(conn.first))] = value;
}
+ parameters.emplace(stringf("\\_TECHMAP_WIREINIT_%s_", log_id(conn.first)), value);
}
+ }
+ {
int unique_bit_id_counter = 0;
- std::map<RTLIL::SigBit, int> unique_bit_id;
+ dict<RTLIL::SigBit, int> unique_bit_id;
unique_bit_id[RTLIL::State::S0] = unique_bit_id_counter++;
unique_bit_id[RTLIL::State::S1] = unique_bit_id_counter++;
unique_bit_id[RTLIL::State::Sx] = unique_bit_id_counter++;
unique_bit_id[RTLIL::State::Sz] = unique_bit_id_counter++;
- for (auto conn : cell->connections())
- if (tpl->avail_parameters.count(stringf("\\_TECHMAP_CONNMAP_%s_", RTLIL::id2cstr(conn.first))) != 0) {
- for (auto &bit : sigmap(conn.second).to_sigbit_vector())
+ for (auto &conn : cell->connections())
+ if (tpl->avail_parameters.count(stringf("\\_TECHMAP_CONNMAP_%s_", log_id(conn.first))) != 0) {
+ for (auto &bit : sigmap(conn.second))
if (unique_bit_id.count(bit) == 0)
unique_bit_id[bit] = unique_bit_id_counter++;
}
@@ -763,14 +696,17 @@ struct TechmapWorker
if (tpl->avail_parameters.count(ID::_TECHMAP_BITS_CONNMAP_))
parameters[ID::_TECHMAP_BITS_CONNMAP_] = bits;
- for (auto conn : cell->connections())
- if (tpl->avail_parameters.count(stringf("\\_TECHMAP_CONNMAP_%s_", RTLIL::id2cstr(conn.first))) != 0) {
+ for (auto &conn : cell->connections())
+ if (tpl->avail_parameters.count(stringf("\\_TECHMAP_CONNMAP_%s_", log_id(conn.first))) != 0) {
RTLIL::Const value;
- for (auto &bit : sigmap(conn.second).to_sigbit_vector()) {
- RTLIL::Const chunk(unique_bit_id.at(bit), bits);
- value.bits.insert(value.bits.end(), chunk.bits.begin(), chunk.bits.end());
+ for (auto &bit : sigmap(conn.second)) {
+ int val = unique_bit_id.at(bit);
+ for (int i = 0; i < bits; i++) {
+ value.bits.push_back((val & 1) != 0 ? State::S1 : State::S0);
+ val = val >> 1;
+ }
}
- parameters[stringf("\\_TECHMAP_CONNMAP_%s_", RTLIL::id2cstr(conn.first))] = value;
+ parameters.emplace(stringf("\\_TECHMAP_CONNMAP_%s_", log_id(conn.first)), value);
}
}
@@ -778,34 +714,31 @@ struct TechmapWorker
use_wrapper_tpl:;
// do not register techmap_wrap modules with techmap_cache
} else {
- std::pair<RTLIL::IdString, std::map<RTLIL::IdString, RTLIL::Const>> key(tpl_name, parameters);
- if (techmap_cache.count(key) > 0) {
- tpl = techmap_cache[key];
+ std::pair<IdString, dict<IdString, RTLIL::Const>> key(tpl_name, parameters);
+ auto it = techmap_cache.find(key);
+ if (it != techmap_cache.end()) {
+ tpl = it->second;
} else {
if (parameters.size() != 0) {
mkdebug.on();
- derived_name = tpl->derive(map, dict<RTLIL::IdString, RTLIL::Const>(parameters.begin(), parameters.end()));
+ derived_name = tpl->derive(map, parameters);
tpl = map->module(derived_name);
log_continue = true;
}
- techmap_cache[key] = tpl;
+ techmap_cache.emplace(std::move(key), tpl);
}
}
- if (flatten_mode) {
- techmap_do_cache[tpl] = true;
- } else {
- RTLIL::Module *constmapped_tpl = map->module(constmap_tpl_name(sigmap, tpl, cell, false));
- if (constmapped_tpl != nullptr)
- tpl = constmapped_tpl;
- }
+ RTLIL::Module *constmapped_tpl = map->module(constmap_tpl_name(sigmap, tpl, cell, false));
+ if (constmapped_tpl != nullptr)
+ tpl = constmapped_tpl;
if (techmap_do_cache.count(tpl) == 0)
{
bool keep_running = true;
techmap_do_cache[tpl] = true;
- std::set<std::string> techmap_wire_names;
+ pool<IdString> techmap_wire_names;
while (keep_running)
{
@@ -815,11 +748,11 @@ struct TechmapWorker
for (auto &it : twd)
techmap_wire_names.insert(it.first);
- for (auto &it : twd["_TECHMAP_FAIL_"]) {
+ for (auto &it : twd[ID::_TECHMAP_FAIL_]) {
RTLIL::SigSpec value = it.value;
if (value.is_fully_const() && value.as_bool()) {
log("Not using module `%s' from techmap as it contains a %s marker wire with non-zero value %s.\n",
- derived_name.c_str(), RTLIL::id2cstr(it.wire->name), log_signal(value));
+ derived_name.c_str(), log_id(it.wire->name), log_signal(value));
techmap_do_cache[tpl] = false;
}
}
@@ -829,13 +762,13 @@ struct TechmapWorker
for (auto &it : twd)
{
- if (it.first.compare(0, 12, "_TECHMAP_DO_") != 0 || it.second.empty())
+ if (!it.first.begins_with("\\_TECHMAP_DO_") || it.second.empty())
continue;
auto &data = it.second.front();
if (!data.value.is_fully_const())
- log_error("Techmap yielded config wire %s with non-const value %s.\n", RTLIL::id2cstr(data.wire->name), log_signal(data.value));
+ log_error("Techmap yielded config wire %s with non-const value %s.\n", log_id(data.wire->name), log_signal(data.value));
techmap_wire_names.erase(it.first);
@@ -851,7 +784,7 @@ struct TechmapWorker
cmd_string = cmd_string.substr(strlen("CONSTMAP; "));
log("Analyzing pattern of constant bits for this cell:\n");
- RTLIL::IdString new_tpl_name = constmap_tpl_name(sigmap, tpl, cell, true);
+ IdString new_tpl_name = constmap_tpl_name(sigmap, tpl, cell, true);
log("Creating constmapped module `%s'.\n", log_id(new_tpl_name));
log_assert(map->module(new_tpl_name) == nullptr);
@@ -862,16 +795,16 @@ struct TechmapWorker
techmap_do_cache[new_tpl] = true;
tpl = new_tpl;
- std::map<RTLIL::SigBit, RTLIL::SigBit> port_new2old_map;
- std::map<RTLIL::SigBit, RTLIL::SigBit> port_connmap;
- std::map<RTLIL::SigBit, RTLIL::SigBit> cellbits_to_tplbits;
+ dict<RTLIL::SigBit, RTLIL::SigBit> port_new2old_map;
+ dict<RTLIL::SigBit, RTLIL::SigBit> port_connmap;
+ dict<RTLIL::SigBit, RTLIL::SigBit> cellbits_to_tplbits;
for (auto wire : tpl->wires().to_vector())
{
if (!wire->port_input || wire->port_output)
continue;
- RTLIL::IdString port_name = wire->name;
+ IdString port_name = wire->name;
tpl->rename(wire, NEW_ID);
RTLIL::Wire *new_wire = tpl->addWire(port_name, wire);
@@ -879,12 +812,12 @@ struct TechmapWorker
wire->port_id = 0;
for (int i = 0; i < wire->width; i++) {
- port_new2old_map[RTLIL::SigBit(new_wire, i)] = RTLIL::SigBit(wire, i);
- port_connmap[RTLIL::SigBit(wire, i)] = RTLIL::SigBit(new_wire, i);
+ port_new2old_map.emplace(RTLIL::SigBit(new_wire, i), RTLIL::SigBit(wire, i));
+ port_connmap.emplace(RTLIL::SigBit(wire, i), RTLIL::SigBit(new_wire, i));
}
}
- for (auto conn : cell->connections())
+ for (auto &conn : cell->connections())
for (int i = 0; i < GetSize(conn.second); i++)
{
RTLIL::SigBit bit = sigmap(conn.second[i]);
@@ -926,7 +859,7 @@ struct TechmapWorker
log_assert(!strncmp(q, "_TECHMAP_DO_", 12));
std::string new_name = data.wire->name.substr(0, q-p) + "_TECHMAP_DONE_" + data.wire->name.substr(q-p+12);
- while (tpl->wires_.count(new_name))
+ while (tpl->wire(new_name) != nullptr)
new_name += "_";
tpl->rename(data.wire->name, new_name);
@@ -937,17 +870,17 @@ struct TechmapWorker
TechmapWires twd = techmap_find_special_wires(tpl);
for (auto &it : twd) {
- if (it.first != "_TECHMAP_FAIL_" && (it.first.substr(0, 20) != "_TECHMAP_REMOVEINIT_" || it.first[it.first.size()-1] != '_') && it.first.substr(0, 12) != "_TECHMAP_DO_" && it.first.substr(0, 14) != "_TECHMAP_DONE_")
- log_error("Techmap yielded unknown config wire %s.\n", it.first.c_str());
+ if (it.first != ID::_TECHMAP_FAIL_ && (!it.first.begins_with("\\_TECHMAP_REMOVEINIT_") || !it.first.ends_with("_")) && !it.first.begins_with("\\_TECHMAP_DO_") && !it.first.begins_with("\\_TECHMAP_DONE_"))
+ log_error("Techmap yielded unknown config wire %s.\n", log_id(it.first));
if (techmap_do_cache[tpl])
for (auto &it2 : it.second)
if (!it2.value.is_fully_const())
- log_error("Techmap yielded config wire %s with non-const value %s.\n", RTLIL::id2cstr(it2.wire->name), log_signal(it2.value));
+ log_error("Techmap yielded config wire %s with non-const value %s.\n", log_id(it2.wire->name), log_signal(it2.value));
techmap_wire_names.erase(it.first);
}
for (auto &it : techmap_wire_names)
- log_error("Techmap special wire %s disappeared. This is considered a fatal error.\n", RTLIL::id2cstr(it));
+ log_error("Techmap special wire %s disappeared. This is considered a fatal error.\n", log_id(it));
if (recursive_mode) {
if (log_continue) {
@@ -970,10 +903,10 @@ struct TechmapWorker
TechmapWires twd = techmap_find_special_wires(tpl);
for (auto &it : twd) {
- if (it.first.substr(0, 20) == "_TECHMAP_REMOVEINIT_") {
+ if (it.first.begins_with("\\_TECHMAP_REMOVEINIT_")) {
for (auto &it2 : it.second) {
auto val = it2.value.as_const();
- auto wirename = RTLIL::escape_id(it.first.substr(20, it.first.size() - 20 - 1));
+ auto wirename = RTLIL::escape_id(it.first.substr(21, it.first.size() - 21 - 1));
auto it = cell->connections().find(wirename);
if (it != cell->connections().end()) {
auto sig = sigmap(it->second);
@@ -1015,7 +948,7 @@ struct TechmapWorker
}
log_debug("%s %s.%s (%s) using %s.\n", mapmsg_prefix.c_str(), log_id(module), log_id(cell), log_id(cell->type), log_id(tpl));
techmap_module_worker(design, module, cell, tpl);
- cell = NULL;
+ cell = nullptr;
}
did_something = true;
mapped_cell = true;
@@ -1059,7 +992,7 @@ struct TechmapWorker
struct TechmapPass : public Pass {
TechmapPass() : Pass("techmap", "generic technology mapper") { }
- void help() YS_OVERRIDE
+ void help() override
{
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
log("\n");
@@ -1219,7 +1152,7 @@ struct TechmapPass : public Pass {
log("essentially techmap but using the design itself as map library).\n");
log("\n");
}
- void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
+ void execute(std::vector<std::string> args, RTLIL::Design *design) override
{
log_header(design, "Executing TECHMAP pass (map to technology primitives).\n");
log_push();
@@ -1275,8 +1208,7 @@ struct TechmapPass : public Pass {
RTLIL::Design *map = new RTLIL::Design;
if (map_files.empty()) {
- std::istringstream f(stdcells_code);
- Frontend::frontend_call(map, &f, "<techmap.v>", verilog_frontend);
+ Frontend::frontend_call(map, nullptr, "+/techmap.v", verilog_frontend);
} else {
for (auto &fn : map_files)
if (fn.compare(0, 1, "%") == 0) {
@@ -1285,35 +1217,30 @@ struct TechmapPass : public Pass {
log_cmd_error("Can't open saved design `%s'.\n", fn.c_str()+1);
}
for (auto mod : saved_designs.at(fn.substr(1))->modules())
- if (!map->has(mod->name))
+ if (!map->module(mod->name))
map->add(mod->clone());
} else {
- std::ifstream f;
- rewrite_filename(fn);
- f.open(fn.c_str());
- yosys_input_files.insert(fn);
- if (f.fail())
- log_cmd_error("Can't open map file `%s'\n", fn.c_str());
- Frontend::frontend_call(map, &f, fn, (fn.size() > 3 && fn.compare(fn.size()-3, std::string::npos, ".il") == 0 ? "ilang" : verilog_frontend));
+ Frontend::frontend_call(map, nullptr, fn, (fn.size() > 3 && fn.compare(fn.size()-3, std::string::npos, ".il") == 0 ? "ilang" : verilog_frontend));
}
}
log_header(design, "Continuing TECHMAP pass.\n");
- std::map<RTLIL::IdString, std::set<RTLIL::IdString, RTLIL::sort_by_id_str>> celltypeMap;
- for (auto &it : map->modules_) {
- if (it.second->attributes.count(ID::techmap_celltype) && !it.second->attributes.at(ID::techmap_celltype).bits.empty()) {
- char *p = strdup(it.second->attributes.at(ID::techmap_celltype).decode_string().c_str());
- for (char *q = strtok(p, " \t\r\n"); q; q = strtok(NULL, " \t\r\n"))
- celltypeMap[RTLIL::escape_id(q)].insert(it.first);
+ dict<IdString, pool<IdString>> celltypeMap;
+ for (auto module : map->modules()) {
+ if (module->attributes.count(ID::techmap_celltype) && !module->attributes.at(ID::techmap_celltype).bits.empty()) {
+ char *p = strdup(module->attributes.at(ID::techmap_celltype).decode_string().c_str());
+ for (char *q = strtok(p, " \t\r\n"); q; q = strtok(nullptr, " \t\r\n"))
+ celltypeMap[RTLIL::escape_id(q)].insert(module->name);
free(p);
} else {
- string module_name = it.first.str();
- if (it.first.begins_with("\\$"))
- module_name = module_name.substr(1);
- celltypeMap[module_name].insert(it.first);
+ IdString module_name = module->name.begins_with("\\$") ?
+ module->name.substr(1) : module->name.str();
+ celltypeMap[module_name].insert(module->name);
}
}
+ for (auto &i : celltypeMap)
+ i.second.sort(RTLIL::sort_by_id_str());
for (auto module : design->modules())
worker.module_queue.insert(module);
@@ -1325,7 +1252,7 @@ struct TechmapPass : public Pass {
int module_max_iter = max_iter;
bool did_something = true;
- std::set<RTLIL::Cell*> handled_cells;
+ pool<RTLIL::Cell*> handled_cells;
while (did_something) {
did_something = false;
if (worker.techmap_module(design, module, map, handled_cells, celltypeMap, false))
@@ -1344,100 +1271,4 @@ struct TechmapPass : public Pass {
}
} TechmapPass;
-struct FlattenPass : public Pass {
- FlattenPass() : Pass("flatten", "flatten design") { }
- void help() YS_OVERRIDE
- {
- // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
- log("\n");
- log(" flatten [options] [selection]\n");
- log("\n");
- log("This pass flattens the design by replacing cells by their implementation. This\n");
- log("pass is very similar to the 'techmap' pass. The only difference is that this\n");
- log("pass is using the current design as mapping library.\n");
- log("\n");
- log("Cells and/or modules with the 'keep_hierarchy' attribute set will not be\n");
- log("flattened by this command.\n");
- log("\n");
- log(" -wb\n");
- log(" Ignore the 'whitebox' attribute on cell implementations.\n");
- log("\n");
- }
- void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
- {
- log_header(design, "Executing FLATTEN pass (flatten design).\n");
- log_push();
-
- TechmapWorker worker;
- worker.flatten_mode = true;
-
- size_t argidx;
- for (argidx = 1; argidx < args.size(); argidx++) {
- if (args[argidx] == "-wb") {
- worker.ignore_wb = true;
- continue;
- }
- break;
- }
- extra_args(args, argidx, design);
-
-
- std::map<RTLIL::IdString, std::set<RTLIL::IdString, RTLIL::sort_by_id_str>> celltypeMap;
- for (auto module : design->modules())
- celltypeMap[module->name].insert(module->name);
-
- RTLIL::Module *top_mod = NULL;
- if (design->full_selection())
- for (auto mod : design->modules())
- if (mod->get_bool_attribute(ID::top))
- top_mod = mod;
-
- std::set<RTLIL::Cell*> handled_cells;
- if (top_mod != NULL) {
- worker.flatten_do_list.insert(top_mod->name);
- while (!worker.flatten_do_list.empty()) {
- auto mod = design->module(*worker.flatten_do_list.begin());
- while (worker.techmap_module(design, mod, design, handled_cells, celltypeMap, false)) { }
- worker.flatten_done_list.insert(mod->name);
- worker.flatten_do_list.erase(mod->name);
- }
- } else {
- for (auto mod : vector<Module*>(design->modules())) {
- while (worker.techmap_module(design, mod, design, handled_cells, celltypeMap, false)) { }
- }
- }
-
- log_suppressed();
- log("No more expansions possible.\n");
-
- if (top_mod != NULL)
- {
- pool<RTLIL::IdString> used_modules, new_used_modules;
- new_used_modules.insert(top_mod->name);
- while (!new_used_modules.empty()) {
- pool<RTLIL::IdString> queue;
- queue.swap(new_used_modules);
- for (auto modname : queue)
- used_modules.insert(modname);
- for (auto modname : queue)
- for (auto cell : design->module(modname)->cells())
- if (design->module(cell->type) && !used_modules[cell->type])
- new_used_modules.insert(cell->type);
- }
-
- dict<RTLIL::IdString, RTLIL::Module*> new_modules;
- for (auto mod : vector<Module*>(design->modules()))
- if (used_modules[mod->name] || mod->get_blackbox_attribute(worker.ignore_wb)) {
- new_modules[mod->name] = mod;
- } else {
- log("Deleting now unused module %s.\n", log_id(mod));
- delete mod;
- }
- design->modules_.swap(new_modules);
- }
-
- log_pop();
- }
-} FlattenPass;
-
PRIVATE_NAMESPACE_END
diff --git a/passes/techmap/tribuf.cc b/passes/techmap/tribuf.cc
index 90f3a9d6f..79ddb4bd7 100644
--- a/passes/techmap/tribuf.cc
+++ b/passes/techmap/tribuf.cc
@@ -143,7 +143,7 @@ struct TribufWorker {
struct TribufPass : public Pass {
TribufPass() : Pass("tribuf", "infer tri-state buffers") { }
- void help() YS_OVERRIDE
+ void help() override
{
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
log("\n");
@@ -160,7 +160,7 @@ struct TribufPass : public Pass {
log(" to non-tristate logic. this option implies -merge.\n");
log("\n");
}
- void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
+ void execute(std::vector<std::string> args, RTLIL::Design *design) override
{
TribufConfig config;
diff --git a/passes/techmap/zinit.cc b/passes/techmap/zinit.cc
index 74604ba3b..cc0b26bcc 100644
--- a/passes/techmap/zinit.cc
+++ b/passes/techmap/zinit.cc
@@ -25,7 +25,7 @@ PRIVATE_NAMESPACE_BEGIN
struct ZinitPass : public Pass {
ZinitPass() : Pass("zinit", "add inverters so all FF are zero-initialized") { }
- void help() YS_OVERRIDE
+ void help() override
{
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
log("\n");
@@ -37,7 +37,7 @@ struct ZinitPass : public Pass {
log(" also add zero initialization to uninitialized FFs\n");
log("\n");
}
- void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
+ void execute(std::vector<std::string> args, RTLIL::Design *design) override
{
bool all_mode = false;
@@ -91,20 +91,29 @@ struct ZinitPass : public Pass {
// FIXME: It would appear that supporting
// $dffsr/$_DFFSR_* would require a new
// cell type where S has priority over R
- ID($ff), ID($dff), ID($dffe), /*ID($dffsr),*/ ID($adff),
+ ID($ff), ID($dff), ID($dffe), /*ID($dffsr),*/ ID($adff), ID($adffe),
+ ID($sdff), ID($sdffe), ID($sdffce),
ID($_FF_), ID($_DFFE_NN_), ID($_DFFE_NP_), ID($_DFFE_PN_), ID($_DFFE_PP_),
/*ID($_DFFSR_NNN_), ID($_DFFSR_NNP_), ID($_DFFSR_NPN_), ID($_DFFSR_NPP_),
ID($_DFFSR_PNN_), ID($_DFFSR_PNP_), ID($_DFFSR_PPN_), ID($_DFFSR_PPP_),*/
ID($_DFF_N_), ID($_DFF_NN0_), ID($_DFF_NN1_), ID($_DFF_NP0_), ID($_DFF_NP1_),
ID($_DFF_P_), ID($_DFF_PN0_), ID($_DFF_PN1_), ID($_DFF_PP0_), ID($_DFF_PP1_),
// Async set/reset
- ID($__DFFE_NN0), ID($__DFFE_NN1), ID($__DFFE_NP0), ID($__DFFE_NP1),
- ID($__DFFE_PN0), ID($__DFFE_PN1), ID($__DFFE_PP0), ID($__DFFE_PP1),
+ ID($_DFFE_NN0P_), ID($_DFFE_NN1P_), ID($_DFFE_NP0P_), ID($_DFFE_NP1P_),
+ ID($_DFFE_PN0P_), ID($_DFFE_PN1P_), ID($_DFFE_PP0P_), ID($_DFFE_PP1P_),
+ ID($_DFFE_NN0N_), ID($_DFFE_NN1N_), ID($_DFFE_NP0N_), ID($_DFFE_NP1N_),
+ ID($_DFFE_PN0N_), ID($_DFFE_PN1N_), ID($_DFFE_PP0N_), ID($_DFFE_PP1N_),
// Sync set/reset
- ID($__DFFS_NN0_), ID($__DFFS_NN1_), ID($__DFFS_NP0_), ID($__DFFS_NP1_),
- ID($__DFFS_PN0_), ID($__DFFS_PN1_), ID($__DFFS_PP0_), ID($__DFFS_PP1_),
- ID($__DFFSE_NN0), ID($__DFFSE_NN1), ID($__DFFSE_NP0), ID($__DFFSE_NP1),
- ID($__DFFSE_PN0), ID($__DFFSE_PN1), ID($__DFFSE_PP0), ID($__DFFSE_PP1)
+ ID($_SDFF_NN0_), ID($_SDFF_NN1_), ID($_SDFF_NP0_), ID($_SDFF_NP1_),
+ ID($_SDFF_PN0_), ID($_SDFF_PN1_), ID($_SDFF_PP0_), ID($_SDFF_PP1_),
+ ID($_SDFFE_NN0P_), ID($_SDFFE_NN1P_), ID($_SDFFE_NP0P_), ID($_SDFFE_NP1P_),
+ ID($_SDFFE_PN0P_), ID($_SDFFE_PN1P_), ID($_SDFFE_PP0P_), ID($_SDFFE_PP1P_),
+ ID($_SDFFE_NN0N_), ID($_SDFFE_NN1N_), ID($_SDFFE_NP0N_), ID($_SDFFE_NP1N_),
+ ID($_SDFFE_PN0N_), ID($_SDFFE_PN1N_), ID($_SDFFE_PP0N_), ID($_SDFFE_PP1N_),
+ ID($_SDFFCE_NN0P_), ID($_SDFFCE_NN1P_), ID($_SDFFCE_NP0P_), ID($_SDFFCE_NP1P_),
+ ID($_SDFFCE_PN0P_), ID($_SDFFCE_PN1P_), ID($_SDFFCE_PP0P_), ID($_SDFFCE_PP1P_),
+ ID($_SDFFCE_NN0N_), ID($_SDFFCE_NN1N_), ID($_SDFFCE_NP0N_), ID($_SDFFCE_NP1N_),
+ ID($_SDFFCE_PN0N_), ID($_SDFFCE_PN1N_), ID($_SDFFCE_PP0N_), ID($_SDFFCE_PP1N_)
};
for (auto cell : module->selected_cells())
@@ -151,13 +160,20 @@ struct ZinitPass : public Pass {
cell->setPort(ID::D, sig_d);
cell->setPort(ID::Q, initwire);
- if (cell->type == ID($adff)) {
+ if (cell->type.in(ID($adff), ID($adffe))) {
auto val = cell->getParam(ID::ARST_VALUE);
for (int i = 0; i < GetSize(initwire); i++)
if (initval[i] == State::S1)
val[i] = (val[i] == State::S1 ? State::S0 : State::S1);
cell->setParam(ID::ARST_VALUE, std::move(val));
}
+ else if (cell->type.in(ID($sdff), ID($sdffe), ID($sdffce))) {
+ auto val = cell->getParam(ID::SRST_VALUE);
+ for (int i = 0; i < GetSize(initwire); i++)
+ if (initval[i] == State::S1)
+ val[i] = (val[i] == State::S1 ? State::S0 : State::S1);
+ cell->setParam(ID::SRST_VALUE, std::move(val));
+ }
else if (initval == State::S1) {
std::string t = cell->type.str();
if (cell->type.in(ID($_DFF_NN0_), ID($_DFF_NN1_), ID($_DFF_NP0_), ID($_DFF_NP1_),
@@ -165,15 +181,29 @@ struct ZinitPass : public Pass {
{
t[8] = (t[8] == '0' ? '1' : '0');
}
- else if (cell->type.in(ID($__DFFE_NN0), ID($__DFFE_NN1), ID($__DFFE_NP0), ID($__DFFE_NP1),
- ID($__DFFE_PN0), ID($__DFFE_PN1), ID($__DFFE_PP0), ID($__DFFE_PP1),
- ID($__DFFS_NN0_), ID($__DFFS_NN1_), ID($__DFFS_NP0_), ID($__DFFS_NP1_),
- ID($__DFFS_PN0_), ID($__DFFS_PN1_), ID($__DFFS_PP0_), ID($__DFFS_PP1_)))
+ else if (cell->type.in(ID($_SDFF_NN0_), ID($_SDFF_NN1_), ID($_SDFF_NP0_), ID($_SDFF_NP1_),
+ ID($_SDFF_PN0_), ID($_SDFF_PN1_), ID($_SDFF_PP0_), ID($_SDFF_PP1_)))
+ {
+ t[9] = (t[9] == '0' ? '1' : '0');
+ }
+ else if (cell->type.in(ID($_DFFE_NN0P_), ID($_DFFE_NN1P_), ID($_DFFE_NP0P_), ID($_DFFE_NP1P_),
+ ID($_DFFE_PN0P_), ID($_DFFE_PN1P_), ID($_DFFE_PP0P_), ID($_DFFE_PP1P_),
+ ID($_DFFE_NN0N_), ID($_DFFE_NN1N_), ID($_DFFE_NP0N_), ID($_DFFE_NP1N_),
+ ID($_DFFE_PN0N_), ID($_DFFE_PN1N_), ID($_DFFE_PP0N_), ID($_DFFE_PP1N_)))
+ {
+ t[9] = (t[9] == '0' ? '1' : '0');
+ }
+ else if (cell->type.in(ID($_SDFFE_NN0P_), ID($_SDFFE_NN1P_), ID($_SDFFE_NP0P_), ID($_SDFFE_NP1P_),
+ ID($_SDFFE_PN0P_), ID($_SDFFE_PN1P_), ID($_SDFFE_PP0P_), ID($_SDFFE_PP1P_),
+ ID($_SDFFE_NN0N_), ID($_SDFFE_NN1N_), ID($_SDFFE_NP0N_), ID($_SDFFE_NP1N_),
+ ID($_SDFFE_PN0N_), ID($_SDFFE_PN1N_), ID($_SDFFE_PP0N_), ID($_SDFFE_PP1N_)))
{
t[10] = (t[10] == '0' ? '1' : '0');
}
- else if (cell->type.in(ID($__DFFSE_NN0), ID($__DFFSE_NN1), ID($__DFFSE_NP0), ID($__DFFSE_NP1),
- ID($__DFFSE_PN0), ID($__DFFSE_PN1), ID($__DFFSE_PP0), ID($__DFFSE_PP1)))
+ else if (cell->type.in(ID($_SDFFCE_NN0P_), ID($_SDFFCE_NN1P_), ID($_SDFFCE_NP0P_), ID($_SDFFCE_NP1P_),
+ ID($_SDFFCE_PN0P_), ID($_SDFFCE_PN1P_), ID($_SDFFCE_PP0P_), ID($_SDFFCE_PP1P_),
+ ID($_SDFFCE_NN0N_), ID($_SDFFCE_NN1N_), ID($_SDFFCE_NP0N_), ID($_SDFFCE_NP1N_),
+ ID($_SDFFCE_PN0N_), ID($_SDFFCE_PN1N_), ID($_SDFFCE_PP0N_), ID($_SDFFCE_PP1N_)))
{
t[11] = (t[11] == '0' ? '1' : '0');
}
diff --git a/passes/tests/test_abcloop.cc b/passes/tests/test_abcloop.cc
index 894610e2b..2d80e66e4 100644
--- a/passes/tests/test_abcloop.cc
+++ b/passes/tests/test_abcloop.cc
@@ -132,7 +132,7 @@ static void test_abcloop()
SatGen satgen(ez.get(), &sigmap);
for (auto c : module->cells()) {
- bool ok YS_ATTRIBUTE(unused) = satgen.importCell(c);
+ bool ok = satgen.importCell(c);
log_assert(ok);
}
@@ -182,7 +182,7 @@ static void test_abcloop()
SatGen satgen(ez.get(), &sigmap);
for (auto c : module->cells()) {
- bool ok YS_ATTRIBUTE(unused) = satgen.importCell(c);
+ bool ok = satgen.importCell(c);
log_assert(ok);
}
@@ -244,7 +244,7 @@ static void test_abcloop()
struct TestAbcloopPass : public Pass {
TestAbcloopPass() : Pass("test_abcloop", "automatically test handling of loops in abc command") { }
- void help() YS_OVERRIDE
+ void help() override
{
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
log("\n");
@@ -259,7 +259,7 @@ struct TestAbcloopPass : public Pass {
log(" use this value as rng seed value (default = unix time).\n");
log("\n");
}
- void execute(std::vector<std::string> args, RTLIL::Design*) YS_OVERRIDE
+ void execute(std::vector<std::string> args, RTLIL::Design*) override
{
int num_iter = 100;
xorshift32_state = 0;
diff --git a/passes/tests/test_autotb.cc b/passes/tests/test_autotb.cc
index 19f21493d..4ab46014d 100644
--- a/passes/tests/test_autotb.cc
+++ b/passes/tests/test_autotb.cc
@@ -327,7 +327,7 @@ static void autotest(std::ostream &f, RTLIL::Design *design, int num_iter, int s
struct TestAutotbBackend : public Backend {
TestAutotbBackend() : Backend("=test_autotb", "generate simple test benches") { }
- void help() YS_OVERRIDE
+ void help() override
{
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
log("\n");
@@ -360,7 +360,7 @@ struct TestAutotbBackend : public Backend {
log(" the current system time.\n");
log("\n");
}
- void execute(std::ostream *&f, std::string filename, std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
+ void execute(std::ostream *&f, std::string filename, std::vector<std::string> args, RTLIL::Design *design) override
{
int num_iter = 1000;
int seed = 0;
diff --git a/passes/tests/test_cell.cc b/passes/tests/test_cell.cc
index cdbe922b2..bdb475d3b 100644
--- a/passes/tests/test_cell.cc
+++ b/passes/tests/test_cell.cc
@@ -264,7 +264,11 @@ static void create_gold_module(RTLIL::Design *design, RTLIL::IdString cell_type,
cell->setPort(ID::Y, wire);
}
- if (muxdiv && cell_type.in(ID($div), ID($mod))) {
+ if (cell_type.in(ID($shl), ID($shr), ID($sshl), ID($sshr))) {
+ cell->parameters[ID::B_SIGNED] = false;
+ }
+
+ if (muxdiv && cell_type.in(ID($div), ID($mod), ID($divfloor), ID($modfloor))) {
auto b_not_zero = module->ReduceBool(NEW_ID, cell->getPort(ID::B));
auto div_out = module->addWire(NEW_ID, GetSize(cell->getPort(ID::Y)));
module->addMux(NEW_ID, RTLIL::SigSpec(0, GetSize(div_out)), div_out, b_not_zero, cell->getPort(ID::Y));
@@ -652,7 +656,7 @@ static void run_eval_test(RTLIL::Design *design, bool verbose, bool nosat, std::
struct TestCellPass : public Pass {
TestCellPass() : Pass("test_cell", "automatically test the implementation of a cell type") { }
- void help() YS_OVERRIDE
+ void help() override
{
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
log("\n");
@@ -712,7 +716,7 @@ struct TestCellPass : public Pass {
log(" create a Verilog test bench to test simlib and write_verilog\n");
log("\n");
}
- void execute(std::vector<std::string> args, RTLIL::Design*) YS_OVERRIDE
+ void execute(std::vector<std::string> args, RTLIL::Design*) override
{
int num_iter = 100;
std::string techmap_cmd = "techmap -assert";
@@ -839,6 +843,8 @@ struct TestCellPass : public Pass {
cell_types[ID($mul)] = "ABSY";
cell_types[ID($div)] = "ABSY";
cell_types[ID($mod)] = "ABSY";
+ cell_types[ID($divfloor)] = "ABSY";
+ cell_types[ID($modfloor)] = "ABSY";
// cell_types[ID($pow)] = "ABsY";
cell_types[ID($logic_not)] = "ASY";
@@ -903,7 +909,7 @@ struct TestCellPass : public Pass {
if (!ilang_file.empty()) {
if (!selected_cell_types.empty())
log_cmd_error("Do not specify any cell types when using -f.\n");
- selected_cell_types.push_back("ilang");
+ selected_cell_types.push_back(ID(ilang));
}
if (selected_cell_types.empty())
@@ -915,7 +921,7 @@ struct TestCellPass : public Pass {
for (int i = 0; i < num_iter; i++)
{
RTLIL::Design *design = new RTLIL::Design;
- if (cell_type == "ilang")
+ if (cell_type == ID(ilang))
Frontend::frontend_call(design, NULL, std::string(), "ilang " + ilang_file);
else
create_gold_module(design, cell_type, cell_types.at(cell_type), constmode, muxdiv);
diff --git a/techlibs/achronix/speedster22i/cells_arith.v b/techlibs/achronix/speedster22i/cells_arith.v
index e2194cbd7..8529706a7 100644
--- a/techlibs/achronix/speedster22i/cells_arith.v
+++ b/techlibs/achronix/speedster22i/cells_arith.v
@@ -26,8 +26,11 @@ module _80_altera_max10_alu (A, B, CI, BI, X, Y, CO);
parameter B_WIDTH = 1;
parameter Y_WIDTH = 1;
+ (* force_downto *)
input [A_WIDTH-1:0] A;
+ (* force_downto *)
input [B_WIDTH-1:0] B;
+ (* force_downto *)
output [Y_WIDTH-1:0] X, Y;
input CI, BI;
@@ -36,11 +39,14 @@ module _80_altera_max10_alu (A, B, CI, BI, X, Y, CO);
wire _TECHMAP_FAIL_ = Y_WIDTH <= 4;
+ (* force_downto *)
wire [Y_WIDTH-1:0] A_buf, B_buf;
\$pos #(.A_SIGNED(A_SIGNED), .A_WIDTH(A_WIDTH), .Y_WIDTH(Y_WIDTH)) A_conv (.A(A), .Y(A_buf));
\$pos #(.A_SIGNED(B_SIGNED), .A_WIDTH(B_WIDTH), .Y_WIDTH(Y_WIDTH)) B_conv (.A(B), .Y(B_buf));
+ (* force_downto *)
wire [Y_WIDTH-1:0] AA = A_buf;
+ (* force_downto *)
wire [Y_WIDTH-1:0] BB = BI ? ~B_buf : B_buf;
//wire [Y_WIDTH:0] C = {CO, CI};
wire [Y_WIDTH+1:0] COx;
diff --git a/techlibs/achronix/speedster22i/cells_map.v b/techlibs/achronix/speedster22i/cells_map.v
index 9f647cbef..a19e53f49 100644
--- a/techlibs/achronix/speedster22i/cells_map.v
+++ b/techlibs/achronix/speedster22i/cells_map.v
@@ -38,6 +38,7 @@ endmodule
module \$lut (A, Y);
parameter WIDTH = 0;
parameter LUT = 0;
+ (* force_downto *)
input [WIDTH-1:0] A;
output Y;
generate
diff --git a/techlibs/achronix/synth_achronix.cc b/techlibs/achronix/synth_achronix.cc
index 262a5e700..ddd9822b9 100644
--- a/techlibs/achronix/synth_achronix.cc
+++ b/techlibs/achronix/synth_achronix.cc
@@ -28,7 +28,7 @@ PRIVATE_NAMESPACE_BEGIN
struct SynthAchronixPass : public ScriptPass {
SynthAchronixPass() : ScriptPass("synth_achronix", "synthesis for Acrhonix Speedster22i FPGAs.") { }
- void help() YS_OVERRIDE
+ void help() override
{
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
log("\n");
@@ -63,7 +63,7 @@ struct SynthAchronixPass : public ScriptPass {
string top_opt, family_opt, vout_file;
bool retime, flatten;
- void clear_flags() YS_OVERRIDE
+ void clear_flags() override
{
top_opt = "-auto-top";
vout_file = "";
@@ -71,7 +71,7 @@ struct SynthAchronixPass : public ScriptPass {
flatten = true;
}
- void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
+ void execute(std::vector<std::string> args, RTLIL::Design *design) override
{
string run_from, run_to;
clear_flags();
@@ -118,7 +118,7 @@ struct SynthAchronixPass : public ScriptPass {
log_pop();
}
- void script() YS_OVERRIDE
+ void script() override
{
if (check_label("begin"))
{
diff --git a/techlibs/anlogic/anlogic_eqn.cc b/techlibs/anlogic/anlogic_eqn.cc
index e4fa4413f..e5fbc186f 100644
--- a/techlibs/anlogic/anlogic_eqn.cc
+++ b/techlibs/anlogic/anlogic_eqn.cc
@@ -25,7 +25,7 @@ PRIVATE_NAMESPACE_BEGIN
struct AnlogicEqnPass : public Pass {
AnlogicEqnPass() : Pass("anlogic_eqn", "Anlogic: Calculate equations for luts") { }
- void help() YS_OVERRIDE
+ void help() override
{
log("\n");
log(" anlogic_eqn [selection]\n");
@@ -63,7 +63,7 @@ struct AnlogicEqnPass : public Pass {
return Const(eqn);
}
- void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
+ void execute(std::vector<std::string> args, RTLIL::Design *design) override
{
log_header(design, "Executing ANLOGIC_EQN pass (calculate equations for luts).\n");
diff --git a/techlibs/anlogic/anlogic_fixcarry.cc b/techlibs/anlogic/anlogic_fixcarry.cc
index f8e70260c..c7dfe3c05 100644
--- a/techlibs/anlogic/anlogic_fixcarry.cc
+++ b/techlibs/anlogic/anlogic_fixcarry.cc
@@ -98,7 +98,7 @@ static void fix_carry_chain(Module *module)
struct AnlogicCarryFixPass : public Pass {
AnlogicCarryFixPass() : Pass("anlogic_fixcarry", "Anlogic: fix carry chain") { }
- void help() YS_OVERRIDE
+ void help() override
{
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
log("\n");
@@ -107,7 +107,7 @@ struct AnlogicCarryFixPass : public Pass {
log("Add Anlogic adders to fix carry chain if needed.\n");
log("\n");
}
- void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
+ void execute(std::vector<std::string> args, RTLIL::Design *design) override
{
log_header(design, "Executing anlogic_fixcarry pass (fix invalid carry chain).\n");
diff --git a/techlibs/anlogic/arith_map.v b/techlibs/anlogic/arith_map.v
index 1186543da..23e190bcb 100644
--- a/techlibs/anlogic/arith_map.v
+++ b/techlibs/anlogic/arith_map.v
@@ -26,24 +26,33 @@ module _80_anlogic_alu (A, B, CI, BI, X, Y, CO);
parameter B_WIDTH = 1;
parameter Y_WIDTH = 1;
+ (* force_downto *)
input [A_WIDTH-1:0] A;
+ (* force_downto *)
input [B_WIDTH-1:0] B;
+ (* force_downto *)
output [Y_WIDTH-1:0] X, Y;
input CI, BI;
+ (* force_downto *)
output [Y_WIDTH-1:0] CO;
wire CIx;
+ (* force_downto *)
wire [Y_WIDTH-1:0] COx;
wire _TECHMAP_FAIL_ = Y_WIDTH <= 2;
+ (* force_downto *)
wire [Y_WIDTH-1:0] A_buf, B_buf;
\$pos #(.A_SIGNED(A_SIGNED), .A_WIDTH(A_WIDTH), .Y_WIDTH(Y_WIDTH)) A_conv (.A(A), .Y(A_buf));
\$pos #(.A_SIGNED(B_SIGNED), .A_WIDTH(B_WIDTH), .Y_WIDTH(Y_WIDTH)) B_conv (.A(B), .Y(B_buf));
+ (* force_downto *)
wire [Y_WIDTH-1:0] AA = A_buf;
+ (* force_downto *)
wire [Y_WIDTH-1:0] BB = BI ? ~B_buf : B_buf;
+ (* force_downto *)
wire [Y_WIDTH-1:0] C = { COx, CIx };
wire dummy;
diff --git a/techlibs/anlogic/cells_map.v b/techlibs/anlogic/cells_map.v
index 8ac087d9d..0bcea9856 100644
--- a/techlibs/anlogic/cells_map.v
+++ b/techlibs/anlogic/cells_map.v
@@ -32,6 +32,7 @@ module \$lut (A, Y);
parameter WIDTH = 0;
parameter LUT = 0;
+ (* force_downto *)
input [WIDTH-1:0] A;
output Y;
diff --git a/techlibs/anlogic/synth_anlogic.cc b/techlibs/anlogic/synth_anlogic.cc
index 791dc922f..d7475df86 100644
--- a/techlibs/anlogic/synth_anlogic.cc
+++ b/techlibs/anlogic/synth_anlogic.cc
@@ -30,7 +30,7 @@ struct SynthAnlogicPass : public ScriptPass
{
SynthAnlogicPass() : ScriptPass("synth_anlogic", "synthesis for Anlogic FPGAs") { }
- void help() YS_OVERRIDE
+ void help() override
{
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
log("\n");
@@ -72,7 +72,7 @@ struct SynthAnlogicPass : public ScriptPass
string top_opt, edif_file, json_file;
bool flatten, retime, nolutram;
- void clear_flags() YS_OVERRIDE
+ void clear_flags() override
{
top_opt = "-auto-top";
edif_file = "";
@@ -82,7 +82,7 @@ struct SynthAnlogicPass : public ScriptPass
nolutram = false;
}
- void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
+ void execute(std::vector<std::string> args, RTLIL::Design *design) override
{
string run_from, run_to;
clear_flags();
@@ -137,7 +137,7 @@ struct SynthAnlogicPass : public ScriptPass
log_pop();
}
- void script() YS_OVERRIDE
+ void script() override
{
if (check_label("begin"))
{
diff --git a/techlibs/common/Makefile.inc b/techlibs/common/Makefile.inc
index 7b1e4b430..607e772a2 100644
--- a/techlibs/common/Makefile.inc
+++ b/techlibs/common/Makefile.inc
@@ -30,4 +30,6 @@ $(eval $(call add_share_file,share,techlibs/common/cmp2lut.v))
$(eval $(call add_share_file,share,techlibs/common/cells.lib))
$(eval $(call add_share_file,share,techlibs/common/mul2dsp.v))
$(eval $(call add_share_file,share,techlibs/common/abc9_model.v))
+$(eval $(call add_share_file,share,techlibs/common/abc9_map.v))
+$(eval $(call add_share_file,share,techlibs/common/abc9_unmap.v))
$(eval $(call add_share_file,share,techlibs/common/cmp2lcu.v))
diff --git a/techlibs/common/abc9_map.v b/techlibs/common/abc9_map.v
new file mode 100644
index 000000000..6ed90b5f5
--- /dev/null
+++ b/techlibs/common/abc9_map.v
@@ -0,0 +1,27 @@
+`ifdef DFF
+(* techmap_celltype = "$_DFF_N_ $_DFF_P_" *)
+module $_DFF_x_(input C, D, output Q);
+ parameter [0:0] _TECHMAP_WIREINIT_Q_ = 1'bx;
+ parameter _TECHMAP_CELLTYPE_ = "";
+ wire D_;
+ generate if (_TECHMAP_CELLTYPE_ == "$_DFF_N_") begin
+ if (_TECHMAP_WIREINIT_Q_ === 1'b0) begin
+ $__DFF_N__$abc9_flop _TECHMAP_REPLACE_ (.C(C), .D(D), .Q(Q), .n1(D_));
+ $_DFF_N_ ff (.C(C), .D(D_), .Q(Q));
+ end
+ else
+ (* abc9_keep *) $_DFF_N_ _TECHMAP_REPLACE_ (.C(C), .D(D), .Q(Q));
+ end
+ else if (_TECHMAP_CELLTYPE_ == "$_DFF_P_") begin
+ if (_TECHMAP_WIREINIT_Q_ === 1'b0) begin
+ $__DFF_P__$abc9_flop _TECHMAP_REPLACE_ (.C(C), .D(D), .Q(Q), .n1(D_));
+ $_DFF_P_ ff (.C(C), .D(D_), .Q(Q));
+ end
+ else
+ (* abc9_keep *) $_DFF_P_ _TECHMAP_REPLACE_ (.C(C), .D(D), .Q(Q));
+ end
+ else if (_TECHMAP_CELLTYPE_ != "")
+ $error("Unrecognised _TECHMAP_CELLTYPE_");
+ endgenerate
+endmodule
+`endif
diff --git a/techlibs/common/abc9_model.v b/techlibs/common/abc9_model.v
index c0c5dc2fd..4fee60f75 100644
--- a/techlibs/common/abc9_model.v
+++ b/techlibs/common/abc9_model.v
@@ -1,10 +1,25 @@
-module \$__ABC9_FF_ (input D, output Q);
-endmodule
-
(* abc9_box *)
-module \$__ABC9_DELAY (input I, output O);
+module $__ABC9_DELAY (input I, output O);
parameter DELAY = 0;
specify
(I => O) = DELAY;
endspecify
endmodule
+
+(* abc9_flop, abc9_box, lib_whitebox *)
+module $__DFF_N__$abc9_flop (input C, D, Q, output n1);
+ assign n1 = D;
+ specify
+ $setup(D, posedge C, 0);
+ (posedge C => (n1:D)) = 0;
+ endspecify
+endmodule
+
+(* abc9_flop, abc9_box, lib_whitebox *)
+module $__DFF_P__$abc9_flop (input C, D, Q, output n1);
+ assign n1 = D;
+ specify
+ $setup(D, posedge C, 0);
+ (posedge C => (n1:D)) = 0;
+ endspecify
+endmodule
diff --git a/techlibs/common/abc9_unmap.v b/techlibs/common/abc9_unmap.v
new file mode 100644
index 000000000..c39648c62
--- /dev/null
+++ b/techlibs/common/abc9_unmap.v
@@ -0,0 +1,11 @@
+(* techmap_celltype = "$__DFF_N__$abc9_flop $__DFF_P__$abc9_flop" *)
+module $__DFF_x__$abc9_flop (input C, D, (* init = 1'b0 *) input Q, output n1);
+ parameter _TECHMAP_CELLTYPE_ = "";
+ generate if (_TECHMAP_CELLTYPE_ == "$__DFF_N__$abc9_flop")
+ $_DFF_N_ _TECHMAP_REPLACE_ (.C(C), .D(D), .Q(Q));
+ else if (_TECHMAP_CELLTYPE_ == "$__DFF_P__$abc9_flop")
+ $_DFF_P_ _TECHMAP_REPLACE_ (.C(C), .D(D), .Q(Q));
+ else if (_TECHMAP_CELLTYPE_ != "")
+ $error("Unrecognised _TECHMAP_CELLTYPE_");
+ endgenerate
+endmodule
diff --git a/techlibs/common/adff2dff.v b/techlibs/common/adff2dff.v
index 86744d415..eca0110eb 100644
--- a/techlibs/common/adff2dff.v
+++ b/techlibs/common/adff2dff.v
@@ -6,8 +6,11 @@ module adff2dff (CLK, ARST, D, Q);
parameter ARST_VALUE = 0;
input CLK, ARST;
+ (* force_downto *)
input [WIDTH-1:0] D;
+ (* force_downto *)
output reg [WIDTH-1:0] Q;
+ (* force_downto *)
wire reg [WIDTH-1:0] NEXT_Q;
wire [1023:0] _TECHMAP_DO_ = "proc;;";
diff --git a/techlibs/common/cmp2lcu.v b/techlibs/common/cmp2lcu.v
index e42f346d1..a221727e7 100644
--- a/techlibs/common/cmp2lcu.v
+++ b/techlibs/common/cmp2lcu.v
@@ -12,8 +12,11 @@ parameter A_WIDTH = 0;
parameter B_WIDTH = 0;
parameter Y_WIDTH = 0;
+(* force_downto *)
input [A_WIDTH-1:0] A;
+(* force_downto *)
input [B_WIDTH-1:0] B;
+(* force_downto *)
output [Y_WIDTH-1:0] Y;
parameter _TECHMAP_CELLTYPE_ = "";
@@ -32,7 +35,9 @@ generate
else begin
// Perform sign extension on A and B
localparam WIDTH = A_WIDTH > B_WIDTH ? A_WIDTH : B_WIDTH;
+ (* force_downto *)
wire [WIDTH-1:0] AA = {{(WIDTH-A_WIDTH){A_SIGNED ? A[A_WIDTH-1] : 1'b0}}, A};
+ (* force_downto *)
wire [WIDTH-1:0] BB = {{(WIDTH-B_WIDTH){B_SIGNED ? B[B_WIDTH-1] : 1'b0}}, B};
// For $ge operation, start with the assumption that A and B are
// equal (propagating this equality if A and B turn out to be so)
@@ -54,9 +59,13 @@ parameter LCU_WIDTH = 1;
parameter BUDGET = 0;
parameter CI = 0;
+(* force_downto *)
input [AB_WIDTH-1:0] A; // A from original $gt/$ge
+(* force_downto *)
input [AB_WIDTH-1:0] B; // B from original $gt/$ge
+(* force_downto *)
input [LCU_WIDTH-1:0] P; // P of $lcu
+(* force_downto *)
input [LCU_WIDTH-1:0] G; // G of $lcu
output Y;
@@ -66,6 +75,7 @@ parameter [LCU_WIDTH-1:0] _TECHMAP_CONSTMSK_P_ = 0;
generate
if (AB_WIDTH == 0) begin
+ (* force_downto *)
wire [LCU_WIDTH-1:0] CO;
$lcu #(.WIDTH(LCU_WIDTH)) _TECHMAP_REPLACE_ (.P(P), .G(G), .CI(CI), .CO(CO));
assign Y = CO[LCU_WIDTH-1];
@@ -104,8 +114,10 @@ generate
else begin
// Propagate only if all pairs are equal
// (inconclusive evidence to say A >= B)
+ (* force_downto *)
wire [LCU_WIDTH-1:0] P_ = {P[LCU_WIDTH-1:1], P[0] & PP};
// Generate if any comparisons call for it
+ (* force_downto *)
wire [LCU_WIDTH-1:0] G_ = {G[LCU_WIDTH-1:1], G[0] | GG};
end
if (AB_WIDTH == 1)
diff --git a/techlibs/common/cmp2lut.v b/techlibs/common/cmp2lut.v
index 8ecd356cc..ec8f98e8d 100644
--- a/techlibs/common/cmp2lut.v
+++ b/techlibs/common/cmp2lut.v
@@ -16,8 +16,11 @@ parameter A_WIDTH = 0;
parameter B_WIDTH = 0;
parameter Y_WIDTH = 0;
+(* force_downto *)
input [A_WIDTH-1:0] A;
+(* force_downto *)
input [B_WIDTH-1:0] B;
+(* force_downto *)
output [Y_WIDTH-1:0] Y;
parameter _TECHMAP_CELLTYPE_ = "";
diff --git a/techlibs/common/dff2ff.v b/techlibs/common/dff2ff.v
index 2dc4d20d3..33a79ffff 100644
--- a/techlibs/common/dff2ff.v
+++ b/techlibs/common/dff2ff.v
@@ -4,7 +4,9 @@ module dff2ff (CLK, D, Q);
parameter CLK_POLARITY = 1;
input CLK;
+ (* force_downto *)
input [WIDTH-1:0] D;
+ (* force_downto *)
output reg [WIDTH-1:0] Q;
wire [1023:0] _TECHMAP_DO_ = "proc;;";
diff --git a/techlibs/common/gen_fine_ffs.py b/techlibs/common/gen_fine_ffs.py
index 0abe48f61..5d331e767 100644
--- a/techlibs/common/gen_fine_ffs.py
+++ b/techlibs/common/gen_fine_ffs.py
@@ -108,6 +108,31 @@ endmodule
"""
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
//-
+//- $_DFFE_{C:N|P}{R:N|P}{V:0|1}{E:N|P}_ (D, C, R, E, Q)
+//-
+//- A {C:negative|positive} edge D-type flip-flop with {R:negative|positive} polarity {V:reset|set} and {E:negative|positive}
+//- polarity clock enable.
+//-
+//- Truth table: D C R E | Q
+//- ---------+---
+//- - - {R:0|1} - | {V:0|1}
+//- d {C:\\|/} - {E:0|1} | d
+//- - - - - | q
+//-
+module \$_DFFE_{C:N|P}{R:N|P}{V:0|1}{E:N|P}_ (D, C, R, E, Q);
+input D, C, R, E;
+output reg Q;
+always @({C:neg|pos}edge C or {R:neg|pos}edge R) begin
+ if (R == {R:0|1})
+ Q <= {V:0|1};
+ else if (E == {E:0|1})
+ Q <= D;
+end
+endmodule
+""",
+"""
+// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
+//-
//- $_DFFSR_{C:N|P}{S:N|P}{R:N|P}_ (C, S, R, D, Q)
//-
//- A {C:negative|positive} edge D-type flip-flop with {S:negative|positive} polarity set and {R:negative|positive}
@@ -136,6 +161,110 @@ endmodule
"""
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
//-
+//- $_DFFSRE_{C:N|P}{S:N|P}{R:N|P}{E:N|P}_ (C, S, R, E, D, Q)
+//-
+//- A {C:negative|positive} edge D-type flip-flop with {S:negative|positive} polarity set, {R:negative|positive}
+//- polarity reset and {E:negative|positive} polarity clock enable.
+//-
+//- Truth table: C S R E D | Q
+//- -----------+---
+//- - - {R:0|1} - - | 0
+//- - {S:0|1} - - - | 1
+//- {C:\\|/} - - {E:0|1} d | d
+//- - - - - - | q
+//-
+module \$_DFFSRE_{C:N|P}{S:N|P}{R:N|P}{E:N|P}_ (C, S, R, E, D, Q);
+input C, S, R, E, D;
+output reg Q;
+always @({C:neg|pos}edge C, {S:neg|pos}edge S, {R:neg|pos}edge R) begin
+ if (R == {R:0|1})
+ Q <= 0;
+ else if (S == {S:0|1})
+ Q <= 1;
+ else if (E == {E:0|1})
+ Q <= D;
+end
+endmodule
+""",
+"""
+// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
+//-
+//- $_SDFF_{C:N|P}{R:N|P}{V:0|1}_ (D, C, R, Q)
+//-
+//- A {C:negative|positive} edge D-type flip-flop with {R:negative|positive} polarity synchronous {V:reset|set}.
+//-
+//- Truth table: D C R | Q
+//- -------+---
+//- - {C:\\|/} {R:0|1} | {V:0|1}
+//- d {C:\\|/} - | d
+//- - - - | q
+//-
+module \$_SDFF_{C:N|P}{R:N|P}{V:0|1}_ (D, C, R, Q);
+input D, C, R;
+output reg Q;
+always @({C:neg|pos}edge C) begin
+ if (R == {R:0|1})
+ Q <= {V:0|1};
+ else
+ Q <= D;
+end
+endmodule
+""",
+"""
+// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
+//-
+//- $_SDFFE_{C:N|P}{R:N|P}{V:0|1}{E:N|P}_ (D, C, R, E, Q)
+//-
+//- A {C:negative|positive} edge D-type flip-flop with {R:negative|positive} polarity synchronous {V:reset|set} and {E:negative|positive}
+//- polarity clock enable (with {V:reset|set} having priority).
+//-
+//- Truth table: D C R E | Q
+//- ---------+---
+//- - {C:\\|/} {R:0|1} - | {V:0|1}
+//- d {C:\\|/} - {E:0|1} | d
+//- - - - - | q
+//-
+module \$_SDFFE_{C:N|P}{R:N|P}{V:0|1}{E:N|P}_ (D, C, R, E, Q);
+input D, C, R, E;
+output reg Q;
+always @({C:neg|pos}edge C) begin
+ if (R == {R:0|1})
+ Q <= {V:0|1};
+ else if (E == {E:0|1})
+ Q <= D;
+end
+endmodule
+""",
+"""
+// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
+//-
+//- $_SDFFCE_{C:N|P}{R:N|P}{V:0|1}{E:N|P}_ (D, C, R, E, Q)
+//-
+//- A {C:negative|positive} edge D-type flip-flop with {R:negative|positive} polarity synchronous {V:reset|set} and {E:negative|positive}
+//- polarity clock enable (with clock enable having priority).
+//-
+//- Truth table: D C R E | Q
+//- ---------+---
+//- - {C:\\|/} {R:0|1} {E:0|1} | {V:0|1}
+//- d {C:\\|/} - {E:0|1} | d
+//- - - - - | q
+//-
+module \$_SDFFCE_{C:N|P}{R:N|P}{V:0|1}{E:N|P}_ (D, C, R, E, Q);
+input D, C, R, E;
+output reg Q;
+always @({C:neg|pos}edge C) begin
+ if (E == {E:0|1}) begin
+ if (R == {R:0|1})
+ Q <= {V:0|1};
+ else
+ Q <= D;
+ end
+end
+endmodule
+""",
+"""
+// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
+//-
//- $_DLATCH_{E:N|P}_ (E, D, Q)
//-
//- A {E:negative|positive} enable D-type latch.
@@ -157,6 +286,30 @@ endmodule
"""
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
//-
+//- $_DLATCH_{E:N|P}{R:N|P}{V:0|1}_ (E, R, D, Q)
+//-
+//- A {E:negative|positive} enable D-type latch with {R:negative|positive} polarity {V:reset|set}.
+//-
+//- Truth table: E R D | Q
+//- -------+---
+//- - {R:0|1} - | {V:0|1}
+//- {E:0|1} - d | d
+//- - - - | q
+//-
+module \$_DLATCH_{E:N|P}{R:N|P}{V:0|1}_ (E, R, D, Q);
+input E, R, D;
+output reg Q;
+always @* begin
+ if (R == {R:0|1})
+ Q <= {V:0|1};
+ else if (E == {E:0|1})
+ Q <= D;
+end
+endmodule
+""",
+"""
+// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
+//-
//- $_DLATCHSR_{E:N|P}{S:N|P}{R:N|P}_ (E, S, R, D, Q)
//-
//- A {E:negative|positive} enable D-type latch with {S:negative|positive} polarity set and {R:negative|positive}
diff --git a/techlibs/common/mul2dsp.v b/techlibs/common/mul2dsp.v
index 4cabb4453..bec47d01f 100644
--- a/techlibs/common/mul2dsp.v
+++ b/techlibs/common/mul2dsp.v
@@ -57,8 +57,11 @@ module _80_mul (A, B, Y);
parameter B_WIDTH = 1;
parameter Y_WIDTH = 1;
+ (* force_downto *)
input [A_WIDTH-1:0] A;
+ (* force_downto *)
input [B_WIDTH-1:0] B;
+ (* force_downto *)
output [Y_WIDTH-1:0] Y;
parameter _TECHMAP_CELLTYPE_ = "";
@@ -119,13 +122,19 @@ module _80_mul (A, B, Y);
localparam last_A_WIDTH = A_WIDTH-n*(`DSP_A_MAXWIDTH_PARTIAL-sign_headroom);
localparam last_Y_WIDTH = B_WIDTH+last_A_WIDTH;
if (A_SIGNED && B_SIGNED) begin
+ (* force_downto *)
wire signed [partial_Y_WIDTH-1:0] partial [n-1:0];
+ (* force_downto *)
wire signed [last_Y_WIDTH-1:0] last_partial;
+ (* force_downto *)
wire signed [Y_WIDTH-1:0] partial_sum [n:0];
end
else begin
+ (* force_downto *)
wire [partial_Y_WIDTH-1:0] partial [n-1:0];
+ (* force_downto *)
wire [last_Y_WIDTH-1:0] last_partial;
+ (* force_downto *)
wire [Y_WIDTH-1:0] partial_sum [n:0];
end
@@ -170,13 +179,19 @@ module _80_mul (A, B, Y);
localparam last_B_WIDTH = B_WIDTH-n*(`DSP_B_MAXWIDTH_PARTIAL-sign_headroom);
localparam last_Y_WIDTH = A_WIDTH+last_B_WIDTH;
if (A_SIGNED && B_SIGNED) begin
+ (* force_downto *)
wire signed [partial_Y_WIDTH-1:0] partial [n-1:0];
+ (* force_downto *)
wire signed [last_Y_WIDTH-1:0] last_partial;
+ (* force_downto *)
wire signed [Y_WIDTH-1:0] partial_sum [n:0];
end
else begin
+ (* force_downto *)
wire [partial_Y_WIDTH-1:0] partial [n-1:0];
+ (* force_downto *)
wire [last_Y_WIDTH-1:0] last_partial;
+ (* force_downto *)
wire [Y_WIDTH-1:0] partial_sum [n:0];
end
@@ -249,8 +264,11 @@ module _90_soft_mul (A, B, Y);
parameter B_WIDTH = 1;
parameter Y_WIDTH = 1;
+ (* force_downto *)
input [A_WIDTH-1:0] A;
+ (* force_downto *)
input [B_WIDTH-1:0] B;
+ (* force_downto *)
output [Y_WIDTH-1:0] Y;
// Indirection necessary since mapping
diff --git a/techlibs/common/prep.cc b/techlibs/common/prep.cc
index cdd21c3b3..93b0910d6 100644
--- a/techlibs/common/prep.cc
+++ b/techlibs/common/prep.cc
@@ -29,7 +29,7 @@ struct PrepPass : public ScriptPass
{
PrepPass() : ScriptPass("prep", "generic synthesis script") { }
- void help() YS_OVERRIDE
+ void help() override
{
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
log("\n");
@@ -81,7 +81,7 @@ struct PrepPass : public ScriptPass
string top_module, fsm_opts;
bool autotop, flatten, ifxmode, memxmode, nomemmode, nokeepdc, nordff;
- void clear_flags() YS_OVERRIDE
+ void clear_flags() override
{
top_module.clear();
@@ -94,7 +94,7 @@ struct PrepPass : public ScriptPass
nordff = true;
}
- void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
+ void execute(std::vector<std::string> args, RTLIL::Design *design) override
{
string run_from, run_to;
@@ -163,7 +163,7 @@ struct PrepPass : public ScriptPass
log_pop();
}
- void script() YS_OVERRIDE
+ void script() override
{
if (check_label("begin"))
@@ -192,7 +192,7 @@ struct PrepPass : public ScriptPass
run(nokeepdc ? "opt_expr" : "opt_expr -keepdc");
run("opt_clean");
run("check");
- run(nokeepdc ? "opt" : "opt -keepdc");
+ run(nokeepdc ? "opt -noff" : "opt -noff -keepdc");
if (!ifxmode) {
if (help_mode)
run("wreduce -keepdc [-memx]");
@@ -208,7 +208,7 @@ struct PrepPass : public ScriptPass
run("opt_clean");
run("memory_collect");
}
- run(nokeepdc ? "opt -fast" : "opt -keepdc -fast");
+ run(nokeepdc ? "opt -noff -fast" : "opt -noff -keepdc -fast");
}
if (check_label("check"))
diff --git a/techlibs/common/simcells.v b/techlibs/common/simcells.v
index 157e8d23b..27ef44232 100644
--- a/techlibs/common/simcells.v
+++ b/techlibs/common/simcells.v
@@ -870,6 +870,390 @@ endmodule
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
//-
+//- $_DFFE_NN0N_ (D, C, R, E, Q)
+//-
+//- A negative edge D-type flip-flop with negative polarity reset and negative
+//- polarity clock enable.
+//-
+//- Truth table: D C R E | Q
+//- ---------+---
+//- - - 0 - | 0
+//- d \ - 0 | d
+//- - - - - | q
+//-
+module \$_DFFE_NN0N_ (D, C, R, E, Q);
+input D, C, R, E;
+output reg Q;
+always @(negedge C or negedge R) begin
+ if (R == 0)
+ Q <= 0;
+ else if (E == 0)
+ Q <= D;
+end
+endmodule
+
+// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
+//-
+//- $_DFFE_NN0P_ (D, C, R, E, Q)
+//-
+//- A negative edge D-type flip-flop with negative polarity reset and positive
+//- polarity clock enable.
+//-
+//- Truth table: D C R E | Q
+//- ---------+---
+//- - - 0 - | 0
+//- d \ - 1 | d
+//- - - - - | q
+//-
+module \$_DFFE_NN0P_ (D, C, R, E, Q);
+input D, C, R, E;
+output reg Q;
+always @(negedge C or negedge R) begin
+ if (R == 0)
+ Q <= 0;
+ else if (E == 1)
+ Q <= D;
+end
+endmodule
+
+// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
+//-
+//- $_DFFE_NN1N_ (D, C, R, E, Q)
+//-
+//- A negative edge D-type flip-flop with negative polarity set and negative
+//- polarity clock enable.
+//-
+//- Truth table: D C R E | Q
+//- ---------+---
+//- - - 0 - | 1
+//- d \ - 0 | d
+//- - - - - | q
+//-
+module \$_DFFE_NN1N_ (D, C, R, E, Q);
+input D, C, R, E;
+output reg Q;
+always @(negedge C or negedge R) begin
+ if (R == 0)
+ Q <= 1;
+ else if (E == 0)
+ Q <= D;
+end
+endmodule
+
+// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
+//-
+//- $_DFFE_NN1P_ (D, C, R, E, Q)
+//-
+//- A negative edge D-type flip-flop with negative polarity set and positive
+//- polarity clock enable.
+//-
+//- Truth table: D C R E | Q
+//- ---------+---
+//- - - 0 - | 1
+//- d \ - 1 | d
+//- - - - - | q
+//-
+module \$_DFFE_NN1P_ (D, C, R, E, Q);
+input D, C, R, E;
+output reg Q;
+always @(negedge C or negedge R) begin
+ if (R == 0)
+ Q <= 1;
+ else if (E == 1)
+ Q <= D;
+end
+endmodule
+
+// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
+//-
+//- $_DFFE_NP0N_ (D, C, R, E, Q)
+//-
+//- A negative edge D-type flip-flop with positive polarity reset and negative
+//- polarity clock enable.
+//-
+//- Truth table: D C R E | Q
+//- ---------+---
+//- - - 1 - | 0
+//- d \ - 0 | d
+//- - - - - | q
+//-
+module \$_DFFE_NP0N_ (D, C, R, E, Q);
+input D, C, R, E;
+output reg Q;
+always @(negedge C or posedge R) begin
+ if (R == 1)
+ Q <= 0;
+ else if (E == 0)
+ Q <= D;
+end
+endmodule
+
+// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
+//-
+//- $_DFFE_NP0P_ (D, C, R, E, Q)
+//-
+//- A negative edge D-type flip-flop with positive polarity reset and positive
+//- polarity clock enable.
+//-
+//- Truth table: D C R E | Q
+//- ---------+---
+//- - - 1 - | 0
+//- d \ - 1 | d
+//- - - - - | q
+//-
+module \$_DFFE_NP0P_ (D, C, R, E, Q);
+input D, C, R, E;
+output reg Q;
+always @(negedge C or posedge R) begin
+ if (R == 1)
+ Q <= 0;
+ else if (E == 1)
+ Q <= D;
+end
+endmodule
+
+// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
+//-
+//- $_DFFE_NP1N_ (D, C, R, E, Q)
+//-
+//- A negative edge D-type flip-flop with positive polarity set and negative
+//- polarity clock enable.
+//-
+//- Truth table: D C R E | Q
+//- ---------+---
+//- - - 1 - | 1
+//- d \ - 0 | d
+//- - - - - | q
+//-
+module \$_DFFE_NP1N_ (D, C, R, E, Q);
+input D, C, R, E;
+output reg Q;
+always @(negedge C or posedge R) begin
+ if (R == 1)
+ Q <= 1;
+ else if (E == 0)
+ Q <= D;
+end
+endmodule
+
+// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
+//-
+//- $_DFFE_NP1P_ (D, C, R, E, Q)
+//-
+//- A negative edge D-type flip-flop with positive polarity set and positive
+//- polarity clock enable.
+//-
+//- Truth table: D C R E | Q
+//- ---------+---
+//- - - 1 - | 1
+//- d \ - 1 | d
+//- - - - - | q
+//-
+module \$_DFFE_NP1P_ (D, C, R, E, Q);
+input D, C, R, E;
+output reg Q;
+always @(negedge C or posedge R) begin
+ if (R == 1)
+ Q <= 1;
+ else if (E == 1)
+ Q <= D;
+end
+endmodule
+
+// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
+//-
+//- $_DFFE_PN0N_ (D, C, R, E, Q)
+//-
+//- A positive edge D-type flip-flop with negative polarity reset and negative
+//- polarity clock enable.
+//-
+//- Truth table: D C R E | Q
+//- ---------+---
+//- - - 0 - | 0
+//- d / - 0 | d
+//- - - - - | q
+//-
+module \$_DFFE_PN0N_ (D, C, R, E, Q);
+input D, C, R, E;
+output reg Q;
+always @(posedge C or negedge R) begin
+ if (R == 0)
+ Q <= 0;
+ else if (E == 0)
+ Q <= D;
+end
+endmodule
+
+// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
+//-
+//- $_DFFE_PN0P_ (D, C, R, E, Q)
+//-
+//- A positive edge D-type flip-flop with negative polarity reset and positive
+//- polarity clock enable.
+//-
+//- Truth table: D C R E | Q
+//- ---------+---
+//- - - 0 - | 0
+//- d / - 1 | d
+//- - - - - | q
+//-
+module \$_DFFE_PN0P_ (D, C, R, E, Q);
+input D, C, R, E;
+output reg Q;
+always @(posedge C or negedge R) begin
+ if (R == 0)
+ Q <= 0;
+ else if (E == 1)
+ Q <= D;
+end
+endmodule
+
+// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
+//-
+//- $_DFFE_PN1N_ (D, C, R, E, Q)
+//-
+//- A positive edge D-type flip-flop with negative polarity set and negative
+//- polarity clock enable.
+//-
+//- Truth table: D C R E | Q
+//- ---------+---
+//- - - 0 - | 1
+//- d / - 0 | d
+//- - - - - | q
+//-
+module \$_DFFE_PN1N_ (D, C, R, E, Q);
+input D, C, R, E;
+output reg Q;
+always @(posedge C or negedge R) begin
+ if (R == 0)
+ Q <= 1;
+ else if (E == 0)
+ Q <= D;
+end
+endmodule
+
+// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
+//-
+//- $_DFFE_PN1P_ (D, C, R, E, Q)
+//-
+//- A positive edge D-type flip-flop with negative polarity set and positive
+//- polarity clock enable.
+//-
+//- Truth table: D C R E | Q
+//- ---------+---
+//- - - 0 - | 1
+//- d / - 1 | d
+//- - - - - | q
+//-
+module \$_DFFE_PN1P_ (D, C, R, E, Q);
+input D, C, R, E;
+output reg Q;
+always @(posedge C or negedge R) begin
+ if (R == 0)
+ Q <= 1;
+ else if (E == 1)
+ Q <= D;
+end
+endmodule
+
+// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
+//-
+//- $_DFFE_PP0N_ (D, C, R, E, Q)
+//-
+//- A positive edge D-type flip-flop with positive polarity reset and negative
+//- polarity clock enable.
+//-
+//- Truth table: D C R E | Q
+//- ---------+---
+//- - - 1 - | 0
+//- d / - 0 | d
+//- - - - - | q
+//-
+module \$_DFFE_PP0N_ (D, C, R, E, Q);
+input D, C, R, E;
+output reg Q;
+always @(posedge C or posedge R) begin
+ if (R == 1)
+ Q <= 0;
+ else if (E == 0)
+ Q <= D;
+end
+endmodule
+
+// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
+//-
+//- $_DFFE_PP0P_ (D, C, R, E, Q)
+//-
+//- A positive edge D-type flip-flop with positive polarity reset and positive
+//- polarity clock enable.
+//-
+//- Truth table: D C R E | Q
+//- ---------+---
+//- - - 1 - | 0
+//- d / - 1 | d
+//- - - - - | q
+//-
+module \$_DFFE_PP0P_ (D, C, R, E, Q);
+input D, C, R, E;
+output reg Q;
+always @(posedge C or posedge R) begin
+ if (R == 1)
+ Q <= 0;
+ else if (E == 1)
+ Q <= D;
+end
+endmodule
+
+// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
+//-
+//- $_DFFE_PP1N_ (D, C, R, E, Q)
+//-
+//- A positive edge D-type flip-flop with positive polarity set and negative
+//- polarity clock enable.
+//-
+//- Truth table: D C R E | Q
+//- ---------+---
+//- - - 1 - | 1
+//- d / - 0 | d
+//- - - - - | q
+//-
+module \$_DFFE_PP1N_ (D, C, R, E, Q);
+input D, C, R, E;
+output reg Q;
+always @(posedge C or posedge R) begin
+ if (R == 1)
+ Q <= 1;
+ else if (E == 0)
+ Q <= D;
+end
+endmodule
+
+// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
+//-
+//- $_DFFE_PP1P_ (D, C, R, E, Q)
+//-
+//- A positive edge D-type flip-flop with positive polarity set and positive
+//- polarity clock enable.
+//-
+//- Truth table: D C R E | Q
+//- ---------+---
+//- - - 1 - | 1
+//- d / - 1 | d
+//- - - - - | q
+//-
+module \$_DFFE_PP1P_ (D, C, R, E, Q);
+input D, C, R, E;
+output reg Q;
+always @(posedge C or posedge R) begin
+ if (R == 1)
+ Q <= 1;
+ else if (E == 1)
+ Q <= D;
+end
+endmodule
+
+// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
+//-
//- $_DFFSR_NNN_ (C, S, R, D, Q)
//-
//- A negative edge D-type flip-flop with negative polarity set and negative
@@ -1086,6 +1470,1422 @@ endmodule
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
//-
+//- $_DFFSRE_NNNN_ (C, S, R, E, D, Q)
+//-
+//- A negative edge D-type flip-flop with negative polarity set, negative
+//- polarity reset and negative polarity clock enable.
+//-
+//- Truth table: C S R E D | Q
+//- -----------+---
+//- - - 0 - - | 0
+//- - 0 - - - | 1
+//- \ - - 0 d | d
+//- - - - - - | q
+//-
+module \$_DFFSRE_NNNN_ (C, S, R, E, D, Q);
+input C, S, R, E, D;
+output reg Q;
+always @(negedge C, negedge S, negedge R) begin
+ if (R == 0)
+ Q <= 0;
+ else if (S == 0)
+ Q <= 1;
+ else if (E == 0)
+ Q <= D;
+end
+endmodule
+
+// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
+//-
+//- $_DFFSRE_NNNP_ (C, S, R, E, D, Q)
+//-
+//- A negative edge D-type flip-flop with negative polarity set, negative
+//- polarity reset and positive polarity clock enable.
+//-
+//- Truth table: C S R E D | Q
+//- -----------+---
+//- - - 0 - - | 0
+//- - 0 - - - | 1
+//- \ - - 1 d | d
+//- - - - - - | q
+//-
+module \$_DFFSRE_NNNP_ (C, S, R, E, D, Q);
+input C, S, R, E, D;
+output reg Q;
+always @(negedge C, negedge S, negedge R) begin
+ if (R == 0)
+ Q <= 0;
+ else if (S == 0)
+ Q <= 1;
+ else if (E == 1)
+ Q <= D;
+end
+endmodule
+
+// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
+//-
+//- $_DFFSRE_NNPN_ (C, S, R, E, D, Q)
+//-
+//- A negative edge D-type flip-flop with negative polarity set, positive
+//- polarity reset and negative polarity clock enable.
+//-
+//- Truth table: C S R E D | Q
+//- -----------+---
+//- - - 1 - - | 0
+//- - 0 - - - | 1
+//- \ - - 0 d | d
+//- - - - - - | q
+//-
+module \$_DFFSRE_NNPN_ (C, S, R, E, D, Q);
+input C, S, R, E, D;
+output reg Q;
+always @(negedge C, negedge S, posedge R) begin
+ if (R == 1)
+ Q <= 0;
+ else if (S == 0)
+ Q <= 1;
+ else if (E == 0)
+ Q <= D;
+end
+endmodule
+
+// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
+//-
+//- $_DFFSRE_NNPP_ (C, S, R, E, D, Q)
+//-
+//- A negative edge D-type flip-flop with negative polarity set, positive
+//- polarity reset and positive polarity clock enable.
+//-
+//- Truth table: C S R E D | Q
+//- -----------+---
+//- - - 1 - - | 0
+//- - 0 - - - | 1
+//- \ - - 1 d | d
+//- - - - - - | q
+//-
+module \$_DFFSRE_NNPP_ (C, S, R, E, D, Q);
+input C, S, R, E, D;
+output reg Q;
+always @(negedge C, negedge S, posedge R) begin
+ if (R == 1)
+ Q <= 0;
+ else if (S == 0)
+ Q <= 1;
+ else if (E == 1)
+ Q <= D;
+end
+endmodule
+
+// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
+//-
+//- $_DFFSRE_NPNN_ (C, S, R, E, D, Q)
+//-
+//- A negative edge D-type flip-flop with positive polarity set, negative
+//- polarity reset and negative polarity clock enable.
+//-
+//- Truth table: C S R E D | Q
+//- -----------+---
+//- - - 0 - - | 0
+//- - 1 - - - | 1
+//- \ - - 0 d | d
+//- - - - - - | q
+//-
+module \$_DFFSRE_NPNN_ (C, S, R, E, D, Q);
+input C, S, R, E, D;
+output reg Q;
+always @(negedge C, posedge S, negedge R) begin
+ if (R == 0)
+ Q <= 0;
+ else if (S == 1)
+ Q <= 1;
+ else if (E == 0)
+ Q <= D;
+end
+endmodule
+
+// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
+//-
+//- $_DFFSRE_NPNP_ (C, S, R, E, D, Q)
+//-
+//- A negative edge D-type flip-flop with positive polarity set, negative
+//- polarity reset and positive polarity clock enable.
+//-
+//- Truth table: C S R E D | Q
+//- -----------+---
+//- - - 0 - - | 0
+//- - 1 - - - | 1
+//- \ - - 1 d | d
+//- - - - - - | q
+//-
+module \$_DFFSRE_NPNP_ (C, S, R, E, D, Q);
+input C, S, R, E, D;
+output reg Q;
+always @(negedge C, posedge S, negedge R) begin
+ if (R == 0)
+ Q <= 0;
+ else if (S == 1)
+ Q <= 1;
+ else if (E == 1)
+ Q <= D;
+end
+endmodule
+
+// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
+//-
+//- $_DFFSRE_NPPN_ (C, S, R, E, D, Q)
+//-
+//- A negative edge D-type flip-flop with positive polarity set, positive
+//- polarity reset and negative polarity clock enable.
+//-
+//- Truth table: C S R E D | Q
+//- -----------+---
+//- - - 1 - - | 0
+//- - 1 - - - | 1
+//- \ - - 0 d | d
+//- - - - - - | q
+//-
+module \$_DFFSRE_NPPN_ (C, S, R, E, D, Q);
+input C, S, R, E, D;
+output reg Q;
+always @(negedge C, posedge S, posedge R) begin
+ if (R == 1)
+ Q <= 0;
+ else if (S == 1)
+ Q <= 1;
+ else if (E == 0)
+ Q <= D;
+end
+endmodule
+
+// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
+//-
+//- $_DFFSRE_NPPP_ (C, S, R, E, D, Q)
+//-
+//- A negative edge D-type flip-flop with positive polarity set, positive
+//- polarity reset and positive polarity clock enable.
+//-
+//- Truth table: C S R E D | Q
+//- -----------+---
+//- - - 1 - - | 0
+//- - 1 - - - | 1
+//- \ - - 1 d | d
+//- - - - - - | q
+//-
+module \$_DFFSRE_NPPP_ (C, S, R, E, D, Q);
+input C, S, R, E, D;
+output reg Q;
+always @(negedge C, posedge S, posedge R) begin
+ if (R == 1)
+ Q <= 0;
+ else if (S == 1)
+ Q <= 1;
+ else if (E == 1)
+ Q <= D;
+end
+endmodule
+
+// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
+//-
+//- $_DFFSRE_PNNN_ (C, S, R, E, D, Q)
+//-
+//- A positive edge D-type flip-flop with negative polarity set, negative
+//- polarity reset and negative polarity clock enable.
+//-
+//- Truth table: C S R E D | Q
+//- -----------+---
+//- - - 0 - - | 0
+//- - 0 - - - | 1
+//- / - - 0 d | d
+//- - - - - - | q
+//-
+module \$_DFFSRE_PNNN_ (C, S, R, E, D, Q);
+input C, S, R, E, D;
+output reg Q;
+always @(posedge C, negedge S, negedge R) begin
+ if (R == 0)
+ Q <= 0;
+ else if (S == 0)
+ Q <= 1;
+ else if (E == 0)
+ Q <= D;
+end
+endmodule
+
+// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
+//-
+//- $_DFFSRE_PNNP_ (C, S, R, E, D, Q)
+//-
+//- A positive edge D-type flip-flop with negative polarity set, negative
+//- polarity reset and positive polarity clock enable.
+//-
+//- Truth table: C S R E D | Q
+//- -----------+---
+//- - - 0 - - | 0
+//- - 0 - - - | 1
+//- / - - 1 d | d
+//- - - - - - | q
+//-
+module \$_DFFSRE_PNNP_ (C, S, R, E, D, Q);
+input C, S, R, E, D;
+output reg Q;
+always @(posedge C, negedge S, negedge R) begin
+ if (R == 0)
+ Q <= 0;
+ else if (S == 0)
+ Q <= 1;
+ else if (E == 1)
+ Q <= D;
+end
+endmodule
+
+// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
+//-
+//- $_DFFSRE_PNPN_ (C, S, R, E, D, Q)
+//-
+//- A positive edge D-type flip-flop with negative polarity set, positive
+//- polarity reset and negative polarity clock enable.
+//-
+//- Truth table: C S R E D | Q
+//- -----------+---
+//- - - 1 - - | 0
+//- - 0 - - - | 1
+//- / - - 0 d | d
+//- - - - - - | q
+//-
+module \$_DFFSRE_PNPN_ (C, S, R, E, D, Q);
+input C, S, R, E, D;
+output reg Q;
+always @(posedge C, negedge S, posedge R) begin
+ if (R == 1)
+ Q <= 0;
+ else if (S == 0)
+ Q <= 1;
+ else if (E == 0)
+ Q <= D;
+end
+endmodule
+
+// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
+//-
+//- $_DFFSRE_PNPP_ (C, S, R, E, D, Q)
+//-
+//- A positive edge D-type flip-flop with negative polarity set, positive
+//- polarity reset and positive polarity clock enable.
+//-
+//- Truth table: C S R E D | Q
+//- -----------+---
+//- - - 1 - - | 0
+//- - 0 - - - | 1
+//- / - - 1 d | d
+//- - - - - - | q
+//-
+module \$_DFFSRE_PNPP_ (C, S, R, E, D, Q);
+input C, S, R, E, D;
+output reg Q;
+always @(posedge C, negedge S, posedge R) begin
+ if (R == 1)
+ Q <= 0;
+ else if (S == 0)
+ Q <= 1;
+ else if (E == 1)
+ Q <= D;
+end
+endmodule
+
+// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
+//-
+//- $_DFFSRE_PPNN_ (C, S, R, E, D, Q)
+//-
+//- A positive edge D-type flip-flop with positive polarity set, negative
+//- polarity reset and negative polarity clock enable.
+//-
+//- Truth table: C S R E D | Q
+//- -----------+---
+//- - - 0 - - | 0
+//- - 1 - - - | 1
+//- / - - 0 d | d
+//- - - - - - | q
+//-
+module \$_DFFSRE_PPNN_ (C, S, R, E, D, Q);
+input C, S, R, E, D;
+output reg Q;
+always @(posedge C, posedge S, negedge R) begin
+ if (R == 0)
+ Q <= 0;
+ else if (S == 1)
+ Q <= 1;
+ else if (E == 0)
+ Q <= D;
+end
+endmodule
+
+// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
+//-
+//- $_DFFSRE_PPNP_ (C, S, R, E, D, Q)
+//-
+//- A positive edge D-type flip-flop with positive polarity set, negative
+//- polarity reset and positive polarity clock enable.
+//-
+//- Truth table: C S R E D | Q
+//- -----------+---
+//- - - 0 - - | 0
+//- - 1 - - - | 1
+//- / - - 1 d | d
+//- - - - - - | q
+//-
+module \$_DFFSRE_PPNP_ (C, S, R, E, D, Q);
+input C, S, R, E, D;
+output reg Q;
+always @(posedge C, posedge S, negedge R) begin
+ if (R == 0)
+ Q <= 0;
+ else if (S == 1)
+ Q <= 1;
+ else if (E == 1)
+ Q <= D;
+end
+endmodule
+
+// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
+//-
+//- $_DFFSRE_PPPN_ (C, S, R, E, D, Q)
+//-
+//- A positive edge D-type flip-flop with positive polarity set, positive
+//- polarity reset and negative polarity clock enable.
+//-
+//- Truth table: C S R E D | Q
+//- -----------+---
+//- - - 1 - - | 0
+//- - 1 - - - | 1
+//- / - - 0 d | d
+//- - - - - - | q
+//-
+module \$_DFFSRE_PPPN_ (C, S, R, E, D, Q);
+input C, S, R, E, D;
+output reg Q;
+always @(posedge C, posedge S, posedge R) begin
+ if (R == 1)
+ Q <= 0;
+ else if (S == 1)
+ Q <= 1;
+ else if (E == 0)
+ Q <= D;
+end
+endmodule
+
+// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
+//-
+//- $_DFFSRE_PPPP_ (C, S, R, E, D, Q)
+//-
+//- A positive edge D-type flip-flop with positive polarity set, positive
+//- polarity reset and positive polarity clock enable.
+//-
+//- Truth table: C S R E D | Q
+//- -----------+---
+//- - - 1 - - | 0
+//- - 1 - - - | 1
+//- / - - 1 d | d
+//- - - - - - | q
+//-
+module \$_DFFSRE_PPPP_ (C, S, R, E, D, Q);
+input C, S, R, E, D;
+output reg Q;
+always @(posedge C, posedge S, posedge R) begin
+ if (R == 1)
+ Q <= 0;
+ else if (S == 1)
+ Q <= 1;
+ else if (E == 1)
+ Q <= D;
+end
+endmodule
+
+// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
+//-
+//- $_SDFF_NN0_ (D, C, R, Q)
+//-
+//- A negative edge D-type flip-flop with negative polarity synchronous reset.
+//-
+//- Truth table: D C R | Q
+//- -------+---
+//- - \ 0 | 0
+//- d \ - | d
+//- - - - | q
+//-
+module \$_SDFF_NN0_ (D, C, R, Q);
+input D, C, R;
+output reg Q;
+always @(negedge C) begin
+ if (R == 0)
+ Q <= 0;
+ else
+ Q <= D;
+end
+endmodule
+
+// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
+//-
+//- $_SDFF_NN1_ (D, C, R, Q)
+//-
+//- A negative edge D-type flip-flop with negative polarity synchronous set.
+//-
+//- Truth table: D C R | Q
+//- -------+---
+//- - \ 0 | 1
+//- d \ - | d
+//- - - - | q
+//-
+module \$_SDFF_NN1_ (D, C, R, Q);
+input D, C, R;
+output reg Q;
+always @(negedge C) begin
+ if (R == 0)
+ Q <= 1;
+ else
+ Q <= D;
+end
+endmodule
+
+// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
+//-
+//- $_SDFF_NP0_ (D, C, R, Q)
+//-
+//- A negative edge D-type flip-flop with positive polarity synchronous reset.
+//-
+//- Truth table: D C R | Q
+//- -------+---
+//- - \ 1 | 0
+//- d \ - | d
+//- - - - | q
+//-
+module \$_SDFF_NP0_ (D, C, R, Q);
+input D, C, R;
+output reg Q;
+always @(negedge C) begin
+ if (R == 1)
+ Q <= 0;
+ else
+ Q <= D;
+end
+endmodule
+
+// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
+//-
+//- $_SDFF_NP1_ (D, C, R, Q)
+//-
+//- A negative edge D-type flip-flop with positive polarity synchronous set.
+//-
+//- Truth table: D C R | Q
+//- -------+---
+//- - \ 1 | 1
+//- d \ - | d
+//- - - - | q
+//-
+module \$_SDFF_NP1_ (D, C, R, Q);
+input D, C, R;
+output reg Q;
+always @(negedge C) begin
+ if (R == 1)
+ Q <= 1;
+ else
+ Q <= D;
+end
+endmodule
+
+// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
+//-
+//- $_SDFF_PN0_ (D, C, R, Q)
+//-
+//- A positive edge D-type flip-flop with negative polarity synchronous reset.
+//-
+//- Truth table: D C R | Q
+//- -------+---
+//- - / 0 | 0
+//- d / - | d
+//- - - - | q
+//-
+module \$_SDFF_PN0_ (D, C, R, Q);
+input D, C, R;
+output reg Q;
+always @(posedge C) begin
+ if (R == 0)
+ Q <= 0;
+ else
+ Q <= D;
+end
+endmodule
+
+// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
+//-
+//- $_SDFF_PN1_ (D, C, R, Q)
+//-
+//- A positive edge D-type flip-flop with negative polarity synchronous set.
+//-
+//- Truth table: D C R | Q
+//- -------+---
+//- - / 0 | 1
+//- d / - | d
+//- - - - | q
+//-
+module \$_SDFF_PN1_ (D, C, R, Q);
+input D, C, R;
+output reg Q;
+always @(posedge C) begin
+ if (R == 0)
+ Q <= 1;
+ else
+ Q <= D;
+end
+endmodule
+
+// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
+//-
+//- $_SDFF_PP0_ (D, C, R, Q)
+//-
+//- A positive edge D-type flip-flop with positive polarity synchronous reset.
+//-
+//- Truth table: D C R | Q
+//- -------+---
+//- - / 1 | 0
+//- d / - | d
+//- - - - | q
+//-
+module \$_SDFF_PP0_ (D, C, R, Q);
+input D, C, R;
+output reg Q;
+always @(posedge C) begin
+ if (R == 1)
+ Q <= 0;
+ else
+ Q <= D;
+end
+endmodule
+
+// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
+//-
+//- $_SDFF_PP1_ (D, C, R, Q)
+//-
+//- A positive edge D-type flip-flop with positive polarity synchronous set.
+//-
+//- Truth table: D C R | Q
+//- -------+---
+//- - / 1 | 1
+//- d / - | d
+//- - - - | q
+//-
+module \$_SDFF_PP1_ (D, C, R, Q);
+input D, C, R;
+output reg Q;
+always @(posedge C) begin
+ if (R == 1)
+ Q <= 1;
+ else
+ Q <= D;
+end
+endmodule
+
+// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
+//-
+//- $_SDFFE_NN0N_ (D, C, R, E, Q)
+//-
+//- A negative edge D-type flip-flop with negative polarity synchronous reset and negative
+//- polarity clock enable (with reset having priority).
+//-
+//- Truth table: D C R E | Q
+//- ---------+---
+//- - \ 0 - | 0
+//- d \ - 0 | d
+//- - - - - | q
+//-
+module \$_SDFFE_NN0N_ (D, C, R, E, Q);
+input D, C, R, E;
+output reg Q;
+always @(negedge C) begin
+ if (R == 0)
+ Q <= 0;
+ else if (E == 0)
+ Q <= D;
+end
+endmodule
+
+// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
+//-
+//- $_SDFFE_NN0P_ (D, C, R, E, Q)
+//-
+//- A negative edge D-type flip-flop with negative polarity synchronous reset and positive
+//- polarity clock enable (with reset having priority).
+//-
+//- Truth table: D C R E | Q
+//- ---------+---
+//- - \ 0 - | 0
+//- d \ - 1 | d
+//- - - - - | q
+//-
+module \$_SDFFE_NN0P_ (D, C, R, E, Q);
+input D, C, R, E;
+output reg Q;
+always @(negedge C) begin
+ if (R == 0)
+ Q <= 0;
+ else if (E == 1)
+ Q <= D;
+end
+endmodule
+
+// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
+//-
+//- $_SDFFE_NN1N_ (D, C, R, E, Q)
+//-
+//- A negative edge D-type flip-flop with negative polarity synchronous set and negative
+//- polarity clock enable (with set having priority).
+//-
+//- Truth table: D C R E | Q
+//- ---------+---
+//- - \ 0 - | 1
+//- d \ - 0 | d
+//- - - - - | q
+//-
+module \$_SDFFE_NN1N_ (D, C, R, E, Q);
+input D, C, R, E;
+output reg Q;
+always @(negedge C) begin
+ if (R == 0)
+ Q <= 1;
+ else if (E == 0)
+ Q <= D;
+end
+endmodule
+
+// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
+//-
+//- $_SDFFE_NN1P_ (D, C, R, E, Q)
+//-
+//- A negative edge D-type flip-flop with negative polarity synchronous set and positive
+//- polarity clock enable (with set having priority).
+//-
+//- Truth table: D C R E | Q
+//- ---------+---
+//- - \ 0 - | 1
+//- d \ - 1 | d
+//- - - - - | q
+//-
+module \$_SDFFE_NN1P_ (D, C, R, E, Q);
+input D, C, R, E;
+output reg Q;
+always @(negedge C) begin
+ if (R == 0)
+ Q <= 1;
+ else if (E == 1)
+ Q <= D;
+end
+endmodule
+
+// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
+//-
+//- $_SDFFE_NP0N_ (D, C, R, E, Q)
+//-
+//- A negative edge D-type flip-flop with positive polarity synchronous reset and negative
+//- polarity clock enable (with reset having priority).
+//-
+//- Truth table: D C R E | Q
+//- ---------+---
+//- - \ 1 - | 0
+//- d \ - 0 | d
+//- - - - - | q
+//-
+module \$_SDFFE_NP0N_ (D, C, R, E, Q);
+input D, C, R, E;
+output reg Q;
+always @(negedge C) begin
+ if (R == 1)
+ Q <= 0;
+ else if (E == 0)
+ Q <= D;
+end
+endmodule
+
+// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
+//-
+//- $_SDFFE_NP0P_ (D, C, R, E, Q)
+//-
+//- A negative edge D-type flip-flop with positive polarity synchronous reset and positive
+//- polarity clock enable (with reset having priority).
+//-
+//- Truth table: D C R E | Q
+//- ---------+---
+//- - \ 1 - | 0
+//- d \ - 1 | d
+//- - - - - | q
+//-
+module \$_SDFFE_NP0P_ (D, C, R, E, Q);
+input D, C, R, E;
+output reg Q;
+always @(negedge C) begin
+ if (R == 1)
+ Q <= 0;
+ else if (E == 1)
+ Q <= D;
+end
+endmodule
+
+// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
+//-
+//- $_SDFFE_NP1N_ (D, C, R, E, Q)
+//-
+//- A negative edge D-type flip-flop with positive polarity synchronous set and negative
+//- polarity clock enable (with set having priority).
+//-
+//- Truth table: D C R E | Q
+//- ---------+---
+//- - \ 1 - | 1
+//- d \ - 0 | d
+//- - - - - | q
+//-
+module \$_SDFFE_NP1N_ (D, C, R, E, Q);
+input D, C, R, E;
+output reg Q;
+always @(negedge C) begin
+ if (R == 1)
+ Q <= 1;
+ else if (E == 0)
+ Q <= D;
+end
+endmodule
+
+// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
+//-
+//- $_SDFFE_NP1P_ (D, C, R, E, Q)
+//-
+//- A negative edge D-type flip-flop with positive polarity synchronous set and positive
+//- polarity clock enable (with set having priority).
+//-
+//- Truth table: D C R E | Q
+//- ---------+---
+//- - \ 1 - | 1
+//- d \ - 1 | d
+//- - - - - | q
+//-
+module \$_SDFFE_NP1P_ (D, C, R, E, Q);
+input D, C, R, E;
+output reg Q;
+always @(negedge C) begin
+ if (R == 1)
+ Q <= 1;
+ else if (E == 1)
+ Q <= D;
+end
+endmodule
+
+// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
+//-
+//- $_SDFFE_PN0N_ (D, C, R, E, Q)
+//-
+//- A positive edge D-type flip-flop with negative polarity synchronous reset and negative
+//- polarity clock enable (with reset having priority).
+//-
+//- Truth table: D C R E | Q
+//- ---------+---
+//- - / 0 - | 0
+//- d / - 0 | d
+//- - - - - | q
+//-
+module \$_SDFFE_PN0N_ (D, C, R, E, Q);
+input D, C, R, E;
+output reg Q;
+always @(posedge C) begin
+ if (R == 0)
+ Q <= 0;
+ else if (E == 0)
+ Q <= D;
+end
+endmodule
+
+// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
+//-
+//- $_SDFFE_PN0P_ (D, C, R, E, Q)
+//-
+//- A positive edge D-type flip-flop with negative polarity synchronous reset and positive
+//- polarity clock enable (with reset having priority).
+//-
+//- Truth table: D C R E | Q
+//- ---------+---
+//- - / 0 - | 0
+//- d / - 1 | d
+//- - - - - | q
+//-
+module \$_SDFFE_PN0P_ (D, C, R, E, Q);
+input D, C, R, E;
+output reg Q;
+always @(posedge C) begin
+ if (R == 0)
+ Q <= 0;
+ else if (E == 1)
+ Q <= D;
+end
+endmodule
+
+// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
+//-
+//- $_SDFFE_PN1N_ (D, C, R, E, Q)
+//-
+//- A positive edge D-type flip-flop with negative polarity synchronous set and negative
+//- polarity clock enable (with set having priority).
+//-
+//- Truth table: D C R E | Q
+//- ---------+---
+//- - / 0 - | 1
+//- d / - 0 | d
+//- - - - - | q
+//-
+module \$_SDFFE_PN1N_ (D, C, R, E, Q);
+input D, C, R, E;
+output reg Q;
+always @(posedge C) begin
+ if (R == 0)
+ Q <= 1;
+ else if (E == 0)
+ Q <= D;
+end
+endmodule
+
+// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
+//-
+//- $_SDFFE_PN1P_ (D, C, R, E, Q)
+//-
+//- A positive edge D-type flip-flop with negative polarity synchronous set and positive
+//- polarity clock enable (with set having priority).
+//-
+//- Truth table: D C R E | Q
+//- ---------+---
+//- - / 0 - | 1
+//- d / - 1 | d
+//- - - - - | q
+//-
+module \$_SDFFE_PN1P_ (D, C, R, E, Q);
+input D, C, R, E;
+output reg Q;
+always @(posedge C) begin
+ if (R == 0)
+ Q <= 1;
+ else if (E == 1)
+ Q <= D;
+end
+endmodule
+
+// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
+//-
+//- $_SDFFE_PP0N_ (D, C, R, E, Q)
+//-
+//- A positive edge D-type flip-flop with positive polarity synchronous reset and negative
+//- polarity clock enable (with reset having priority).
+//-
+//- Truth table: D C R E | Q
+//- ---------+---
+//- - / 1 - | 0
+//- d / - 0 | d
+//- - - - - | q
+//-
+module \$_SDFFE_PP0N_ (D, C, R, E, Q);
+input D, C, R, E;
+output reg Q;
+always @(posedge C) begin
+ if (R == 1)
+ Q <= 0;
+ else if (E == 0)
+ Q <= D;
+end
+endmodule
+
+// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
+//-
+//- $_SDFFE_PP0P_ (D, C, R, E, Q)
+//-
+//- A positive edge D-type flip-flop with positive polarity synchronous reset and positive
+//- polarity clock enable (with reset having priority).
+//-
+//- Truth table: D C R E | Q
+//- ---------+---
+//- - / 1 - | 0
+//- d / - 1 | d
+//- - - - - | q
+//-
+module \$_SDFFE_PP0P_ (D, C, R, E, Q);
+input D, C, R, E;
+output reg Q;
+always @(posedge C) begin
+ if (R == 1)
+ Q <= 0;
+ else if (E == 1)
+ Q <= D;
+end
+endmodule
+
+// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
+//-
+//- $_SDFFE_PP1N_ (D, C, R, E, Q)
+//-
+//- A positive edge D-type flip-flop with positive polarity synchronous set and negative
+//- polarity clock enable (with set having priority).
+//-
+//- Truth table: D C R E | Q
+//- ---------+---
+//- - / 1 - | 1
+//- d / - 0 | d
+//- - - - - | q
+//-
+module \$_SDFFE_PP1N_ (D, C, R, E, Q);
+input D, C, R, E;
+output reg Q;
+always @(posedge C) begin
+ if (R == 1)
+ Q <= 1;
+ else if (E == 0)
+ Q <= D;
+end
+endmodule
+
+// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
+//-
+//- $_SDFFE_PP1P_ (D, C, R, E, Q)
+//-
+//- A positive edge D-type flip-flop with positive polarity synchronous set and positive
+//- polarity clock enable (with set having priority).
+//-
+//- Truth table: D C R E | Q
+//- ---------+---
+//- - / 1 - | 1
+//- d / - 1 | d
+//- - - - - | q
+//-
+module \$_SDFFE_PP1P_ (D, C, R, E, Q);
+input D, C, R, E;
+output reg Q;
+always @(posedge C) begin
+ if (R == 1)
+ Q <= 1;
+ else if (E == 1)
+ Q <= D;
+end
+endmodule
+
+// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
+//-
+//- $_SDFFCE_NN0N_ (D, C, R, E, Q)
+//-
+//- A negative edge D-type flip-flop with negative polarity synchronous reset and negative
+//- polarity clock enable (with clock enable having priority).
+//-
+//- Truth table: D C R E | Q
+//- ---------+---
+//- - \ 0 0 | 0
+//- d \ - 0 | d
+//- - - - - | q
+//-
+module \$_SDFFCE_NN0N_ (D, C, R, E, Q);
+input D, C, R, E;
+output reg Q;
+always @(negedge C) begin
+ if (E == 0) begin
+ if (R == 0)
+ Q <= 0;
+ else
+ Q <= D;
+ end
+end
+endmodule
+
+// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
+//-
+//- $_SDFFCE_NN0P_ (D, C, R, E, Q)
+//-
+//- A negative edge D-type flip-flop with negative polarity synchronous reset and positive
+//- polarity clock enable (with clock enable having priority).
+//-
+//- Truth table: D C R E | Q
+//- ---------+---
+//- - \ 0 1 | 0
+//- d \ - 1 | d
+//- - - - - | q
+//-
+module \$_SDFFCE_NN0P_ (D, C, R, E, Q);
+input D, C, R, E;
+output reg Q;
+always @(negedge C) begin
+ if (E == 1) begin
+ if (R == 0)
+ Q <= 0;
+ else
+ Q <= D;
+ end
+end
+endmodule
+
+// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
+//-
+//- $_SDFFCE_NN1N_ (D, C, R, E, Q)
+//-
+//- A negative edge D-type flip-flop with negative polarity synchronous set and negative
+//- polarity clock enable (with clock enable having priority).
+//-
+//- Truth table: D C R E | Q
+//- ---------+---
+//- - \ 0 0 | 1
+//- d \ - 0 | d
+//- - - - - | q
+//-
+module \$_SDFFCE_NN1N_ (D, C, R, E, Q);
+input D, C, R, E;
+output reg Q;
+always @(negedge C) begin
+ if (E == 0) begin
+ if (R == 0)
+ Q <= 1;
+ else
+ Q <= D;
+ end
+end
+endmodule
+
+// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
+//-
+//- $_SDFFCE_NN1P_ (D, C, R, E, Q)
+//-
+//- A negative edge D-type flip-flop with negative polarity synchronous set and positive
+//- polarity clock enable (with clock enable having priority).
+//-
+//- Truth table: D C R E | Q
+//- ---------+---
+//- - \ 0 1 | 1
+//- d \ - 1 | d
+//- - - - - | q
+//-
+module \$_SDFFCE_NN1P_ (D, C, R, E, Q);
+input D, C, R, E;
+output reg Q;
+always @(negedge C) begin
+ if (E == 1) begin
+ if (R == 0)
+ Q <= 1;
+ else
+ Q <= D;
+ end
+end
+endmodule
+
+// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
+//-
+//- $_SDFFCE_NP0N_ (D, C, R, E, Q)
+//-
+//- A negative edge D-type flip-flop with positive polarity synchronous reset and negative
+//- polarity clock enable (with clock enable having priority).
+//-
+//- Truth table: D C R E | Q
+//- ---------+---
+//- - \ 1 0 | 0
+//- d \ - 0 | d
+//- - - - - | q
+//-
+module \$_SDFFCE_NP0N_ (D, C, R, E, Q);
+input D, C, R, E;
+output reg Q;
+always @(negedge C) begin
+ if (E == 0) begin
+ if (R == 1)
+ Q <= 0;
+ else
+ Q <= D;
+ end
+end
+endmodule
+
+// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
+//-
+//- $_SDFFCE_NP0P_ (D, C, R, E, Q)
+//-
+//- A negative edge D-type flip-flop with positive polarity synchronous reset and positive
+//- polarity clock enable (with clock enable having priority).
+//-
+//- Truth table: D C R E | Q
+//- ---------+---
+//- - \ 1 1 | 0
+//- d \ - 1 | d
+//- - - - - | q
+//-
+module \$_SDFFCE_NP0P_ (D, C, R, E, Q);
+input D, C, R, E;
+output reg Q;
+always @(negedge C) begin
+ if (E == 1) begin
+ if (R == 1)
+ Q <= 0;
+ else
+ Q <= D;
+ end
+end
+endmodule
+
+// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
+//-
+//- $_SDFFCE_NP1N_ (D, C, R, E, Q)
+//-
+//- A negative edge D-type flip-flop with positive polarity synchronous set and negative
+//- polarity clock enable (with clock enable having priority).
+//-
+//- Truth table: D C R E | Q
+//- ---------+---
+//- - \ 1 0 | 1
+//- d \ - 0 | d
+//- - - - - | q
+//-
+module \$_SDFFCE_NP1N_ (D, C, R, E, Q);
+input D, C, R, E;
+output reg Q;
+always @(negedge C) begin
+ if (E == 0) begin
+ if (R == 1)
+ Q <= 1;
+ else
+ Q <= D;
+ end
+end
+endmodule
+
+// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
+//-
+//- $_SDFFCE_NP1P_ (D, C, R, E, Q)
+//-
+//- A negative edge D-type flip-flop with positive polarity synchronous set and positive
+//- polarity clock enable (with clock enable having priority).
+//-
+//- Truth table: D C R E | Q
+//- ---------+---
+//- - \ 1 1 | 1
+//- d \ - 1 | d
+//- - - - - | q
+//-
+module \$_SDFFCE_NP1P_ (D, C, R, E, Q);
+input D, C, R, E;
+output reg Q;
+always @(negedge C) begin
+ if (E == 1) begin
+ if (R == 1)
+ Q <= 1;
+ else
+ Q <= D;
+ end
+end
+endmodule
+
+// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
+//-
+//- $_SDFFCE_PN0N_ (D, C, R, E, Q)
+//-
+//- A positive edge D-type flip-flop with negative polarity synchronous reset and negative
+//- polarity clock enable (with clock enable having priority).
+//-
+//- Truth table: D C R E | Q
+//- ---------+---
+//- - / 0 0 | 0
+//- d / - 0 | d
+//- - - - - | q
+//-
+module \$_SDFFCE_PN0N_ (D, C, R, E, Q);
+input D, C, R, E;
+output reg Q;
+always @(posedge C) begin
+ if (E == 0) begin
+ if (R == 0)
+ Q <= 0;
+ else
+ Q <= D;
+ end
+end
+endmodule
+
+// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
+//-
+//- $_SDFFCE_PN0P_ (D, C, R, E, Q)
+//-
+//- A positive edge D-type flip-flop with negative polarity synchronous reset and positive
+//- polarity clock enable (with clock enable having priority).
+//-
+//- Truth table: D C R E | Q
+//- ---------+---
+//- - / 0 1 | 0
+//- d / - 1 | d
+//- - - - - | q
+//-
+module \$_SDFFCE_PN0P_ (D, C, R, E, Q);
+input D, C, R, E;
+output reg Q;
+always @(posedge C) begin
+ if (E == 1) begin
+ if (R == 0)
+ Q <= 0;
+ else
+ Q <= D;
+ end
+end
+endmodule
+
+// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
+//-
+//- $_SDFFCE_PN1N_ (D, C, R, E, Q)
+//-
+//- A positive edge D-type flip-flop with negative polarity synchronous set and negative
+//- polarity clock enable (with clock enable having priority).
+//-
+//- Truth table: D C R E | Q
+//- ---------+---
+//- - / 0 0 | 1
+//- d / - 0 | d
+//- - - - - | q
+//-
+module \$_SDFFCE_PN1N_ (D, C, R, E, Q);
+input D, C, R, E;
+output reg Q;
+always @(posedge C) begin
+ if (E == 0) begin
+ if (R == 0)
+ Q <= 1;
+ else
+ Q <= D;
+ end
+end
+endmodule
+
+// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
+//-
+//- $_SDFFCE_PN1P_ (D, C, R, E, Q)
+//-
+//- A positive edge D-type flip-flop with negative polarity synchronous set and positive
+//- polarity clock enable (with clock enable having priority).
+//-
+//- Truth table: D C R E | Q
+//- ---------+---
+//- - / 0 1 | 1
+//- d / - 1 | d
+//- - - - - | q
+//-
+module \$_SDFFCE_PN1P_ (D, C, R, E, Q);
+input D, C, R, E;
+output reg Q;
+always @(posedge C) begin
+ if (E == 1) begin
+ if (R == 0)
+ Q <= 1;
+ else
+ Q <= D;
+ end
+end
+endmodule
+
+// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
+//-
+//- $_SDFFCE_PP0N_ (D, C, R, E, Q)
+//-
+//- A positive edge D-type flip-flop with positive polarity synchronous reset and negative
+//- polarity clock enable (with clock enable having priority).
+//-
+//- Truth table: D C R E | Q
+//- ---------+---
+//- - / 1 0 | 0
+//- d / - 0 | d
+//- - - - - | q
+//-
+module \$_SDFFCE_PP0N_ (D, C, R, E, Q);
+input D, C, R, E;
+output reg Q;
+always @(posedge C) begin
+ if (E == 0) begin
+ if (R == 1)
+ Q <= 0;
+ else
+ Q <= D;
+ end
+end
+endmodule
+
+// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
+//-
+//- $_SDFFCE_PP0P_ (D, C, R, E, Q)
+//-
+//- A positive edge D-type flip-flop with positive polarity synchronous reset and positive
+//- polarity clock enable (with clock enable having priority).
+//-
+//- Truth table: D C R E | Q
+//- ---------+---
+//- - / 1 1 | 0
+//- d / - 1 | d
+//- - - - - | q
+//-
+module \$_SDFFCE_PP0P_ (D, C, R, E, Q);
+input D, C, R, E;
+output reg Q;
+always @(posedge C) begin
+ if (E == 1) begin
+ if (R == 1)
+ Q <= 0;
+ else
+ Q <= D;
+ end
+end
+endmodule
+
+// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
+//-
+//- $_SDFFCE_PP1N_ (D, C, R, E, Q)
+//-
+//- A positive edge D-type flip-flop with positive polarity synchronous set and negative
+//- polarity clock enable (with clock enable having priority).
+//-
+//- Truth table: D C R E | Q
+//- ---------+---
+//- - / 1 0 | 1
+//- d / - 0 | d
+//- - - - - | q
+//-
+module \$_SDFFCE_PP1N_ (D, C, R, E, Q);
+input D, C, R, E;
+output reg Q;
+always @(posedge C) begin
+ if (E == 0) begin
+ if (R == 1)
+ Q <= 1;
+ else
+ Q <= D;
+ end
+end
+endmodule
+
+// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
+//-
+//- $_SDFFCE_PP1P_ (D, C, R, E, Q)
+//-
+//- A positive edge D-type flip-flop with positive polarity synchronous set and positive
+//- polarity clock enable (with clock enable having priority).
+//-
+//- Truth table: D C R E | Q
+//- ---------+---
+//- - / 1 1 | 1
+//- d / - 1 | d
+//- - - - - | q
+//-
+module \$_SDFFCE_PP1P_ (D, C, R, E, Q);
+input D, C, R, E;
+output reg Q;
+always @(posedge C) begin
+ if (E == 1) begin
+ if (R == 1)
+ Q <= 1;
+ else
+ Q <= D;
+ end
+end
+endmodule
+
+// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
+//-
//- $_DLATCH_N_ (E, D, Q)
//-
//- A negative enable D-type latch.
@@ -1126,6 +2926,190 @@ endmodule
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
//-
+//- $_DLATCH_NN0_ (E, R, D, Q)
+//-
+//- A negative enable D-type latch with negative polarity reset.
+//-
+//- Truth table: E R D | Q
+//- -------+---
+//- - 0 - | 0
+//- 0 - d | d
+//- - - - | q
+//-
+module \$_DLATCH_NN0_ (E, R, D, Q);
+input E, R, D;
+output reg Q;
+always @* begin
+ if (R == 0)
+ Q <= 0;
+ else if (E == 0)
+ Q <= D;
+end
+endmodule
+
+// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
+//-
+//- $_DLATCH_NN1_ (E, R, D, Q)
+//-
+//- A negative enable D-type latch with negative polarity set.
+//-
+//- Truth table: E R D | Q
+//- -------+---
+//- - 0 - | 1
+//- 0 - d | d
+//- - - - | q
+//-
+module \$_DLATCH_NN1_ (E, R, D, Q);
+input E, R, D;
+output reg Q;
+always @* begin
+ if (R == 0)
+ Q <= 1;
+ else if (E == 0)
+ Q <= D;
+end
+endmodule
+
+// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
+//-
+//- $_DLATCH_NP0_ (E, R, D, Q)
+//-
+//- A negative enable D-type latch with positive polarity reset.
+//-
+//- Truth table: E R D | Q
+//- -------+---
+//- - 1 - | 0
+//- 0 - d | d
+//- - - - | q
+//-
+module \$_DLATCH_NP0_ (E, R, D, Q);
+input E, R, D;
+output reg Q;
+always @* begin
+ if (R == 1)
+ Q <= 0;
+ else if (E == 0)
+ Q <= D;
+end
+endmodule
+
+// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
+//-
+//- $_DLATCH_NP1_ (E, R, D, Q)
+//-
+//- A negative enable D-type latch with positive polarity set.
+//-
+//- Truth table: E R D | Q
+//- -------+---
+//- - 1 - | 1
+//- 0 - d | d
+//- - - - | q
+//-
+module \$_DLATCH_NP1_ (E, R, D, Q);
+input E, R, D;
+output reg Q;
+always @* begin
+ if (R == 1)
+ Q <= 1;
+ else if (E == 0)
+ Q <= D;
+end
+endmodule
+
+// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
+//-
+//- $_DLATCH_PN0_ (E, R, D, Q)
+//-
+//- A positive enable D-type latch with negative polarity reset.
+//-
+//- Truth table: E R D | Q
+//- -------+---
+//- - 0 - | 0
+//- 1 - d | d
+//- - - - | q
+//-
+module \$_DLATCH_PN0_ (E, R, D, Q);
+input E, R, D;
+output reg Q;
+always @* begin
+ if (R == 0)
+ Q <= 0;
+ else if (E == 1)
+ Q <= D;
+end
+endmodule
+
+// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
+//-
+//- $_DLATCH_PN1_ (E, R, D, Q)
+//-
+//- A positive enable D-type latch with negative polarity set.
+//-
+//- Truth table: E R D | Q
+//- -------+---
+//- - 0 - | 1
+//- 1 - d | d
+//- - - - | q
+//-
+module \$_DLATCH_PN1_ (E, R, D, Q);
+input E, R, D;
+output reg Q;
+always @* begin
+ if (R == 0)
+ Q <= 1;
+ else if (E == 1)
+ Q <= D;
+end
+endmodule
+
+// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
+//-
+//- $_DLATCH_PP0_ (E, R, D, Q)
+//-
+//- A positive enable D-type latch with positive polarity reset.
+//-
+//- Truth table: E R D | Q
+//- -------+---
+//- - 1 - | 0
+//- 1 - d | d
+//- - - - | q
+//-
+module \$_DLATCH_PP0_ (E, R, D, Q);
+input E, R, D;
+output reg Q;
+always @* begin
+ if (R == 1)
+ Q <= 0;
+ else if (E == 1)
+ Q <= D;
+end
+endmodule
+
+// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
+//-
+//- $_DLATCH_PP1_ (E, R, D, Q)
+//-
+//- A positive enable D-type latch with positive polarity set.
+//-
+//- Truth table: E R D | Q
+//- -------+---
+//- - 1 - | 1
+//- 1 - d | d
+//- - - - | q
+//-
+module \$_DLATCH_PP1_ (E, R, D, Q);
+input E, R, D;
+output reg Q;
+always @* begin
+ if (R == 1)
+ Q <= 1;
+ else if (E == 1)
+ Q <= D;
+end
+endmodule
+
+// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
+//-
//- $_DLATCHSR_NNN_ (E, S, R, D, Q)
//-
//- A negative enable D-type latch with negative polarity set and negative
diff --git a/techlibs/common/simlib.v b/techlibs/common/simlib.v
index 2cdddeabb..2660e6f15 100644
--- a/techlibs/common/simlib.v
+++ b/techlibs/common/simlib.v
@@ -997,6 +997,12 @@ endmodule
// --------------------------------------------------------
+// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
+//-
+//- $div (A, B, Y)
+//-
+//- Division with truncated result (rounded towards 0).
+//-
module \$div (A, B, Y);
parameter A_SIGNED = 0;
@@ -1021,6 +1027,14 @@ endmodule
// --------------------------------------------------------
+// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
+//-
+//- $mod (A, B, Y)
+//-
+//- Modulo/remainder of division with truncated result (rounded towards 0).
+//-
+//- Invariant: $div(A, B) * B + $mod(A, B) == A
+//-
module \$mod (A, B, Y);
parameter A_SIGNED = 0;
@@ -1044,6 +1058,83 @@ endgenerate
endmodule
// --------------------------------------------------------
+
+// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
+//-
+//- $divfloor (A, B, Y)
+//-
+//- Division with floored result (rounded towards negative infinity).
+//-
+module \$divfloor (A, B, Y);
+
+parameter A_SIGNED = 0;
+parameter B_SIGNED = 0;
+parameter A_WIDTH = 0;
+parameter B_WIDTH = 0;
+parameter Y_WIDTH = 0;
+
+input [A_WIDTH-1:0] A;
+input [B_WIDTH-1:0] B;
+output [Y_WIDTH-1:0] Y;
+
+generate
+ if (A_SIGNED && B_SIGNED) begin:BLOCK1
+ localparam WIDTH =
+ A_WIDTH >= B_WIDTH && A_WIDTH >= Y_WIDTH ? A_WIDTH :
+ B_WIDTH >= A_WIDTH && B_WIDTH >= Y_WIDTH ? B_WIDTH : Y_WIDTH;
+ wire [WIDTH:0] A_buf, B_buf, N_buf;
+ assign A_buf = $signed(A);
+ assign B_buf = $signed(B);
+ assign N_buf = (A[A_WIDTH-1] == B[B_WIDTH-1]) || A == 0 ? A_buf : $signed(A_buf - (B[B_WIDTH-1] ? B_buf+1 : B_buf-1));
+ assign Y = $signed(N_buf) / $signed(B_buf);
+ end else begin:BLOCK2
+ assign Y = A / B;
+ end
+endgenerate
+
+endmodule
+
+// --------------------------------------------------------
+
+// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
+//-
+//- $modfloor (A, B, Y)
+//-
+//- Modulo/remainder of division with floored result (rounded towards negative infinity).
+//-
+//- Invariant: $divfloor(A, B) * B + $modfloor(A, B) == A
+//-
+module \$modfloor (A, B, Y);
+
+parameter A_SIGNED = 0;
+parameter B_SIGNED = 0;
+parameter A_WIDTH = 0;
+parameter B_WIDTH = 0;
+parameter Y_WIDTH = 0;
+
+input [A_WIDTH-1:0] A;
+input [B_WIDTH-1:0] B;
+output [Y_WIDTH-1:0] Y;
+
+generate
+ if (A_SIGNED && B_SIGNED) begin:BLOCK1
+ localparam WIDTH = B_WIDTH >= Y_WIDTH ? B_WIDTH : Y_WIDTH;
+ wire [WIDTH-1:0] B_buf, Y_trunc;
+ assign B_buf = $signed(B);
+ assign Y_trunc = $signed(A) % $signed(B);
+ // flooring mod is the same as truncating mod for positive division results (A and B have
+ // the same sign), as well as when there's no remainder.
+ // For all other cases, they behave as `floor - trunc = B`
+ assign Y = (A[A_WIDTH-1] == B[B_WIDTH-1]) || Y_trunc == 0 ? Y_trunc : $signed(B_buf) + $signed(Y_trunc);
+ end else begin:BLOCK2
+ // no difference between truncating and flooring for unsigned
+ assign Y = A % B;
+ end
+endgenerate
+
+endmodule
+
+// --------------------------------------------------------
`ifndef SIMLIB_NOPOW
module \$pow (A, B, Y);
@@ -1731,6 +1822,39 @@ endgenerate
endmodule
+// --------------------------------------------------------
+
+module \$dffsre (CLK, SET, CLR, EN, D, Q);
+
+parameter WIDTH = 0;
+parameter CLK_POLARITY = 1'b1;
+parameter SET_POLARITY = 1'b1;
+parameter CLR_POLARITY = 1'b1;
+parameter EN_POLARITY = 1'b1;
+
+input CLK, EN;
+input [WIDTH-1:0] SET, CLR, D;
+output reg [WIDTH-1:0] Q;
+
+wire pos_clk = CLK == CLK_POLARITY;
+wire [WIDTH-1:0] pos_set = SET_POLARITY ? SET : ~SET;
+wire [WIDTH-1:0] pos_clr = CLR_POLARITY ? CLR : ~CLR;
+
+genvar i;
+generate
+ for (i = 0; i < WIDTH; i = i+1) begin:bitslices
+ always @(posedge pos_set[i], posedge pos_clr[i], posedge pos_clk)
+ if (pos_clr[i])
+ Q[i] <= 0;
+ else if (pos_set[i])
+ Q[i] <= 1;
+ else if (EN == EN_POLARITY)
+ Q[i] <= D[i];
+ end
+endgenerate
+
+endmodule
+
`endif
// --------------------------------------------------------
@@ -1758,6 +1882,107 @@ endmodule
// --------------------------------------------------------
+module \$sdff (CLK, SRST, D, Q);
+
+parameter WIDTH = 0;
+parameter CLK_POLARITY = 1'b1;
+parameter SRST_POLARITY = 1'b1;
+parameter SRST_VALUE = 0;
+
+input CLK, SRST;
+input [WIDTH-1:0] D;
+output reg [WIDTH-1:0] Q;
+wire pos_clk = CLK == CLK_POLARITY;
+wire pos_srst = SRST == SRST_POLARITY;
+
+always @(posedge pos_clk) begin
+ if (pos_srst)
+ Q <= SRST_VALUE;
+ else
+ Q <= D;
+end
+
+endmodule
+
+// --------------------------------------------------------
+
+module \$adffe (CLK, ARST, EN, D, Q);
+
+parameter WIDTH = 0;
+parameter CLK_POLARITY = 1'b1;
+parameter EN_POLARITY = 1'b1;
+parameter ARST_POLARITY = 1'b1;
+parameter ARST_VALUE = 0;
+
+input CLK, ARST, EN;
+input [WIDTH-1:0] D;
+output reg [WIDTH-1:0] Q;
+wire pos_clk = CLK == CLK_POLARITY;
+wire pos_arst = ARST == ARST_POLARITY;
+
+always @(posedge pos_clk, posedge pos_arst) begin
+ if (pos_arst)
+ Q <= ARST_VALUE;
+ else if (EN == EN_POLARITY)
+ Q <= D;
+end
+
+endmodule
+
+// --------------------------------------------------------
+
+module \$sdffe (CLK, SRST, EN, D, Q);
+
+parameter WIDTH = 0;
+parameter CLK_POLARITY = 1'b1;
+parameter EN_POLARITY = 1'b1;
+parameter SRST_POLARITY = 1'b1;
+parameter SRST_VALUE = 0;
+
+input CLK, SRST, EN;
+input [WIDTH-1:0] D;
+output reg [WIDTH-1:0] Q;
+wire pos_clk = CLK == CLK_POLARITY;
+wire pos_srst = SRST == SRST_POLARITY;
+
+always @(posedge pos_clk) begin
+ if (pos_srst)
+ Q <= SRST_VALUE;
+ else if (EN == EN_POLARITY)
+ Q <= D;
+end
+
+endmodule
+
+// --------------------------------------------------------
+
+module \$sdffce (CLK, SRST, EN, D, Q);
+
+parameter WIDTH = 0;
+parameter CLK_POLARITY = 1'b1;
+parameter EN_POLARITY = 1'b1;
+parameter SRST_POLARITY = 1'b1;
+parameter SRST_VALUE = 0;
+
+input CLK, SRST, EN;
+input [WIDTH-1:0] D;
+output reg [WIDTH-1:0] Q;
+wire pos_clk = CLK == CLK_POLARITY;
+wire pos_srst = SRST == SRST_POLARITY;
+
+always @(posedge pos_clk) begin
+ if (EN == EN_POLARITY) begin
+ if (pos_srst)
+ Q <= SRST_VALUE;
+ else
+ Q <= D;
+ end
+end
+
+endmodule
+
+// --------------------------------------------------------
+
module \$dlatch (EN, D, Q);
parameter WIDTH = 0;
@@ -1775,6 +2000,28 @@ end
endmodule
// --------------------------------------------------------
+
+module \$adlatch (EN, ARST, D, Q);
+
+parameter WIDTH = 0;
+parameter EN_POLARITY = 1'b1;
+parameter ARST_POLARITY = 1'b1;
+parameter ARST_VALUE = 0;
+
+input EN, ARST;
+input [WIDTH-1:0] D;
+output reg [WIDTH-1:0] Q;
+
+always @* begin
+ if (ARST == ARST_POLARITY)
+ Q = ARST_VALUE;
+ else if (EN == EN_POLARITY)
+ Q = D;
+end
+
+endmodule
+
+// --------------------------------------------------------
`ifndef SIMLIB_NOSR
module \$dlatchsr (EN, SET, CLR, D, Q);
diff --git a/techlibs/common/synth.cc b/techlibs/common/synth.cc
index d6dffdd7f..b4c65e658 100644
--- a/techlibs/common/synth.cc
+++ b/techlibs/common/synth.cc
@@ -29,7 +29,7 @@ struct SynthPass : public ScriptPass
{
SynthPass() : ScriptPass("synth", "generic synthesis script") { }
- void help() YS_OVERRIDE
+ void help() override
{
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
log("\n");
@@ -91,7 +91,7 @@ struct SynthPass : public ScriptPass
bool autotop, flatten, noalumacc, nofsm, noabc, noshare, flowmap;
int lut;
- void clear_flags() YS_OVERRIDE
+ void clear_flags() override
{
top_module.clear();
fsm_opts.clear();
@@ -108,7 +108,7 @@ struct SynthPass : public ScriptPass
abc = "abc";
}
- void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
+ void execute(std::vector<std::string> args, RTLIL::Design *design) override
{
string run_from, run_to;
clear_flags();
@@ -195,7 +195,7 @@ struct SynthPass : public ScriptPass
log_pop();
}
- void script() YS_OVERRIDE
+ void script() override
{
if (check_label("begin"))
{
diff --git a/techlibs/common/techmap.v b/techlibs/common/techmap.v
index 225cff449..9607302b7 100644
--- a/techlibs/common/techmap.v
+++ b/techlibs/common/techmap.v
@@ -64,7 +64,7 @@ module _90_simplemap_various;
endmodule
(* techmap_simplemap *)
-(* techmap_celltype = "$sr $ff $dff $dffe $adff $dffsr $dlatch" *)
+(* techmap_celltype = "$sr $ff $dff $dffe $adff $adffe $sdff $sdffe $sdffce $dffsr $dffsre $dlatch $adlatch $dlatchsr" *)
module _90_simplemap_registers;
endmodule
@@ -85,8 +85,11 @@ module _90_shift_ops_shr_shl_sshl_sshr (A, B, Y);
localparam shift_left = _TECHMAP_CELLTYPE_ == "$shl" || _TECHMAP_CELLTYPE_ == "$sshl";
localparam sign_extend = A_SIGNED && _TECHMAP_CELLTYPE_ == "$sshr";
+ (* force_downto *)
input [A_WIDTH-1:0] A;
+ (* force_downto *)
input [B_WIDTH-1:0] B;
+ (* force_downto *)
output [Y_WIDTH-1:0] Y;
localparam WIDTH = `MAX(A_WIDTH, Y_WIDTH);
@@ -96,6 +99,7 @@ module _90_shift_ops_shr_shl_sshl_sshr (A, B, Y);
wire [1023:0] _TECHMAP_DO_01_ = "RECURSION; CONSTMAP; opt_muxtree; opt_expr -mux_undef -mux_bool -fine;;;";
integer i;
+ (* force_downto *)
reg [WIDTH-1:0] buffer;
reg overflow;
@@ -125,8 +129,11 @@ module _90_shift_shiftx (A, B, Y);
parameter B_WIDTH = 1;
parameter Y_WIDTH = 1;
+ (* force_downto *)
input [A_WIDTH-1:0] A;
+ (* force_downto *)
input [B_WIDTH-1:0] B;
+ (* force_downto *)
output [Y_WIDTH-1:0] Y;
parameter _TECHMAP_CELLTYPE_ = "";
@@ -173,6 +180,7 @@ module _90_shift_shiftx (A, B, Y);
wire [1023:0] _TECHMAP_DO_01_ = "CONSTMAP; opt_muxtree; opt_expr -mux_undef -mux_bool -fine;;;";
integer i;
+ (* force_downto *)
reg [WIDTH-1:0] buffer;
reg overflow;
@@ -216,9 +224,12 @@ endmodule
module _90_fa (A, B, C, X, Y);
parameter WIDTH = 1;
+ (* force_downto *)
input [WIDTH-1:0] A, B, C;
+ (* force_downto *)
output [WIDTH-1:0] X, Y;
+ (* force_downto *)
wire [WIDTH-1:0] t1, t2, t3;
assign t1 = A ^ B, t2 = A & B, t3 = C & t1;
@@ -229,12 +240,15 @@ endmodule
module _90_lcu (P, G, CI, CO);
parameter WIDTH = 2;
+ (* force_downto *)
input [WIDTH-1:0] P, G;
input CI;
+ (* force_downto *)
output [WIDTH-1:0] CO;
integer i, j;
+ (* force_downto *)
reg [WIDTH-1:0] p, g;
wire [1023:0] _TECHMAP_DO_ = "proc; opt -fast";
@@ -278,38 +292,26 @@ module _90_alu (A, B, CI, BI, X, Y, CO);
parameter B_WIDTH = 1;
parameter Y_WIDTH = 1;
+ (* force_downto *)
input [A_WIDTH-1:0] A;
+ (* force_downto *)
input [B_WIDTH-1:0] B;
+ (* force_downto *)
output [Y_WIDTH-1:0] X, Y;
input CI, BI;
+ (* force_downto *)
output [Y_WIDTH-1:0] CO;
- wire [Y_WIDTH-1:0] AA, BB;
+ (* force_downto *)
+ wire [Y_WIDTH-1:0] AA = A_buf;
+ (* force_downto *)
wire [Y_WIDTH-1:0] BB = BI ? ~B_buf : B_buf;
- if (A_WIDTH == 0) begin
- wire [Y_WIDTH-1:0] B_buf;
- \$pos #(.A_SIGNED(B_SIGNED), .A_WIDTH(B_WIDTH), .Y_WIDTH(Y_WIDTH)) B_conv (.A(B), .Y(B_buf));
-
- assign AA = {Y_WIDTH{1'b0}};
- assign BB = BI ? ~B_buf : B_buf;
- end
- else if (B_WIDTH == 0) begin
- wire [Y_WIDTH-1:0] A_buf;
- \$pos #(.A_SIGNED(A_SIGNED), .A_WIDTH(A_WIDTH), .Y_WIDTH(Y_WIDTH)) A_conv (.A(A), .Y(A_buf));
-
- assign AA = A_buf;
- assign BB = {Y_WIDTH{BI ? 1'b0 : 1'b1}};
- end
- else begin
- wire [Y_WIDTH-1:0] A_buf, B_buf;
- \$pos #(.A_SIGNED(A_SIGNED), .A_WIDTH(A_WIDTH), .Y_WIDTH(Y_WIDTH)) A_conv (.A(A), .Y(A_buf));
- \$pos #(.A_SIGNED(B_SIGNED), .A_WIDTH(B_WIDTH), .Y_WIDTH(Y_WIDTH)) B_conv (.A(B), .Y(B_buf));
-
- assign AA = A_buf;
- assign BB = BI ? ~B_buf : B_buf;
- end
+ (* force_downto *)
+ wire [Y_WIDTH-1:0] A_buf, B_buf;
+ \$pos #(.A_SIGNED(A_SIGNED), .A_WIDTH(A_WIDTH), .Y_WIDTH(Y_WIDTH)) A_conv (.A(A), .Y(A_buf));
+ \$pos #(.A_SIGNED(B_SIGNED), .A_WIDTH(B_WIDTH), .Y_WIDTH(Y_WIDTH)) B_conv (.A(B), .Y(B_buf));
\$lcu #(.WIDTH(Y_WIDTH)) lcu (.P(X), .G(AA & BB), .CI(CI), .CO(CO));
@@ -335,15 +337,19 @@ endmodule
module \$__div_mod_u (A, B, Y, R);
parameter WIDTH = 1;
+ (* force_downto *)
input [WIDTH-1:0] A, B;
+ (* force_downto *)
output [WIDTH-1:0] Y, R;
+ (* force_downto *)
wire [WIDTH*WIDTH-1:0] chaindata;
assign R = chaindata[WIDTH*WIDTH-1:WIDTH*(WIDTH-1)];
genvar i;
generate begin
for (i = 0; i < WIDTH; i=i+1) begin:stage
+ (* force_downto *)
wire [WIDTH-1:0] stage_in;
if (i == 0) begin:cp
@@ -358,7 +364,8 @@ module \$__div_mod_u (A, B, Y, R);
end endgenerate
endmodule
-module \$__div_mod (A, B, Y, R);
+// truncating signed division/modulo
+module \$__div_mod_trunc (A, B, Y, R);
parameter A_SIGNED = 0;
parameter B_SIGNED = 0;
parameter A_WIDTH = 1;
@@ -369,14 +376,19 @@ module \$__div_mod (A, B, Y, R);
A_WIDTH >= B_WIDTH && A_WIDTH >= Y_WIDTH ? A_WIDTH :
B_WIDTH >= A_WIDTH && B_WIDTH >= Y_WIDTH ? B_WIDTH : Y_WIDTH;
+ (* force_downto *)
input [A_WIDTH-1:0] A;
+ (* force_downto *)
input [B_WIDTH-1:0] B;
+ (* force_downto *)
output [Y_WIDTH-1:0] Y, R;
+ (* force_downto *)
wire [WIDTH-1:0] A_buf, B_buf;
\$pos #(.A_SIGNED(A_SIGNED), .A_WIDTH(A_WIDTH), .Y_WIDTH(WIDTH)) A_conv (.A(A), .Y(A_buf));
\$pos #(.A_SIGNED(B_SIGNED), .A_WIDTH(B_WIDTH), .Y_WIDTH(WIDTH)) B_conv (.A(B), .Y(B_buf));
+ (* force_downto *)
wire [WIDTH-1:0] A_buf_u, B_buf_u, Y_u, R_u;
assign A_buf_u = A_SIGNED && A_buf[WIDTH-1] ? -A_buf : A_buf;
assign B_buf_u = B_SIGNED && B_buf[WIDTH-1] ? -B_buf : B_buf;
@@ -402,11 +414,14 @@ module _90_div (A, B, Y);
parameter B_WIDTH = 1;
parameter Y_WIDTH = 1;
+ (* force_downto *)
input [A_WIDTH-1:0] A;
+ (* force_downto *)
input [B_WIDTH-1:0] B;
+ (* force_downto *)
output [Y_WIDTH-1:0] Y;
- \$__div_mod #(
+ \$__div_mod_trunc #(
.A_SIGNED(A_SIGNED),
.B_SIGNED(B_SIGNED),
.A_WIDTH(A_WIDTH),
@@ -427,11 +442,114 @@ module _90_mod (A, B, Y);
parameter B_WIDTH = 1;
parameter Y_WIDTH = 1;
+ (* force_downto *)
+ input [A_WIDTH-1:0] A;
+ (* force_downto *)
+ input [B_WIDTH-1:0] B;
+ (* force_downto *)
+ output [Y_WIDTH-1:0] Y;
+
+ \$__div_mod_trunc #(
+ .A_SIGNED(A_SIGNED),
+ .B_SIGNED(B_SIGNED),
+ .A_WIDTH(A_WIDTH),
+ .B_WIDTH(B_WIDTH),
+ .Y_WIDTH(Y_WIDTH)
+ ) div_mod (
+ .A(A),
+ .B(B),
+ .R(Y)
+ );
+endmodule
+
+// flooring signed division/modulo
+module \$__div_mod_floor (A, B, Y, R);
+ parameter A_SIGNED = 0;
+ parameter B_SIGNED = 0;
+ parameter A_WIDTH = 1;
+ parameter B_WIDTH = 1;
+ parameter Y_WIDTH = 1;
+
+ localparam WIDTH =
+ A_WIDTH >= B_WIDTH && A_WIDTH >= Y_WIDTH ? A_WIDTH :
+ B_WIDTH >= A_WIDTH && B_WIDTH >= Y_WIDTH ? B_WIDTH : Y_WIDTH;
+
+ input [A_WIDTH-1:0] A;
+ input [B_WIDTH-1:0] B;
+ output [Y_WIDTH-1:0] Y, R;
+
+ wire [WIDTH-1:0] A_buf, B_buf;
+ \$pos #(.A_SIGNED(A_SIGNED), .A_WIDTH(A_WIDTH), .Y_WIDTH(WIDTH)) A_conv (.A(A), .Y(A_buf));
+ \$pos #(.A_SIGNED(B_SIGNED), .A_WIDTH(B_WIDTH), .Y_WIDTH(WIDTH)) B_conv (.A(B), .Y(B_buf));
+
+ wire [WIDTH-1:0] A_buf_u, B_buf_u, Y_u, R_u, R_s;
+ assign A_buf_u = A_SIGNED && A_buf[WIDTH-1] ? -A_buf : A_buf;
+ assign B_buf_u = B_SIGNED && B_buf[WIDTH-1] ? -B_buf : B_buf;
+
+ \$__div_mod_u #(
+ .WIDTH(WIDTH)
+ ) div_mod_u (
+ .A(A_buf_u),
+ .B(B_buf_u),
+ .Y(Y_u),
+ .R(R_u)
+ );
+
+ // For negative results, if there was a remainder, subtract one to turn
+ // the round towards 0 into a round towards -inf
+ assign Y = A_SIGNED && B_SIGNED && (A_buf[WIDTH-1] != B_buf[WIDTH-1]) ? (R_u == 0 ? -Y_u : -Y_u-1) : Y_u;
+
+ // truncating modulo
+ assign R_s = A_SIGNED && B_SIGNED && A_buf[WIDTH-1] ? -R_u : R_u;
+ // Flooring modulo differs from truncating modulo only if it is nonzero and
+ // A and B have different signs - then `floor - trunc = B`
+ assign R = (R_s != 0) && A_SIGNED && B_SIGNED && (A_buf[WIDTH-1] != B_buf[WIDTH-1]) ? $signed(B_buf) + $signed(R_s) : R_s;
+endmodule
+
+(* techmap_celltype = "$divfloor" *)
+module _90_divfloor (A, B, Y);
+ parameter A_SIGNED = 0;
+ parameter B_SIGNED = 0;
+ parameter A_WIDTH = 1;
+ parameter B_WIDTH = 1;
+ parameter Y_WIDTH = 1;
+
+ (* force_downto *)
+ input [A_WIDTH-1:0] A;
+ (* force_downto *)
+ input [B_WIDTH-1:0] B;
+ (* force_downto *)
+ output [Y_WIDTH-1:0] Y;
+
+ \$__div_mod_floor #(
+ .A_SIGNED(A_SIGNED),
+ .B_SIGNED(B_SIGNED),
+ .A_WIDTH(A_WIDTH),
+ .B_WIDTH(B_WIDTH),
+ .Y_WIDTH(Y_WIDTH)
+ ) div_mod (
+ .A(A),
+ .B(B),
+ .Y(Y)
+ );
+endmodule
+
+(* techmap_celltype = "$modfloor" *)
+module _90_modfloor (A, B, Y);
+ parameter A_SIGNED = 0;
+ parameter B_SIGNED = 0;
+ parameter A_WIDTH = 1;
+ parameter B_WIDTH = 1;
+ parameter Y_WIDTH = 1;
+
+ (* force_downto *)
input [A_WIDTH-1:0] A;
+ (* force_downto *)
input [B_WIDTH-1:0] B;
+ (* force_downto *)
output [Y_WIDTH-1:0] Y;
- \$__div_mod #(
+ \$__div_mod_floor #(
.A_SIGNED(A_SIGNED),
.B_SIGNED(B_SIGNED),
.A_WIDTH(A_WIDTH),
@@ -457,8 +575,11 @@ module _90_pow (A, B, Y);
parameter B_WIDTH = 1;
parameter Y_WIDTH = 1;
+ (* force_downto *)
input [A_WIDTH-1:0] A;
+ (* force_downto *)
input [B_WIDTH-1:0] B;
+ (* force_downto *)
output [Y_WIDTH-1:0] Y;
wire _TECHMAP_FAIL_ = 1;
@@ -474,20 +595,27 @@ module _90_pmux (A, B, S, Y);
parameter WIDTH = 1;
parameter S_WIDTH = 1;
+ (* force_downto *)
input [WIDTH-1:0] A;
+ (* force_downto *)
input [WIDTH*S_WIDTH-1:0] B;
+ (* force_downto *)
input [S_WIDTH-1:0] S;
+ (* force_downto *)
output [WIDTH-1:0] Y;
+ (* force_downto *)
wire [WIDTH-1:0] Y_B;
genvar i, j;
generate
+ (* force_downto *)
wire [WIDTH*S_WIDTH-1:0] B_AND_S;
for (i = 0; i < S_WIDTH; i = i + 1) begin:B_AND
assign B_AND_S[WIDTH*(i+1)-1:WIDTH*i] = B[WIDTH*(i+1)-1:WIDTH*i] & {WIDTH{S[i]}};
end:B_AND
for (i = 0; i < WIDTH; i = i + 1) begin:B_OR
+ (* force_downto *)
wire [S_WIDTH-1:0] B_AND_BITS;
for (j = 0; j < S_WIDTH; j = j + 1) begin:B_AND_BITS_COLLECT
assign B_AND_BITS[j] = B_AND_S[WIDTH*j+i];
diff --git a/techlibs/coolrunner2/cells_counter_map.v b/techlibs/coolrunner2/cells_counter_map.v
index b474fa522..f9c44c80f 100644
--- a/techlibs/coolrunner2/cells_counter_map.v
+++ b/techlibs/coolrunner2/cells_counter_map.v
@@ -3,6 +3,7 @@ module \$__COUNT_ (CE, CLK, OUT, POUT, RST, UP);
input wire CE;
input wire CLK;
output wire OUT;
+ (* force_downto *)
output wire[WIDTH-1:0] POUT;
input wire RST;
input wire UP;
diff --git a/techlibs/coolrunner2/coolrunner2_fixup.cc b/techlibs/coolrunner2/coolrunner2_fixup.cc
index 8bbff9ba5..50710e2bd 100644
--- a/techlibs/coolrunner2/coolrunner2_fixup.cc
+++ b/techlibs/coolrunner2/coolrunner2_fixup.cc
@@ -112,7 +112,7 @@ RTLIL::Wire *makeptermbuffer(RTLIL::Module *module, SigBit inwire)
struct Coolrunner2FixupPass : public Pass {
Coolrunner2FixupPass() : Pass("coolrunner2_fixup", "insert necessary buffer cells for CoolRunner-II architecture") { }
- void help() YS_OVERRIDE
+ void help() override
{
log("\n");
log(" coolrunner2_fixup [options] [selection]\n");
@@ -120,7 +120,7 @@ struct Coolrunner2FixupPass : public Pass {
log("Insert necessary buffer cells for CoolRunner-II architecture.\n");
log("\n");
}
- void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
+ void execute(std::vector<std::string> args, RTLIL::Design *design) override
{
log_header(design, "Executing COOLRUNNER2_FIXUP pass (insert necessary buffer cells for CoolRunner-II architecture).\n");
extra_args(args, 1, design);
diff --git a/techlibs/coolrunner2/coolrunner2_sop.cc b/techlibs/coolrunner2/coolrunner2_sop.cc
index 045c73978..17e0d8432 100644
--- a/techlibs/coolrunner2/coolrunner2_sop.cc
+++ b/techlibs/coolrunner2/coolrunner2_sop.cc
@@ -25,7 +25,7 @@ PRIVATE_NAMESPACE_BEGIN
struct Coolrunner2SopPass : public Pass {
Coolrunner2SopPass() : Pass("coolrunner2_sop", "break $sop cells into ANDTERM/ORTERM cells") { }
- void help() YS_OVERRIDE
+ void help() override
{
log("\n");
log(" coolrunner2_sop [options] [selection]\n");
@@ -33,7 +33,7 @@ struct Coolrunner2SopPass : public Pass {
log("Break $sop cells into ANDTERM/ORTERM cells.\n");
log("\n");
}
- void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
+ void execute(std::vector<std::string> args, RTLIL::Design *design) override
{
log_header(design, "Executing COOLRUNNER2_SOP pass (break $sop cells into ANDTERM/ORTERM cells).\n");
extra_args(args, 1, design);
diff --git a/techlibs/coolrunner2/synth_coolrunner2.cc b/techlibs/coolrunner2/synth_coolrunner2.cc
index d5eeaf547..47102fbb1 100644
--- a/techlibs/coolrunner2/synth_coolrunner2.cc
+++ b/techlibs/coolrunner2/synth_coolrunner2.cc
@@ -29,7 +29,7 @@ struct SynthCoolrunner2Pass : public ScriptPass
{
SynthCoolrunner2Pass() : ScriptPass("synth_coolrunner2", "synthesis for Xilinx Coolrunner-II CPLDs") { }
- void help() YS_OVERRIDE
+ void help() override
{
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
log("\n");
@@ -66,7 +66,7 @@ struct SynthCoolrunner2Pass : public ScriptPass
string top_opt, json_file;
bool flatten, retime;
- void clear_flags() YS_OVERRIDE
+ void clear_flags() override
{
top_opt = "-auto-top";
json_file = "";
@@ -74,7 +74,7 @@ struct SynthCoolrunner2Pass : public ScriptPass
retime = false;
}
- void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
+ void execute(std::vector<std::string> args, RTLIL::Design *design) override
{
string run_from, run_to;
clear_flags();
@@ -121,7 +121,7 @@ struct SynthCoolrunner2Pass : public ScriptPass
log_pop();
}
- void script() YS_OVERRIDE
+ void script() override
{
if (check_label("begin"))
{
diff --git a/techlibs/easic/synth_easic.cc b/techlibs/easic/synth_easic.cc
index b4a3a1ac9..897bc1c40 100644
--- a/techlibs/easic/synth_easic.cc
+++ b/techlibs/easic/synth_easic.cc
@@ -29,7 +29,7 @@ struct SynthEasicPass : public ScriptPass
{
SynthEasicPass() : ScriptPass("synth_easic", "synthesis for eASIC platform") { }
- void help() YS_OVERRIDE
+ void help() override
{
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
log("\n");
@@ -67,7 +67,7 @@ struct SynthEasicPass : public ScriptPass
string top_opt, vlog_file, etools_path;
bool flatten, retime;
- void clear_flags() YS_OVERRIDE
+ void clear_flags() override
{
top_opt = "-auto-top";
vlog_file = "";
@@ -76,7 +76,7 @@ struct SynthEasicPass : public ScriptPass
retime = false;
}
- void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
+ void execute(std::vector<std::string> args, RTLIL::Design *design) override
{
string run_from, run_to;
clear_flags();
@@ -127,7 +127,7 @@ struct SynthEasicPass : public ScriptPass
log_pop();
}
- void script() YS_OVERRIDE
+ void script() override
{
string phys_clk_lib = stringf("%s/data_ruby28/design_libs/logical/timing/gp/n3x_phys_clk_0v893ff125c.lib", etools_path.c_str());
string logic_lut_lib = stringf("%s/data_ruby28/design_libs/logical/timing/gp/n3x_logic_lut_0v893ff125c.lib", etools_path.c_str());
diff --git a/techlibs/ecp5/Makefile.inc b/techlibs/ecp5/Makefile.inc
index 217151e96..9d564c78c 100644
--- a/techlibs/ecp5/Makefile.inc
+++ b/techlibs/ecp5/Makefile.inc
@@ -24,10 +24,6 @@ $(eval $(call add_share_file,share/ecp5,techlibs/ecp5/arith_map.v))
$(eval $(call add_share_file,share/ecp5,techlibs/ecp5/latches_map.v))
$(eval $(call add_share_file,share/ecp5,techlibs/ecp5/dsp_map.v))
-$(eval $(call add_share_file,share/ecp5,techlibs/ecp5/abc9_map.v))
-$(eval $(call add_share_file,share/ecp5,techlibs/ecp5/abc9_unmap.v))
-$(eval $(call add_share_file,share/ecp5,techlibs/ecp5/abc9_model.v))
-
EXTRA_OBJS += techlibs/ecp5/brams_init.mk techlibs/ecp5/brams_connect.mk
.SECONDARY: techlibs/ecp5/brams_init.mk techlibs/ecp5/brams_connect.mk
diff --git a/techlibs/ecp5/abc9_map.v b/techlibs/ecp5/abc9_map.v
deleted file mode 100644
index 113a35b91..000000000
--- a/techlibs/ecp5/abc9_map.v
+++ /dev/null
@@ -1,27 +0,0 @@
-// ---------------------------------------
-
-// Attach a (combinatorial) black-box onto the output
-// of this LUTRAM primitive to capture its
-// asynchronous read behaviour
-module TRELLIS_DPR16X4 (
- (* techmap_autopurge *) input [3:0] DI,
- (* techmap_autopurge *) input [3:0] WAD,
- (* techmap_autopurge *) input WRE,
- (* techmap_autopurge *) input WCK,
- (* techmap_autopurge *) input [3:0] RAD,
- output [3:0] DO
-);
- parameter WCKMUX = "WCK";
- parameter WREMUX = "WRE";
- parameter [63:0] INITVAL = 64'h0000000000000000;
- wire [3:0] $DO;
-
- TRELLIS_DPR16X4 #(
- .WCKMUX(WCKMUX), .WREMUX(WREMUX), .INITVAL(INITVAL)
- ) _TECHMAP_REPLACE_ (
- .DI(DI), .WAD(WAD), .WRE(WRE), .WCK(WCK),
- .RAD(RAD), .DO($DO)
- );
-
- $__ABC9_DPR16X4_COMB do (.$DO($DO), .RAD(RAD), .DO(DO));
-endmodule
diff --git a/techlibs/ecp5/abc9_model.v b/techlibs/ecp5/abc9_model.v
deleted file mode 100644
index b7ecd7358..000000000
--- a/techlibs/ecp5/abc9_model.v
+++ /dev/null
@@ -1,12 +0,0 @@
-// ---------------------------------------
-
-(* abc9_box *)
-module \$__ABC9_DPR16X4_COMB (input [3:0] $DO, RAD, output [3:0] DO);
- specify
- ($DO => DO) = 0;
- (RAD[0] *> DO) = 141;
- (RAD[1] *> DO) = 379;
- (RAD[2] *> DO) = 275;
- (RAD[3] *> DO) = 379;
- endspecify
-endmodule
diff --git a/techlibs/ecp5/abc9_unmap.v b/techlibs/ecp5/abc9_unmap.v
deleted file mode 100644
index cbdffdaf1..000000000
--- a/techlibs/ecp5/abc9_unmap.v
+++ /dev/null
@@ -1,5 +0,0 @@
-// ---------------------------------------
-
-module \$__ABC9_DPR16X4_COMB (input [3:0] $DO, RAD, output [3:0] DO);
- assign DO = $DO;
-endmodule
diff --git a/techlibs/ecp5/arith_map.v b/techlibs/ecp5/arith_map.v
index 17bde0497..ffd42469c 100644
--- a/techlibs/ecp5/arith_map.v
+++ b/techlibs/ecp5/arith_map.v
@@ -26,15 +26,20 @@ module _80_ecp5_alu (A, B, CI, BI, X, Y, CO);
parameter B_WIDTH = 1;
parameter Y_WIDTH = 1;
+ (* force_downto *)
input [A_WIDTH-1:0] A;
+ (* force_downto *)
input [B_WIDTH-1:0] B;
+ (* force_downto *)
output [Y_WIDTH-1:0] X, Y;
input CI, BI;
+ (* force_downto *)
output [Y_WIDTH-1:0] CO;
wire _TECHMAP_FAIL_ = Y_WIDTH <= 4;
+ (* force_downto *)
wire [Y_WIDTH-1:0] A_buf, B_buf;
\$pos #(.A_SIGNED(A_SIGNED), .A_WIDTH(A_WIDTH), .Y_WIDTH(Y_WIDTH)) A_conv (.A(A), .Y(A_buf));
\$pos #(.A_SIGNED(B_SIGNED), .A_WIDTH(B_WIDTH), .Y_WIDTH(Y_WIDTH)) B_conv (.A(B), .Y(B_buf));
@@ -48,10 +53,15 @@ module _80_ecp5_alu (A, B, CI, BI, X, Y, CO);
localparam Y_WIDTH2 = round_up2(Y_WIDTH);
+ (* force_downto *)
wire [Y_WIDTH2-1:0] AA = A_buf;
+ (* force_downto *)
wire [Y_WIDTH2-1:0] BB = BI ? ~B_buf : B_buf;
+ (* force_downto *)
wire [Y_WIDTH2-1:0] BX = B_buf;
+ (* force_downto *)
wire [Y_WIDTH2-1:0] C = {CO, CI};
+ (* force_downto *)
wire [Y_WIDTH2-1:0] FCO, Y1;
genvar i;
diff --git a/techlibs/ecp5/cells_map.v b/techlibs/ecp5/cells_map.v
index c031703a9..80f497cc3 100644
--- a/techlibs/ecp5/cells_map.v
+++ b/techlibs/ecp5/cells_map.v
@@ -17,35 +17,35 @@ module \$_DFF_NP1_ (input D, C, R, output Q); TRELLIS_FF #(.GSR("AUTO"), .CEMUX
module \$_DFF_PP0_ (input D, C, R, output Q); TRELLIS_FF #(.GSR("AUTO"), .CEMUX("1"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("ASYNC")) _TECHMAP_REPLACE_ (.CLK(C), .LSR(R), .DI(D), .Q(Q)); endmodule
module \$_DFF_PP1_ (input D, C, R, output Q); TRELLIS_FF #(.GSR("AUTO"), .CEMUX("1"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("SET"), .SRMODE("ASYNC")) _TECHMAP_REPLACE_ (.CLK(C), .LSR(R), .DI(D), .Q(Q)); endmodule
-module \$__DFFS_NN0_ (input D, C, R, output Q); TRELLIS_FF #(.GSR("AUTO"), .CEMUX("1"), .CLKMUX("INV"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("LSR_OVER_CE")) _TECHMAP_REPLACE_ (.CLK(C), .LSR(!R), .DI(D), .Q(Q)); endmodule
-module \$__DFFS_NN1_ (input D, C, R, output Q); TRELLIS_FF #(.GSR("AUTO"), .CEMUX("1"), .CLKMUX("INV"), .LSRMUX("LSR"), .REGSET("SET"), .SRMODE("LSR_OVER_CE")) _TECHMAP_REPLACE_ (.CLK(C), .LSR(!R), .DI(D), .Q(Q)); endmodule
-module \$__DFFS_PN0_ (input D, C, R, output Q); TRELLIS_FF #(.GSR("AUTO"), .CEMUX("1"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("LSR_OVER_CE")) _TECHMAP_REPLACE_ (.CLK(C), .LSR(!R), .DI(D), .Q(Q)); endmodule
-module \$__DFFS_PN1_ (input D, C, R, output Q); TRELLIS_FF #(.GSR("AUTO"), .CEMUX("1"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("SET"), .SRMODE("LSR_OVER_CE")) _TECHMAP_REPLACE_ (.CLK(C), .LSR(!R), .DI(D), .Q(Q)); endmodule
-
-module \$__DFFS_NP0_ (input D, C, R, output Q); TRELLIS_FF #(.GSR("AUTO"), .CEMUX("1"), .CLKMUX("INV"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("LSR_OVER_CE")) _TECHMAP_REPLACE_ (.CLK(C), .LSR(R), .DI(D), .Q(Q)); endmodule
-module \$__DFFS_NP1_ (input D, C, R, output Q); TRELLIS_FF #(.GSR("AUTO"), .CEMUX("1"), .CLKMUX("INV"), .LSRMUX("LSR"), .REGSET("SET"), .SRMODE("LSR_OVER_CE")) _TECHMAP_REPLACE_ (.CLK(C), .LSR(R), .DI(D), .Q(Q)); endmodule
-module \$__DFFS_PP0_ (input D, C, R, output Q); TRELLIS_FF #(.GSR("AUTO"), .CEMUX("1"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("LSR_OVER_CE")) _TECHMAP_REPLACE_ (.CLK(C), .LSR(R), .DI(D), .Q(Q)); endmodule
-module \$__DFFS_PP1_ (input D, C, R, output Q); TRELLIS_FF #(.GSR("AUTO"), .CEMUX("1"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("SET"), .SRMODE("LSR_OVER_CE")) _TECHMAP_REPLACE_ (.CLK(C), .LSR(R), .DI(D), .Q(Q)); endmodule
-
-module \$__DFFE_NN0 (input D, C, E, R, output Q); TRELLIS_FF #(.GSR("AUTO"), .CEMUX("CE"), .CLKMUX("INV"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("ASYNC")) _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(!R), .DI(D), .Q(Q)); endmodule
-module \$__DFFE_NN1 (input D, C, E, R, output Q); TRELLIS_FF #(.GSR("AUTO"), .CEMUX("CE"), .CLKMUX("INV"), .LSRMUX("LSR"), .REGSET("SET"), .SRMODE("ASYNC")) _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(!R), .DI(D), .Q(Q)); endmodule
-module \$__DFFE_PN0 (input D, C, E, R, output Q); TRELLIS_FF #(.GSR("AUTO"), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("ASYNC")) _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(!R), .DI(D), .Q(Q)); endmodule
-module \$__DFFE_PN1 (input D, C, E, R, output Q); TRELLIS_FF #(.GSR("AUTO"), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("SET"), .SRMODE("ASYNC")) _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(!R), .DI(D), .Q(Q)); endmodule
-
-module \$__DFFE_NP0 (input D, C, E, R, output Q); TRELLIS_FF #(.GSR("AUTO"), .CEMUX("CE"), .CLKMUX("INV"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("ASYNC")) _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(R), .DI(D), .Q(Q)); endmodule
-module \$__DFFE_NP1 (input D, C, E, R, output Q); TRELLIS_FF #(.GSR("AUTO"), .CEMUX("CE"), .CLKMUX("INV"), .LSRMUX("LSR"), .REGSET("SET"), .SRMODE("ASYNC")) _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(R), .DI(D), .Q(Q)); endmodule
-module \$__DFFE_PP0 (input D, C, E, R, output Q); TRELLIS_FF #(.GSR("AUTO"), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("ASYNC")) _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(R), .DI(D), .Q(Q)); endmodule
-module \$__DFFE_PP1 (input D, C, E, R, output Q); TRELLIS_FF #(.GSR("AUTO"), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("SET"), .SRMODE("ASYNC")) _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(R), .DI(D), .Q(Q)); endmodule
-
-module \$__DFFSE_NN0 (input D, C, E, R, output Q); TRELLIS_FF #(.GSR("AUTO"), .CEMUX("CE"), .CLKMUX("INV"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("LSR_OVER_CE")) _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(!R), .DI(D), .Q(Q)); endmodule
-module \$__DFFSE_NN1 (input D, C, E, R, output Q); TRELLIS_FF #(.GSR("AUTO"), .CEMUX("CE"), .CLKMUX("INV"), .LSRMUX("LSR"), .REGSET("SET"), .SRMODE("LSR_OVER_CE")) _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(!R), .DI(D), .Q(Q)); endmodule
-module \$__DFFSE_PN0 (input D, C, E, R, output Q); TRELLIS_FF #(.GSR("AUTO"), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("LSR_OVER_CE")) _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(!R), .DI(D), .Q(Q)); endmodule
-module \$__DFFSE_PN1 (input D, C, E, R, output Q); TRELLIS_FF #(.GSR("AUTO"), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("SET"), .SRMODE("LSR_OVER_CE")) _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(!R), .DI(D), .Q(Q)); endmodule
-
-module \$__DFFSE_NP0 (input D, C, E, R, output Q); TRELLIS_FF #(.GSR("AUTO"), .CEMUX("CE"), .CLKMUX("INV"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("LSR_OVER_CE")) _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(R), .DI(D), .Q(Q)); endmodule
-module \$__DFFSE_NP1 (input D, C, E, R, output Q); TRELLIS_FF #(.GSR("AUTO"), .CEMUX("CE"), .CLKMUX("INV"), .LSRMUX("LSR"), .REGSET("SET"), .SRMODE("LSR_OVER_CE")) _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(R), .DI(D), .Q(Q)); endmodule
-module \$__DFFSE_PP0 (input D, C, E, R, output Q); TRELLIS_FF #(.GSR("AUTO"), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("LSR_OVER_CE")) _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(R), .DI(D), .Q(Q)); endmodule
-module \$__DFFSE_PP1 (input D, C, E, R, output Q); TRELLIS_FF #(.GSR("AUTO"), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("SET"), .SRMODE("LSR_OVER_CE")) _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(R), .DI(D), .Q(Q)); endmodule
+module \$_SDFF_NN0_ (input D, C, R, output Q); TRELLIS_FF #(.GSR("AUTO"), .CEMUX("1"), .CLKMUX("INV"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("LSR_OVER_CE")) _TECHMAP_REPLACE_ (.CLK(C), .LSR(!R), .DI(D), .Q(Q)); endmodule
+module \$_SDFF_NN1_ (input D, C, R, output Q); TRELLIS_FF #(.GSR("AUTO"), .CEMUX("1"), .CLKMUX("INV"), .LSRMUX("LSR"), .REGSET("SET"), .SRMODE("LSR_OVER_CE")) _TECHMAP_REPLACE_ (.CLK(C), .LSR(!R), .DI(D), .Q(Q)); endmodule
+module \$_SDFF_PN0_ (input D, C, R, output Q); TRELLIS_FF #(.GSR("AUTO"), .CEMUX("1"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("LSR_OVER_CE")) _TECHMAP_REPLACE_ (.CLK(C), .LSR(!R), .DI(D), .Q(Q)); endmodule
+module \$_SDFF_PN1_ (input D, C, R, output Q); TRELLIS_FF #(.GSR("AUTO"), .CEMUX("1"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("SET"), .SRMODE("LSR_OVER_CE")) _TECHMAP_REPLACE_ (.CLK(C), .LSR(!R), .DI(D), .Q(Q)); endmodule
+
+module \$_SDFF_NP0_ (input D, C, R, output Q); TRELLIS_FF #(.GSR("AUTO"), .CEMUX("1"), .CLKMUX("INV"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("LSR_OVER_CE")) _TECHMAP_REPLACE_ (.CLK(C), .LSR(R), .DI(D), .Q(Q)); endmodule
+module \$_SDFF_NP1_ (input D, C, R, output Q); TRELLIS_FF #(.GSR("AUTO"), .CEMUX("1"), .CLKMUX("INV"), .LSRMUX("LSR"), .REGSET("SET"), .SRMODE("LSR_OVER_CE")) _TECHMAP_REPLACE_ (.CLK(C), .LSR(R), .DI(D), .Q(Q)); endmodule
+module \$_SDFF_PP0_ (input D, C, R, output Q); TRELLIS_FF #(.GSR("AUTO"), .CEMUX("1"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("LSR_OVER_CE")) _TECHMAP_REPLACE_ (.CLK(C), .LSR(R), .DI(D), .Q(Q)); endmodule
+module \$_SDFF_PP1_ (input D, C, R, output Q); TRELLIS_FF #(.GSR("AUTO"), .CEMUX("1"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("SET"), .SRMODE("LSR_OVER_CE")) _TECHMAP_REPLACE_ (.CLK(C), .LSR(R), .DI(D), .Q(Q)); endmodule
+
+module \$_DFFE_NN0P_ (input D, C, E, R, output Q); TRELLIS_FF #(.GSR("AUTO"), .CEMUX("CE"), .CLKMUX("INV"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("ASYNC")) _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(!R), .DI(D), .Q(Q)); endmodule
+module \$_DFFE_NN1P_ (input D, C, E, R, output Q); TRELLIS_FF #(.GSR("AUTO"), .CEMUX("CE"), .CLKMUX("INV"), .LSRMUX("LSR"), .REGSET("SET"), .SRMODE("ASYNC")) _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(!R), .DI(D), .Q(Q)); endmodule
+module \$_DFFE_PN0P_ (input D, C, E, R, output Q); TRELLIS_FF #(.GSR("AUTO"), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("ASYNC")) _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(!R), .DI(D), .Q(Q)); endmodule
+module \$_DFFE_PN1P_ (input D, C, E, R, output Q); TRELLIS_FF #(.GSR("AUTO"), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("SET"), .SRMODE("ASYNC")) _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(!R), .DI(D), .Q(Q)); endmodule
+
+module \$_DFFE_NP0P_ (input D, C, E, R, output Q); TRELLIS_FF #(.GSR("AUTO"), .CEMUX("CE"), .CLKMUX("INV"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("ASYNC")) _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(R), .DI(D), .Q(Q)); endmodule
+module \$_DFFE_NP1P_ (input D, C, E, R, output Q); TRELLIS_FF #(.GSR("AUTO"), .CEMUX("CE"), .CLKMUX("INV"), .LSRMUX("LSR"), .REGSET("SET"), .SRMODE("ASYNC")) _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(R), .DI(D), .Q(Q)); endmodule
+module \$_DFFE_PP0P_ (input D, C, E, R, output Q); TRELLIS_FF #(.GSR("AUTO"), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("ASYNC")) _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(R), .DI(D), .Q(Q)); endmodule
+module \$_DFFE_PP1P_ (input D, C, E, R, output Q); TRELLIS_FF #(.GSR("AUTO"), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("SET"), .SRMODE("ASYNC")) _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(R), .DI(D), .Q(Q)); endmodule
+
+module \$_SDFFE_NN0P_ (input D, C, E, R, output Q); TRELLIS_FF #(.GSR("AUTO"), .CEMUX("CE"), .CLKMUX("INV"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("LSR_OVER_CE")) _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(!R), .DI(D), .Q(Q)); endmodule
+module \$_SDFFE_NN1P_ (input D, C, E, R, output Q); TRELLIS_FF #(.GSR("AUTO"), .CEMUX("CE"), .CLKMUX("INV"), .LSRMUX("LSR"), .REGSET("SET"), .SRMODE("LSR_OVER_CE")) _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(!R), .DI(D), .Q(Q)); endmodule
+module \$_SDFFE_PN0P_ (input D, C, E, R, output Q); TRELLIS_FF #(.GSR("AUTO"), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("LSR_OVER_CE")) _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(!R), .DI(D), .Q(Q)); endmodule
+module \$_SDFFE_PN1P_ (input D, C, E, R, output Q); TRELLIS_FF #(.GSR("AUTO"), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("SET"), .SRMODE("LSR_OVER_CE")) _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(!R), .DI(D), .Q(Q)); endmodule
+
+module \$_SDFFE_NP0P_ (input D, C, E, R, output Q); TRELLIS_FF #(.GSR("AUTO"), .CEMUX("CE"), .CLKMUX("INV"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("LSR_OVER_CE")) _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(R), .DI(D), .Q(Q)); endmodule
+module \$_SDFFE_NP1P_ (input D, C, E, R, output Q); TRELLIS_FF #(.GSR("AUTO"), .CEMUX("CE"), .CLKMUX("INV"), .LSRMUX("LSR"), .REGSET("SET"), .SRMODE("LSR_OVER_CE")) _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(R), .DI(D), .Q(Q)); endmodule
+module \$_SDFFE_PP0P_ (input D, C, E, R, output Q); TRELLIS_FF #(.GSR("AUTO"), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("LSR_OVER_CE")) _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(R), .DI(D), .Q(Q)); endmodule
+module \$_SDFFE_PP1P_ (input D, C, E, R, output Q); TRELLIS_FF #(.GSR("AUTO"), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("SET"), .SRMODE("LSR_OVER_CE")) _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(R), .DI(D), .Q(Q)); endmodule
`ifdef ASYNC_PRLD
module \$_DLATCH_N_ (input E, input D, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("1"), .LSRMODE("PRLD"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("ASYNC")) _TECHMAP_REPLACE_ (.LSR(!E), .DI(1'b0), .M(D), .Q(Q)); endmodule
@@ -70,6 +70,7 @@ module \$lut (A, Y);
parameter WIDTH = 0;
parameter LUT = 0;
+ (* force_downto *)
input [WIDTH-1:0] A;
output Y;
diff --git a/techlibs/ecp5/cells_sim.v b/techlibs/ecp5/cells_sim.v
index 12b33e925..357fd9173 100644
--- a/techlibs/ecp5/cells_sim.v
+++ b/techlibs/ecp5/cells_sim.v
@@ -186,6 +186,7 @@ module PFUMX (input ALUT, BLUT, C0, output Z);
endmodule
// ---------------------------------------
+(* abc9_box, lib_whitebox *)
module TRELLIS_DPR16X4 (
input [3:0] DI,
input [3:0] WAD,
@@ -222,10 +223,16 @@ module TRELLIS_DPR16X4 (
mem[WAD] <= DI;
assign DO = mem[RAD];
+
+ specify
+ // TODO
+ (RAD *> DO) = 0;
+ endspecify
endmodule
// ---------------------------------------
+(* abc9_box, lib_whitebox *)
module DPR16X4C (
input [3:0] DI,
input WCK, WRE,
@@ -281,6 +288,10 @@ module DPR16X4C (
assign DO = ram[RAD];
+ specify
+ // TODO
+ (RAD *> DO) = 0;
+ endspecify
endmodule
// ---------------------------------------
@@ -294,6 +305,9 @@ endmodule
// ---------------------------------------
+`ifdef YOSYS
+(* abc9_flop=(SRMODE != "ASYNC"), abc9_box=(SRMODE == "ASYNC"), lib_whitebox *)
+`endif
module TRELLIS_FF(input CLK, LSR, CE, DI, M, output reg Q);
parameter GSR = "ENABLED";
parameter [127:0] CEMUX = "1";
@@ -340,6 +354,38 @@ module TRELLIS_FF(input CLK, LSR, CE, DI, M, output reg Q);
Q <= DI;
end
endgenerate
+
+ generate
+ // TODO
+ if (CLKMUX == "INV")
+ specify
+ $setup(DI, negedge CLK, 0);
+ $setup(CE, negedge CLK, 0);
+ $setup(LSR, negedge CLK, 0);
+`ifndef YOSYS
+ if (SRMODE == "ASYNC" && muxlsr) (negedge CLK => (Q : srval)) = 0;
+`else
+ if (SRMODE == "ASYNC" && muxlsr) (LSR => Q) = 0; // Technically, this should be an edge sensitive path
+ // but for facilitating a bypass box, let's pretend it's
+ // a simple path
+`endif
+ if (!muxlsr && muxce) (negedge CLK => (Q : DI)) = 0;
+ endspecify
+ else
+ specify
+ $setup(DI, posedge CLK, 0);
+ $setup(CE, posedge CLK, 0);
+ $setup(LSR, posedge CLK, 0);
+`ifndef YOSYS
+ if (SRMODE == "ASYNC" && muxlsr) (posedge CLK => (Q : srval)) = 0;
+`else
+ if (SRMODE == "ASYNC" && muxlsr) (LSR => Q) = 0; // Technically, this should be an edge sensitive path
+ // but for facilitating a bypass box, let's pretend it's
+ // a simple path
+`endif
+ if (!muxlsr && muxce) (posedge CLK => (Q : DI)) = 0;
+ endspecify
+ endgenerate
endmodule
// ---------------------------------------
diff --git a/techlibs/ecp5/ecp5_ffinit.cc b/techlibs/ecp5/ecp5_ffinit.cc
index ba72bd0c6..0ecc86388 100644
--- a/techlibs/ecp5/ecp5_ffinit.cc
+++ b/techlibs/ecp5/ecp5_ffinit.cc
@@ -26,7 +26,7 @@ PRIVATE_NAMESPACE_BEGIN
struct Ecp5FfinitPass : public Pass {
Ecp5FfinitPass() : Pass("ecp5_ffinit", "ECP5: handle FF init values") { }
- void help() YS_OVERRIDE
+ void help() override
{
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
log("\n");
@@ -36,7 +36,7 @@ struct Ecp5FfinitPass : public Pass {
log("If reset is not used, set the reset value to the init value, otherwise\n");
log("unmap out the reset (if not an async reset).\n");
}
- void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
+ void execute(std::vector<std::string> args, RTLIL::Design *design) override
{
log_header(design, "Executing ECP5_FFINIT pass (implement FF init values).\n");
diff --git a/techlibs/ecp5/ecp5_gsr.cc b/techlibs/ecp5/ecp5_gsr.cc
index 3d3f8e1c1..18d99cfb2 100644
--- a/techlibs/ecp5/ecp5_gsr.cc
+++ b/techlibs/ecp5/ecp5_gsr.cc
@@ -26,7 +26,7 @@ PRIVATE_NAMESPACE_BEGIN
struct Ecp5GsrPass : public Pass {
Ecp5GsrPass() : Pass("ecp5_gsr", "ECP5: handle GSR") { }
- void help() YS_OVERRIDE
+ void help() override
{
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
log("\n");
@@ -40,7 +40,7 @@ struct Ecp5GsrPass : public Pass {
log("is not set, otherwise it will be resolved to \"DISABLED\".\n");
log("\n");
}
- void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
+ void execute(std::vector<std::string> args, RTLIL::Design *design) override
{
log_header(design, "Executing ECP5_GSR pass (implement FF init values).\n");
diff --git a/techlibs/ecp5/synth_ecp5.cc b/techlibs/ecp5/synth_ecp5.cc
index b9b236a0c..0874b954a 100644
--- a/techlibs/ecp5/synth_ecp5.cc
+++ b/techlibs/ecp5/synth_ecp5.cc
@@ -30,12 +30,12 @@ struct SynthEcp5Pass : public ScriptPass
{
SynthEcp5Pass() : ScriptPass("synth_ecp5", "synthesis for ECP5 FPGAs") { }
- void on_register() YS_OVERRIDE
+ void on_register() override
{
RTLIL::constpad["synth_ecp5.abc9.W"] = "300";
}
- void help() YS_OVERRIDE
+ void help() override
{
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
log("\n");
@@ -66,6 +66,9 @@ struct SynthEcp5Pass : public ScriptPass
log(" -noflatten\n");
log(" do not flatten design before synthesis\n");
log("\n");
+ log(" -dff\n");
+ log(" run 'abc'/'abc9' with -dff option\n");
+ log("\n");
log(" -retime\n");
log(" run 'abc' with '-dff -D 1' options\n");
log("\n");
@@ -107,9 +110,9 @@ struct SynthEcp5Pass : public ScriptPass
}
string top_opt, blif_file, edif_file, json_file;
- bool noccu2, nodffe, nobram, nolutram, nowidelut, asyncprld, flatten, retime, abc2, abc9, nodsp, vpr;
+ bool noccu2, nodffe, nobram, nolutram, nowidelut, asyncprld, flatten, dff, retime, abc2, abc9, nodsp, vpr;
- void clear_flags() YS_OVERRIDE
+ void clear_flags() override
{
top_opt = "-auto-top";
blif_file = "";
@@ -122,6 +125,7 @@ struct SynthEcp5Pass : public ScriptPass
nowidelut = false;
asyncprld = false;
flatten = true;
+ dff = false;
retime = false;
abc2 = false;
vpr = false;
@@ -129,7 +133,7 @@ struct SynthEcp5Pass : public ScriptPass
nodsp = false;
}
- void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
+ void execute(std::vector<std::string> args, RTLIL::Design *design) override
{
string run_from, run_to;
clear_flags();
@@ -169,6 +173,10 @@ struct SynthEcp5Pass : public ScriptPass
flatten = false;
continue;
}
+ if (args[argidx] == "-dff") {
+ dff = true;
+ continue;
+ }
if (args[argidx] == "-retime") {
retime = true;
continue;
@@ -231,7 +239,7 @@ struct SynthEcp5Pass : public ScriptPass
log_pop();
}
- void script() YS_OVERRIDE
+ void script() override
{
if (check_label("begin"))
{
@@ -306,7 +314,9 @@ struct SynthEcp5Pass : public ScriptPass
run("dff2dffs");
run("opt_clean");
if (!nodffe)
- run("dff2dffe -direct-match $_DFF_* -direct-match $__DFFS_*");
+ run("dff2dffe -direct-match $_DFF_* -direct-match $_SDFF_*");
+ if ((abc9 && dff) || help_mode)
+ run("zinit -all w:* t:$_DFF_?_ t:$_DFFE_??_ t:$_SDFF*", "(only if -abc9 and -dff");
run(stringf("techmap -D NO_LUT %s -map +/ecp5/cells_map.v", help_mode ? "[-D ASYNC_PRLD]" : (asyncprld ? "-D ASYNC_PRLD" : "")));
run("opt_expr -undriven -mux_undef");
run("simplemap");
@@ -318,17 +328,12 @@ struct SynthEcp5Pass : public ScriptPass
if (check_label("map_luts"))
{
- if (abc2 || help_mode) {
+ if (abc2 || help_mode)
run("abc", " (only if -abc2)");
- }
- std::string techmap_args = asyncprld ? "" : "-map +/ecp5/latches_map.v";
- if (abc9)
- techmap_args += " -map +/ecp5/abc9_map.v -max_iter 1";
- if (!asyncprld || abc9)
- run("techmap " + techmap_args);
+ if (!asyncprld || help_mode)
+ run("techmap -map +/ecp5/latches_map.v", "(skip if -asyncprld)");
if (abc9) {
- run("read_verilog -icells -lib -specify +/abc9_model.v +/ecp5/abc9_model.v");
std::string abc9_opts;
if (nowidelut)
abc9_opts += " -maxlut 4";
@@ -338,26 +343,29 @@ struct SynthEcp5Pass : public ScriptPass
else
abc9_opts += stringf(" -W %s", RTLIL::constpad.at(k).c_str());
if (nowidelut)
- run("abc9 -maxlut 4 -W 200");
- else
- run("abc9 -W 200");
- run("techmap -map +/ecp5/abc9_unmap.v");
+ abc9_opts += " -maxlut 4";
+ if (dff)
+ abc9_opts += " -dff";
+ run("abc9" + abc9_opts);
} else {
+ std::string abc_args = " -dress";
if (nowidelut)
- run("abc -lut 4 -dress");
+ abc_args += " -lut 4";
else
- run("abc -lut 4:7 -dress");
+ abc_args += " -lut 4:7";
+ if (dff)
+ abc_args += " -dff";
+ run("abc" + abc_args);
}
run("clean");
}
if (check_label("map_cells"))
{
- if (vpr)
- run("techmap -D NO_LUT -map +/ecp5/cells_map.v");
- else
- run("techmap -map +/ecp5/cells_map.v", "(with -D NO_LUT in vpr mode)");
-
+ if (help_mode)
+ run("techmap -map +/ecp5/cells_map.v", "(skip if -vpr)");
+ else if (!vpr)
+ run("techmap -map +/ecp5/cells_map.v");
run("opt_lut_ins -tech ecp5");
run("clean");
}
diff --git a/techlibs/efinix/arith_map.v b/techlibs/efinix/arith_map.v
index 178f57bc5..4dac360b9 100644
--- a/techlibs/efinix/arith_map.v
+++ b/techlibs/efinix/arith_map.v
@@ -26,24 +26,33 @@ module _80_efinix_alu (A, B, CI, BI, X, Y, CO);
parameter B_WIDTH = 1;
parameter Y_WIDTH = 1;
+ (* force_downto *)
input [A_WIDTH-1:0] A;
+ (* force_downto *)
input [B_WIDTH-1:0] B;
+ (* force_downto *)
output [Y_WIDTH-1:0] X, Y;
input CI, BI;
+ (* force_downto *)
output [Y_WIDTH-1:0] CO;
wire CIx;
+ (* force_downto *)
wire [Y_WIDTH-1:0] COx;
wire _TECHMAP_FAIL_ = Y_WIDTH <= 2;
+ (* force_downto *)
wire [Y_WIDTH-1:0] A_buf, B_buf;
\$pos #(.A_SIGNED(A_SIGNED), .A_WIDTH(A_WIDTH), .Y_WIDTH(Y_WIDTH)) A_conv (.A(A), .Y(A_buf));
\$pos #(.A_SIGNED(B_SIGNED), .A_WIDTH(B_WIDTH), .Y_WIDTH(Y_WIDTH)) B_conv (.A(B), .Y(B_buf));
+ (* force_downto *)
wire [Y_WIDTH-1:0] AA = A_buf;
+ (* force_downto *)
wire [Y_WIDTH-1:0] BB = BI ? ~B_buf : B_buf;
+ (* force_downto *)
wire [Y_WIDTH-1:0] C = { COx, CIx };
EFX_ADD #(.I0_POLARITY(1'b1),.I1_POLARITY(1'b1))
@@ -76,4 +85,4 @@ module _80_efinix_alu (A, B, CI, BI, X, Y, CO);
/* End implementation */
assign X = AA ^ BB;
-endmodule \ No newline at end of file
+endmodule
diff --git a/techlibs/efinix/cells_map.v b/techlibs/efinix/cells_map.v
index 3ecec3bac..1090f8b27 100644
--- a/techlibs/efinix/cells_map.v
+++ b/techlibs/efinix/cells_map.v
@@ -34,6 +34,7 @@ module \$lut (A, Y);
parameter WIDTH = 0;
parameter LUT = 0;
+ (* force_downto *)
input [WIDTH-1:0] A;
output Y;
diff --git a/techlibs/efinix/efinix_fixcarry.cc b/techlibs/efinix/efinix_fixcarry.cc
index 1a1733a17..486b8e89c 100644
--- a/techlibs/efinix/efinix_fixcarry.cc
+++ b/techlibs/efinix/efinix_fixcarry.cc
@@ -90,7 +90,7 @@ static void fix_carry_chain(Module *module)
struct EfinixCarryFixPass : public Pass {
EfinixCarryFixPass() : Pass("efinix_fixcarry", "Efinix: fix carry chain") { }
- void help() YS_OVERRIDE
+ void help() override
{
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
log("\n");
@@ -99,7 +99,7 @@ struct EfinixCarryFixPass : public Pass {
log("Add Efinix adders to fix carry chain if needed.\n");
log("\n");
}
- void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
+ void execute(std::vector<std::string> args, RTLIL::Design *design) override
{
log_header(design, "Executing EFINIX_FIXCARRY pass (fix invalid carry chain).\n");
diff --git a/techlibs/efinix/efinix_gbuf.cc b/techlibs/efinix/efinix_gbuf.cc
index 55dfb3c79..ae191359a 100644
--- a/techlibs/efinix/efinix_gbuf.cc
+++ b/techlibs/efinix/efinix_gbuf.cc
@@ -87,7 +87,7 @@ static void handle_gbufs(Module *module)
struct EfinixGbufPass : public Pass {
EfinixGbufPass() : Pass("efinix_gbuf", "Efinix: insert global clock buffers") { }
- void help() YS_OVERRIDE
+ void help() override
{
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
log("\n");
@@ -96,7 +96,7 @@ struct EfinixGbufPass : public Pass {
log("Add Efinix global clock buffers to top module as needed.\n");
log("\n");
}
- void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
+ void execute(std::vector<std::string> args, RTLIL::Design *design) override
{
log_header(design, "Executing efinix_gbuf pass (insert global clock buffers).\n");
diff --git a/techlibs/efinix/synth_efinix.cc b/techlibs/efinix/synth_efinix.cc
index f9a7ef865..6ca44eed1 100644
--- a/techlibs/efinix/synth_efinix.cc
+++ b/techlibs/efinix/synth_efinix.cc
@@ -30,7 +30,7 @@ struct SynthEfinixPass : public ScriptPass
{
SynthEfinixPass() : ScriptPass("synth_efinix", "synthesis for Efinix FPGAs") { }
- void help() YS_OVERRIDE
+ void help() override
{
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
log("\n");
@@ -72,7 +72,7 @@ struct SynthEfinixPass : public ScriptPass
string top_opt, edif_file, json_file;
bool flatten, retime, nobram;
- void clear_flags() YS_OVERRIDE
+ void clear_flags() override
{
top_opt = "-auto-top";
edif_file = "";
@@ -82,7 +82,7 @@ struct SynthEfinixPass : public ScriptPass
nobram = false;
}
- void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
+ void execute(std::vector<std::string> args, RTLIL::Design *design) override
{
string run_from, run_to;
clear_flags();
@@ -137,7 +137,7 @@ struct SynthEfinixPass : public ScriptPass
log_pop();
}
- void script() YS_OVERRIDE
+ void script() override
{
if (check_label("begin"))
{
diff --git a/techlibs/gowin/arith_map.v b/techlibs/gowin/arith_map.v
index b6f9e8c38..42aaba870 100644
--- a/techlibs/gowin/arith_map.v
+++ b/techlibs/gowin/arith_map.v
@@ -26,21 +26,29 @@ module _80_gw1n_alu(A, B, CI, BI, X, Y, CO);
parameter B_WIDTH = 1;
parameter Y_WIDTH = 1;
+ (* force_downto *)
input [A_WIDTH-1:0] A;
+ (* force_downto *)
input [B_WIDTH-1:0] B;
+ (* force_downto *)
output [Y_WIDTH-1:0] X, Y;
input CI, BI;
+ (* force_downto *)
output [Y_WIDTH-1:0] CO;
wire _TECHMAP_FAIL_ = Y_WIDTH <= 2;
+ (* force_downto *)
wire [Y_WIDTH-1:0] A_buf, B_buf;
\$pos #(.A_SIGNED(A_SIGNED), .A_WIDTH(A_WIDTH), .Y_WIDTH(Y_WIDTH)) A_conv (.A(A), .Y(A_buf));
\$pos #(.A_SIGNED(B_SIGNED), .A_WIDTH(B_WIDTH), .Y_WIDTH(Y_WIDTH)) B_conv (.A(B), .Y(B_buf));
+ (* force_downto *)
wire [Y_WIDTH-1:0] AA = A_buf;
+ (* force_downto *)
wire [Y_WIDTH-1:0] BB = B_buf;
+ (* force_downto *)
wire [Y_WIDTH-1:0] C = {CO, CI};
genvar i;
diff --git a/techlibs/gowin/cells_map.v b/techlibs/gowin/cells_map.v
index aee912256..5460274ca 100644
--- a/techlibs/gowin/cells_map.v
+++ b/techlibs/gowin/cells_map.v
@@ -67,82 +67,82 @@ module \$_DFFE_NN_ #(parameter _TECHMAP_WIREINIT_Q_ = 1'bx) (input D, C, E, outp
endmodule
// DFFR D Flip-Flop with Synchronous Reset
-module \$__DFFS_PN0_ #(parameter _TECHMAP_WIREINIT_Q_ = 1'bx) (input D, C, R, output Q);
+module \$_SDFF_PN0_ #(parameter _TECHMAP_WIREINIT_Q_ = 1'bx) (input D, C, R, output Q);
DFFR _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .RESET(!R));
wire _TECHMAP_REMOVEINIT_Q_ = _TECHMAP_WIREINIT_Q_ !== 1'b1;
endmodule
-module \$__DFFS_PP0_ #(parameter _TECHMAP_WIREINIT_Q_ = 1'bx) (input D, C, R, output Q);
+module \$_SDFF_PP0_ #(parameter _TECHMAP_WIREINIT_Q_ = 1'bx) (input D, C, R, output Q);
DFFR _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .RESET(R));
wire _TECHMAP_REMOVEINIT_Q_ = _TECHMAP_WIREINIT_Q_ !== 1'b1;
endmodule
// DFFNR D Flip-Flop with Negative-Edge Clock and Synchronous Reset
-module \$__DFFS_NN0_ #(parameter _TECHMAP_WIREINIT_Q_ = 1'bx) (input D, C, R, output Q);
+module \$_SDFF_NN0_ #(parameter _TECHMAP_WIREINIT_Q_ = 1'bx) (input D, C, R, output Q);
DFFNR _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .RESET(!R));
wire _TECHMAP_REMOVEINIT_Q_ = _TECHMAP_WIREINIT_Q_ !== 1'b1;
endmodule
-module \$__DFFS_NP0_ #(parameter _TECHMAP_WIREINIT_Q_ = 1'bx) (input D, C, R, output Q);
+module \$_SDFF_NP0_ #(parameter _TECHMAP_WIREINIT_Q_ = 1'bx) (input D, C, R, output Q);
DFFNR _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .RESET(R));
wire _TECHMAP_REMOVEINIT_Q_ = _TECHMAP_WIREINIT_Q_ !== 1'b1;
endmodule
// DFFRE D Flip-Flop with Clock Enable and Synchronous Reset
-module \$__DFFSE_PN0 #(parameter _TECHMAP_WIREINIT_Q_ = 1'bx) (input D, C, R, E, output Q);
+module \$_SDFFE_PN0P_ #(parameter _TECHMAP_WIREINIT_Q_ = 1'bx) (input D, C, R, E, output Q);
DFFRE _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .RESET(!R), .CE(E));
wire _TECHMAP_REMOVEINIT_Q_ = _TECHMAP_WIREINIT_Q_ !== 1'b1;
endmodule
-module \$__DFFSE_PP0 #(parameter _TECHMAP_WIREINIT_Q_ = 1'bx) (input D, C, R, E, output Q);
+module \$_SDFFE_PP0P_ #(parameter _TECHMAP_WIREINIT_Q_ = 1'bx) (input D, C, R, E, output Q);
DFFRE _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .RESET(R), .CE(E));
wire _TECHMAP_REMOVEINIT_Q_ = _TECHMAP_WIREINIT_Q_ !== 1'b1;
endmodule
// DFFNRE D Flip-Flop with Negative-Edge Clock,Clock Enable, and Synchronous Reset
-module \$__DFFSE_NN0 #(parameter _TECHMAP_WIREINIT_Q_ = 1'bx) (input D, C, R, E, output Q);
+module \$_SDFFE_NN0P_ #(parameter _TECHMAP_WIREINIT_Q_ = 1'bx) (input D, C, R, E, output Q);
DFFNRE _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .RESET(!R), .CE(E));
wire _TECHMAP_REMOVEINIT_Q_ = _TECHMAP_WIREINIT_Q_ !== 1'b1;
endmodule
-module \$__DFFSE_NP0 #(parameter _TECHMAP_WIREINIT_Q_ = 1'bx) (input D, C, R, E, output Q);
+module \$_SDFFE_NP0P_ #(parameter _TECHMAP_WIREINIT_Q_ = 1'bx) (input D, C, R, E, output Q);
DFFNRE _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .RESET(R), .CE(E));
wire _TECHMAP_REMOVEINIT_Q_ = _TECHMAP_WIREINIT_Q_ !== 1'b1;
endmodule
// DFFS D Flip-Flop with Synchronous Set
-module \$__DFFS_PN1_ #(parameter _TECHMAP_WIREINIT_Q_ = 1'bx) (input D, C, R, output Q);
+module \$_SDFF_PN1_ #(parameter _TECHMAP_WIREINIT_Q_ = 1'bx) (input D, C, R, output Q);
DFFS _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .SET(!R));
wire _TECHMAP_REMOVEINIT_Q_ = _TECHMAP_WIREINIT_Q_ !== 1'b0;
endmodule
-module \$__DFFS_PP1_ #(parameter _TECHMAP_WIREINIT_Q_ = 1'bx) (input D, C, R, output Q);
+module \$_SDFF_PP1_ #(parameter _TECHMAP_WIREINIT_Q_ = 1'bx) (input D, C, R, output Q);
DFFS _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .SET(R));
wire _TECHMAP_REMOVEINIT_Q_ = _TECHMAP_WIREINIT_Q_ !== 1'b0;
endmodule
// DFFNS D Flip-Flop with Negative-Edge Clock and Synchronous Set
-module \$__DFFS_NN1_ #(parameter _TECHMAP_WIREINIT_Q_ = 1'bx) (input D, C, R, output Q);
+module \$_SDFF_NN1_ #(parameter _TECHMAP_WIREINIT_Q_ = 1'bx) (input D, C, R, output Q);
DFFNS _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .SET(!R));
wire _TECHMAP_REMOVEINIT_Q_ = _TECHMAP_WIREINIT_Q_ !== 1'b0;
endmodule
-module \$__DFFS_NP1_ #(parameter _TECHMAP_WIREINIT_Q_ = 1'bx) (input D, C, R, output Q);
+module \$_SDFF_NP1_ #(parameter _TECHMAP_WIREINIT_Q_ = 1'bx) (input D, C, R, output Q);
DFFNS _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .SET(R));
wire _TECHMAP_REMOVEINIT_Q_ = _TECHMAP_WIREINIT_Q_ !== 1'b0;
endmodule
// DFFSE D Flip-Flop with Clock Enable and Synchronous Set
-module \$__DFFSE_PN1 #(parameter _TECHMAP_WIREINIT_Q_ = 1'bx) (input D, C, R, E, output Q);
+module \$_SDFFE_PN1P_ #(parameter _TECHMAP_WIREINIT_Q_ = 1'bx) (input D, C, R, E, output Q);
DFFSE _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .SET(!R), .CE(E));
wire _TECHMAP_REMOVEINIT_Q_ = _TECHMAP_WIREINIT_Q_ !== 1'b0;
endmodule
-module \$__DFFSE_PP1 #(parameter _TECHMAP_WIREINIT_Q_ = 1'bx) (input D, C, R, E, output Q);
+module \$_SDFFE_PP1P_ #(parameter _TECHMAP_WIREINIT_Q_ = 1'bx) (input D, C, R, E, output Q);
DFFSE _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .SET(R), .CE(E));
wire _TECHMAP_REMOVEINIT_Q_ = _TECHMAP_WIREINIT_Q_ !== 1'b0;
endmodule
// DFFNSE D Flip-Flop with Negative-Edge Clock,Clock Enable,and Synchronous Set
-module \$__DFFSE_NN1 #(parameter _TECHMAP_WIREINIT_Q_ = 1'bx) (input D, C, R, E, output Q);
+module \$_SDFFE_NN1P_ #(parameter _TECHMAP_WIREINIT_Q_ = 1'bx) (input D, C, R, E, output Q);
DFFNSE _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .SET(!R), .CE(E));
wire _TECHMAP_REMOVEINIT_Q_ = _TECHMAP_WIREINIT_Q_ !== 1'b0;
endmodule
-module \$__DFFSE_NP1 #(parameter _TECHMAP_WIREINIT_Q_ = 1'bx) (input D, C, R, E, output Q);
+module \$_SDFFE_NP1P_ #(parameter _TECHMAP_WIREINIT_Q_ = 1'bx) (input D, C, R, E, output Q);
DFFNSE _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .SET(R), .CE(E));
wire _TECHMAP_REMOVEINIT_Q_ = _TECHMAP_WIREINIT_Q_ !== 1'b0;
endmodule
@@ -188,41 +188,41 @@ module \$_DFF_NN0_ #(parameter _TECHMAP_WIREINIT_Q_ = 1'bx) (input D, C, R, outp
endmodule
// DFFPE D Flip-Flop with Clock Enable and Asynchronous Preset
-module \$__DFFE_PP1 #(parameter _TECHMAP_WIREINIT_Q_ = 1'bx) (input D, C, R, E, output Q);
+module \$_DFFE_PP1P_ #(parameter _TECHMAP_WIREINIT_Q_ = 1'bx) (input D, C, R, E, output Q);
DFFPE _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .PRESET(R), .CE(E));
wire _TECHMAP_REMOVEINIT_Q_ = _TECHMAP_WIREINIT_Q_ !== 1'b0;
endmodule
-module \$__DFFE_PN1 #(parameter _TECHMAP_WIREINIT_Q_ = 1'bx) (input D, C, R, E, output Q);
+module \$_DFFE_PN1P_ #(parameter _TECHMAP_WIREINIT_Q_ = 1'bx) (input D, C, R, E, output Q);
DFFPE _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .PRESET(!R), .CE(E));
wire _TECHMAP_REMOVEINIT_Q_ = _TECHMAP_WIREINIT_Q_ !== 1'b0;
endmodule
// DFFNPE D Flip-Flop with Negative-Edge Clock,Clock Enable, and Asynchronous Preset
-module \$__DFFE_NP1 #(parameter _TECHMAP_WIREINIT_Q_ = 1'bx) (input D, C, R, E, output Q);
+module \$_DFFE_NP1P_ #(parameter _TECHMAP_WIREINIT_Q_ = 1'bx) (input D, C, R, E, output Q);
DFFNPE _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .PRESET(R), .CE(E));
wire _TECHMAP_REMOVEINIT_Q_ = _TECHMAP_WIREINIT_Q_ !== 1'b0;
endmodule
-module \$__DFFE_NN1 #(parameter _TECHMAP_WIREINIT_Q_ = 1'bx) (input D, C, R, E, output Q);
+module \$_DFFE_NN1P_ #(parameter _TECHMAP_WIREINIT_Q_ = 1'bx) (input D, C, R, E, output Q);
DFFNPE _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .PRESET(!R), .CE(E));
wire _TECHMAP_REMOVEINIT_Q_ = _TECHMAP_WIREINIT_Q_ !== 1'b0;
endmodule
// DFFCE D Flip-Flop with Clock Enable and Asynchronous Clear
-module \$__DFFE_PP0 #(parameter _TECHMAP_WIREINIT_Q_ = 1'bx) (input D, C, R, E, output Q);
+module \$_DFFE_PP0P_ #(parameter _TECHMAP_WIREINIT_Q_ = 1'bx) (input D, C, R, E, output Q);
DFFCE _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .CLEAR(R), .CE(E));
wire _TECHMAP_REMOVEINIT_Q_ = _TECHMAP_WIREINIT_Q_ !== 1'b1;
endmodule
-module \$__DFFE_PN0 #(parameter _TECHMAP_WIREINIT_Q_ = 1'bx) (input D, C, R, E, output Q);
+module \$_DFFE_PN0P_ #(parameter _TECHMAP_WIREINIT_Q_ = 1'bx) (input D, C, R, E, output Q);
DFFCE _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .CLEAR(!R), .CE(E));
wire _TECHMAP_REMOVEINIT_Q_ = _TECHMAP_WIREINIT_Q_ !== 1'b1;
endmodule
// DFFNCE D Flip-Flop with Negative-Edge Clock,Clock Enable and Asynchronous Clear
-module \$__DFFE_NP0 #(parameter _TECHMAP_WIREINIT_Q_ = 1'bx) (input D, C, R, E, output Q);
+module \$_DFFE_NP0P_ #(parameter _TECHMAP_WIREINIT_Q_ = 1'bx) (input D, C, R, E, output Q);
DFFNCE _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .CLEAR(R), .CE(E));
wire _TECHMAP_REMOVEINIT_Q_ = _TECHMAP_WIREINIT_Q_ !== 1'b1;
endmodule
-module \$__DFFE_NN0 #(parameter _TECHMAP_WIREINIT_Q_ = 1'bx) (input D, C, R, E, output Q);
+module \$_DFFE_NN0P_ #(parameter _TECHMAP_WIREINIT_Q_ = 1'bx) (input D, C, R, E, output Q);
DFFNCE _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .CLEAR(!R), .CE(E));
wire _TECHMAP_REMOVEINIT_Q_ = _TECHMAP_WIREINIT_Q_ !== 1'b1;
endmodule
@@ -232,6 +232,7 @@ module \$lut (A, Y);
parameter WIDTH = 0;
parameter LUT = 0;
+ (* force_downto *)
input [WIDTH-1:0] A;
output Y;
diff --git a/techlibs/gowin/determine_init.cc b/techlibs/gowin/determine_init.cc
index 18a64e451..15ff115de 100644
--- a/techlibs/gowin/determine_init.cc
+++ b/techlibs/gowin/determine_init.cc
@@ -25,7 +25,7 @@ PRIVATE_NAMESPACE_BEGIN
struct DetermineInitPass : public Pass {
DetermineInitPass() : Pass("determine_init", "Determine the init value of cells") { }
- void help() YS_OVERRIDE
+ void help() override
{
log("\n");
log(" determine_init [selection]\n");
@@ -44,7 +44,7 @@ struct DetermineInitPass : public Pass {
return init;
}
- void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
+ void execute(std::vector<std::string> args, RTLIL::Design *design) override
{
log_header(design, "Executing DETERMINE_INIT pass (determine init value for cells).\n");
diff --git a/techlibs/gowin/synth_gowin.cc b/techlibs/gowin/synth_gowin.cc
index dd965c0b8..32d9cc0a5 100644
--- a/techlibs/gowin/synth_gowin.cc
+++ b/techlibs/gowin/synth_gowin.cc
@@ -29,7 +29,7 @@ struct SynthGowinPass : public ScriptPass
{
SynthGowinPass() : ScriptPass("synth_gowin", "synthesis for Gowin FPGAs") { }
- void help() YS_OVERRIDE
+ void help() override
{
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
log("\n");
@@ -82,7 +82,7 @@ struct SynthGowinPass : public ScriptPass
string top_opt, vout_file;
bool retime, nobram, nolutram, flatten, nodffe, nowidelut, abc9, noiopads;
- void clear_flags() YS_OVERRIDE
+ void clear_flags() override
{
top_opt = "-auto-top";
vout_file = "";
@@ -96,7 +96,7 @@ struct SynthGowinPass : public ScriptPass
noiopads = false;
}
- void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
+ void execute(std::vector<std::string> args, RTLIL::Design *design) override
{
string run_from, run_to;
clear_flags();
@@ -167,7 +167,7 @@ struct SynthGowinPass : public ScriptPass
log_pop();
}
- void script() YS_OVERRIDE
+ void script() override
{
if (check_label("begin"))
{
@@ -222,7 +222,7 @@ struct SynthGowinPass : public ScriptPass
run("dff2dffs -match-init");
run("opt_clean");
if (!nodffe)
- run("dff2dffe -direct-match $_DFF_* -direct-match $__DFFS_*");
+ run("dff2dffe -direct-match $_DFF_* -direct-match $_SDFF_*");
run("techmap -map +/gowin/cells_map.v");
run("opt_expr -mux_undef");
run("simplemap");
diff --git a/techlibs/greenpak4/cells_map.v b/techlibs/greenpak4/cells_map.v
index 51c85183d..316be3f73 100644
--- a/techlibs/greenpak4/cells_map.v
+++ b/techlibs/greenpak4/cells_map.v
@@ -115,6 +115,7 @@ module \$lut (A, Y);
parameter WIDTH = 0;
parameter LUT = 0;
+ (* force_downto *)
input [WIDTH-1:0] A;
output Y;
@@ -150,6 +151,7 @@ module \$__COUNT_ (CE, CLK, OUT, POUT, RST, UP);
input wire CE;
input wire CLK;
output reg OUT;
+ (* force_downto *)
output reg[WIDTH-1:0] POUT;
input wire RST;
input wire UP;
diff --git a/techlibs/greenpak4/greenpak4_dffinv.cc b/techlibs/greenpak4/greenpak4_dffinv.cc
index 62057318b..b8797bc19 100644
--- a/techlibs/greenpak4/greenpak4_dffinv.cc
+++ b/techlibs/greenpak4/greenpak4_dffinv.cc
@@ -91,7 +91,7 @@ void invert_gp_dff(Cell *cell, bool invert_input)
struct Greenpak4DffInvPass : public Pass {
Greenpak4DffInvPass() : Pass("greenpak4_dffinv", "merge greenpak4 inverters and DFF/latches") { }
- void help() YS_OVERRIDE
+ void help() override
{
log("\n");
log(" greenpak4_dffinv [options] [selection]\n");
@@ -99,7 +99,7 @@ struct Greenpak4DffInvPass : public Pass {
log("Merge GP_INV cells with GP_DFF* and GP_DLATCH* cells.\n");
log("\n");
}
- void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
+ void execute(std::vector<std::string> args, RTLIL::Design *design) override
{
log_header(design, "Executing GREENPAK4_DFFINV pass (merge input/output inverters into FF/latch cells).\n");
diff --git a/techlibs/greenpak4/synth_greenpak4.cc b/techlibs/greenpak4/synth_greenpak4.cc
index bfbb56d15..17b5d4782 100644
--- a/techlibs/greenpak4/synth_greenpak4.cc
+++ b/techlibs/greenpak4/synth_greenpak4.cc
@@ -29,7 +29,7 @@ struct SynthGreenPAK4Pass : public ScriptPass
{
SynthGreenPAK4Pass() : ScriptPass("synth_greenpak4", "synthesis for GreenPAK4 FPGAs") { }
- void help() YS_OVERRIDE
+ void help() override
{
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
log("\n");
@@ -70,7 +70,7 @@ struct SynthGreenPAK4Pass : public ScriptPass
string top_opt, part, json_file;
bool flatten, retime;
- void clear_flags() YS_OVERRIDE
+ void clear_flags() override
{
top_opt = "-auto-top";
part = "SLG46621V";
@@ -79,7 +79,7 @@ struct SynthGreenPAK4Pass : public ScriptPass
retime = false;
}
- void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
+ void execute(std::vector<std::string> args, RTLIL::Design *design) override
{
string run_from, run_to;
clear_flags();
@@ -133,7 +133,7 @@ struct SynthGreenPAK4Pass : public ScriptPass
log_pop();
}
- void script() YS_OVERRIDE
+ void script() override
{
if (check_label("begin"))
{
diff --git a/techlibs/ice40/Makefile.inc b/techlibs/ice40/Makefile.inc
index b9e504a9d..1a8caf9a9 100644
--- a/techlibs/ice40/Makefile.inc
+++ b/techlibs/ice40/Makefile.inc
@@ -23,6 +23,7 @@ techlibs/ice40/brams_init3.vh: techlibs/ice40/brams_init.mk
$(eval $(call add_share_file,share/ice40,techlibs/ice40/arith_map.v))
$(eval $(call add_share_file,share/ice40,techlibs/ice40/cells_map.v))
+$(eval $(call add_share_file,share/ice40,techlibs/ice40/ff_map.v))
$(eval $(call add_share_file,share/ice40,techlibs/ice40/cells_sim.v))
$(eval $(call add_share_file,share/ice40,techlibs/ice40/latches_map.v))
$(eval $(call add_share_file,share/ice40,techlibs/ice40/brams.txt))
diff --git a/techlibs/ice40/arith_map.v b/techlibs/ice40/arith_map.v
index ed4140e44..3950e882b 100644
--- a/techlibs/ice40/arith_map.v
+++ b/techlibs/ice40/arith_map.v
@@ -25,21 +25,29 @@ module _80_ice40_alu (A, B, CI, BI, X, Y, CO);
parameter B_WIDTH = 1;
parameter Y_WIDTH = 1;
+ (* force_downto *)
input [A_WIDTH-1:0] A;
+ (* force_downto *)
input [B_WIDTH-1:0] B;
+ (* force_downto *)
output [Y_WIDTH-1:0] X, Y;
input CI, BI;
+ (* force_downto *)
output [Y_WIDTH-1:0] CO;
wire _TECHMAP_FAIL_ = Y_WIDTH <= 2;
+ (* force_downto *)
wire [Y_WIDTH-1:0] A_buf, B_buf;
\$pos #(.A_SIGNED(A_SIGNED), .A_WIDTH(A_WIDTH), .Y_WIDTH(Y_WIDTH)) A_conv (.A(A), .Y(A_buf));
\$pos #(.A_SIGNED(B_SIGNED), .A_WIDTH(B_WIDTH), .Y_WIDTH(Y_WIDTH)) B_conv (.A(B), .Y(B_buf));
+ (* force_downto *)
wire [Y_WIDTH-1:0] AA = A_buf;
+ (* force_downto *)
wire [Y_WIDTH-1:0] BB = BI ? ~B_buf : B_buf;
+ (* force_downto *)
wire [Y_WIDTH-1:0] C = {CO, CI};
genvar i;
diff --git a/techlibs/ice40/cells_map.v b/techlibs/ice40/cells_map.v
index d5362eb83..7e5c07879 100644
--- a/techlibs/ice40/cells_map.v
+++ b/techlibs/ice40/cells_map.v
@@ -1,37 +1,8 @@
-module \$_DFF_N_ (input D, C, output Q); SB_DFFN _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C)); endmodule
-module \$_DFF_P_ (input D, C, output Q); SB_DFF _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C)); endmodule
-
-module \$_DFFE_NN_ (input D, C, E, output Q); SB_DFFNE _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .E(!E)); endmodule
-module \$_DFFE_PN_ (input D, C, E, output Q); SB_DFFE _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .E(!E)); endmodule
-
-module \$_DFFE_NP_ (input D, C, E, output Q); SB_DFFNE _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .E(E)); endmodule
-module \$_DFFE_PP_ (input D, C, E, output Q); SB_DFFE _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .E(E)); endmodule
-
-module \$_DFF_NN0_ (input D, C, R, output Q); SB_DFFNR _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .R(!R)); endmodule
-module \$_DFF_NN1_ (input D, C, R, output Q); SB_DFFNS _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .S(!R)); endmodule
-module \$_DFF_PN0_ (input D, C, R, output Q); SB_DFFR _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .R(!R)); endmodule
-module \$_DFF_PN1_ (input D, C, R, output Q); SB_DFFS _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .S(!R)); endmodule
-
-module \$_DFF_NP0_ (input D, C, R, output Q); SB_DFFNR _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .R(R)); endmodule
-module \$_DFF_NP1_ (input D, C, R, output Q); SB_DFFNS _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .S(R)); endmodule
-module \$_DFF_PP0_ (input D, C, R, output Q); SB_DFFR _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .R(R)); endmodule
-module \$_DFF_PP1_ (input D, C, R, output Q); SB_DFFS _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .S(R)); endmodule
-
-module \$__DFFE_NN0 (input D, C, E, R, output Q); SB_DFFNER _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .E(E), .R(!R)); endmodule
-module \$__DFFE_NN1 (input D, C, E, R, output Q); SB_DFFNES _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .E(E), .S(!R)); endmodule
-module \$__DFFE_PN0 (input D, C, E, R, output Q); SB_DFFER _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .E(E), .R(!R)); endmodule
-module \$__DFFE_PN1 (input D, C, E, R, output Q); SB_DFFES _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .E(E), .S(!R)); endmodule
-
-module \$__DFFE_NP0 (input D, C, E, R, output Q); SB_DFFNER _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .E(E), .R(R)); endmodule
-module \$__DFFE_NP1 (input D, C, E, R, output Q); SB_DFFNES _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .E(E), .S(R)); endmodule
-module \$__DFFE_PP0 (input D, C, E, R, output Q); SB_DFFER _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .E(E), .R(R)); endmodule
-module \$__DFFE_PP1 (input D, C, E, R, output Q); SB_DFFES _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .E(E), .S(R)); endmodule
-
-`ifndef NO_LUT
module \$lut (A, Y);
parameter WIDTH = 0;
parameter LUT = 0;
+ (* force_downto *)
input [WIDTH-1:0] A;
output Y;
@@ -59,4 +30,3 @@ module \$lut (A, Y);
end
endgenerate
endmodule
-`endif
diff --git a/techlibs/ice40/cells_sim.v b/techlibs/ice40/cells_sim.v
index 5d107989d..7ee809262 100644
--- a/techlibs/ice40/cells_sim.v
+++ b/techlibs/ice40/cells_sim.v
@@ -245,6 +245,7 @@ endmodule
// Positive Edge SiliconBlue FF Cells
+(* abc9_flop, lib_whitebox *)
module SB_DFF (
output `SB_DFF_REG,
input C, D
@@ -280,6 +281,7 @@ module SB_DFF (
`endif
endmodule
+(* abc9_flop, lib_whitebox *)
module SB_DFFE (
output `SB_DFF_REG,
input C, E, D
@@ -322,6 +324,7 @@ module SB_DFFE (
`endif
endmodule
+(* abc9_flop, lib_whitebox *)
module SB_DFFSR (
output `SB_DFF_REG,
input C, R, D
@@ -369,6 +372,7 @@ module SB_DFFSR (
`endif
endmodule
+(* abc9_box, lib_whitebox *)
module SB_DFFR (
output `SB_DFF_REG,
input C, R, D
@@ -386,7 +390,13 @@ module SB_DFFR (
// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L63
$setup(negedge R, posedge C, 160);
// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L91
+`ifndef YOSYS
(posedge R => (Q : 1'b0)) = 599;
+`else
+ if (R) (R => Q) = 599; // Technically, this should be an edge sensitive path
+ // but for facilitating a bypass box, let's pretend it's
+ // a simple path
+`endif
// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L90
if (!R) (posedge C => (Q : D)) = 540;
endspecify
@@ -399,7 +409,13 @@ module SB_DFFR (
// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L63
$setup(negedge R, posedge C, 235);
// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L91
+`ifndef YOSYS
(posedge R => (Q : 1'b0)) = 883;
+`else
+ if (R) (R => Q) = 883; // Technically, this should be an edge sensitive path
+ // but for facilitating a bypass box, let's pretend it's
+ // a simple path
+`endif
// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L90
if (!R) (posedge C => (Q : D)) = 796;
endspecify
@@ -412,13 +428,20 @@ module SB_DFFR (
// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L75
$setup(negedge R, posedge C, 424);
// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L103
+`ifndef YOSYS
(posedge R => (Q : 1'b0)) = 1589;
+`else
+ if (R) (R => Q) = 1589; // Technically, this should be an edge sensitive path
+ // but for facilitating a bypass box, let's pretend it's
+ // a simple path
+`endif
// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L102
if (!R) (posedge C => (Q : D)) = 1391;
endspecify
`endif
endmodule
+(* abc9_flop, lib_whitebox *)
module SB_DFFSS (
output `SB_DFF_REG,
input C, S, D
@@ -466,6 +489,7 @@ module SB_DFFSS (
`endif
endmodule
+(* abc9_box, lib_whitebox *)
module SB_DFFS (
output `SB_DFF_REG,
input C, S, D
@@ -483,7 +507,13 @@ module SB_DFFS (
// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L63
$setup(negedge S, posedge C, 160);
// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L91
+`ifndef YOSYS
(posedge S => (Q : 1'b1)) = 599;
+`else
+ if (S) (S => Q) = 599; // Technically, this should be an edge sensitive path
+ // but for facilitating a bypass box, let's pretend it's
+ // a simple path
+`endif
// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L90
if (!S) (posedge C => (Q : D)) = 540;
endspecify
@@ -496,7 +526,13 @@ module SB_DFFS (
// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L63
$setup(negedge S, posedge C, 235);
// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L91
+`ifndef YOSYS
(posedge S => (Q : 1'b1)) = 883;
+`else
+ if (S) (S => Q) = 883; // Technically, this should be an edge sensitive path
+ // but for facilitating a bypass box, let's pretend it's
+ // a simple path
+`endif
// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L90
if (!S) (posedge C => (Q : D)) = 796;
endspecify
@@ -509,13 +545,20 @@ module SB_DFFS (
// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L75
$setup(negedge S, posedge C, 424);
// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L103
+`ifndef YOSYS
(posedge S => (Q : 1'b1)) = 1589;
+`else
+ if (S) (S => Q) = 1589; // Technically, this should be an edge sensitive path
+ // but for facilitating a bypass box, let's pretend it's
+ // a simple path
+`endif
// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L102
if (!S) (posedge C => (Q : D)) = 1391;
endspecify
`endif
endmodule
+(* abc9_flop, lib_whitebox *)
module SB_DFFESR (
output `SB_DFF_REG,
input C, E, R, D
@@ -571,6 +614,7 @@ module SB_DFFESR (
`endif
endmodule
+(* abc9_box, lib_whitebox *)
module SB_DFFER (
output `SB_DFF_REG,
input C, E, R, D
@@ -590,7 +634,13 @@ module SB_DFFER (
// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L63
$setup(negedge R, posedge C, 160);
// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L91
+`ifndef YOSYS
(posedge R => (Q : 1'b0)) = 599;
+`else
+ if (R) (R => Q) = 599; // Technically, this should be an edge sensitive path
+ // but for facilitating a bypass box, let's pretend it's
+ // a simple path
+`endif
// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L90
if (E && !R) (posedge C => (Q : D)) = 540;
endspecify
@@ -605,7 +655,13 @@ module SB_DFFER (
// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L63
$setup(negedge R, posedge C, 235);
// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L91
+`ifndef YOSYS
(posedge R => (Q : 1'b0)) = 883;
+`else
+ if (R) (R => Q) = 883; // Technically, this should be an edge sensitive path
+ // but for facilitating a bypass box, let's pretend it's
+ // a simple path
+`endif
// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L90
if (E && !R) (posedge C => (Q : D)) = 796;
endspecify
@@ -620,13 +676,20 @@ module SB_DFFER (
// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L75
$setup(negedge R, posedge C, 424);
// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L103
+`ifndef YOSYS
(posedge R => (Q : 1'b0)) = 1589;
+`else
+ if (R) (R => Q) = 1589; // Technically, this should be an edge sensitive path
+ // but for facilitating a bypass box, let's pretend it's
+ // a simple path
+`endif
// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L102
if (E && !R) (posedge C => (Q : D)) = 1391;
endspecify
`endif
endmodule
+(* abc9_flop, lib_whitebox *)
module SB_DFFESS (
output `SB_DFF_REG,
input C, E, S, D
@@ -682,6 +745,7 @@ module SB_DFFESS (
`endif
endmodule
+(* abc9_box, lib_whitebox *)
module SB_DFFES (
output `SB_DFF_REG,
input C, E, S, D
@@ -701,7 +765,13 @@ module SB_DFFES (
// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L63
$setup(posedge S, posedge C, 160);
// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L91
+`ifndef YOSYS
(posedge S => (Q : 1'b1)) = 599;
+`else
+ if (S) (S => Q) = 599; // Technically, this should be an edge sensitive path
+ // but for facilitating a bypass box, let's pretend it's
+ // a simple path
+`endif
// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L90
if (E && !S) (posedge C => (Q : D)) = 540;
endspecify
@@ -716,7 +786,13 @@ module SB_DFFES (
// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L63
$setup(posedge S, posedge C, 235);
// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L91
+`ifndef YOSYS
(posedge S => (Q : 1'b1)) = 883;
+`else
+ if (S) (S => Q) = 883; // Technically, this should be an edge sensitive path
+ // but for facilitating a bypass box, let's pretend it's
+ // a simple path
+`endif
// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L90
if (E && !S) (posedge C => (Q : D)) = 796;
endspecify
@@ -731,7 +807,13 @@ module SB_DFFES (
// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L75
$setup(posedge S, posedge C, 424);
// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L103
+`ifndef YOSYS
(posedge S => (Q : 1'b1)) = 1589;
+`else
+ if (S) (S => Q) = 1589; // Technically, this should be an edge sensitive path
+ // but for facilitating a bypass box, let's pretend it's
+ // a simple path
+`endif
// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L102
if (E && !S) (posedge C => (Q : D)) = 1391;
endspecify
@@ -740,6 +822,7 @@ endmodule
// Negative Edge SiliconBlue FF Cells
+(* abc9_flop, lib_whitebox *)
module SB_DFFN (
output `SB_DFF_REG,
input C, D
@@ -775,6 +858,7 @@ module SB_DFFN (
`endif
endmodule
+(* abc9_flop, lib_whitebox *)
module SB_DFFNE (
output `SB_DFF_REG,
input C, E, D
@@ -817,6 +901,7 @@ module SB_DFFNE (
`endif
endmodule
+(* abc9_flop, lib_whitebox *)
module SB_DFFNSR (
output `SB_DFF_REG,
input C, R, D
@@ -864,6 +949,7 @@ module SB_DFFNSR (
`endif
endmodule
+(* abc9_flop, lib_whitebox *)
module SB_DFFNR (
output `SB_DFF_REG,
input C, R, D
@@ -881,7 +967,13 @@ module SB_DFFNR (
// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L63
$setup(negedge R, negedge C, 160);
// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L91
+`ifndef YOSYS
(posedge R => (Q : 1'b0)) = 599;
+`else
+ if (R) (R => Q) = 599; // Technically, this should be an edge sensitive path
+ // but for facilitating a bypass box, let's pretend it's
+ // a simple path
+`endif
// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L90
if (!R) (negedge C => (Q : D)) = 540;
endspecify
@@ -894,7 +986,13 @@ module SB_DFFNR (
// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L63
$setup(negedge R, negedge C, 235);
// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L91
+`ifndef YOSYS
(posedge R => (Q : 1'b0)) = 883;
+`else
+ if (R) (R => Q) = 883; // Technically, this should be an edge sensitive path
+ // but for facilitating a bypass box, let's pretend it's
+ // a simple path
+`endif
// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L90
if (!R) (negedge C => (Q : D)) = 796;
endspecify
@@ -907,13 +1005,20 @@ module SB_DFFNR (
// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L75
$setup(negedge R, negedge C, 424);
// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L103
+`ifndef YOSYS
(posedge R => (Q : 1'b0)) = 1589;
+`else
+ if (R) (R => Q) = 1589; // Technically, this should be an edge sensitive path
+ // but for facilitating a bypass box, let's pretend it's
+ // a simple path
+`endif
// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L102
if (!R) (negedge C => (Q : D)) = 1391;
endspecify
`endif
endmodule
+(* abc9_flop, lib_whitebox *)
module SB_DFFNSS (
output `SB_DFF_REG,
input C, S, D
@@ -961,6 +1066,7 @@ module SB_DFFNSS (
`endif
endmodule
+(* abc9_box, lib_whitebox *)
module SB_DFFNS (
output `SB_DFF_REG,
input C, S, D
@@ -978,7 +1084,13 @@ module SB_DFFNS (
// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L63
$setup(negedge S, negedge C, 160);
// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L91
+`ifndef YOSYS
(posedge S => (Q : 1'b1)) = 599;
+`else
+ if (S) (S => Q) = 599; // Technically, this should be an edge sensitive path
+ // but for facilitating a bypass box, let's pretend it's
+ // a simple path
+`endif
// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L90
if (!S) (negedge C => (Q : D)) = 540;
endspecify
@@ -991,7 +1103,13 @@ module SB_DFFNS (
// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L63
$setup(negedge S, negedge C, 235);
// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L91
+`ifndef YOSYS
(posedge S => (Q : 1'b1)) = 883;
+`else
+ if (S) (S => Q) = 883; // Technically, this should be an edge sensitive path
+ // but for facilitating a bypass box, let's pretend it's
+ // a simple path
+`endif
// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L90
if (!S) (negedge C => (Q : D)) = 796;
endspecify
@@ -1004,13 +1122,20 @@ module SB_DFFNS (
// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L75
$setup(negedge S, negedge C, 424);
// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L103
+`ifndef YOSYS
(posedge S => (Q : 1'b1)) = 1589;
+`else
+ if (S) (S => Q) = 1589; // Technically, this should be an edge sensitive path
+ // but for facilitating a bypass box, let's pretend it's
+ // a simple path
+`endif
// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L102
if (!S) (negedge C => (Q : D)) = 1391;
endspecify
`endif
endmodule
+(* abc9_flop, lib_whitebox *)
module SB_DFFNESR (
output `SB_DFF_REG,
input C, E, R, D
@@ -1066,6 +1191,7 @@ module SB_DFFNESR (
`endif
endmodule
+(* abc9_box, lib_whitebox *)
module SB_DFFNER (
output `SB_DFF_REG,
input C, E, R, D
@@ -1085,7 +1211,13 @@ module SB_DFFNER (
// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L63
$setup(R, negedge C, 2160);
// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L91
+`ifndef YOSYS
(posedge R => (Q : 1'b0)) = 599;
+`else
+ if (R) (R => Q) = 599; // Technically, this should be an edge sensitive path
+ // but for facilitating a bypass box, let's pretend it's
+ // a simple path
+`endif
// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L90
if (E && !R) (negedge C => (Q : D)) = 540;
endspecify
@@ -1100,7 +1232,13 @@ module SB_DFFNER (
// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L63
$setup(R, negedge C, 235);
// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L91
+`ifndef YOSYS
(posedge R => (Q : 1'b0)) = 883;
+`else
+ if (R) (R => Q) = 883; // Technically, this should be an edge sensitive path
+ // but for facilitating a bypass box, let's pretend it's
+ // a simple path
+`endif
// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L90
if (E && !R) (negedge C => (Q : D)) = 796;
endspecify
@@ -1115,13 +1253,20 @@ module SB_DFFNER (
// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L75
$setup(negedge R, negedge C, 424);
// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L103
+`ifndef YOSYS
(posedge R => (Q : 1'b0)) = 1589;
+`else
+ if (R) (R => Q) = 1589; // Technically, this should be an edge sensitive path
+ // but for facilitating a bypass box, let's pretend it's
+ // a simple path
+`endif
// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L102
if (E && !R) (negedge C => (Q : D)) = 1391;
endspecify
`endif
endmodule
+(* abc9_flop, lib_whitebox *)
module SB_DFFNESS (
output `SB_DFF_REG,
input C, E, S, D
@@ -1177,6 +1322,7 @@ module SB_DFFNESS (
`endif
endmodule
+(* abc9_box, lib_whitebox *)
module SB_DFFNES (
output `SB_DFF_REG,
input C, E, S, D
@@ -1196,7 +1342,14 @@ module SB_DFFNES (
// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L63
$setup(negedge S, negedge C, 160);
// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L91
+`ifndef YOSYS
(posedge S => (Q : 1'b1)) = 599;
+`else
+ if (S) (S => Q) = 599; // Technically, this should be an edge sensitive path
+ // but for facilitating a bypass box, let's pretend it's
+ // a simple path
+`endif
+
// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L90
if (E && !S) (negedge C => (Q : D)) = 540;
endspecify
@@ -1211,7 +1364,13 @@ module SB_DFFNES (
// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L63
$setup(negedge S, negedge C, 235);
// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L91
+`ifndef YOSYS
(posedge S => (Q : 1'b1)) = 883;
+`else
+ if (S) (S => Q) = 883; // Technically, this should be an edge sensitive path
+ // but for facilitating a bypass box, let's pretend it's
+ // a simple path
+`endif
// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L90
if (E && !S) (negedge C => (Q : D)) = 796;
endspecify
@@ -1226,7 +1385,13 @@ module SB_DFFNES (
// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L75
$setup(negedge S, negedge C, 424);
// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L103
+`ifndef YOSYS
(posedge S => (Q : 1'b1)) = 1589;
+`else
+ if (S) (S => Q) = 1589; // Technically, this should be an edge sensitive path
+ // but for facilitating a bypass box, let's pretend it's
+ // a simple path
+`endif
// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L102
if (E && !S) (negedge C => (Q : D)) = 1391;
endspecify
@@ -2343,7 +2508,7 @@ module SB_SPRAM256KA (
always @(negedge POWEROFF) begin
for (i = 0; i <= 16383; i = i+1)
- mem[i] = 'bx;
+ mem[i] = 16'bx;
end
always @(posedge CLOCK, posedge off) begin
@@ -2351,17 +2516,17 @@ module SB_SPRAM256KA (
DATAOUT <= 0;
end else
if (STANDBY) begin
- DATAOUT <= 'bx;
+ DATAOUT <= 16'bx;
end else
if (CHIPSELECT) begin
if (!WREN) begin
DATAOUT <= mem[ADDRESS];
end else begin
- if (MASKWREN[0]) mem[ADDRESS][ 3: 0] = DATAIN[ 3: 0];
- if (MASKWREN[1]) mem[ADDRESS][ 7: 4] = DATAIN[ 7: 4];
- if (MASKWREN[2]) mem[ADDRESS][11: 8] = DATAIN[11: 8];
- if (MASKWREN[3]) mem[ADDRESS][15:12] = DATAIN[15:12];
- DATAOUT <= 'bx;
+ if (MASKWREN[0]) mem[ADDRESS][ 3: 0] <= DATAIN[ 3: 0];
+ if (MASKWREN[1]) mem[ADDRESS][ 7: 4] <= DATAIN[ 7: 4];
+ if (MASKWREN[2]) mem[ADDRESS][11: 8] <= DATAIN[11: 8];
+ if (MASKWREN[3]) mem[ADDRESS][15:12] <= DATAIN[15:12];
+ DATAOUT <= 16'bx;
end
end
end
@@ -2723,6 +2888,7 @@ module SB_IO_OD (
`endif
endmodule
+//(* abc9_box, lib_whitebox *) // TODO
module SB_MAC16 (
input CLK, CE,
input [15:0] C, A, B, D,
diff --git a/techlibs/ice40/ff_map.v b/techlibs/ice40/ff_map.v
new file mode 100644
index 000000000..990cd74f1
--- /dev/null
+++ b/techlibs/ice40/ff_map.v
@@ -0,0 +1,28 @@
+module \$_DFF_N_ (input D, C, output Q); SB_DFFN _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C)); endmodule
+module \$_DFF_P_ (input D, C, output Q); SB_DFF _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C)); endmodule
+
+module \$_DFFE_NN_ (input D, C, E, output Q); SB_DFFNE _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .E(!E)); endmodule
+module \$_DFFE_PN_ (input D, C, E, output Q); SB_DFFE _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .E(!E)); endmodule
+
+module \$_DFFE_NP_ (input D, C, E, output Q); SB_DFFNE _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .E(E)); endmodule
+module \$_DFFE_PP_ (input D, C, E, output Q); SB_DFFE _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .E(E)); endmodule
+
+module \$_DFF_NN0_ (input D, C, R, output Q); SB_DFFNR _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .R(!R)); endmodule
+module \$_DFF_NN1_ (input D, C, R, output Q); SB_DFFNS _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .S(!R)); endmodule
+module \$_DFF_PN0_ (input D, C, R, output Q); SB_DFFR _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .R(!R)); endmodule
+module \$_DFF_PN1_ (input D, C, R, output Q); SB_DFFS _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .S(!R)); endmodule
+
+module \$_DFF_NP0_ (input D, C, R, output Q); SB_DFFNR _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .R(R)); endmodule
+module \$_DFF_NP1_ (input D, C, R, output Q); SB_DFFNS _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .S(R)); endmodule
+module \$_DFF_PP0_ (input D, C, R, output Q); SB_DFFR _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .R(R)); endmodule
+module \$_DFF_PP1_ (input D, C, R, output Q); SB_DFFS _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .S(R)); endmodule
+
+module \$_DFFE_NN0P_ (input D, C, E, R, output Q); SB_DFFNER _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .E(E), .R(!R)); endmodule
+module \$_DFFE_NN1P_ (input D, C, E, R, output Q); SB_DFFNES _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .E(E), .S(!R)); endmodule
+module \$_DFFE_PN0P_ (input D, C, E, R, output Q); SB_DFFER _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .E(E), .R(!R)); endmodule
+module \$_DFFE_PN1P_ (input D, C, E, R, output Q); SB_DFFES _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .E(E), .S(!R)); endmodule
+
+module \$_DFFE_NP0P_ (input D, C, E, R, output Q); SB_DFFNER _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .E(E), .R(R)); endmodule
+module \$_DFFE_NP1P_ (input D, C, E, R, output Q); SB_DFFNES _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .E(E), .S(R)); endmodule
+module \$_DFFE_PP0P_ (input D, C, E, R, output Q); SB_DFFER _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .E(E), .R(R)); endmodule
+module \$_DFFE_PP1P_ (input D, C, E, R, output Q); SB_DFFES _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .E(E), .S(R)); endmodule
diff --git a/techlibs/ice40/ice40_braminit.cc b/techlibs/ice40/ice40_braminit.cc
index 936c189ea..e5d1f7e24 100644
--- a/techlibs/ice40/ice40_braminit.cc
+++ b/techlibs/ice40/ice40_braminit.cc
@@ -128,7 +128,7 @@ static void run_ice40_braminit(Module *module)
struct Ice40BRAMInitPass : public Pass {
Ice40BRAMInitPass() : Pass("ice40_braminit", "iCE40: perform SB_RAM40_4K initialization from file") { }
- void help() YS_OVERRIDE
+ void help() override
{
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
log("\n");
@@ -138,7 +138,7 @@ struct Ice40BRAMInitPass : public Pass {
log("parameter and converts it into the required INIT_x attributes\n");
log("\n");
}
- void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
+ void execute(std::vector<std::string> args, RTLIL::Design *design) override
{
log_header(design, "Executing ICE40_BRAMINIT pass.\n");
diff --git a/techlibs/ice40/ice40_ffinit.cc b/techlibs/ice40/ice40_ffinit.cc
index d7715135e..2eef3fa93 100644
--- a/techlibs/ice40/ice40_ffinit.cc
+++ b/techlibs/ice40/ice40_ffinit.cc
@@ -25,7 +25,7 @@ PRIVATE_NAMESPACE_BEGIN
struct Ice40FfinitPass : public Pass {
Ice40FfinitPass() : Pass("ice40_ffinit", "iCE40: handle FF init values") { }
- void help() YS_OVERRIDE
+ void help() override
{
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
log("\n");
@@ -35,7 +35,7 @@ struct Ice40FfinitPass : public Pass {
log("nonzero init values.\n");
log("\n");
}
- void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
+ void execute(std::vector<std::string> args, RTLIL::Design *design) override
{
log_header(design, "Executing ICE40_FFINIT pass (implement FF init values).\n");
diff --git a/techlibs/ice40/ice40_ffssr.cc b/techlibs/ice40/ice40_ffssr.cc
index ffb8c74b1..492029b77 100644
--- a/techlibs/ice40/ice40_ffssr.cc
+++ b/techlibs/ice40/ice40_ffssr.cc
@@ -25,7 +25,7 @@ PRIVATE_NAMESPACE_BEGIN
struct Ice40FfssrPass : public Pass {
Ice40FfssrPass() : Pass("ice40_ffssr", "iCE40: merge synchronous set/reset into FF cells") { }
- void help() YS_OVERRIDE
+ void help() override
{
log("\n");
log(" ice40_ffssr [options] [selection]\n");
@@ -33,7 +33,7 @@ struct Ice40FfssrPass : public Pass {
log("Merge synchronous set/reset $_MUX_ cells into iCE40 FFs.\n");
log("\n");
}
- void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
+ void execute(std::vector<std::string> args, RTLIL::Design *design) override
{
log_header(design, "Executing ICE40_FFSSR pass (merge synchronous set/reset into FF cells).\n");
diff --git a/techlibs/ice40/ice40_opt.cc b/techlibs/ice40/ice40_opt.cc
index 18c1a58cf..1a70fa8c0 100644
--- a/techlibs/ice40/ice40_opt.cc
+++ b/techlibs/ice40/ice40_opt.cc
@@ -203,7 +203,7 @@ static void run_ice40_opts(Module *module)
struct Ice40OptPass : public Pass {
Ice40OptPass() : Pass("ice40_opt", "iCE40: perform simple optimizations") { }
- void help() YS_OVERRIDE
+ void help() override
{
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
log("\n");
@@ -220,7 +220,7 @@ struct Ice40OptPass : public Pass {
log(" while <changed design>\n");
log("\n");
}
- void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
+ void execute(std::vector<std::string> args, RTLIL::Design *design) override
{
string opt_expr_args = "-mux_undef -undriven";
diff --git a/techlibs/ice40/synth_ice40.cc b/techlibs/ice40/synth_ice40.cc
index 6e05ab0b2..6464368eb 100644
--- a/techlibs/ice40/synth_ice40.cc
+++ b/techlibs/ice40/synth_ice40.cc
@@ -29,14 +29,14 @@ struct SynthIce40Pass : public ScriptPass
{
SynthIce40Pass() : ScriptPass("synth_ice40", "synthesis for iCE40 FPGAs") { }
- void on_register() YS_OVERRIDE
+ void on_register() override
{
RTLIL::constpad["synth_ice40.abc9.hx.W"] = "250";
RTLIL::constpad["synth_ice40.abc9.lp.W"] = "400";
RTLIL::constpad["synth_ice40.abc9.u.W"] = "750";
}
- void help() YS_OVERRIDE
+ void help() override
{
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
log("\n");
@@ -71,6 +71,9 @@ struct SynthIce40Pass : public ScriptPass
log(" -noflatten\n");
log(" do not flatten design before synthesis\n");
log("\n");
+ log(" -dff\n");
+ log(" run 'abc'/'abc9' with -dff option\n");
+ log("\n");
log(" -retime\n");
log(" run 'abc' with '-dff -D 1' options\n");
log("\n");
@@ -113,10 +116,10 @@ struct SynthIce40Pass : public ScriptPass
}
string top_opt, blif_file, edif_file, json_file, device_opt;
- bool nocarry, nodffe, nobram, dsp, flatten, retime, noabc, abc2, vpr, abc9, flowmap;
+ bool nocarry, nodffe, nobram, dsp, flatten, retime, noabc, abc2, vpr, abc9, dff, flowmap;
int min_ce_use;
- void clear_flags() YS_OVERRIDE
+ void clear_flags() override
{
top_opt = "-auto-top";
blif_file = "";
@@ -137,7 +140,7 @@ struct SynthIce40Pass : public ScriptPass
device_opt = "hx";
}
- void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
+ void execute(std::vector<std::string> args, RTLIL::Design *design) override
{
string run_from, run_to;
clear_flags();
@@ -221,6 +224,10 @@ struct SynthIce40Pass : public ScriptPass
abc9 = true;
continue;
}
+ if (args[argidx] == "-dff") {
+ dff = true;
+ continue;
+ }
if (args[argidx] == "-device" && argidx+1 < args.size()) {
device_opt = args[++argidx];
continue;
@@ -255,7 +262,7 @@ struct SynthIce40Pass : public ScriptPass
log_pop();
}
- void script() YS_OVERRIDE
+ void script() override
{
std::string define;
if (device_opt == "lp")
@@ -354,7 +361,9 @@ struct SynthIce40Pass : public ScriptPass
run(stringf("dff2dffe -unmap-mince %d", min_ce_use));
run("simplemap t:$dff");
}
- run("techmap -D NO_LUT -D NO_ADDER -map +/ice40/cells_map.v");
+ if ((abc9 && dff) || help_mode)
+ run("zinit -all w:* t:$_DFF_?_ t:$_DFFE_??_ t:$_SDFF*", "(only if -abc9 and -dff");
+ run("techmap -map +/ice40/ff_map.v");
run("opt_expr -mux_undef");
run("simplemap");
run("ice40_ffinit");
@@ -378,7 +387,7 @@ struct SynthIce40Pass : public ScriptPass
}
if (!noabc) {
if (abc9) {
- run("read_verilog " + define + " -icells -lib -specify +/abc9_model.v +/ice40/abc9_model.v");
+ run("read_verilog " + define + " -icells -lib -specify +/ice40/abc9_model.v");
std::string abc9_opts;
std::string k = "synth_ice40.abc9.W";
if (active_design && active_design->scratchpad.count(k))
@@ -387,24 +396,25 @@ struct SynthIce40Pass : public ScriptPass
k = stringf("synth_ice40.abc9.%s.W", device_opt.c_str());
abc9_opts += stringf(" -W %s", RTLIL::constpad.at(k).c_str());
}
+ if (dff)
+ abc9_opts += " -dff";
run("abc9 " + abc9_opts);
}
else
- run("abc -dress -lut 4", "(skip if -noabc)");
+ run(stringf("abc -dress -lut 4 %s", dff ? "-dff" : ""), "(skip if -noabc)");
}
run("ice40_wrapcarry -unwrap");
- run("techmap -D NO_LUT -map +/ice40/cells_map.v");
+ run("techmap -map +/ice40/ff_map.v");
run("clean");
run("opt_lut -dlogic SB_CARRY:I0=2:I1=1:CI=0");
}
if (check_label("map_cells"))
{
- if (vpr)
- run("techmap -D NO_LUT -map +/ice40/cells_map.v");
- else
- run("techmap -map +/ice40/cells_map.v", "(with -D NO_LUT in vpr mode)");
-
+ if (help_mode)
+ run("techmap -map +/ice40/cells_map.v", "(skip if -vpr)");
+ else if (!vpr)
+ run("techmap -map +/ice40/cells_map.v");
run("clean");
}
diff --git a/techlibs/intel/arria10gx/cells_arith.v b/techlibs/intel/arria10gx/cells_arith.v
index 89fb4561f..6a52a0f95 100644
--- a/techlibs/intel/arria10gx/cells_arith.v
+++ b/techlibs/intel/arria10gx/cells_arith.v
@@ -26,8 +26,11 @@ module _80_altera_a10gx_alu (A, B, CI, BI, X, Y, CO);
parameter B_WIDTH = 1;
parameter Y_WIDTH = 1;
+ (* force_downto *)
input [A_WIDTH-1:0] A;
+ (* force_downto *)
input [B_WIDTH-1:0] B;
+ (* force_downto *)
output [Y_WIDTH-1:0] X, Y;
input CI, BI;
@@ -36,11 +39,14 @@ module _80_altera_a10gx_alu (A, B, CI, BI, X, Y, CO);
wire _TECHMAP_FAIL_ = Y_WIDTH <= 4;
+ (* force_downto *)
wire [Y_WIDTH-1:0] A_buf, B_buf;
\$pos #(.A_SIGNED(A_SIGNED), .A_WIDTH(A_WIDTH), .Y_WIDTH(Y_WIDTH)) A_conv (.A(A), .Y(A_buf));
\$pos #(.A_SIGNED(B_SIGNED), .A_WIDTH(B_WIDTH), .Y_WIDTH(Y_WIDTH)) B_conv (.A(B), .Y(B_buf));
+ (* force_downto *)
wire [Y_WIDTH-1:0] AA = A_buf;
+ (* force_downto *)
wire [Y_WIDTH-1:0] BB = BI ? ~B_buf : B_buf;
//wire [Y_WIDTH:0] C = {CO, CI};
wire [Y_WIDTH+1:0] COx;
diff --git a/techlibs/intel/arria10gx/cells_map.v b/techlibs/intel/arria10gx/cells_map.v
index 1430e8551..83f5881da 100644
--- a/techlibs/intel/arria10gx/cells_map.v
+++ b/techlibs/intel/arria10gx/cells_map.v
@@ -30,6 +30,7 @@ endmodule
module \$lut (A, Y);
parameter WIDTH = 0;
parameter LUT = 0;
+ (* force_downto *)
input [WIDTH-1:0] A;
output Y;
generate
diff --git a/techlibs/intel/cyclone10lp/cells_arith.v b/techlibs/intel/cyclone10lp/cells_arith.v
index 5ae8d6cea..d8c46e865 100644
--- a/techlibs/intel/cyclone10lp/cells_arith.v
+++ b/techlibs/intel/cyclone10lp/cells_arith.v
@@ -26,8 +26,11 @@ module _80_altera_a10gx_alu (A, B, CI, BI, X, Y, CO);
parameter B_WIDTH = 1;
parameter Y_WIDTH = 1;
+ (* force_downto *)
input [A_WIDTH-1:0] A;
+ (* force_downto *)
input [B_WIDTH-1:0] B;
+ (* force_downto *)
output [Y_WIDTH-1:0] X, Y;
input CI, BI;
@@ -36,11 +39,14 @@ module _80_altera_a10gx_alu (A, B, CI, BI, X, Y, CO);
wire _TECHMAP_FAIL_ = Y_WIDTH <= 4;
+ (* force_downto *)
wire [Y_WIDTH-1:0] A_buf, B_buf;
\$pos #(.A_SIGNED(A_SIGNED), .A_WIDTH(A_WIDTH), .Y_WIDTH(Y_WIDTH)) A_conv (.A(A), .Y(A_buf));
\$pos #(.A_SIGNED(B_SIGNED), .A_WIDTH(B_WIDTH), .Y_WIDTH(Y_WIDTH)) B_conv (.A(B), .Y(B_buf));
+ (* force_downto *)
wire [Y_WIDTH-1:0] AA = A_buf;
+ (* force_downto *)
wire [Y_WIDTH-1:0] BB = BI ? ~B_buf : B_buf;
//wire [Y_WIDTH:0] C = {CO, CI};
wire [Y_WIDTH+1:0] COx;
diff --git a/techlibs/intel/cyclone10lp/cells_map.v b/techlibs/intel/cyclone10lp/cells_map.v
index c2f6f403c..25d73711c 100644
--- a/techlibs/intel/cyclone10lp/cells_map.v
+++ b/techlibs/intel/cyclone10lp/cells_map.v
@@ -48,7 +48,7 @@ module \$_DFF_PP0_ (input D, C, R, output Q);
dffeas #(.is_wysiwyg(WYSIWYG), .power_up(power_up)) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(C), .clrn(R_i), .prn(1'b1), .ena(1'b1), .asdata(1'b0), .aload(1'b0), .sclr(1'b0), .sload(1'b0));
endmodule
-module \$__DFFE_PP0 (input D, C, E, R, output Q);
+module \$_DFFE_PP0P_ (input D, C, E, R, output Q);
parameter WYSIWYG="TRUE";
parameter power_up=1'bx;
wire E_i = ~ E;
@@ -71,6 +71,7 @@ endmodule
module \$lut (A, Y);
parameter WIDTH = 0;
parameter LUT = 0;
+ (* force_downto *)
input [WIDTH-1:0] A;
output Y;
generate
diff --git a/techlibs/intel/cycloneiv/cells_arith.v b/techlibs/intel/cycloneiv/cells_arith.v
index 010a4b5da..f7bc3cd65 100644
--- a/techlibs/intel/cycloneiv/cells_arith.v
+++ b/techlibs/intel/cycloneiv/cells_arith.v
@@ -70,8 +70,11 @@ module _80_cycloneiv_alu (A, B, CI, BI, X, Y, CO);
parameter B_WIDTH = 1;
parameter Y_WIDTH = 1;
+ (* force_downto *)
input [A_WIDTH-1:0] A;
+ (* force_downto *)
input [B_WIDTH-1:0] B;
+ (* force_downto *)
output [Y_WIDTH-1:0] X, Y;
input CI, BI;
@@ -79,11 +82,14 @@ module _80_cycloneiv_alu (A, B, CI, BI, X, Y, CO);
wire _TECHMAP_FAIL_ = Y_WIDTH < 6;
+ (* force_downto *)
wire [Y_WIDTH-1:0] A_buf, B_buf;
\$pos #(.A_SIGNED(A_SIGNED), .A_WIDTH(A_WIDTH), .Y_WIDTH(Y_WIDTH)) A_conv (.A(A), .Y(A_buf));
\$pos #(.A_SIGNED(B_SIGNED), .A_WIDTH(B_WIDTH), .Y_WIDTH(Y_WIDTH)) B_conv (.A(B), .Y(B_buf));
+ (* force_downto *)
wire [Y_WIDTH-1:0] AA = A_buf;
+ (* force_downto *)
wire [Y_WIDTH-1:0] BB = BI ? ~B_buf : B_buf;
wire [Y_WIDTH:0] C = {CO, CI};
diff --git a/techlibs/intel/cycloneiv/cells_map.v b/techlibs/intel/cycloneiv/cells_map.v
index 191488430..56d32e586 100644
--- a/techlibs/intel/cycloneiv/cells_map.v
+++ b/techlibs/intel/cycloneiv/cells_map.v
@@ -48,7 +48,7 @@ module \$_DFF_PP0_ (input D, C, R, output Q);
dffeas #(.is_wysiwyg(WYSIWYG), .power_up(power_up)) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(C), .clrn(R_i), .prn(1'b1), .ena(1'b1), .asdata(1'b0), .aload(1'b0), .sclr(1'b0), .sload(1'b0));
endmodule
-module \$__DFFE_PP0 (input D, C, E, R, output Q);
+module \$_DFFE_PP0P_ (input D, C, E, R, output Q);
parameter WYSIWYG="TRUE";
parameter power_up=1'bx;
wire E_i = ~ E;
@@ -71,6 +71,7 @@ endmodule
module \$lut (A, Y);
parameter WIDTH = 0;
parameter LUT = 0;
+ (* force_downto *)
input [WIDTH-1:0] A;
output Y;
generate
diff --git a/techlibs/intel/cycloneive/arith_map.v b/techlibs/intel/cycloneive/arith_map.v
index 49e36aa25..a755e10db 100644
--- a/techlibs/intel/cycloneive/arith_map.v
+++ b/techlibs/intel/cycloneive/arith_map.v
@@ -66,8 +66,11 @@ module _80_cycloneive_alu (A, B, CI, BI, X, Y, CO);
parameter B_WIDTH = 1;
parameter Y_WIDTH = 1;
+ (* force_downto *)
input [A_WIDTH-1:0] A;
+ (* force_downto *)
input [B_WIDTH-1:0] B;
+ (* force_downto *)
output [Y_WIDTH-1:0] X, Y;
input CI, BI;
@@ -75,11 +78,14 @@ module _80_cycloneive_alu (A, B, CI, BI, X, Y, CO);
wire _TECHMAP_FAIL_ = Y_WIDTH < 5;
+ (* force_downto *)
wire [Y_WIDTH-1:0] A_buf, B_buf;
\$pos #(.A_SIGNED(A_SIGNED), .A_WIDTH(A_WIDTH), .Y_WIDTH(Y_WIDTH)) A_conv (.A(A), .Y(A_buf));
\$pos #(.A_SIGNED(B_SIGNED), .A_WIDTH(B_WIDTH), .Y_WIDTH(Y_WIDTH)) B_conv (.A(B), .Y(B_buf));
+ (* force_downto *)
wire [Y_WIDTH-1:0] AA = A_buf;
+ (* force_downto *)
wire [Y_WIDTH-1:0] BB = BI ? ~B_buf : B_buf;
wire [Y_WIDTH:0] C = {CO, CI};
diff --git a/techlibs/intel/cycloneive/cells_map.v b/techlibs/intel/cycloneive/cells_map.v
index abeb92eef..43a1183de 100644
--- a/techlibs/intel/cycloneive/cells_map.v
+++ b/techlibs/intel/cycloneive/cells_map.v
@@ -48,7 +48,7 @@ module \$_DFF_PP0_ (input D, C, R, output Q);
dffeas #(.is_wysiwyg(WYSIWYG), .power_up(power_up)) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(C), .clrn(R_i), .prn(1'b1), .ena(1'b1), .asdata(1'b0), .aload(1'b0), .sclr(1'b0), .sload(1'b0));
endmodule
-module \$__DFFE_PP0 (input D, C, E, R, output Q);
+module \$_DFFE_PP0P_ (input D, C, E, R, output Q);
parameter WYSIWYG="TRUE";
parameter power_up=1'bx;
wire E_i = ~ E;
@@ -71,6 +71,7 @@ endmodule
module \$lut (A, Y);
parameter WIDTH = 0;
parameter LUT = 0;
+ (* force_downto *)
input [WIDTH-1:0] A;
output Y;
generate
diff --git a/techlibs/intel/cyclonev/cells_arith.v b/techlibs/intel/cyclonev/cells_arith.v
index 89fb4561f..6a52a0f95 100644
--- a/techlibs/intel/cyclonev/cells_arith.v
+++ b/techlibs/intel/cyclonev/cells_arith.v
@@ -26,8 +26,11 @@ module _80_altera_a10gx_alu (A, B, CI, BI, X, Y, CO);
parameter B_WIDTH = 1;
parameter Y_WIDTH = 1;
+ (* force_downto *)
input [A_WIDTH-1:0] A;
+ (* force_downto *)
input [B_WIDTH-1:0] B;
+ (* force_downto *)
output [Y_WIDTH-1:0] X, Y;
input CI, BI;
@@ -36,11 +39,14 @@ module _80_altera_a10gx_alu (A, B, CI, BI, X, Y, CO);
wire _TECHMAP_FAIL_ = Y_WIDTH <= 4;
+ (* force_downto *)
wire [Y_WIDTH-1:0] A_buf, B_buf;
\$pos #(.A_SIGNED(A_SIGNED), .A_WIDTH(A_WIDTH), .Y_WIDTH(Y_WIDTH)) A_conv (.A(A), .Y(A_buf));
\$pos #(.A_SIGNED(B_SIGNED), .A_WIDTH(B_WIDTH), .Y_WIDTH(Y_WIDTH)) B_conv (.A(B), .Y(B_buf));
+ (* force_downto *)
wire [Y_WIDTH-1:0] AA = A_buf;
+ (* force_downto *)
wire [Y_WIDTH-1:0] BB = BI ? ~B_buf : B_buf;
//wire [Y_WIDTH:0] C = {CO, CI};
wire [Y_WIDTH+1:0] COx;
diff --git a/techlibs/intel/cyclonev/cells_map.v b/techlibs/intel/cyclonev/cells_map.v
index f8d142bc9..8223df3c6 100644
--- a/techlibs/intel/cyclonev/cells_map.v
+++ b/techlibs/intel/cyclonev/cells_map.v
@@ -50,7 +50,7 @@ module \$_DFF_PP0_ (input D, C, R, output Q);
dffeas #(.is_wysiwyg(WYSIWYG), .power_up(power_up)) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(C), .clrn(R_i), .prn(1'b1), .ena(1'b1), .asdata(1'b0), .aload(1'b0), .sclr(1'b0), .sload(1'b0));
endmodule
-module \$__DFFE_PP0 (input D, C, E, R, output Q);
+module \$_DFFE_PP0P_ (input D, C, E, R, output Q);
parameter WYSIWYG="TRUE";
parameter power_up=1'bx;
wire E_i = ~ E;
@@ -71,6 +71,7 @@ endmodule
module \$lut (A, Y);
parameter WIDTH = 0;
parameter LUT = 0;
+ (* force_downto *)
input [WIDTH-1:0] A;
output Y;
wire VCC;
diff --git a/techlibs/intel/max10/cells_arith.v b/techlibs/intel/max10/cells_arith.v
index e2194cbd7..8529706a7 100644
--- a/techlibs/intel/max10/cells_arith.v
+++ b/techlibs/intel/max10/cells_arith.v
@@ -26,8 +26,11 @@ module _80_altera_max10_alu (A, B, CI, BI, X, Y, CO);
parameter B_WIDTH = 1;
parameter Y_WIDTH = 1;
+ (* force_downto *)
input [A_WIDTH-1:0] A;
+ (* force_downto *)
input [B_WIDTH-1:0] B;
+ (* force_downto *)
output [Y_WIDTH-1:0] X, Y;
input CI, BI;
@@ -36,11 +39,14 @@ module _80_altera_max10_alu (A, B, CI, BI, X, Y, CO);
wire _TECHMAP_FAIL_ = Y_WIDTH <= 4;
+ (* force_downto *)
wire [Y_WIDTH-1:0] A_buf, B_buf;
\$pos #(.A_SIGNED(A_SIGNED), .A_WIDTH(A_WIDTH), .Y_WIDTH(Y_WIDTH)) A_conv (.A(A), .Y(A_buf));
\$pos #(.A_SIGNED(B_SIGNED), .A_WIDTH(B_WIDTH), .Y_WIDTH(Y_WIDTH)) B_conv (.A(B), .Y(B_buf));
+ (* force_downto *)
wire [Y_WIDTH-1:0] AA = A_buf;
+ (* force_downto *)
wire [Y_WIDTH-1:0] BB = BI ? ~B_buf : B_buf;
//wire [Y_WIDTH:0] C = {CO, CI};
wire [Y_WIDTH+1:0] COx;
diff --git a/techlibs/intel/max10/cells_map.v b/techlibs/intel/max10/cells_map.v
index 6d604e072..55b393080 100644
--- a/techlibs/intel/max10/cells_map.v
+++ b/techlibs/intel/max10/cells_map.v
@@ -48,7 +48,7 @@ module \$_DFF_PP0_ (input D, C, R, output Q);
dffeas #(.is_wysiwyg(WYSIWYG), .power_up(power_up)) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(C), .clrn(R_i), .prn(1'b1), .ena(1'b1), .asdata(1'b0), .aload(1'b0), .sclr(1'b0), .sload(1'b0));
endmodule
-module \$__DFFE_PP0 (input D, C, E, R, output Q);
+module \$_DFFE_PP0P_ (input D, C, E, R, output Q);
parameter WYSIWYG="TRUE";
parameter power_up=1'bx;
wire E_i = ~ E;
@@ -71,6 +71,7 @@ endmodule
module \$lut (A, Y);
parameter WIDTH = 0;
parameter LUT = 0;
+ (* force_downto *)
input [WIDTH-1:0] A;
output Y;
generate
diff --git a/techlibs/intel/synth_intel.cc b/techlibs/intel/synth_intel.cc
index 8601ebb37..f3709498c 100644
--- a/techlibs/intel/synth_intel.cc
+++ b/techlibs/intel/synth_intel.cc
@@ -28,7 +28,7 @@ PRIVATE_NAMESPACE_BEGIN
struct SynthIntelPass : public ScriptPass {
SynthIntelPass() : ScriptPass("synth_intel", "synthesis for Intel (Altera) FPGAs.") { experimental(); }
- void help() YS_OVERRIDE
+ void help() override
{
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
log("\n");
@@ -81,7 +81,7 @@ struct SynthIntelPass : public ScriptPass {
string top_opt, family_opt, vout_file, blif_file;
bool retime, flatten, nobram, iopads;
- void clear_flags() YS_OVERRIDE
+ void clear_flags() override
{
top_opt = "-auto-top";
family_opt = "max10";
@@ -93,7 +93,7 @@ struct SynthIntelPass : public ScriptPass {
iopads = false;
}
- void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
+ void execute(std::vector<std::string> args, RTLIL::Design *design) override
{
string run_from, run_to;
clear_flags();
@@ -163,7 +163,7 @@ struct SynthIntelPass : public ScriptPass {
log_pop();
}
- void script() YS_OVERRIDE
+ void script() override
{
if (check_label("begin")) {
if (check_label("family"))
diff --git a/techlibs/intel_alm/common/alm_map.v b/techlibs/intel_alm/common/alm_map.v
index fe646c5d6..6697b2e78 100644
--- a/techlibs/intel_alm/common/alm_map.v
+++ b/techlibs/intel_alm/common/alm_map.v
@@ -3,6 +3,7 @@ module \$lut (A, Y);
parameter WIDTH = 1;
parameter LUT = 0;
+(* force_downto *)
input [WIDTH-1:0] A;
output Y;
diff --git a/techlibs/intel_alm/common/arith_alm_map.v b/techlibs/intel_alm/common/arith_alm_map.v
index ddf81d9d0..8515eeb56 100644
--- a/techlibs/intel_alm/common/arith_alm_map.v
+++ b/techlibs/intel_alm/common/arith_alm_map.v
@@ -11,17 +11,24 @@ parameter Y_WIDTH = 1;
parameter _TECHMAP_CONSTMSK_CI_ = 0;
parameter _TECHMAP_CONSTVAL_CI_ = 0;
+(* force_downto *)
input [A_WIDTH-1:0] A;
+(* force_downto *)
input [B_WIDTH-1:0] B;
input CI, BI;
+(* force_downto *)
output [Y_WIDTH-1:0] X, Y, CO;
+(* force_downto *)
wire [Y_WIDTH-1:0] A_buf, B_buf;
\$pos #(.A_SIGNED(A_SIGNED), .A_WIDTH(A_WIDTH), .Y_WIDTH(Y_WIDTH)) A_conv (.A(A), .Y(A_buf));
\$pos #(.A_SIGNED(B_SIGNED), .A_WIDTH(B_WIDTH), .Y_WIDTH(Y_WIDTH)) B_conv (.A(B), .Y(B_buf));
+(* force_downto *)
wire [Y_WIDTH-1:0] AA = A_buf;
+(* force_downto *)
wire [Y_WIDTH-1:0] BB = BI ? ~B_buf : B_buf;
+(* force_downto *)
wire [Y_WIDTH-1:0] BX = B_buf;
wire [Y_WIDTH:0] ALM_CARRY;
diff --git a/techlibs/intel_alm/synth_intel_alm.cc b/techlibs/intel_alm/synth_intel_alm.cc
index bf9e746b8..fabfc9003 100644
--- a/techlibs/intel_alm/synth_intel_alm.cc
+++ b/techlibs/intel_alm/synth_intel_alm.cc
@@ -29,7 +29,7 @@ PRIVATE_NAMESPACE_BEGIN
struct SynthIntelALMPass : public ScriptPass {
SynthIntelALMPass() : ScriptPass("synth_intel_alm", "synthesis for ALM-based Intel (Altera) FPGAs.") {}
- void help() YS_OVERRIDE
+ void help() override
{
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
log("\n");
@@ -74,7 +74,7 @@ struct SynthIntelALMPass : public ScriptPass {
string top_opt, family_opt, bram_type, vout_file;
bool flatten, quartus, nolutram, nobram;
- void clear_flags() YS_OVERRIDE
+ void clear_flags() override
{
top_opt = "-auto-top";
family_opt = "cyclonev";
@@ -86,7 +86,7 @@ struct SynthIntelALMPass : public ScriptPass {
nobram = false;
}
- void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
+ void execute(std::vector<std::string> args, RTLIL::Design *design) override
{
string run_from, run_to;
clear_flags();
@@ -153,7 +153,7 @@ struct SynthIntelALMPass : public ScriptPass {
log_pop();
}
- void script() YS_OVERRIDE
+ void script() override
{
if (help_mode) {
family_opt = "<family>";
@@ -199,7 +199,7 @@ struct SynthIntelALMPass : public ScriptPass {
}
if (check_label("map_ffs")) {
- run("dff2dffe -direct-match $_DFF_*");
+ run("dff2dffe");
// As mentioned in common/dff_sim.v, Intel flops power up to zero,
// so use `zinit` to add inverters where needed.
run("zinit");
@@ -209,7 +209,6 @@ struct SynthIntelALMPass : public ScriptPass {
}
if (check_label("map_luts")) {
- run("read_verilog -icells -specify -lib +/abc9_model.v");
run("abc9 -maxlut 6 -W 200");
run("techmap -map +/intel_alm/common/alm_map.v");
run("opt -fast");
diff --git a/techlibs/sf2/cells_map.v b/techlibs/sf2/cells_map.v
index 6ad7807d2..70f3b3b16 100644
--- a/techlibs/sf2/cells_map.v
+++ b/techlibs/sf2/cells_map.v
@@ -44,21 +44,22 @@ endmodule
// module \$_DFFE_NP_ (input D, C, E, output Q); SB_DFFNE _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .E(E)); endmodule
// module \$_DFFE_PP_ (input D, C, E, output Q); SB_DFFE _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .E(E)); endmodule
//
-// module \$__DFFE_NN0 (input D, C, E, R, output Q); SB_DFFNER _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .E(E), .R(!R)); endmodule
-// module \$__DFFE_NN1 (input D, C, E, R, output Q); SB_DFFNES _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .E(E), .S(!R)); endmodule
-// module \$__DFFE_PN0 (input D, C, E, R, output Q); SB_DFFER _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .E(E), .R(!R)); endmodule
-// module \$__DFFE_PN1 (input D, C, E, R, output Q); SB_DFFES _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .E(E), .S(!R)); endmodule
+// module \$_DFFE_NN0P_ (input D, C, E, R, output Q); SB_DFFNER _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .E(E), .R(!R)); endmodule
+// module \$_DFFE_NN1P_ (input D, C, E, R, output Q); SB_DFFNES _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .E(E), .S(!R)); endmodule
+// module \$_DFFE_PN0P_ (input D, C, E, R, output Q); SB_DFFER _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .E(E), .R(!R)); endmodule
+// module \$_DFFE_PN1P_ (input D, C, E, R, output Q); SB_DFFES _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .E(E), .S(!R)); endmodule
//
-// module \$__DFFE_NP0 (input D, C, E, R, output Q); SB_DFFNER _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .E(E), .R(R)); endmodule
-// module \$__DFFE_NP1 (input D, C, E, R, output Q); SB_DFFNES _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .E(E), .S(R)); endmodule
-// module \$__DFFE_PP0 (input D, C, E, R, output Q); SB_DFFER _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .E(E), .R(R)); endmodule
-// module \$__DFFE_PP1 (input D, C, E, R, output Q); SB_DFFES _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .E(E), .S(R)); endmodule
+// module \$_DFFE_NP0P_ (input D, C, E, R, output Q); SB_DFFNER _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .E(E), .R(R)); endmodule
+// module \$_DFFE_NP1P_ (input D, C, E, R, output Q); SB_DFFNES _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .E(E), .S(R)); endmodule
+// module \$_DFFE_PP0P_ (input D, C, E, R, output Q); SB_DFFER _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .E(E), .R(R)); endmodule
+// module \$_DFFE_PP1P_ (input D, C, E, R, output Q); SB_DFFES _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .E(E), .S(R)); endmodule
`ifndef NO_LUT
module \$lut (A, Y);
parameter WIDTH = 0;
parameter LUT = 0;
+ (* force_downto *)
input [WIDTH-1:0] A;
output Y;
diff --git a/techlibs/sf2/sf2_iobs.cc b/techlibs/sf2/sf2_iobs.cc
index 619888d38..5fd719ce5 100644
--- a/techlibs/sf2/sf2_iobs.cc
+++ b/techlibs/sf2/sf2_iobs.cc
@@ -155,7 +155,7 @@ static void handle_clkint(Module *module)
struct Sf2IobsPass : public Pass {
Sf2IobsPass() : Pass("sf2_iobs", "SF2: insert IO buffers") { }
- void help() YS_OVERRIDE
+ void help() override
{
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
log("\n");
@@ -167,7 +167,7 @@ struct Sf2IobsPass : public Pass {
log(" Insert PAD->global_net clock buffers\n");
log("\n");
}
- void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
+ void execute(std::vector<std::string> args, RTLIL::Design *design) override
{
bool clkbuf_mode = false;
diff --git a/techlibs/sf2/synth_sf2.cc b/techlibs/sf2/synth_sf2.cc
index 34a7e68be..6b2a3f9b8 100644
--- a/techlibs/sf2/synth_sf2.cc
+++ b/techlibs/sf2/synth_sf2.cc
@@ -29,7 +29,7 @@ struct SynthSf2Pass : public ScriptPass
{
SynthSf2Pass() : ScriptPass("synth_sf2", "synthesis for SmartFusion2 and IGLOO2 FPGAs") { }
- void help() YS_OVERRIDE
+ void help() override
{
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
log("\n");
@@ -78,7 +78,7 @@ struct SynthSf2Pass : public ScriptPass
string top_opt, edif_file, vlog_file, json_file;
bool flatten, retime, iobs, clkbuf;
- void clear_flags() YS_OVERRIDE
+ void clear_flags() override
{
top_opt = "-auto-top";
edif_file = "";
@@ -90,7 +90,7 @@ struct SynthSf2Pass : public ScriptPass
clkbuf = false;
}
- void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
+ void execute(std::vector<std::string> args, RTLIL::Design *design) override
{
string run_from, run_to;
clear_flags();
@@ -153,7 +153,7 @@ struct SynthSf2Pass : public ScriptPass
log_pop();
}
- void script() YS_OVERRIDE
+ void script() override
{
if (check_label("begin"))
{
diff --git a/techlibs/xilinx/Makefile.inc b/techlibs/xilinx/Makefile.inc
index 9984290a6..d4d863831 100644
--- a/techlibs/xilinx/Makefile.inc
+++ b/techlibs/xilinx/Makefile.inc
@@ -54,8 +54,6 @@ $(eval $(call add_share_file,share/xilinx,techlibs/xilinx/xc5v_dsp_map.v))
$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/xc7_dsp_map.v))
$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/xcu_dsp_map.v))
-$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/abc9_map.v))
-$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/abc9_unmap.v))
$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/abc9_model.v))
$(eval $(call add_gen_share_file,share/xilinx,techlibs/xilinx/brams_init_36.vh))
diff --git a/techlibs/xilinx/abc9_map.v b/techlibs/xilinx/abc9_map.v
deleted file mode 100644
index 81f8a1d42..000000000
--- a/techlibs/xilinx/abc9_map.v
+++ /dev/null
@@ -1,786 +0,0 @@
-/*
- * yosys -- Yosys Open SYnthesis Suite
- *
- * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
- * 2019 Eddie Hung <eddie@fpgeh.com>
- *
- * Permission to use, copy, modify, and/or distribute this software for any
- * purpose with or without fee is hereby granted, provided that the above
- * copyright notice and this permission notice appear in all copies.
- *
- * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
- * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
- * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
- * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
- * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
- * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
- *
- */
-
-// The following techmapping rules are intended to be run (with -max_iter 1)
-// before invoking the `abc9` pass in order to transform the design into
-// a format that it understands.
-
-`ifdef DFF_MODE
-// For example, (complex) flip-flops are expected to be described as an
-// combinatorial box (containing all control logic such as clock enable
-// or synchronous resets) followed by a basic D-Q flop.
-// Yosys will automatically analyse the simulation model (described in
-// cells_sim.v) and detach any $_DFF_P_ or $_DFF_N_ cells present in
-// order to extract the combinatorial control logic left behind.
-// Specifically, a simulation model similar to the one below:
-//
-// ++===================================++
-// || Sim model ||
-// || /\/\/\/\ ||
-// D -->>-----< > +------+ ||
-// R -->>-----< Comb. > |$_DFF_| ||
-// CE -->>-----< logic >-----| [NP]_|---+---->>-- Q
-// || +--< > +------+ | ||
-// || | \/\/\/\/ | ||
-// || | | ||
-// || +----------------------------+ ||
-// || ||
-// ++===================================++
-//
-// is transformed into:
-//
-// ++==================++
-// || Comb box ||
-// || ||
-// || /\/\/\/\ ||
-// D -->>-----< > ||
-// R -->>-----< Comb. > || +-----------+
-// CE -->>-----< logic >--->>-- $Q --|$__ABC9_FF_|--+-->> Q
-// abc9_ff.Q +-->>-----< > || +-----------+ |
-// | || \/\/\/\/ || |
-// | || || |
-// | ++==================++ |
-// | |
-// +-----------------------------------------------+
-//
-// The purpose of the following FD* rules are to wrap the flop with:
-// (a) a special $__ABC9_FF_ in front of the FD*'s output, indicating to abc9
-// the connectivity of its basic D-Q flop
-// (b) an optional $__ABC9_ASYNC_ cell in front of $__ABC_FF_'s output to
-// capture asynchronous behaviour
-// (c) a special abc9_ff.clock wire to capture its clock domain and polarity
-// (indicated to `abc9' so that it only performs sequential synthesis
-// (with reachability analysis) correctly on one domain at a time)
-// (d) an (* abc9_init *) attribute on the $__ABC9_FF_ cell capturing its
-// initial state
-// NOTE: in order to perform sequential synthesis, `abc9' requires that
-// the initial value of all flops be zero
-// (e) a special _TECHMAP_REPLACE_.abc9_ff.Q wire that will be used for feedback
-// into the (combinatorial) FD* cell to facilitate clock-enable behaviour
-
-module FDRE (output Q, (* techmap_autopurge *) input C, CE, D, R);
- parameter [0:0] INIT = 1'b0;
- parameter [0:0] IS_C_INVERTED = 1'b0;
- parameter [0:0] IS_D_INVERTED = 1'b0;
- parameter [0:0] IS_R_INVERTED = 1'b0;
- wire QQ, $Q;
- generate if (INIT == 1'b1) begin
- assign Q = ~QQ;
- FDSE #(
- .INIT(1'b0),
- .IS_C_INVERTED(IS_C_INVERTED),
- .IS_D_INVERTED(IS_D_INVERTED),
- .IS_S_INVERTED(IS_R_INVERTED)
- ) _TECHMAP_REPLACE_ (
- .D(~D), .Q($Q), .C(C), .CE(CE), .S(R)
- );
- end
- else begin
- assign Q = QQ;
- FDRE #(
- .INIT(1'b0),
- .IS_C_INVERTED(IS_C_INVERTED),
- .IS_D_INVERTED(IS_D_INVERTED),
- .IS_R_INVERTED(IS_R_INVERTED)
- ) _TECHMAP_REPLACE_ (
- .D(D), .Q($Q), .C(C), .CE(CE), .R(R)
- );
- end
- endgenerate
- (* abc9_init = 1'b0 *)
- $__ABC9_FF_ abc9_ff (.D($Q), .Q(QQ));
-
- // Special signals
- wire [1:0] abc9_ff.clock = {C, IS_C_INVERTED};
- wire [0:0] _TECHMAP_REPLACE_.abc9_ff.Q = QQ;
-endmodule
-module FDRE_1 (output Q, (* techmap_autopurge *) input C, CE, D, R);
- parameter [0:0] INIT = 1'b0;
- wire QQ, $Q;
- generate if (INIT == 1'b1) begin
- assign Q = ~QQ;
- FDSE_1 #(
- .INIT(1'b0)
- ) _TECHMAP_REPLACE_ (
- .D(~D), .Q($Q), .C(C), .CE(CE), .S(R)
- );
- end
- else begin
- assign Q = QQ;
- FDRE_1 #(
- .INIT(1'b0)
- ) _TECHMAP_REPLACE_ (
- .D(D), .Q($Q), .C(C), .CE(CE), .R(R)
- );
- end
- endgenerate
- (* abc9_init = 1'b0 *)
- $__ABC9_FF_ abc9_ff (.D($Q), .Q(QQ));
-
- // Special signals
- wire [1:0] abc9_ff.clock = {C, 1'b1 /* IS_C_INVERTED */};
- wire [0:0] _TECHMAP_REPLACE_.abc9_ff.Q = QQ;
-endmodule
-
-module FDSE (output Q, (* techmap_autopurge *) input C, CE, D, S);
- parameter [0:0] INIT = 1'b1;
- parameter [0:0] IS_C_INVERTED = 1'b0;
- parameter [0:0] IS_D_INVERTED = 1'b0;
- parameter [0:0] IS_S_INVERTED = 1'b0;
- wire QQ, $Q;
- generate if (INIT == 1'b1) begin
- assign Q = ~QQ;
- FDRE #(
- .INIT(1'b0),
- .IS_C_INVERTED(IS_C_INVERTED),
- .IS_D_INVERTED(IS_D_INVERTED),
- .IS_R_INVERTED(IS_S_INVERTED)
- ) _TECHMAP_REPLACE_ (
- .D(~D), .Q($Q), .C(C), .CE(CE), .R(S)
- );
- end
- else begin
- assign Q = QQ;
- FDSE #(
- .INIT(1'b0),
- .IS_C_INVERTED(IS_C_INVERTED),
- .IS_D_INVERTED(IS_D_INVERTED),
- .IS_S_INVERTED(IS_S_INVERTED)
- ) _TECHMAP_REPLACE_ (
- .D(D), .Q($Q), .C(C), .CE(CE), .S(S)
- );
- end endgenerate
- (* abc9_init = 1'b0 *)
- $__ABC9_FF_ abc9_ff (.D($Q), .Q(QQ));
-
- // Special signals
- wire [1:0] abc9_ff.clock = {C, IS_C_INVERTED};
- wire [0:0] _TECHMAP_REPLACE_.abc9_ff.Q = QQ;
-endmodule
-module FDSE_1 (output Q, (* techmap_autopurge *) input C, CE, D, S);
- parameter [0:0] INIT = 1'b1;
- wire QQ, $Q;
- generate if (INIT == 1'b1) begin
- assign Q = ~QQ;
- FDRE_1 #(
- .INIT(1'b0)
- ) _TECHMAP_REPLACE_ (
- .D(~D), .Q($Q), .C(C), .CE(CE), .R(S)
- );
- end
- else begin
- assign Q = QQ;
- FDSE_1 #(
- .INIT(1'b0)
- ) _TECHMAP_REPLACE_ (
- .D(D), .Q($Q), .C(C), .CE(CE), .S(S)
- );
- end endgenerate
- (* abc9_init = 1'b0 *)
- $__ABC9_FF_ abc9_ff (.D($Q), .Q(QQ));
-
- // Special signals
- wire [1:0] abc9_ff.clock = {C, 1'b1 /* IS_C_INVERTED */};
- wire [0:0] _TECHMAP_REPLACE_.abc9_ff.Q = QQ;
-endmodule
-
-module FDCE (output Q, (* techmap_autopurge *) input C, CE, D, CLR);
- parameter [0:0] INIT = 1'b0;
- parameter [0:0] IS_C_INVERTED = 1'b0;
- parameter [0:0] IS_D_INVERTED = 1'b0;
- parameter [0:0] IS_CLR_INVERTED = 1'b0;
- wire QQ, $Q, $QQ;
- generate if (INIT == 1'b1) begin
- assign Q = ~QQ;
- FDPE #(
- .INIT(1'b0),
- .IS_C_INVERTED(IS_C_INVERTED),
- .IS_D_INVERTED(IS_D_INVERTED),
- .IS_PRE_INVERTED(IS_CLR_INVERTED)
- ) _TECHMAP_REPLACE_ (
- .D(~D), .Q($Q), .C(C), .CE(CE), .PRE(CLR)
- // ^^^ Note that async
- // control is not directly
- // supported by abc9 but its
- // behaviour is captured by
- // $__ABC9_ASYNC1 below
- );
- // Since this is an async flop, async behaviour is dealt with here
- $__ABC9_ASYNC1 abc_async (.A($QQ), .S(CLR ^ IS_CLR_INVERTED), .Y(QQ));
- end
- else begin
- assign Q = QQ;
- FDCE #(
- .INIT(1'b0),
- .IS_C_INVERTED(IS_C_INVERTED),
- .IS_D_INVERTED(IS_D_INVERTED),
- .IS_CLR_INVERTED(IS_CLR_INVERTED)
- ) _TECHMAP_REPLACE_ (
- .D(D), .Q($Q), .C(C), .CE(CE), .CLR(CLR)
- // ^^^ Note that async
- // control is not directly
- // supported by abc9 but its
- // behaviour is captured by
- // $__ABC9_ASYNC0 below
- );
- // Since this is an async flop, async behaviour is dealt with here
- $__ABC9_ASYNC0 abc_async (.A($QQ), .S(CLR ^ IS_CLR_INVERTED), .Y(QQ));
- end endgenerate
- (* abc9_init = 1'b0 *)
- $__ABC9_FF_ abc9_ff (.D($Q), .Q($QQ));
-
- // Special signals
- wire [1:0] abc9_ff.clock = {C, IS_C_INVERTED};
- wire [0:0] _TECHMAP_REPLACE_.abc9_ff.Q = $QQ;
-endmodule
-module FDCE_1 (output Q, (* techmap_autopurge *) input C, CE, D, CLR);
- parameter [0:0] INIT = 1'b0;
- wire QQ, $Q, $QQ;
- generate if (INIT == 1'b1) begin
- assign Q = ~QQ;
- FDPE_1 #(
- .INIT(1'b0)
- ) _TECHMAP_REPLACE_ (
- .D(~D), .Q($Q), .C(C), .CE(CE), .PRE(CLR)
- // ^^^ Note that async
- // control is not directly
- // supported by abc9 but its
- // behaviour is captured by
- // $__ABC9_ASYNC1 below
- );
- $__ABC9_ASYNC1 abc_async (.A($QQ), .S(CLR), .Y(QQ));
- end
- else begin
- assign Q = QQ;
- FDCE_1 #(
- .INIT(1'b0)
- ) _TECHMAP_REPLACE_ (
- .D(D), .Q($Q), .C(C), .CE(CE), .CLR(CLR)
- // ^^^ Note that async
- // control is not directly
- // supported by abc9 but its
- // behaviour is captured by
- // $__ABC9_ASYNC0 below
- );
- $__ABC9_ASYNC0 abc_async (.A($QQ), .S(CLR), .Y(QQ));
- end endgenerate
- (* abc9_init = 1'b0 *)
- $__ABC9_FF_ abc9_ff (.D($Q), .Q($QQ));
-
- // Special signals
- wire [1:0] abc9_ff.clock = {C, 1'b1 /* IS_C_INVERTED */};
- wire [0:0] _TECHMAP_REPLACE_.abc9_ff.Q = $QQ;
-endmodule
-
-module FDPE (output Q, (* techmap_autopurge *) input C, CE, D, PRE);
- parameter [0:0] INIT = 1'b1;
- parameter [0:0] IS_C_INVERTED = 1'b0;
- parameter [0:0] IS_D_INVERTED = 1'b0;
- parameter [0:0] IS_PRE_INVERTED = 1'b0;
- wire QQ, $Q, $QQ;
- generate if (INIT == 1'b1) begin
- assign Q = ~QQ;
- FDCE #(
- .INIT(1'b0),
- .IS_C_INVERTED(IS_C_INVERTED),
- .IS_D_INVERTED(IS_D_INVERTED),
- .IS_CLR_INVERTED(IS_PRE_INVERTED),
- ) _TECHMAP_REPLACE_ (
- .D(~D), .Q($Q), .C(C), .CE(CE), .CLR(PRE)
- // ^^^ Note that async
- // control is not directly
- // supported by abc9 but its
- // behaviour is captured by
- // $__ABC9_ASYNC0 below
- );
- $__ABC9_ASYNC0 abc_async (.A($QQ), .S(PRE ^ IS_PRE_INVERTED), .Y(QQ));
- end
- else begin
- assign Q = QQ;
- FDPE #(
- .INIT(1'b0),
- .IS_C_INVERTED(IS_C_INVERTED),
- .IS_D_INVERTED(IS_D_INVERTED),
- .IS_PRE_INVERTED(IS_PRE_INVERTED),
- ) _TECHMAP_REPLACE_ (
- .D(D), .Q($Q), .C(C), .CE(CE), .PRE(PRE)
- // ^^^ Note that async
- // control is not directly
- // supported by abc9 but its
- // behaviour is captured by
- // $__ABC9_ASYNC1 below
- );
- $__ABC9_ASYNC1 abc_async (.A($QQ), .S(PRE ^ IS_PRE_INVERTED), .Y(QQ));
- end endgenerate
- (* abc9_init = 1'b0 *)
- $__ABC9_FF_ abc9_ff (.D($Q), .Q($QQ));
-
- // Special signals
- wire [1:0] abc9_ff.clock = {C, IS_C_INVERTED};
- wire [0:0] _TECHMAP_REPLACE_.abc9_ff.Q = $QQ;
-endmodule
-module FDPE_1 (output Q, (* techmap_autopurge *) input C, CE, D, PRE);
- parameter [0:0] INIT = 1'b1;
- wire QQ, $Q, $QQ;
- generate if (INIT == 1'b1) begin
- assign Q = ~QQ;
- FDCE_1 #(
- .INIT(1'b0)
- ) _TECHMAP_REPLACE_ (
- .D(~D), .Q($Q), .C(C), .CE(CE), .CLR(PRE)
- // ^^^ Note that async
- // control is not directly
- // supported by abc9 but its
- // behaviour is captured by
- // $__ABC9_ASYNC0 below
- );
- $__ABC9_ASYNC0 abc_async (.A($QQ), .S(PRE), .Y(QQ));
- end
- else begin
- assign Q = QQ;
- FDPE_1 #(
- .INIT(1'b0)
- ) _TECHMAP_REPLACE_ (
- .D(D), .Q($Q), .C(C), .CE(CE), .PRE(PRE)
- // ^^^ Note that async
- // control is not directly
- // supported by abc9 but its
- // behaviour is captured by
- // $__ABC9_ASYNC1 below
- );
- $__ABC9_ASYNC1 abc_async (.A($QQ), .S(PRE), .Y(QQ));
- end endgenerate
- (* abc9_init = 1'b0 *)
- $__ABC9_FF_ abc9_ff (.D($Q), .Q($QQ));
-
- // Special signals
- wire [1:0] abc9_ff.clock = {C, 1'b1 /* IS_C_INVERTED */};
- wire [0:0] _TECHMAP_REPLACE_.abc9_ff.Q = $QQ;
-endmodule
-`endif
-
-// Attach a (combinatorial) black-box onto the output
-// of thes LUTRAM primitives to capture their
-// asynchronous read behaviour
-module RAM32X1D (
- output DPO, SPO,
- (* techmap_autopurge *) input D,
- (* techmap_autopurge *) input WCLK,
- (* techmap_autopurge *) input WE,
- (* techmap_autopurge *) input A0, A1, A2, A3, A4,
- (* techmap_autopurge *) input DPRA0, DPRA1, DPRA2, DPRA3, DPRA4
-);
- parameter INIT = 32'h0;
- parameter IS_WCLK_INVERTED = 1'b0;
- wire $DPO, $SPO;
- RAM32X1D #(
- .INIT(INIT), .IS_WCLK_INVERTED(IS_WCLK_INVERTED)
- ) _TECHMAP_REPLACE_ (
- .DPO($DPO), .SPO($SPO),
- .D(D), .WCLK(WCLK), .WE(WE),
- .A0(A0), .A1(A1), .A2(A2), .A3(A3), .A4(A4),
- .DPRA0(DPRA0), .DPRA1(DPRA1), .DPRA2(DPRA2), .DPRA3(DPRA3), .DPRA4(DPRA4)
- );
- $__ABC9_RAM6 spo (.A($SPO), .S({1'b1, A4, A3, A2, A1, A0}), .Y(SPO));
- $__ABC9_RAM6 dpo (.A($DPO), .S({1'b1, DPRA4, DPRA3, DPRA2, DPRA1, DPRA0}), .Y(DPO));
-endmodule
-
-module RAM64X1D (
- output DPO, SPO,
- (* techmap_autopurge *) input D,
- (* techmap_autopurge *) input WCLK,
- (* techmap_autopurge *) input WE,
- (* techmap_autopurge *) input A0, A1, A2, A3, A4, A5,
- (* techmap_autopurge *) input DPRA0, DPRA1, DPRA2, DPRA3, DPRA4, DPRA5
-);
- parameter INIT = 64'h0;
- parameter IS_WCLK_INVERTED = 1'b0;
- wire $DPO, $SPO;
- RAM64X1D #(
- .INIT(INIT), .IS_WCLK_INVERTED(IS_WCLK_INVERTED)
- ) _TECHMAP_REPLACE_ (
- .DPO($DPO), .SPO($SPO),
- .D(D), .WCLK(WCLK), .WE(WE),
- .A0(A0), .A1(A1), .A2(A2), .A3(A3), .A4(A4), .A5(A5),
- .DPRA0(DPRA0), .DPRA1(DPRA1), .DPRA2(DPRA2), .DPRA3(DPRA3), .DPRA4(DPRA4), .DPRA5(DPRA5)
- );
- $__ABC9_RAM6 spo (.A($SPO), .S({A5, A4, A3, A2, A1, A0}), .Y(SPO));
- $__ABC9_RAM6 dpo (.A($DPO), .S({DPRA5, DPRA4, DPRA3, DPRA2, DPRA1, DPRA0}), .Y(DPO));
-endmodule
-
-module RAM128X1D (
- output DPO, SPO,
- (* techmap_autopurge *) input D,
- (* techmap_autopurge *) input WCLK,
- (* techmap_autopurge *) input WE,
- (* techmap_autopurge *) input [6:0] A, DPRA
-);
- parameter INIT = 128'h0;
- parameter IS_WCLK_INVERTED = 1'b0;
- wire $DPO, $SPO;
- RAM128X1D #(
- .INIT(INIT), .IS_WCLK_INVERTED(IS_WCLK_INVERTED)
- ) _TECHMAP_REPLACE_ (
- .DPO($DPO), .SPO($SPO),
- .D(D), .WCLK(WCLK), .WE(WE),
- .A(A),
- .DPRA(DPRA)
- );
- $__ABC9_RAM7 spo (.A($SPO), .S(A), .Y(SPO));
- $__ABC9_RAM7 dpo (.A($DPO), .S(DPRA), .Y(DPO));
-endmodule
-
-module RAM32M (
- output [1:0] DOA,
- output [1:0] DOB,
- output [1:0] DOC,
- output [1:0] DOD,
- (* techmap_autopurge *) input [4:0] ADDRA,
- (* techmap_autopurge *) input [4:0] ADDRB,
- (* techmap_autopurge *) input [4:0] ADDRC,
- (* techmap_autopurge *) input [4:0] ADDRD,
- (* techmap_autopurge *) input [1:0] DIA,
- (* techmap_autopurge *) input [1:0] DIB,
- (* techmap_autopurge *) input [1:0] DIC,
- (* techmap_autopurge *) input [1:0] DID,
- (* techmap_autopurge *) input WCLK,
- (* techmap_autopurge *) input WE
-);
- parameter [63:0] INIT_A = 64'h0000000000000000;
- parameter [63:0] INIT_B = 64'h0000000000000000;
- parameter [63:0] INIT_C = 64'h0000000000000000;
- parameter [63:0] INIT_D = 64'h0000000000000000;
- parameter [0:0] IS_WCLK_INVERTED = 1'b0;
- wire [1:0] $DOA, $DOB, $DOC, $DOD;
- RAM32M #(
- .INIT_A(INIT_A), .INIT_B(INIT_B), .INIT_C(INIT_C), .INIT_D(INIT_D),
- .IS_WCLK_INVERTED(IS_WCLK_INVERTED)
- ) _TECHMAP_REPLACE_ (
- .DOA($DOA), .DOB($DOB), .DOC($DOC), .DOD($DOD),
- .WCLK(WCLK), .WE(WE),
- .ADDRA(ADDRA), .ADDRB(ADDRB), .ADDRC(ADDRC), .ADDRD(ADDRD),
- .DIA(DIA), .DIB(DIB), .DIC(DIC), .DID(DID)
- );
- $__ABC9_RAM6 doa0 (.A($DOA[0]), .S({1'b1, ADDRA}), .Y(DOA[0]));
- $__ABC9_RAM6 doa1 (.A($DOA[1]), .S({1'b1, ADDRA}), .Y(DOA[1]));
- $__ABC9_RAM6 dob0 (.A($DOB[0]), .S({1'b1, ADDRB}), .Y(DOB[0]));
- $__ABC9_RAM6 dob1 (.A($DOB[1]), .S({1'b1, ADDRB}), .Y(DOB[1]));
- $__ABC9_RAM6 doc0 (.A($DOC[0]), .S({1'b1, ADDRC}), .Y(DOC[0]));
- $__ABC9_RAM6 doc1 (.A($DOC[1]), .S({1'b1, ADDRC}), .Y(DOC[1]));
- $__ABC9_RAM6 dod0 (.A($DOD[0]), .S({1'b1, ADDRD}), .Y(DOD[0]));
- $__ABC9_RAM6 dod1 (.A($DOD[1]), .S({1'b1, ADDRD}), .Y(DOD[1]));
-endmodule
-
-module RAM64M (
- output DOA,
- output DOB,
- output DOC,
- output DOD,
- (* techmap_autopurge *) input [5:0] ADDRA,
- (* techmap_autopurge *) input [5:0] ADDRB,
- (* techmap_autopurge *) input [5:0] ADDRC,
- (* techmap_autopurge *) input [5:0] ADDRD,
- (* techmap_autopurge *) input DIA,
- (* techmap_autopurge *) input DIB,
- (* techmap_autopurge *) input DIC,
- (* techmap_autopurge *) input DID,
- (* techmap_autopurge *) input WCLK,
- (* techmap_autopurge *) input WE
-);
- parameter [63:0] INIT_A = 64'h0000000000000000;
- parameter [63:0] INIT_B = 64'h0000000000000000;
- parameter [63:0] INIT_C = 64'h0000000000000000;
- parameter [63:0] INIT_D = 64'h0000000000000000;
- parameter [0:0] IS_WCLK_INVERTED = 1'b0;
- wire $DOA, $DOB, $DOC, $DOD;
- RAM64M #(
- .INIT_A(INIT_A), .INIT_B(INIT_B), .INIT_C(INIT_C), .INIT_D(INIT_D),
- .IS_WCLK_INVERTED(IS_WCLK_INVERTED)
- ) _TECHMAP_REPLACE_ (
- .DOA($DOA), .DOB($DOB), .DOC($DOC), .DOD($DOD),
- .WCLK(WCLK), .WE(WE),
- .ADDRA(ADDRA), .ADDRB(ADDRB), .ADDRC(ADDRC), .ADDRD(ADDRD),
- .DIA(DIA), .DIB(DIB), .DIC(DIC), .DID(DID)
- );
- $__ABC9_RAM6 doa (.A($DOA), .S(ADDRA), .Y(DOA));
- $__ABC9_RAM6 dob (.A($DOB), .S(ADDRB), .Y(DOB));
- $__ABC9_RAM6 doc (.A($DOC), .S(ADDRC), .Y(DOC));
- $__ABC9_RAM6 dod (.A($DOD), .S(ADDRD), .Y(DOD));
-endmodule
-
-module SRL16 (
- output Q,
- (* techmap_autopurge *) input A0, A1, A2, A3, CLK, D
-);
- parameter [15:0] INIT = 16'h0000;
- wire $Q;
- SRL16 #(
- .INIT(INIT),
- ) _TECHMAP_REPLACE_ (
- .Q($Q),
- .A0(A0), .A1(A1), .A2(A2), .A3(A3), .CLK(CLK), .D(D)
- );
- $__ABC9_RAM6 q (.A($Q), .S({1'b1, A3, A2, A1, A0, 1'b1}), .Y(Q));
-endmodule
-
-module SRL16E (
- output Q,
- (* techmap_autopurge *) input A0, A1, A2, A3, CE, CLK, D
-);
- parameter [15:0] INIT = 16'h0000;
- parameter [0:0] IS_CLK_INVERTED = 1'b0;
- wire $Q;
- SRL16E #(
- .INIT(INIT), .IS_CLK_INVERTED(IS_CLK_INVERTED)
- ) _TECHMAP_REPLACE_ (
- .Q($Q),
- .A0(A0), .A1(A1), .A2(A2), .A3(A3), .CE(CE), .CLK(CLK), .D(D)
- );
- $__ABC9_RAM6 q (.A($Q), .S({1'b1, A3, A2, A1, A0, 1'b1}), .Y(Q));
-endmodule
-
-module SRLC16 (
- output Q, Q15,
- (* techmap_autopurge *) input A0, A1, A2, A3, CLK, D
-);
- parameter [15:0] INIT = 16'h0000;
- wire $Q;
- SRLC16 #(
- .INIT(INIT),
- ) _TECHMAP_REPLACE_ (
- .Q($Q), .Q(Q15),
- .A0(A0), .A1(A1), .A2(A2), .A3(A3), .CLK(CLK), .D(D)
- );
- $__ABC9_RAM6 q (.A($Q), .S({1'b1, A3, A2, A1, A0, 1'b1}), .Y(Q));
-endmodule
-
-module SRLC16E (
- output Q, Q15,
- (* techmap_autopurge *) input A0, A1, A2, A3, CE, CLK, D
-);
- parameter [15:0] INIT = 16'h0000;
- parameter [0:0] IS_CLK_INVERTED = 1'b0;
- wire $Q;
- SRLC16E #(
- .INIT(INIT), .IS_CLK_INVERTED(IS_CLK_INVERTED)
- ) _TECHMAP_REPLACE_ (
- .Q($Q), .Q(Q15),
- .A0(A0), .A1(A1), .A2(A2), .A3(A3), .CE(CE), .CLK(CLK), .D(D)
- );
- $__ABC9_RAM6 q (.A($Q), .S({1'b1, A3, A2, A1, A0, 1'b1}), .Y(Q));
-endmodule
-
-module SRLC32E (
- output Q,
- output Q31,
- (* techmap_autopurge *) input [4:0] A,
- (* techmap_autopurge *) input CE, CLK, D
-);
- parameter [31:0] INIT = 32'h00000000;
- parameter [0:0] IS_CLK_INVERTED = 1'b0;
- wire $Q;
- SRLC32E #(
- .INIT(INIT), .IS_CLK_INVERTED(IS_CLK_INVERTED)
- ) _TECHMAP_REPLACE_ (
- .Q($Q), .Q31(Q31),
- .A(A), .CE(CE), .CLK(CLK), .D(D)
- );
- $__ABC9_RAM6 q (.A($Q), .S({1'b1, A}), .Y(Q));
-endmodule
-
-module DSP48E1 (
- (* techmap_autopurge *) output [29:0] ACOUT,
- (* techmap_autopurge *) output [17:0] BCOUT,
- (* techmap_autopurge *) output reg CARRYCASCOUT,
- (* techmap_autopurge *) output reg [3:0] CARRYOUT,
- (* techmap_autopurge *) output reg MULTSIGNOUT,
- (* techmap_autopurge *) output OVERFLOW,
- (* techmap_autopurge *) output reg signed [47:0] P,
- (* techmap_autopurge *) output PATTERNBDETECT,
- (* techmap_autopurge *) output PATTERNDETECT,
- (* techmap_autopurge *) output [47:0] PCOUT,
- (* techmap_autopurge *) output UNDERFLOW,
- (* techmap_autopurge *) input signed [29:0] A,
- (* techmap_autopurge *) input [29:0] ACIN,
- (* techmap_autopurge *) input [3:0] ALUMODE,
- (* techmap_autopurge *) input signed [17:0] B,
- (* techmap_autopurge *) input [17:0] BCIN,
- (* techmap_autopurge *) input [47:0] C,
- (* techmap_autopurge *) input CARRYCASCIN,
- (* techmap_autopurge *) input CARRYIN,
- (* techmap_autopurge *) input [2:0] CARRYINSEL,
- (* techmap_autopurge *) input CEA1,
- (* techmap_autopurge *) input CEA2,
- (* techmap_autopurge *) input CEAD,
- (* techmap_autopurge *) input CEALUMODE,
- (* techmap_autopurge *) input CEB1,
- (* techmap_autopurge *) input CEB2,
- (* techmap_autopurge *) input CEC,
- (* techmap_autopurge *) input CECARRYIN,
- (* techmap_autopurge *) input CECTRL,
- (* techmap_autopurge *) input CED,
- (* techmap_autopurge *) input CEINMODE,
- (* techmap_autopurge *) input CEM,
- (* techmap_autopurge *) input CEP,
- (* techmap_autopurge *) input CLK,
- (* techmap_autopurge *) input [24:0] D,
- (* techmap_autopurge *) input [4:0] INMODE,
- (* techmap_autopurge *) input MULTSIGNIN,
- (* techmap_autopurge *) input [6:0] OPMODE,
- (* techmap_autopurge *) input [47:0] PCIN,
- (* techmap_autopurge *) input RSTA,
- (* techmap_autopurge *) input RSTALLCARRYIN,
- (* techmap_autopurge *) input RSTALUMODE,
- (* techmap_autopurge *) input RSTB,
- (* techmap_autopurge *) input RSTC,
- (* techmap_autopurge *) input RSTCTRL,
- (* techmap_autopurge *) input RSTD,
- (* techmap_autopurge *) input RSTINMODE,
- (* techmap_autopurge *) input RSTM,
- (* techmap_autopurge *) input RSTP
-);
- parameter integer ACASCREG = 1;
- parameter integer ADREG = 1;
- parameter integer ALUMODEREG = 1;
- parameter integer AREG = 1;
- parameter AUTORESET_PATDET = "NO_RESET";
- parameter A_INPUT = "DIRECT";
- parameter integer BCASCREG = 1;
- parameter integer BREG = 1;
- parameter B_INPUT = "DIRECT";
- parameter integer CARRYINREG = 1;
- parameter integer CARRYINSELREG = 1;
- parameter integer CREG = 1;
- parameter integer DREG = 1;
- parameter integer INMODEREG = 1;
- parameter integer MREG = 1;
- parameter integer OPMODEREG = 1;
- parameter integer PREG = 1;
- parameter SEL_MASK = "MASK";
- parameter SEL_PATTERN = "PATTERN";
- parameter USE_DPORT = "FALSE";
- parameter USE_MULT = "MULTIPLY";
- parameter USE_PATTERN_DETECT = "NO_PATDET";
- parameter USE_SIMD = "ONE48";
- parameter [47:0] MASK = 48'h3FFFFFFFFFFF;
- parameter [47:0] PATTERN = 48'h000000000000;
- parameter [3:0] IS_ALUMODE_INVERTED = 4'b0;
- parameter [0:0] IS_CARRYIN_INVERTED = 1'b0;
- parameter [0:0] IS_CLK_INVERTED = 1'b0;
- parameter [4:0] IS_INMODE_INVERTED = 5'b0;
- parameter [6:0] IS_OPMODE_INVERTED = 7'b0;
-
- wire [47:0] $P, $PCOUT;
-
- DSP48E1 #(
- .ACASCREG(ACASCREG),
- .ADREG(ADREG),
- .ALUMODEREG(ALUMODEREG),
- .AREG(AREG),
- .AUTORESET_PATDET(AUTORESET_PATDET),
- .A_INPUT(A_INPUT),
- .BCASCREG(BCASCREG),
- .BREG(BREG),
- .B_INPUT(B_INPUT),
- .CARRYINREG(CARRYINREG),
- .CARRYINSELREG(CARRYINSELREG),
- .CREG(CREG),
- .DREG(DREG),
- .INMODEREG(INMODEREG),
- .MREG(MREG),
- .OPMODEREG(OPMODEREG),
- .PREG(PREG),
- .SEL_MASK(SEL_MASK),
- .SEL_PATTERN(SEL_PATTERN),
- .USE_DPORT(USE_DPORT),
- .USE_MULT(USE_MULT),
- .USE_PATTERN_DETECT(USE_PATTERN_DETECT),
- .USE_SIMD(USE_SIMD),
- .MASK(MASK),
- .PATTERN(PATTERN),
- .IS_ALUMODE_INVERTED(IS_ALUMODE_INVERTED),
- .IS_CARRYIN_INVERTED(IS_CARRYIN_INVERTED),
- .IS_CLK_INVERTED(IS_CLK_INVERTED),
- .IS_INMODE_INVERTED(IS_INMODE_INVERTED),
- .IS_OPMODE_INVERTED(IS_OPMODE_INVERTED)
- ) _TECHMAP_REPLACE_ (
- .ACOUT(ACOUT),
- .BCOUT(BCOUT),
- .CARRYCASCOUT(CARRYCASCOUT),
- .CARRYOUT(CARRYOUT),
- .MULTSIGNOUT(MULTSIGNOUT),
- .OVERFLOW(OVERFLOW),
- .P($P),
- .PATTERNBDETECT(PATTERNBDETECT),
- .PATTERNDETECT(PATTERNDETECT),
- .PCOUT($PCOUT),
- .UNDERFLOW(UNDERFLOW),
- .A(A),
- .ACIN(ACIN),
- .ALUMODE(ALUMODE),
- .B(B),
- .BCIN(BCIN),
- .C(C),
- .CARRYCASCIN(CARRYCASCIN),
- .CARRYIN(CARRYIN),
- .CARRYINSEL(CARRYINSEL),
- .CEA1(CEA1),
- .CEA2(CEA2),
- .CEAD(CEAD),
- .CEALUMODE(CEALUMODE),
- .CEB1(CEB1),
- .CEB2(CEB2),
- .CEC(CEC),
- .CECARRYIN(CECARRYIN),
- .CECTRL(CECTRL),
- .CED(CED),
- .CEINMODE(CEINMODE),
- .CEM(CEM),
- .CEP(CEP),
- .CLK(CLK),
- .D(D),
- .INMODE(INMODE),
- .MULTSIGNIN(MULTSIGNIN),
- .OPMODE(OPMODE),
- .PCIN(PCIN),
- .RSTA(RSTA),
- .RSTALLCARRYIN(RSTALLCARRYIN),
- .RSTALUMODE(RSTALUMODE),
- .RSTB(RSTB),
- .RSTC(RSTC),
- .RSTCTRL(RSTCTRL),
- .RSTD(RSTD),
- .RSTINMODE(RSTINMODE),
- .RSTM(RSTM),
- .RSTP(RSTP)
- );
- $__ABC9_DSP48E1 #(
- .ADREG(ADREG),
- .AREG(AREG),
- .BREG(BREG),
- .CREG(CREG),
- .DREG(DREG),
- .MREG(MREG),
- .PREG(PREG),
- .USE_DPORT(USE_DPORT),
- .USE_MULT(USE_MULT)
- ) dsp_comb (
- .$A(A), .$B(B), .$C(C), .$D(D), .$P($P), .$PCIN(PCIN), .$PCOUT($PCOUT), .P(P), .PCOUT(PCOUT));
-endmodule
diff --git a/techlibs/xilinx/abc9_model.v b/techlibs/xilinx/abc9_model.v
index 2d109ef8a..db44ff00b 100644
--- a/techlibs/xilinx/abc9_model.v
+++ b/techlibs/xilinx/abc9_model.v
@@ -37,174 +37,3 @@ module \$__XILINX_MUXF78 (output O, input I0, I1, I2, I3, S0, S1);
(S1 => O) = 273;
endspecify
endmodule
-
-// Box to emulate async behaviour of FDC*
-(* abc9_box, lib_whitebox *)
-module \$__ABC9_ASYNC0 (input A, S, output Y);
- assign Y = S ? 1'b0 : A;
- specify
- (A => Y) = 0;
- // https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/slicel.sdf#L270
- (S => Y) = 764;
- endspecify
-endmodule
-
-// Box to emulate async behaviour of FDP*
-(* abc9_box, lib_whitebox *)
-module \$__ABC9_ASYNC1 (input A, S, output Y);
- assign Y = S ? 1'b1 : A;
- specify
- (A => Y) = 0;
- // https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/slicel.sdf#L270
- (S => Y) = 764;
- endspecify
-endmodule
-
-// Box to emulate comb/seq behaviour of RAM{32,64} and SRL{16,32}
-// Necessary since RAMD* and SRL* have both combinatorial (i.e.
-// same-cycle read operation) and sequential (write operation
-// is only committed on the next clock edge).
-// To model the combinatorial path, such cells have to be split
-// into comb and seq parts, with this box modelling only the former.
-(* abc9_box *)
-module \$__ABC9_RAM6 (input A, input [5:0] S, output Y);
- specify
- (A => Y) = 0;
- (S[0] => Y) = 642;
- (S[1] => Y) = 631;
- (S[2] => Y) = 472;
- (S[3] => Y) = 407;
- (S[4] => Y) = 238;
- (S[5] => Y) = 127;
- endspecify
-endmodule
-// Box to emulate comb/seq behaviour of RAM128
-(* abc9_box *)
-module \$__ABC9_RAM7 (input A, input [6:0] S, output Y);
- specify
- (A => Y) = 0;
- // https://github.com/SymbiFlow/prjxray-db/blob/1c85daf1b115da4d27ca83c6b89f53a94de39748/artix7/timings/slicel.sdf#L867
- (S[0] => Y) = 642 + 223 /* to cross F7BMUX */ + 174 /* CMUX */;
- (S[1] => Y) = 631 + 223 /* to cross F7BMUX */ + 174 /* CMUX */;
- (S[2] => Y) = 472 + 223 /* to cross F7BMUX */ + 174 /* CMUX */;
- (S[3] => Y) = 407 + 223 /* to cross F7BMUX */ + 174 /* CMUX */;
- (S[4] => Y) = 238 + 223 /* to cross F7BMUX */ + 174 /* CMUX */;
- (S[5] => Y) = 127 + 223 /* to cross F7BMUX */ + 174 /* CMUX */;
- (S[6] => Y) = 0 + 296 /* to select F7BMUX */ + 174 /* CMUX */;
- endspecify
-endmodule
-
-// Boxes used to represent the comb behaviour of DSP48E1
-(* abc9_box *)
-module $__ABC9_DSP48E1 (
- input [29:0] $A,
- input [17:0] $B,
- input [47:0] $C,
- input [24:0] $D,
- input [47:0] $P,
- input [47:0] $PCIN,
- input [47:0] $PCOUT,
- output [47:0] P,
- output [47:0] PCOUT
-);
- parameter integer ADREG = 1;
- parameter integer AREG = 1;
- parameter integer BREG = 1;
- parameter integer CREG = 1;
- parameter integer DREG = 1;
- parameter integer MREG = 1;
- parameter integer PREG = 1;
- parameter USE_DPORT = "FALSE";
- parameter USE_MULT = "MULTIPLY";
-
- function integer \A.P.comb ;
- begin
- if (USE_MULT == "MULTIPLY" && USE_DPORT == "FALSE") \A.P.comb = 2823;
- else if (USE_MULT == "MULTIPLY" && USE_DPORT == "TRUE") \A.P.comb = 3806;
- else if (USE_MULT == "NONE" && USE_DPORT == "FALSE") \A.P.comb = 1523;
- end
- endfunction
- function integer \A.PCOUT.comb ;
- begin
- if (USE_MULT == "MULTIPLY" && USE_DPORT == "FALSE") \A.PCOUT.comb = 2970;
- else if (USE_MULT == "MULTIPLY" && USE_DPORT == "TRUE") \A.PCOUT.comb = 3954;
- else if (USE_MULT == "NONE" && USE_DPORT == "FALSE") \A.PCOUT.comb = 1671;
- end
- endfunction
- function integer \B.P.comb ;
- begin
- if (USE_MULT == "MULTIPLY" && USE_DPORT == "FALSE") \B.P.comb = 2690;
- else if (USE_MULT == "MULTIPLY" && USE_DPORT == "TRUE") \B.P.comb = 2690;
- else if (USE_MULT == "NONE" && USE_DPORT == "FALSE") \B.P.comb = 1509;
- end
- endfunction
- function integer \B.PCOUT.comb ;
- begin
- if (USE_MULT == "MULTIPLY" && USE_DPORT == "FALSE") \B.PCOUT.comb = 2838;
- else if (USE_MULT == "MULTIPLY" && USE_DPORT == "TRUE") \B.PCOUT.comb = 2838;
- else if (USE_MULT == "NONE" && USE_DPORT == "FALSE") \B.PCOUT.comb = 1658;
- end
- endfunction
- function integer \C.P.comb ;
- begin
- if (USE_MULT == "MULTIPLY" && USE_DPORT == "FALSE") \C.P.comb = 1325;
- else if (USE_MULT == "MULTIPLY" && USE_DPORT == "TRUE") \C.P.comb = 1325;
- else if (USE_MULT == "NONE" && USE_DPORT == "FALSE") \C.P.comb = 1325;
- end
- endfunction
- function integer \C.PCOUT.comb ;
- begin
- if (USE_MULT == "MULTIPLY" && USE_DPORT == "FALSE") \C.PCOUT.comb = 1474;
- else if (USE_MULT == "MULTIPLY" && USE_DPORT == "TRUE") \C.PCOUT.comb = 1474;
- else if (USE_MULT == "NONE" && USE_DPORT == "FALSE") \C.PCOUT.comb = 1474;
- end
- endfunction
- function integer \D.P.comb ;
- begin
- if (USE_MULT == "MULTIPLY" && USE_DPORT == "TRUE") \D.P.comb = 3717;
- end
- endfunction
- function integer \D.PCOUT.comb ;
- begin
- if (USE_MULT == "MULTIPLY" && USE_DPORT == "TRUE") \D.PCOUT.comb = 3700;
- end
- endfunction
-
- specify
- ($P *> P) = 0;
- ($PCOUT *> PCOUT) = 0;
- endspecify
-
- // Identical comb delays to DSP48E1 in cells_sim.v
- generate
- if (PREG == 0 && MREG == 0 && AREG == 0 && ADREG == 0)
- specify
- ($A *> P) = \A.P.comb ();
- ($A *> PCOUT) = \A.PCOUT.comb ();
- endspecify
-
- if (PREG == 0 && MREG == 0 && BREG == 0)
- specify
- ($B *> P) = \B.P.comb ();
- ($B *> PCOUT) = \B.PCOUT.comb ();
- endspecify
-
- if (PREG == 0 && CREG == 0)
- specify
- ($C *> P) = \C.P.comb ();
- ($C *> PCOUT) = \C.PCOUT.comb ();
- endspecify
-
- if (PREG == 0 && MREG == 0 && ADREG == 0 && DREG == 0)
- specify
- ($D *> P) = \D.P.comb ();
- ($D *> PCOUT) = \D.PCOUT.comb ();
- endspecify
-
- if (PREG == 0)
- specify
- ($PCIN *> P) = 1107;
- ($PCIN *> PCOUT) = 1255;
- endspecify
- endgenerate
-endmodule
diff --git a/techlibs/xilinx/abc9_unmap.v b/techlibs/xilinx/abc9_unmap.v
deleted file mode 100644
index 5604ceb0a..000000000
--- a/techlibs/xilinx/abc9_unmap.v
+++ /dev/null
@@ -1,61 +0,0 @@
-/*
- * yosys -- Yosys Open SYnthesis Suite
- *
- * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
- * 2019 Eddie Hung <eddie@fpgeh.com>
- *
- * Permission to use, copy, modify, and/or distribute this software for any
- * purpose with or without fee is hereby granted, provided that the above
- * copyright notice and this permission notice appear in all copies.
- *
- * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
- * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
- * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
- * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
- * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
- * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
- *
- */
-
-// ============================================================================
-
-(* techmap_celltype = "$__ABC9_ASYNC0 $__ABC9_ASYNC1" *)
-module $__ABC9_ASYNC01(input A, S, output Y);
- assign Y = A;
-endmodule
-
-module $__ABC9_FF_(input D, output Q);
- assign Q = D;
-endmodule
-
-module $__ABC9_RAM6(input A, input [5:0] S, output Y);
- assign Y = A;
-endmodule
-module $__ABC9_RAM7(input A, input [6:0] S, output Y);
- assign Y = A;
-endmodule
-
-module $__ABC9_DSP48E1(
- input [29:0] $A,
- input [17:0] $B,
- input [47:0] $C,
- input [24:0] $D,
- input [47:0] $P,
- input [47:0] $PCIN,
- input [47:0] $PCOUT,
- output [47:0] P,
- output [47:0] PCOUT
-);
- parameter integer ADREG = 1;
- parameter integer AREG = 1;
- parameter integer BREG = 1;
- parameter integer CREG = 1;
- parameter integer DREG = 1;
- parameter integer MREG = 1;
- parameter integer PREG = 1;
- parameter USE_DPORT = "FALSE";
- parameter USE_MULT = "MULTIPLY";
-
- assign P = $P, PCOUT = $PCOUT;
-endmodule
diff --git a/techlibs/xilinx/arith_map.v b/techlibs/xilinx/arith_map.v
index 2b8b0dcc1..2fc216908 100644
--- a/techlibs/xilinx/arith_map.v
+++ b/techlibs/xilinx/arith_map.v
@@ -24,9 +24,11 @@
module _80_xilinx_lcu (P, G, CI, CO);
parameter WIDTH = 2;
+ (* force_downto *)
input [WIDTH-1:0] P, G;
input CI;
+ (* force_downto *)
output [WIDTH-1:0] CO;
wire _TECHMAP_FAIL_ = WIDTH <= 2;
@@ -41,7 +43,9 @@ module _80_xilinx_lcu (P, G, CI, CO);
generate if (EXPLICIT_CARRY || `LUT_SIZE == 4) begin
+ (* force_downto *)
wire [WIDTH-1:0] C = {CO, CI};
+ (* force_downto *)
wire [WIDTH-1:0] S = P & ~G;
generate for (i = 0; i < WIDTH; i = i + 1) begin:slice
@@ -59,8 +63,11 @@ end else begin
localparam MAX_WIDTH = CARRY4_COUNT * 4;
localparam PAD_WIDTH = MAX_WIDTH - WIDTH;
+ (* force_downto *)
wire [MAX_WIDTH-1:0] S = {{PAD_WIDTH{1'b0}}, P & ~G};
+ (* force_downto *)
wire [MAX_WIDTH-1:0] GG = {{PAD_WIDTH{1'b0}}, G};
+ (* force_downto *)
wire [MAX_WIDTH-1:0] C;
assign CO = C;
@@ -103,20 +110,27 @@ module _80_xilinx_alu (A, B, CI, BI, X, Y, CO);
parameter _TECHMAP_CONSTVAL_CI_ = 0;
parameter _TECHMAP_CONSTMSK_CI_ = 0;
+ (* force_downto *)
input [A_WIDTH-1:0] A;
+ (* force_downto *)
input [B_WIDTH-1:0] B;
+ (* force_downto *)
output [Y_WIDTH-1:0] X, Y;
input CI, BI;
+ (* force_downto *)
output [Y_WIDTH-1:0] CO;
wire _TECHMAP_FAIL_ = Y_WIDTH <= 2;
+ (* force_downto *)
wire [Y_WIDTH-1:0] A_buf, B_buf;
\$pos #(.A_SIGNED(A_SIGNED), .A_WIDTH(A_WIDTH), .Y_WIDTH(Y_WIDTH)) A_conv (.A(A), .Y(A_buf));
\$pos #(.A_SIGNED(B_SIGNED), .A_WIDTH(B_WIDTH), .Y_WIDTH(Y_WIDTH)) B_conv (.A(B), .Y(B_buf));
+ (* force_downto *)
wire [Y_WIDTH-1:0] AA = A_buf;
+ (* force_downto *)
wire [Y_WIDTH-1:0] BB = BI ? ~B_buf : B_buf;
genvar i;
@@ -129,7 +143,9 @@ module _80_xilinx_alu (A, B, CI, BI, X, Y, CO);
generate if (`LUT_SIZE == 4) begin
+ (* force_downto *)
wire [Y_WIDTH-1:0] C = {CO, CI};
+ (* force_downto *)
wire [Y_WIDTH-1:0] S = {AA ^ BB};
genvar i;
@@ -149,6 +165,7 @@ generate if (`LUT_SIZE == 4) begin
end else if (EXPLICIT_CARRY) begin
+ (* force_downto *)
wire [Y_WIDTH-1:0] S = AA ^ BB;
wire CINIT;
@@ -161,7 +178,9 @@ end else if (EXPLICIT_CARRY) begin
// So we maintain two wire sets, CO_CHAIN is the carry that is for VPR,
// e.g. off fabric dedicated chain. CO is the carry outputs that are
// available to the fabric.
+ (* force_downto *)
wire [Y_WIDTH-1:0] CO_CHAIN;
+ (* force_downto *)
wire [Y_WIDTH-1:0] C = {CO_CHAIN, CINIT};
// If carry chain is being initialized to a constant, techmap the constant
@@ -250,10 +269,14 @@ end else begin
localparam MAX_WIDTH = CARRY4_COUNT * 4;
localparam PAD_WIDTH = MAX_WIDTH - Y_WIDTH;
+ (* force_downto *)
wire [MAX_WIDTH-1:0] S = {{PAD_WIDTH{1'b0}}, AA ^ BB};
+ (* force_downto *)
wire [MAX_WIDTH-1:0] DI = {{PAD_WIDTH{1'b0}}, AA};
+ (* force_downto *)
wire [MAX_WIDTH-1:0] O;
+ (* force_downto *)
wire [MAX_WIDTH-1:0] C;
assign Y = O, CO = C;
diff --git a/techlibs/xilinx/cells_map.v b/techlibs/xilinx/cells_map.v
index cc180f2b9..97f050f76 100644
--- a/techlibs/xilinx/cells_map.v
+++ b/techlibs/xilinx/cells_map.v
@@ -28,32 +28,32 @@ module _90_dff_nn1_to_np1 (input D, C, R, output Q); \$_DFF_NP1_ _TECHMAP_REPL
(* techmap_celltype = "$_DFF_PN1_" *)
module _90_dff_pn1_to_pp1 (input D, C, R, output Q); \$_DFF_PP1_ _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .R(~R)); endmodule
-(* techmap_celltype = "$__DFFE_NN0" *)
-module _90_dffe_nn0_to_np0 (input D, C, R, E, output Q); \$__DFFE_NP0 _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .R(~R), .E(E)); endmodule
-(* techmap_celltype = "$__DFFE_PN0" *)
-module _90_dffe_pn0_to_pp0 (input D, C, R, E, output Q); \$__DFFE_PP0 _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .R(~R), .E(E)); endmodule
-(* techmap_celltype = "$__DFFE_NN1" *)
-module _90_dffe_nn1_to_np1 (input D, C, R, E, output Q); \$__DFFE_NP1 _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .R(~R), .E(E)); endmodule
-(* techmap_celltype = "$__DFFE_PN1" *)
-module _90_dffe_pn1_to_pp1 (input D, C, R, E, output Q); \$__DFFE_PP1 _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .R(~R), .E(E)); endmodule
+(* techmap_celltype = "$_DFFE_NN0P_" *)
+module _90_dffe_nn0_to_np0 (input D, C, R, E, output Q); \$_DFFE_NP0P_ _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .R(~R), .E(E)); endmodule
+(* techmap_celltype = "$_DFFE_PN0P_" *)
+module _90_dffe_pn0_to_pp0 (input D, C, R, E, output Q); \$_DFFE_PP0P_ _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .R(~R), .E(E)); endmodule
+(* techmap_celltype = "$_DFFE_NN1P_" *)
+module _90_dffe_nn1_to_np1 (input D, C, R, E, output Q); \$_DFFE_NP1P_ _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .R(~R), .E(E)); endmodule
+(* techmap_celltype = "$_DFFE_PN1P_" *)
+module _90_dffe_pn1_to_pp1 (input D, C, R, E, output Q); \$_DFFE_PP1P_ _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .R(~R), .E(E)); endmodule
-(* techmap_celltype = "$__DFFS_NN0_" *)
-module _90_dffs_nn0_to_np0 (input D, C, R, output Q); \$__DFFS_NP0_ _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .R(~R)); endmodule
-(* techmap_celltype = "$__DFFS_PN0_" *)
-module _90_dffs_pn0_to_pp0 (input D, C, R, output Q); \$__DFFS_PP0_ _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .R(~R)); endmodule
-(* techmap_celltype = "$__DFFS_NN1_" *)
-module _90_dffs_nn1_to_np1 (input D, C, R, output Q); \$__DFFS_NP1_ _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .R(~R)); endmodule
-(* techmap_celltype = "$__DFFS_PN1_" *)
-module _90_dffs_pn1_to_pp1 (input D, C, R, output Q); \$__DFFS_PP1_ _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .R(~R)); endmodule
+(* techmap_celltype = "$_SDFF_NN0_" *)
+module _90_dffs_nn0_to_np0 (input D, C, R, output Q); \$_SDFF_NP0_ _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .R(~R)); endmodule
+(* techmap_celltype = "$_SDFF_PN0_" *)
+module _90_dffs_pn0_to_pp0 (input D, C, R, output Q); \$_SDFF_PP0_ _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .R(~R)); endmodule
+(* techmap_celltype = "$_SDFF_NN1_" *)
+module _90_dffs_nn1_to_np1 (input D, C, R, output Q); \$_SDFF_NP1_ _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .R(~R)); endmodule
+(* techmap_celltype = "$_SDFF_PN1_" *)
+module _90_dffs_pn1_to_pp1 (input D, C, R, output Q); \$_SDFF_PP1_ _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .R(~R)); endmodule
-(* techmap_celltype = "$__DFFSE_NN0" *)
-module _90_dffse_nn0_to_np0 (input D, C, R, E, output Q); \$__DFFSE_NP0 _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .R(~R), .E(E)); endmodule
-(* techmap_celltype = "$__DFFSE_PN0" *)
-module _90_dffse_pn0_to_pp0 (input D, C, R, E, output Q); \$__DFFSE_PP0 _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .R(~R), .E(E)); endmodule
-(* techmap_celltype = "$__DFFSE_NN1" *)
-module _90_dffse_nn1_to_np1 (input D, C, R, E, output Q); \$__DFFSE_NP1 _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .R(~R), .E(E)); endmodule
-(* techmap_celltype = "$__DFFSE_PN1" *)
-module _90_dffse_pn1_to_pp1 (input D, C, R, E, output Q); \$__DFFSE_PP1 _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .R(~R), .E(E)); endmodule
+(* techmap_celltype = "$_SDFFE_NN0P_" *)
+module _90_dffse_nn0_to_np0 (input D, C, R, E, output Q); \$_SDFFE_NP0P_ _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .R(~R), .E(E)); endmodule
+(* techmap_celltype = "$_SDFFE_PN0P_" *)
+module _90_dffse_pn0_to_pp0 (input D, C, R, E, output Q); \$_SDFFE_PP0P_ _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .R(~R), .E(E)); endmodule
+(* techmap_celltype = "$_SDFFE_NN1P_" *)
+module _90_dffse_nn1_to_np1 (input D, C, R, E, output Q); \$_SDFFE_NP1P_ _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .R(~R), .E(E)); endmodule
+(* techmap_celltype = "$_SDFFE_PN1P_" *)
+module _90_dffse_pn1_to_pp1 (input D, C, R, E, output Q); \$_SDFFE_PP1P_ _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .R(~R), .E(E)); endmodule
module \$__SHREG_ (input C, input D, input E, output Q);
parameter DEPTH = 0;
@@ -184,8 +184,11 @@ module \$__XILINX_SHIFTX (A, B, Y);
parameter B_WIDTH = 1;
parameter Y_WIDTH = 1;
+ (* force_downto *)
input [A_WIDTH-1:0] A;
+ (* force_downto *)
input [B_WIDTH-1:0] B;
+ (* force_downto *)
output [Y_WIDTH-1:0] Y;
parameter [A_WIDTH-1:0] _TECHMAP_CONSTMSK_A_ = 0;
@@ -321,8 +324,11 @@ module _90__XILINX_SHIFTX (A, B, Y);
parameter B_WIDTH = 1;
parameter Y_WIDTH = 1;
+ (* force_downto *)
input [A_WIDTH-1:0] A;
+ (* force_downto *)
input [B_WIDTH-1:0] B;
+ (* force_downto *)
output [Y_WIDTH-1:0] Y;
\$shiftx #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(A_WIDTH), .B_WIDTH(B_WIDTH), .Y_WIDTH(Y_WIDTH)) _TECHMAP_REPLACE_ (.A(A), .B(B), .Y(Y));
diff --git a/techlibs/xilinx/cells_sim.v b/techlibs/xilinx/cells_sim.v
index 63223afbf..f5850d8a2 100644
--- a/techlibs/xilinx/cells_sim.v
+++ b/techlibs/xilinx/cells_sim.v
@@ -36,6 +36,9 @@ module IBUF(
parameter IOSTANDARD = "default";
parameter IBUF_LOW_PWR = 0;
assign O = I;
+ specify
+ (I => O) = 0;
+ endspecify
endmodule
module IBUFG(
@@ -57,6 +60,9 @@ module OBUF(
parameter DRIVE = 12;
parameter SLEW = "SLOW";
assign O = I;
+ specify
+ (I => O) = 0;
+ endspecify
endmodule
module IOBUF (
@@ -72,6 +78,10 @@ module IOBUF (
parameter SLEW = "SLOW";
assign IO = T ? 1'bz : I;
assign O = IO;
+ specify
+ (I => IO) = 0;
+ (IO => O) = 0;
+ endspecify
endmodule
module OBUFT (
@@ -85,14 +95,20 @@ module OBUFT (
parameter IOSTANDARD = "DEFAULT";
parameter SLEW = "SLOW";
assign O = T ? 1'bz : I;
+ specify
+ (I => O) = 0;
+ endspecify
endmodule
module BUFG(
(* clkbuf_driver *)
output O,
input I);
-
assign O = I;
+ specify
+ // https://github.com/SymbiFlow/prjxray-db/blob/4bc6385ab300b1819848371f508185f57b649a0e/artix7/timings/CLK_BUFG_TOP_R.sdf#L11
+ (I => O) = 96;
+ endspecify
endmodule
module BUFGCTRL(
@@ -499,8 +515,8 @@ module FDRE (
endgenerate
specify
// https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/slicel.sdf#L249
- //$setup(D , posedge C &&& CE && !IS_C_INVERTED , -46); // Negative times not currently supported
- //$setup(D , negedge C &&& CE && IS_C_INVERTED , -46); // Negative times not currently supported
+ $setup(D , posedge C &&& CE && !IS_C_INVERTED , /*-46*/ 0); // Negative times not currently supported
+ $setup(D , negedge C &&& CE && IS_C_INVERTED , /*-46*/ 0); // Negative times not currently supported
// https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/slicel.sdf#L248
$setup(CE, posedge C &&& !IS_C_INVERTED, 109);
$setup(CE, negedge C &&& IS_C_INVERTED, 109);
@@ -508,10 +524,10 @@ module FDRE (
$setup(R , posedge C &&& !IS_C_INVERTED, 404);
$setup(R , negedge C &&& IS_C_INVERTED, 404);
// https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLL_L.sdf#L243
- if (!IS_C_INVERTED && R ^ IS_R_INVERTED) (posedge C => (Q : 1'b0)) = 303;
- if ( IS_C_INVERTED && R ^ IS_R_INVERTED) (negedge C => (Q : 1'b0)) = 303;
- if (!IS_C_INVERTED && R ~^ IS_R_INVERTED && CE) (posedge C => (Q : D ^ IS_D_INVERTED)) = 303;
- if ( IS_C_INVERTED && R ~^ IS_R_INVERTED && CE) (negedge C => (Q : D ^ IS_D_INVERTED)) = 303;
+ if (!IS_C_INVERTED && R != IS_R_INVERTED) (posedge C => (Q : 1'b0)) = 303;
+ if ( IS_C_INVERTED && R != IS_R_INVERTED) (negedge C => (Q : 1'b0)) = 303;
+ if (!IS_C_INVERTED && R == IS_R_INVERTED && CE) (posedge C => (Q : D ^ IS_D_INVERTED)) = 303;
+ if ( IS_C_INVERTED && R == IS_R_INVERTED && CE) (negedge C => (Q : D ^ IS_D_INVERTED)) = 303;
endspecify
endmodule
@@ -529,7 +545,7 @@ module FDRE_1 (
always @(negedge C) if (R) Q <= 1'b0; else if (CE) Q <= D;
specify
// https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/slicel.sdf#L249
- //$setup(D , negedge C &&& CE, -46); // Negative times not currently supported
+ $setup(D , negedge C &&& CE, /*-46*/ 0); // Negative times not currently supported
// https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/slicel.sdf#L248
$setup(CE, negedge C, 109);
// https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/slicel.sdf#L274
@@ -564,8 +580,8 @@ module FDSE (
endgenerate
specify
// https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/slicel.sdf#L249
- //$setup(D , posedge C &&& !IS_C_INVERTED && CE, -46); // Negative times not currently supported
- //$setup(D , negedge C &&& IS_C_INVERTED && CE, -46); // Negative times not currently supported
+ $setup(D , posedge C &&& !IS_C_INVERTED && CE, /*-46*/ 0); // Negative times not currently supported
+ $setup(D , negedge C &&& IS_C_INVERTED && CE, /*-46*/ 0); // Negative times not currently supported
// https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/slicel.sdf#L248
$setup(CE, posedge C &&& !IS_C_INVERTED, 109);
$setup(CE, negedge C &&& IS_C_INVERTED, 109);
@@ -573,10 +589,10 @@ module FDSE (
$setup(S , posedge C &&& !IS_C_INVERTED, 404);
$setup(S , negedge C &&& IS_C_INVERTED, 404);
// https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLL_L.sdf#L243
- if (!IS_C_INVERTED && S ^ IS_S_INVERTED) (posedge C => (Q : 1'b1)) = 303;
- if ( IS_C_INVERTED && S ^ IS_S_INVERTED) (negedge C => (Q : 1'b1)) = 303;
- if (!IS_C_INVERTED && S ~^ IS_S_INVERTED && CE) (posedge C => (Q : D ^ IS_D_INVERTED)) = 303;
- if ( IS_C_INVERTED && S ~^ IS_S_INVERTED && CE) (negedge C => (Q : D ^ IS_D_INVERTED)) = 303;
+ if (!IS_C_INVERTED && S != IS_S_INVERTED) (posedge C => (Q : 1'b1)) = 303;
+ if ( IS_C_INVERTED && S != IS_S_INVERTED) (negedge C => (Q : 1'b1)) = 303;
+ if (!IS_C_INVERTED && S == IS_S_INVERTED && CE) (posedge C => (Q : D ^ IS_D_INVERTED)) = 303;
+ if ( IS_C_INVERTED && S == IS_S_INVERTED && CE) (negedge C => (Q : D ^ IS_D_INVERTED)) = 303;
endspecify
endmodule
@@ -594,7 +610,7 @@ module FDSE_1 (
always @(negedge C) if (S) Q <= 1'b1; else if (CE) Q <= D;
specify
// https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/slicel.sdf#L249
- //$setup(D , negedge C &&& CE, -46); // Negative times not currently supported
+ $setup(D , negedge C &&& CE, /*-46*/ 0); // Negative times not currently supported
// https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/slicel.sdf#L248
$setup(CE, negedge C, 109);
// https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/slicel.sdf#L274
@@ -640,7 +656,7 @@ module FDRSE (
Q <= d;
endmodule
-(* abc9_flop, lib_whitebox *)
+(* abc9_box, lib_whitebox *)
module FDCE (
output reg Q,
(* clkbuf_sink *)
@@ -667,8 +683,8 @@ module FDCE (
endgenerate
specify
// https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/slicel.sdf#L249
- //$setup(D , posedge C &&& !IS_C_INVERTED && CE, -46); // Negative times not currently supported
- //$setup(D , negedge C &&& IS_C_INVERTED && CE, -46); // Negative times not currently supported
+ $setup(D , posedge C &&& !IS_C_INVERTED && CE, /*-46*/ 0); // Negative times not currently supported
+ $setup(D , negedge C &&& IS_C_INVERTED && CE, /*-46*/ 0); // Negative times not currently supported
// https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/slicel.sdf#L248
$setup(CE , posedge C &&& !IS_C_INVERTED, 109);
$setup(CE , negedge C &&& IS_C_INVERTED, 109);
@@ -676,14 +692,20 @@ module FDCE (
$setup(CLR, posedge C &&& !IS_C_INVERTED, 404);
$setup(CLR, negedge C &&& IS_C_INVERTED, 404);
// https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/slicel.sdf#L270
- //if (!IS_CLR_INVERTED) (posedge CLR => (Q : 1'b0)) = 764; // Captured by $__ABC9_ASYNC0
- //if ( IS_CLR_INVERTED) (negedge CLR => (Q : 1'b0)) = 764; // Captured by $__ABC9_ASYNC0
- if (!IS_C_INVERTED && CLR ~^ IS_CLR_INVERTED && CE) (posedge C => (Q : D ^ IS_D_INVERTED)) = 303;
- if ( IS_C_INVERTED && CLR ~^ IS_CLR_INVERTED && CE) (negedge C => (Q : D ^ IS_D_INVERTED)) = 303;
+`ifndef YOSYS
+ if (!IS_CLR_INVERTED) (posedge CLR => (Q : 1'b0)) = 764;
+ if ( IS_CLR_INVERTED) (negedge CLR => (Q : 1'b0)) = 764;
+`else
+ if (IS_CLR_INVERTED != CLR) (CLR => Q) = 764; // Technically, this should be an edge sensitive path
+ // but for facilitating a bypass box, let's pretend it's
+ // a simple path
+`endif
+ if (!IS_C_INVERTED && CLR == IS_CLR_INVERTED && CE) (posedge C => (Q : D ^ IS_D_INVERTED)) = 303;
+ if ( IS_C_INVERTED && CLR == IS_CLR_INVERTED && CE) (negedge C => (Q : D ^ IS_D_INVERTED)) = 303;
endspecify
endmodule
-(* abc9_flop, lib_whitebox *)
+(* abc9_box, lib_whitebox *)
module FDCE_1 (
output reg Q,
(* clkbuf_sink *)
@@ -697,18 +719,24 @@ module FDCE_1 (
always @(negedge C, posedge CLR) if (CLR) Q <= 1'b0; else if (CE) Q <= D;
specify
// https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/slicel.sdf#L249
- //$setup(D , negedge C &&& CE, -46); // Negative times not currently supported
+ $setup(D , negedge C &&& CE, /*-46*/ 0); // Negative times not currently supported
// https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/slicel.sdf#L248
$setup(CE , negedge C, 109);
// https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/slicel.sdf#L274
$setup(CLR, negedge C, 404);
// https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/slicel.sdf#L270
- //(posedge CLR => (Q : 1'b0)) = 764; // Captured by $__ABC9_ASYNC0
+`ifndef YOSYS
+ (posedge CLR => (Q : 1'b0)) = 764;
+`else
+ if (CLR) (CLR => Q) = 764; // Technically, this should be an edge sensitive path
+ // but for facilitating a bypass box, let's pretend it's
+ // a simple path
+`endif
if (!CLR && CE) (negedge C => (Q : D)) = 303;
endspecify
endmodule
-(* abc9_flop, lib_whitebox *)
+(* abc9_box, lib_whitebox *)
module FDPE (
output reg Q,
(* clkbuf_sink *)
@@ -734,8 +762,8 @@ module FDPE (
endgenerate
specify
// https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/slicel.sdf#L249
- //$setup(D , posedge C &&& !IS_C_INVERTED && CE, -46); // Negative times not currently supported
- //$setup(D , negedge C &&& IS_C_INVERTED && CE, -46); // Negative times not currently supported
+ $setup(D , posedge C &&& !IS_C_INVERTED && CE, /*-46*/ 0); // Negative times not currently supported
+ $setup(D , negedge C &&& IS_C_INVERTED && CE, /*-46*/ 0); // Negative times not currently supported
// https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/slicel.sdf#L248
$setup(CE , posedge C &&& !IS_C_INVERTED, 109);
$setup(CE , negedge C &&& IS_C_INVERTED, 109);
@@ -743,14 +771,20 @@ module FDPE (
$setup(PRE, posedge C &&& !IS_C_INVERTED, 404);
$setup(PRE, negedge C &&& IS_C_INVERTED, 404);
// https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/slicel.sdf#L270
- //if (!IS_PRE_INVERTED) (posedge PRE => (Q : 1'b1)) = 764; // Captured by $__ABC9_ASYNC1
- //if ( IS_PRE_INVERTED) (negedge PRE => (Q : 1'b1)) = 764; // Captured by $__ABC9_ASYNC1
- if (!IS_C_INVERTED && PRE ~^ IS_PRE_INVERTED && CE) (posedge C => (Q : D ^ IS_D_INVERTED)) = 303;
- if ( IS_C_INVERTED && PRE ~^ IS_PRE_INVERTED && CE) (negedge C => (Q : D ^ IS_D_INVERTED)) = 303;
+`ifndef YOSYS
+ if (!IS_PRE_INVERTED) (posedge PRE => (Q : 1'b1)) = 764;
+ if ( IS_PRE_INVERTED) (negedge PRE => (Q : 1'b1)) = 764;
+`else
+ if (IS_PRE_INVERTED != PRE) (PRE => Q) = 764; // Technically, this should be an edge sensitive path
+ // but for facilitating a bypass box, let's pretend it's
+ // a simple path
+`endif
+ if (!IS_C_INVERTED && PRE == IS_PRE_INVERTED && CE) (posedge C => (Q : D ^ IS_D_INVERTED)) = 303;
+ if ( IS_C_INVERTED && PRE == IS_PRE_INVERTED && CE) (negedge C => (Q : D ^ IS_D_INVERTED)) = 303;
endspecify
endmodule
-(* abc9_flop, lib_whitebox *)
+(* abc9_box, lib_whitebox *)
module FDPE_1 (
output reg Q,
(* clkbuf_sink *)
@@ -764,14 +798,19 @@ module FDPE_1 (
always @(negedge C, posedge PRE) if (PRE) Q <= 1'b1; else if (CE) Q <= D;
specify
// https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/slicel.sdf#L249
- //$setup(D , negedge C &&& CE, -46); // Negative times not currently supported
+ $setup(D , negedge C &&& CE, /*-46*/ 0); // Negative times not currently supported
// https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/slicel.sdf#L248
$setup(CE , negedge C, 109);
// https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/slicel.sdf#L274
$setup(PRE, negedge C, 404);
// https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/slicel.sdf#L270
- //if (!IS_PRE_INVERTED) (posedge PRE => (Q : 1'b1)) = 764; // Captured by $__ABC9_ASYNC1
- //if (IS_PRE_INVERTED) (negedge PRE => (Q : 1'b1)) = 764; // Captured by $__ABC9_ASYNC1
+`ifndef YOSYS
+ (posedge PRE => (Q : 1'b1)) = 764;
+`else
+ if (PRE) (PRE => Q) = 764; // Technically, this should be an edge sensitive path
+ // but for facilitating a bypass box, let's pretend it's
+ // a simple path
+`endif
if (!PRE && CE) (negedge C => (Q : D)) = 303;
endspecify
endmodule
@@ -1383,6 +1422,7 @@ module RAM16X1D_1 (
always @(negedge clk) if (WE) mem[a] <= D;
endmodule
+(* abc9_box, lib_whitebox *)
module RAM32X1D (
output DPO, SPO,
input D,
@@ -1429,15 +1469,15 @@ module RAM32X1D (
if (!IS_WCLK_INVERTED) (posedge WCLK => (DPO : 1'bx)) = 1153;
if ( IS_WCLK_INVERTED) (posedge WCLK => (SPO : D)) = 1153;
if ( IS_WCLK_INVERTED) (negedge WCLK => (DPO : 1'bx)) = 1153;
- // Captured by $__ABC9_RAM6
- //({A0,DPRA0} => {SPO,DPO}) = 642;
- //({A1,DPRA1} => {SPO,DPO}) = 631;
- //({A2,DPRA2} => {SPO,DPO}) = 472;
- //({A3,DPRA3} => {SPO,DPO}) = 407;
- //({A4,DPRA4} => {SPO,DPO}) = 238;
+ (A0 => SPO) = 642; (DPRA0 => DPO) = 642;
+ (A1 => SPO) = 632; (DPRA1 => DPO) = 631;
+ (A2 => SPO) = 472; (DPRA2 => DPO) = 472;
+ (A3 => SPO) = 407; (DPRA3 => DPO) = 407;
+ (A4 => SPO) = 238; (DPRA4 => DPO) = 238;
endspecify
endmodule
+(* abc9_box, lib_whitebox *)
module RAM32X1D_1 (
output DPO, SPO,
input D,
@@ -1479,15 +1519,15 @@ module RAM32X1D_1 (
// Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L981
if (WE) (negedge WCLK => (SPO : D)) = 1153;
if (WE) (negedge WCLK => (DPO : 1'bx)) = 1153;
- // Captured by $__ABC9_RAM6
- //({A0,DPRA0} => {SPO,DPO}) = 642;
- //({A1,DPRA1} => {SPO,DPO}) = 631;
- //({A2,DPRA2} => {SPO,DPO}) = 472;
- //({A3,DPRA3} => {SPO,DPO}) = 407;
- //({A4,DPRA4} => {SPO,DPO}) = 238;
+ (A0 => SPO) = 642; (DPRA0 => DPO) = 642;
+ (A1 => SPO) = 632; (DPRA1 => DPO) = 631;
+ (A2 => SPO) = 472; (DPRA2 => DPO) = 472;
+ (A3 => SPO) = 407; (DPRA3 => DPO) = 407;
+ (A4 => SPO) = 238; (DPRA4 => DPO) = 238;
endspecify
endmodule
+(* abc9_box, lib_whitebox *)
module RAM64X1D (
output DPO, SPO,
input D,
@@ -1537,13 +1577,12 @@ module RAM64X1D (
if (!IS_WCLK_INVERTED && WE) (posedge WCLK => (DPO : 1'bx)) = 1153;
if ( IS_WCLK_INVERTED && WE) (negedge WCLK => (SPO : D)) = 1153;
if ( IS_WCLK_INVERTED && WE) (negedge WCLK => (DPO : 1'bx)) = 1153;
- // Captured by $__ABC9_RAM6
- //({A0,DPRA0} => {SPO,DPO}) = 642;
- //({A1,DPRA1} => {SPO,DPO}) = 631;
- //({A2,DPRA2} => {SPO,DPO}) = 472;
- //({A3,DPRA3} => {SPO,DPO}) = 407;
- //({A4,DPRA4} => {SPO,DPO}) = 238;
- //({A5,DPRA5} => {SPO,DPO}) = 127;
+ (A0 => SPO) = 642; (DPRA0 => DPO) = 642;
+ (A1 => SPO) = 632; (DPRA1 => DPO) = 631;
+ (A2 => SPO) = 472; (DPRA2 => DPO) = 472;
+ (A3 => SPO) = 407; (DPRA3 => DPO) = 407;
+ (A4 => SPO) = 238; (DPRA4 => DPO) = 238;
+ (A5 => SPO) = 127; (DPRA5 => DPO) = 127;
endspecify
endmodule
@@ -1586,9 +1625,16 @@ module RAM64X1D_1 (
// Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L981
if (WE) (negedge WCLK => (SPO : D)) = 1153;
if (WE) (negedge WCLK => (DPO : 1'bx)) = 1153;
+ (A0 => SPO) = 642; (DPRA0 => DPO) = 642;
+ (A1 => SPO) = 632; (DPRA1 => DPO) = 631;
+ (A2 => SPO) = 472; (DPRA2 => DPO) = 472;
+ (A3 => SPO) = 407; (DPRA3 => DPO) = 407;
+ (A4 => SPO) = 238; (DPRA4 => DPO) = 238;
+ (A5 => SPO) = 127; (DPRA5 => DPO) = 127;
endspecify
endmodule
+(* abc9_box, lib_whitebox *)
module RAM128X1D (
output DPO, SPO,
input D,
@@ -1632,22 +1678,21 @@ module RAM128X1D (
// Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L981
if (!IS_WCLK_INVERTED && WE) (posedge WCLK => (SPO : D)) = 1153 + 217 /* to cross F7AMUX */ + 175 /* AMUX */;
if ( IS_WCLK_INVERTED && WE) (negedge WCLK => (DPO : 1'bx)) = 1153 + 223 /* to cross F7BMUX */ + 174 /* CMUX */;
+ (A[0] => SPO) = 642 + 193 /* to cross F7AMUX */ + 175 /* AMUX */;
+ (A[1] => SPO) = 631 + 193 /* to cross F7AMUX */ + 175 /* AMUX */;
+ (A[2] => SPO) = 472 + 193 /* to cross F7AMUX */ + 175 /* AMUX */;
+ (A[3] => SPO) = 407 + 193 /* to cross F7AMUX */ + 175 /* AMUX */;
+ (A[4] => SPO) = 238 + 193 /* to cross F7AMUX */ + 175 /* AMUX */;
+ (A[5] => SPO) = 127 + 193 /* to cross F7AMUX */ + 175 /* AMUX */;
+ (A[6] => SPO) = 0 + 276 /* to select F7AMUX */ + 175 /* AMUX */;
+ (DPRA[0] => DPO) = 642 + 223 /* to cross MUXF7 */ + 174 /* CMUX */;
+ (DPRA[1] => DPO) = 631 + 223 /* to cross MUXF7 */ + 174 /* CMUX */;
+ (DPRA[2] => DPO) = 472 + 223 /* to cross MUXF7 */ + 174 /* CMUX */;
+ (DPRA[3] => DPO) = 407 + 223 /* to cross MUXF7 */ + 174 /* CMUX */;
+ (DPRA[4] => DPO) = 238 + 223 /* to cross MUXF7 */ + 174 /* CMUX */;
+ (DPRA[5] => DPO) = 127 + 223 /* to cross MUXF7 */ + 174 /* CMUX */;
+ (DPRA[6] => DPO) = 0 + 296 /* to select MUXF7 */ + 174 /* CMUX */;
`endif
- // Captured by $__ABC9_RAM7
- //(A[0] => SPO) = 642 + 193 /* to cross F7AMUX */ + 175 /* AMUX */;
- //(A[1] => SPO) = 631 + 193 /* to cross F7AMUX */ + 175 /* AMUX */;
- //(A[2] => SPO) = 472 + 193 /* to cross F7AMUX */ + 175 /* AMUX */;
- //(A[3] => SPO) = 407 + 193 /* to cross F7AMUX */ + 175 /* AMUX */;
- //(A[4] => SPO) = 238 + 193 /* to cross F7AMUX */ + 175 /* AMUX */;
- //(A[5] => SPO) = 127 + 193 /* to cross F7AMUX */ + 175 /* AMUX */;
- //(A[6] => SPO) = 0 + 276 /* to select F7AMUX */ + 175 /* AMUX */;
- //(DPRA[0] => DPO) = 642 + 223 /* to cross MUXF7 */ + 174 /* CMUX */;
- //(DPRA[1] => DPO) = 631 + 223 /* to cross MUXF7 */ + 174 /* CMUX */;
- //(DPRA[2] => DPO) = 472 + 223 /* to cross MUXF7 */ + 174 /* CMUX */;
- //(DPRA[3] => DPO) = 407 + 223 /* to cross MUXF7 */ + 174 /* CMUX */;
- //(DPRA[4] => DPO) = 238 + 223 /* to cross MUXF7 */ + 174 /* CMUX */;
- //(DPRA[5] => DPO) = 127 + 223 /* to cross MUXF7 */ + 174 /* CMUX */;
- //(DPRA[6] => DPO) = 0 + 296 /* to select MUXF7 */ + 174 /* CMUX */;
endspecify
endmodule
@@ -1671,6 +1716,7 @@ endmodule
// Multi port.
+(* abc9_box, lib_whitebox *)
module RAM32M (
output [1:0] DOA,
output [1:0] DOB,
@@ -1767,12 +1813,11 @@ module RAM32M (
// Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L1061
if (!IS_WCLK_INVERTED && WE) (posedge WCLK => (DOD[1] : DID[1])) = 1190;
if ( IS_WCLK_INVERTED && WE) (negedge WCLK => (DOD[1] : DID[1])) = 1190;
- // Captured by $__ABC9_RAM6
- //({{2{ADDRA[0]}},{2{ADDRB[0]}},{2{ADDRC[0]}},{2{ADDRD[0]}}} => {DOA,DOB,DOC,DOD}) = 642;
- //({{2{ADDRA[1]}},{2{ADDRB[1]}},{2{ADDRC[1]}},{2{ADDRD[1]}}} => {DOA,DOB,DOC,DOD}) = 631;
- //({{2{ADDRA[2]}},{2{ADDRB[2]}},{2{ADDRC[2]}},{2{ADDRD[2]}}} => {DOA,DOB,DOC,DOD}) = 472;
- //({{2{ADDRA[3]}},{2{ADDRB[3]}},{2{ADDRC[3]}},{2{ADDRD[3]}}} => {DOA,DOB,DOC,DOD}) = 407;
- //({{2{ADDRA[4]}},{2{ADDRB[4]}},{2{ADDRC[4]}},{2{ADDRD[4]}}} => {DOA,DOB,DOC,DOD}) = 238;
+ (ADDRA[0] *> DOA) = 642; (ADDRB[0] *> DOB) = 642; (ADDRC[0] *> DOC) = 642; (ADDRD[0] *> DOD) = 642;
+ (ADDRA[1] *> DOA) = 631; (ADDRB[1] *> DOB) = 631; (ADDRC[1] *> DOC) = 631; (ADDRD[1] *> DOD) = 631;
+ (ADDRA[2] *> DOA) = 472; (ADDRB[2] *> DOB) = 472; (ADDRC[2] *> DOC) = 472; (ADDRD[2] *> DOD) = 472;
+ (ADDRA[3] *> DOA) = 407; (ADDRB[3] *> DOB) = 407; (ADDRC[3] *> DOC) = 407; (ADDRD[3] *> DOD) = 407;
+ (ADDRA[4] *> DOA) = 238; (ADDRB[4] *> DOB) = 238; (ADDRC[4] *> DOC) = 238; (ADDRD[4] *> DOD) = 238;
endspecify
endmodule
@@ -1845,6 +1890,7 @@ module RAM32M16 (
end
endmodule
+(* abc9_box, lib_whitebox *)
module RAM64M (
output DOA,
output DOB,
@@ -1923,12 +1969,11 @@ module RAM64M (
// Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L1093
if (!IS_WCLK_INVERTED && WE) (posedge WCLK => (DOD : DID)) = 1163;
if ( IS_WCLK_INVERTED && WE) (negedge WCLK => (DOD : DID)) = 1163;
- // Captured by $__ABC9_RAM6
- //({ADDRA[0],ADDRB[0],ADDRC[0],ADDRD[0]} => {DOA,DOB,DOC,DOD}) = 642;
- //({ADDRA[1],ADDRB[1],ADDRC[1],ADDRD[1]} => {DOA,DOB,DOC,DOD}) = 631;
- //({ADDRA[2],ADDRB[2],ADDRC[2],ADDRD[2]} => {DOA,DOB,DOC,DOD}) = 472;
- //({ADDRA[3],ADDRB[3],ADDRC[3],ADDRD[3]} => {DOA,DOB,DOC,DOD}) = 407;
- //({ADDRA[4],ADDRB[4],ADDRC[4],ADDRD[4]} => {DOA,DOB,DOC,DOD}) = 238;
+ (ADDRA[0] => DOA) = 642; (ADDRB[0] => DOB) = 642; (ADDRC[0] => DOC) = 642; (ADDRD[0] => DOD) = 642;
+ (ADDRA[1] => DOA) = 631; (ADDRB[1] => DOB) = 631; (ADDRC[1] => DOC) = 631; (ADDRD[1] => DOD) = 631;
+ (ADDRA[2] => DOA) = 472; (ADDRB[2] => DOB) = 472; (ADDRC[2] => DOC) = 472; (ADDRD[2] => DOD) = 472;
+ (ADDRA[3] => DOA) = 407; (ADDRB[3] => DOB) = 407; (ADDRC[3] => DOC) = 407; (ADDRD[3] => DOD) = 407;
+ (ADDRA[4] => DOA) = 238; (ADDRB[4] => DOB) = 238; (ADDRC[4] => DOC) = 238; (ADDRD[4] => DOD) = 238;
endspecify
endmodule
@@ -2045,6 +2090,7 @@ endmodule
// Shift registers.
+(* abc9_box, lib_whitebox *)
module SRL16 (
output Q,
input A0, A1, A2, A3,
@@ -2063,14 +2109,14 @@ module SRL16 (
(posedge CLK => (Q : 1'bx)) = 1472;
// Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L912
$setup(D , posedge CLK, 173);
- // Captured by $__ABC9_RAM6
- //(A0 => Q) = 631;
- //(A1 => Q) = 472;
- //(A2 => Q) = 407;
- //(A3 => Q) = 238;
+ (A0 => Q) = 631;
+ (A1 => Q) = 472;
+ (A2 => Q) = 407;
+ (A3 => Q) = 238;
endspecify
endmodule
+(* abc9_box, lib_whitebox *)
module SRL16E (
output Q,
input A0, A1, A2, A3, CE,
@@ -2096,16 +2142,19 @@ module SRL16E (
$setup(D , posedge CLK &&& !IS_CLK_INVERTED, 173);
$setup(D , negedge CLK &&& IS_CLK_INVERTED, 173);
// Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L905
+ if (!IS_CLK_INVERTED && CE) (posedge CLK => (Q : D)) = 1472;
+ if ( IS_CLK_INVERTED && CE) (negedge CLK => (Q : D)) = 1472;
+ // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L905
if (!IS_CLK_INVERTED && CE) (posedge CLK => (Q : 1'bx)) = 1472;
if ( IS_CLK_INVERTED && CE) (negedge CLK => (Q : 1'bx)) = 1472;
- // Captured by $__ABC9_RAM6
- //(A0 => Q) = 631;
- //(A1 => Q) = 472;
- //(A2 => Q) = 407;
- //(A3 => Q) = 238;
+ (A0 => Q) = 631;
+ (A1 => Q) = 472;
+ (A2 => Q) = 407;
+ (A3 => Q) = 238;
endspecify
endmodule
+(* abc9_box, lib_whitebox *)
module SRLC16 (
output Q,
output Q15,
@@ -2122,18 +2171,20 @@ module SRLC16 (
always @(posedge CLK) r <= { r[14:0], D };
specify
- // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L905
- (posedge CLK => (Q : 1'bx)) = 1472;
// Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L912
$setup(D , posedge CLK, 173);
- // Captured by $__ABC9_RAM6
- //(A0 => Q) = 631;
- //(A1 => Q) = 472;
- //(A2 => Q) = 407;
- //(A3 => Q) = 238;
+ // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L905
+ (posedge CLK => (Q : 1'bx)) = 1472;
+ // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L904
+ (posedge CLK => (Q15 : 1'bx)) = 1114;
+ (A0 => Q) = 631;
+ (A1 => Q) = 472;
+ (A2 => Q) = 407;
+ (A3 => Q) = 238;
endspecify
endmodule
+(* abc9_box, lib_whitebox *)
module SRLC16E (
output Q,
output Q15,
@@ -2160,18 +2211,23 @@ module SRLC16E (
// Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L912
$setup(D , posedge CLK &&& !IS_CLK_INVERTED, 173);
$setup(D , negedge CLK &&& IS_CLK_INVERTED, 173);
+ // https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/slicel.sdf#L248
+ $setup(CE, posedge CLK &&& !IS_CLK_INVERTED, 109);
+ $setup(CE, negedge CLK &&& IS_CLK_INVERTED, 109);
// Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L905
if (!IS_CLK_INVERTED && CE) (posedge CLK => (Q : D)) = 1472;
if ( IS_CLK_INVERTED && CE) (negedge CLK => (Q : D)) = 1472;
- // Captured by $__ABC9_RAM6
- //(A0 => Q) = 642;
- //(A1 => Q) = 631;
- //(A2 => Q) = 472;
- //(A3 => Q) = 407;
- //(A4 => Q) = 238;
+ // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L904
+ if (!IS_CLK_INVERTED && CE) (posedge CLK => (Q15 : 1'bx)) = 1114;
+ if ( IS_CLK_INVERTED && CE) (negedge CLK => (Q15 : 1'bx)) = 1114;
+ (A0 => Q) = 631;
+ (A1 => Q) = 472;
+ (A2 => Q) = 407;
+ (A3 => Q) = 238;
endspecify
endmodule
+(* abc9_box, lib_whitebox *)
module SRLC32E (
output Q,
output Q31,
@@ -2199,18 +2255,20 @@ module SRLC32E (
// Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L912
$setup(D , posedge CLK &&& !IS_CLK_INVERTED, 173);
$setup(D , negedge CLK &&& IS_CLK_INVERTED, 173);
+ // https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/slicel.sdf#L248
+ $setup(CE, posedge CLK &&& !IS_CLK_INVERTED, 109);
+ $setup(CE, negedge CLK &&& IS_CLK_INVERTED, 109);
// Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L905
if (!IS_CLK_INVERTED && CE) (posedge CLK => (Q : 1'bx)) = 1472;
if ( IS_CLK_INVERTED && CE) (negedge CLK => (Q : 1'bx)) = 1472;
// Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L904
- if (!IS_CLK_INVERTED && CE) (posedge CLK => (Q : 1'bx)) = 1114;
- if ( IS_CLK_INVERTED && CE) (negedge CLK => (Q : 1'bx)) = 1114;
- // Captured by $__ABC9_RAM6
- //(A0 => Q) = 642;
- //(A1 => Q) = 631;
- //(A2 => Q) = 472;
- //(A3 => Q) = 407;
- //(A4 => Q) = 238;
+ if (!IS_CLK_INVERTED && CE) (posedge CLK => (Q31 : 1'bx)) = 1114;
+ if ( IS_CLK_INVERTED && CE) (negedge CLK => (Q31 : 1'bx)) = 1114;
+ (A[0] => Q) = 642;
+ (A[1] => Q) = 631;
+ (A[2] => Q) = 472;
+ (A[3] => Q) = 407;
+ (A[4] => Q) = 238;
endspecify
endmodule
@@ -2978,6 +3036,10 @@ endmodule
// Virtex 6, Series 7.
+`ifdef YOSYS
+(* abc9_box=!(PREG || AREG || ADREG || BREG || CREG || DREG || MREG),
+ lib_whitebox=!(PREG || AREG || ADREG || BREG || CREG || DREG || MREG) *)
+`endif
module DSP48E1 (
output [29:0] ACOUT,
output [17:0] BCOUT,
@@ -3325,10 +3387,10 @@ module DSP48E1 (
reg signed [24:0] Dr;
reg signed [17:0] Br1, Br2;
reg signed [47:0] Cr;
- reg [4:0] INMODEr = 5'b0;
- reg [6:0] OPMODEr = 7'b0;
- reg [3:0] ALUMODEr = 4'b0;
- reg [2:0] CARRYINSELr = 3'b0;
+ reg [4:0] INMODEr;
+ reg [6:0] OPMODEr;
+ reg [3:0] ALUMODEr;
+ reg [2:0] CARRYINSELr;
generate
// Configurable A register
@@ -3510,11 +3572,13 @@ module DSP48E1 (
// Carry in
wire A24_xnor_B17d = A_MULT[24] ~^ B_MULT[17];
- reg CARRYINr = 1'b0, A24_xnor_B17 = 1'b0;
+ reg CARRYINr, A24_xnor_B17;
generate
+ if (CARRYINREG == 1) initial CARRYINr = 1'b0;
if (CARRYINREG == 1) begin always @(posedge CLK) if (RSTALLCARRYIN) CARRYINr <= 1'b0; else if (CECARRYIN) CARRYINr <= CARRYIN; end
else always @* CARRYINr = CARRYIN;
+ if (MREG == 1) initial A24_xnor_B17 = 1'b0;
if (MREG == 1) begin always @(posedge CLK) if (RSTALLCARRYIN) A24_xnor_B17 <= 1'b0; else if (CEM) A24_xnor_B17 <= A24_xnor_B17d; end
else always @* A24_xnor_B17 = A24_xnor_B17d;
endgenerate
diff --git a/techlibs/xilinx/lut_map.v b/techlibs/xilinx/lut_map.v
index ec2e3b234..2ab6075f1 100644
--- a/techlibs/xilinx/lut_map.v
+++ b/techlibs/xilinx/lut_map.v
@@ -26,6 +26,7 @@ module \$lut (A, Y);
parameter WIDTH = 0;
parameter LUT = 0;
+ (* force_downto *)
input [WIDTH-1:0] A;
output Y;
diff --git a/techlibs/xilinx/mux_map.v b/techlibs/xilinx/mux_map.v
index 91aaf2118..bb31d21ec 100644
--- a/techlibs/xilinx/mux_map.v
+++ b/techlibs/xilinx/mux_map.v
@@ -30,8 +30,11 @@ module \$shiftx (A, B, Y);
parameter B_WIDTH = 1;
parameter Y_WIDTH = 1;
+ (* force_downto *)
input [A_WIDTH-1:0] A;
+ (* force_downto *)
input [B_WIDTH-1:0] B;
+ (* force_downto *)
output [Y_WIDTH-1:0] Y;
parameter [B_WIDTH-1:0] _TECHMAP_CONSTMSK_B_ = 0;
diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc
index 229ffcb3d..b66dc850d 100644
--- a/techlibs/xilinx/synth_xilinx.cc
+++ b/techlibs/xilinx/synth_xilinx.cc
@@ -30,13 +30,13 @@ struct SynthXilinxPass : public ScriptPass
{
SynthXilinxPass() : ScriptPass("synth_xilinx", "synthesis for Xilinx FPGAs") { }
- void on_register() YS_OVERRIDE
+ void on_register() override
{
RTLIL::constpad["synth_xilinx.abc9.xc7.W"] = "300"; // Number with which ABC will map a 6-input gate
// to one LUT6 (instead of a LUT5 + LUT2)
}
- void help() YS_OVERRIDE
+ void help() override
{
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
log("\n");
@@ -143,13 +143,13 @@ struct SynthXilinxPass : public ScriptPass
std::string top_opt, edif_file, blif_file, family;
bool flatten, retime, vpr, ise, noiopad, noclkbuf, nobram, nolutram, nosrl, nocarry, nowidelut, nodsp, uram;
- bool abc9, dff_mode;
+ bool abc9, dff;
bool flatten_before_abc;
int widemux;
int lut_size;
int widelut_size;
- void clear_flags() YS_OVERRIDE
+ void clear_flags() override
{
top_opt = "-auto-top";
edif_file.clear();
@@ -170,13 +170,13 @@ struct SynthXilinxPass : public ScriptPass
nodsp = false;
uram = false;
abc9 = false;
- dff_mode = false;
+ dff = false;
flatten_before_abc = false;
widemux = 0;
lut_size = 6;
}
- void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
+ void execute(std::vector<std::string> args, RTLIL::Design *design) override
{
std::string run_from, run_to;
clear_flags();
@@ -217,7 +217,7 @@ struct SynthXilinxPass : public ScriptPass
continue;
}
if (args[argidx] == "-retime") {
- dff_mode = true;
+ dff = true;
retime = true;
continue;
}
@@ -281,7 +281,7 @@ struct SynthXilinxPass : public ScriptPass
continue;
}
if (args[argidx] == "-dff") {
- dff_mode = true;
+ dff = true;
continue;
}
break;
@@ -337,7 +337,7 @@ struct SynthXilinxPass : public ScriptPass
log_pop();
}
- void script() YS_OVERRIDE
+ void script() override
{
std::string lut_size_s = std::to_string(lut_size);
if (help_mode)
@@ -540,7 +540,7 @@ struct SynthXilinxPass : public ScriptPass
}
if (check_label("fine")) {
- run("dff2dffe -direct-match $_DFF_* -direct-match $__DFFS_*");
+ run("dff2dffe -direct-match $_DFF_* -direct-match $_SDFF_*");
if (help_mode)
run("muxcover <internal options> ('-widemux' only)");
else if (widemux > 0) {
@@ -595,9 +595,11 @@ struct SynthXilinxPass : public ScriptPass
run("clean");
}
- if (check_label("map_ffs")) {
+ if (check_label("map_ffs", "('-abc9' only)")) {
if (abc9 || help_mode) {
- run("techmap -map " + ff_map_file, "('-abc9' only)");
+ if (dff || help_mode)
+ run("zinit -all w:* t:$_DFF_?_ t:$_DFFE_??_ t:$_SDFF*", "('-dff' only)");
+ run("techmap -map " + ff_map_file);
}
}
@@ -606,18 +608,14 @@ struct SynthXilinxPass : public ScriptPass
if (flatten_before_abc)
run("flatten");
if (help_mode)
- run("abc -luts 2:2,3,6:5[,10,20] [-dff] [-D 1]", "(option for 'nowidelut', '-dff', '-retime')");
+ run("abc -luts 2:2,3,6:5[,10,20] [-dff] [-D 1]", "(option for '-nowidelut', '-dff', '-retime')");
else if (abc9) {
if (lut_size != 6)
log_error("'synth_xilinx -abc9' not currently supported for LUT4-based devices.\n");
if (family != "xc7")
log_warning("'synth_xilinx -abc9' not currently supported for the '%s' family, "
"will use timing for 'xc7' instead.\n", family.c_str());
- std::string techmap_args = "-map +/xilinx/abc9_map.v -max_iter 1";
- if (dff_mode)
- techmap_args += " -D DFF_MODE";
- run("techmap " + techmap_args);
- run("read_verilog -icells -lib -specify +/abc9_model.v +/xilinx/abc9_model.v");
+ run("read_verilog -icells -lib -specify +/xilinx/abc9_model.v");
std::string abc9_opts;
std::string k = "synth_xilinx.abc9.W";
if (active_design && active_design->scratchpad.count(k))
@@ -628,10 +626,9 @@ struct SynthXilinxPass : public ScriptPass
}
if (nowidelut)
abc9_opts += stringf(" -maxlut %d", lut_size);
- if (dff_mode)
+ if (dff)
abc9_opts += " -dff";
run("abc9" + abc9_opts);
- run("techmap -map +/xilinx/abc9_unmap.v");
}
else {
std::string abc_opts;
@@ -648,7 +645,7 @@ struct SynthXilinxPass : public ScriptPass
else
abc_opts += " -luts 2:2,3,6:5,10,20,40";
}
- if (dff_mode)
+ if (dff)
abc_opts += " -dff";
if (retime)
abc_opts += " -D 1";
diff --git a/techlibs/xilinx/xc6s_ff_map.v b/techlibs/xilinx/xc6s_ff_map.v
index c40f446e0..a1e4218b9 100644
--- a/techlibs/xilinx/xc6s_ff_map.v
+++ b/techlibs/xilinx/xc6s_ff_map.v
@@ -111,7 +111,7 @@ endmodule
// Async reset, enable.
-module \$__DFFE_NP0 (input D, C, E, R, output Q);
+module \$_DFFE_NP0P_ (input D, C, E, R, output Q);
parameter [0:0] _TECHMAP_WIREINIT_Q_ = 1'bx;
generate if (_TECHMAP_WIREINIT_Q_ === 1'b1)
$error("Spartan 6 doesn't support FFs with asynchronous reset initialized to 1");
@@ -120,7 +120,7 @@ module \$__DFFE_NP0 (input D, C, E, R, output Q);
endgenerate
wire _TECHMAP_REMOVEINIT_Q_ = 1;
endmodule
-module \$__DFFE_PP0 (input D, C, E, R, output Q);
+module \$_DFFE_PP0P_ (input D, C, E, R, output Q);
parameter [0:0] _TECHMAP_WIREINIT_Q_ = 1'bx;
generate if (_TECHMAP_WIREINIT_Q_ === 1'b1)
$error("Spartan 6 doesn't support FFs with asynchronous reset initialized to 1");
@@ -130,7 +130,7 @@ module \$__DFFE_PP0 (input D, C, E, R, output Q);
wire _TECHMAP_REMOVEINIT_Q_ = 1;
endmodule
-module \$__DFFE_NP1 (input D, C, E, R, output Q);
+module \$_DFFE_NP1P_ (input D, C, E, R, output Q);
parameter [0:0] _TECHMAP_WIREINIT_Q_ = 1'bx;
generate if (_TECHMAP_WIREINIT_Q_ === 1'b0)
$error("Spartan 6 doesn't support FFs with asynchronous set initialized to 0");
@@ -139,7 +139,7 @@ module \$__DFFE_NP1 (input D, C, E, R, output Q);
endgenerate
wire _TECHMAP_REMOVEINIT_Q_ = 1;
endmodule
-module \$__DFFE_PP1 (input D, C, E, R, output Q);
+module \$_DFFE_PP1P_ (input D, C, E, R, output Q);
parameter [0:0] _TECHMAP_WIREINIT_Q_ = 1'bx;
generate if (_TECHMAP_WIREINIT_Q_ === 1'b0)
$error("Spartan 6 doesn't support FFs with asynchronous set initialized to 0");
@@ -151,7 +151,7 @@ endmodule
// Sync reset.
-module \$__DFFS_NP0_ (input D, C, R, output Q);
+module \$_SDFF_NP0_ (input D, C, R, output Q);
parameter [0:0] _TECHMAP_WIREINIT_Q_ = 1'bx;
generate if (_TECHMAP_WIREINIT_Q_ === 1'b1)
$error("Spartan 6 doesn't support FFs with reset initialized to 1");
@@ -160,7 +160,7 @@ module \$__DFFS_NP0_ (input D, C, R, output Q);
endgenerate
wire _TECHMAP_REMOVEINIT_Q_ = 1;
endmodule
-module \$__DFFS_PP0_ (input D, C, R, output Q);
+module \$_SDFF_PP0_ (input D, C, R, output Q);
parameter [0:0] _TECHMAP_WIREINIT_Q_ = 1'bx;
generate if (_TECHMAP_WIREINIT_Q_ === 1'b1)
$error("Spartan 6 doesn't support FFs with reset initialized to 1");
@@ -170,7 +170,7 @@ module \$__DFFS_PP0_ (input D, C, R, output Q);
wire _TECHMAP_REMOVEINIT_Q_ = 1;
endmodule
-module \$__DFFS_NP1_ (input D, C, R, output Q);
+module \$_SDFF_NP1_ (input D, C, R, output Q);
parameter [0:0] _TECHMAP_WIREINIT_Q_ = 1'bx;
generate if (_TECHMAP_WIREINIT_Q_ === 1'b0)
$error("Spartan 6 doesn't support FFs with set initialized to 0");
@@ -179,7 +179,7 @@ module \$__DFFS_NP1_ (input D, C, R, output Q);
endgenerate
wire _TECHMAP_REMOVEINIT_Q_ = 1;
endmodule
-module \$__DFFS_PP1_ (input D, C, R, output Q);
+module \$_SDFF_PP1_ (input D, C, R, output Q);
parameter [0:0] _TECHMAP_WIREINIT_Q_ = 1'bx;
generate if (_TECHMAP_WIREINIT_Q_ === 1'b0)
$error("Spartan 6 doesn't support FFs with set initialized to 0");
@@ -191,7 +191,7 @@ endmodule
// Sync reset, enable.
-module \$__DFFSE_NP0 (input D, C, E, R, output Q);
+module \$_SDFFE_NP0P_ (input D, C, E, R, output Q);
parameter [0:0] _TECHMAP_WIREINIT_Q_ = 1'bx;
generate if (_TECHMAP_WIREINIT_Q_ === 1'b1)
$error("Spartan 6 doesn't support FFs with reset initialized to 1");
@@ -200,7 +200,7 @@ module \$__DFFSE_NP0 (input D, C, E, R, output Q);
endgenerate
wire _TECHMAP_REMOVEINIT_Q_ = 1;
endmodule
-module \$__DFFSE_PP0 (input D, C, E, R, output Q);
+module \$_SDFFE_PP0P_ (input D, C, E, R, output Q);
parameter [0:0] _TECHMAP_WIREINIT_Q_ = 1'bx;
generate if (_TECHMAP_WIREINIT_Q_ === 1'b1)
$error("Spartan 6 doesn't support FFs with reset initialized to 1");
@@ -210,7 +210,7 @@ module \$__DFFSE_PP0 (input D, C, E, R, output Q);
wire _TECHMAP_REMOVEINIT_Q_ = 1;
endmodule
-module \$__DFFSE_NP1 (input D, C, E, R, output Q);
+module \$_SDFFE_NP1P_ (input D, C, E, R, output Q);
parameter [0:0] _TECHMAP_WIREINIT_Q_ = 1'bx;
generate if (_TECHMAP_WIREINIT_Q_ === 1'b0)
$error("Spartan 6 doesn't support FFs with set initialized to 0");
@@ -219,7 +219,7 @@ module \$__DFFSE_NP1 (input D, C, E, R, output Q);
endgenerate
wire _TECHMAP_REMOVEINIT_Q_ = 1;
endmodule
-module \$__DFFSE_PP1 (input D, C, E, R, output Q);
+module \$_SDFFE_PP1P_ (input D, C, E, R, output Q);
parameter [0:0] _TECHMAP_WIREINIT_Q_ = 1'bx;
generate if (_TECHMAP_WIREINIT_Q_ === 1'b0)
$error("Spartan 6 doesn't support FFs with set initialized to 0");
diff --git a/techlibs/xilinx/xc7_ff_map.v b/techlibs/xilinx/xc7_ff_map.v
index 2bd874457..750e8f8eb 100644
--- a/techlibs/xilinx/xc7_ff_map.v
+++ b/techlibs/xilinx/xc7_ff_map.v
@@ -89,23 +89,23 @@ endmodule
// Async reset, enable.
-module \$__DFFE_NP0 (input D, C, E, R, output Q);
+module \$_DFFE_NP0P_ (input D, C, E, R, output Q);
parameter _TECHMAP_WIREINIT_Q_ = 1'bx;
FDCE_1 #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(E), .CLR( R));
wire _TECHMAP_REMOVEINIT_Q_ = 1;
endmodule
-module \$__DFFE_PP0 (input D, C, E, R, output Q);
+module \$_DFFE_PP0P_ (input D, C, E, R, output Q);
parameter _TECHMAP_WIREINIT_Q_ = 1'bx;
FDCE #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(E), .CLR( R));
wire _TECHMAP_REMOVEINIT_Q_ = 1;
endmodule
-module \$__DFFE_NP1 (input D, C, E, R, output Q);
+module \$_DFFE_NP1P_ (input D, C, E, R, output Q);
parameter _TECHMAP_WIREINIT_Q_ = 1'bx;
FDPE_1 #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(E), .PRE( R));
wire _TECHMAP_REMOVEINIT_Q_ = 1;
endmodule
-module \$__DFFE_PP1 (input D, C, E, R, output Q);
+module \$_DFFE_PP1P_ (input D, C, E, R, output Q);
parameter _TECHMAP_WIREINIT_Q_ = 1'bx;
FDPE #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(E), .PRE( R));
wire _TECHMAP_REMOVEINIT_Q_ = 1;
@@ -113,23 +113,23 @@ endmodule
// Sync reset.
-module \$__DFFS_NP0_ (input D, C, R, output Q);
+module \$_SDFF_NP0_ (input D, C, R, output Q);
parameter _TECHMAP_WIREINIT_Q_ = 1'bx;
FDRE_1 #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(1'b1), .R( R));
wire _TECHMAP_REMOVEINIT_Q_ = 1;
endmodule
-module \$__DFFS_PP0_ (input D, C, R, output Q);
+module \$_SDFF_PP0_ (input D, C, R, output Q);
parameter _TECHMAP_WIREINIT_Q_ = 1'bx;
FDRE #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(1'b1), .R( R));
wire _TECHMAP_REMOVEINIT_Q_ = 1;
endmodule
-module \$__DFFS_NP1_ (input D, C, R, output Q);
+module \$_SDFF_NP1_ (input D, C, R, output Q);
parameter _TECHMAP_WIREINIT_Q_ = 1'bx;
FDSE_1 #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(1'b1), .S( R));
wire _TECHMAP_REMOVEINIT_Q_ = 1;
endmodule
-module \$__DFFS_PP1_ (input D, C, R, output Q);
+module \$_SDFF_PP1_ (input D, C, R, output Q);
parameter _TECHMAP_WIREINIT_Q_ = 1'bx;
FDSE #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(1'b1), .S( R));
wire _TECHMAP_REMOVEINIT_Q_ = 1;
@@ -137,23 +137,23 @@ endmodule
// Sync reset, enable.
-module \$__DFFSE_NP0 (input D, C, E, R, output Q);
+module \$_SDFFE_NP0P_ (input D, C, E, R, output Q);
parameter _TECHMAP_WIREINIT_Q_ = 1'bx;
FDRE_1 #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(E), .R( R));
wire _TECHMAP_REMOVEINIT_Q_ = 1;
endmodule
-module \$__DFFSE_PP0 (input D, C, E, R, output Q);
+module \$_SDFFE_PP0P_ (input D, C, E, R, output Q);
parameter _TECHMAP_WIREINIT_Q_ = 1'bx;
FDRE #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(E), .R( R));
wire _TECHMAP_REMOVEINIT_Q_ = 1;
endmodule
-module \$__DFFSE_NP1 (input D, C, E, R, output Q);
+module \$_SDFFE_NP1P_ (input D, C, E, R, output Q);
parameter _TECHMAP_WIREINIT_Q_ = 1'bx;
FDSE_1 #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(E), .S( R));
wire _TECHMAP_REMOVEINIT_Q_ = 1;
endmodule
-module \$__DFFSE_PP1 (input D, C, E, R, output Q);
+module \$_SDFFE_PP1P_ (input D, C, E, R, output Q);
parameter _TECHMAP_WIREINIT_Q_ = 1'bx;
FDSE #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(E), .S( R));
wire _TECHMAP_REMOVEINIT_Q_ = 1;
diff --git a/techlibs/xilinx/xilinx_dffopt.cc b/techlibs/xilinx/xilinx_dffopt.cc
index c9d63c9f7..365f505fb 100644
--- a/techlibs/xilinx/xilinx_dffopt.cc
+++ b/techlibs/xilinx/xilinx_dffopt.cc
@@ -99,7 +99,7 @@ bool merge_lut(LutData &result, const LutData &data, const LutData select, bool
struct XilinxDffOptPass : public Pass {
XilinxDffOptPass() : Pass("xilinx_dffopt", "Xilinx: optimize FF control signal usage") { }
- void help() YS_OVERRIDE
+ void help() override
{
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
log("\n");
@@ -113,7 +113,7 @@ struct XilinxDffOptPass : public Pass {
log(" Assume a LUT4-based device (instead of a LUT6-based device).\n");
log("\n");
}
- void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
+ void execute(std::vector<std::string> args, RTLIL::Design *design) override
{
log_header(design, "Executing XILINX_DFFOPT pass (optimize FF control signal usage).\n");
diff --git a/tests/arch/ecp5/latches_abc9.ys b/tests/arch/ecp5/latches_abc9.ys
new file mode 100644
index 000000000..4daf04050
--- /dev/null
+++ b/tests/arch/ecp5/latches_abc9.ys
@@ -0,0 +1,13 @@
+read_verilog <<EOT
+module top(input e, d, output q);
+reg l;
+always @*
+ if (e)
+ l = ~d;
+assign q = ~l;
+endmodule
+EOT
+# Can't run any sort of equivalence check because latches are blown to LUTs
+synth_ecp5 -abc9
+select -assert-count 2 t:LUT4
+select -assert-none t:LUT4 %% t:* %D
diff --git a/tests/arch/ice40/mux.ys b/tests/arch/ice40/mux.ys
index 99822391d..2b661fd6b 100644
--- a/tests/arch/ice40/mux.ys
+++ b/tests/arch/ice40/mux.ys
@@ -35,6 +35,7 @@ proc
equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd mux16 # Constrain all select calls below inside the top module
-select -assert-count 11 t:SB_LUT4
+select -assert-min 11 t:SB_LUT4
+select -assert-max 12 t:SB_LUT4
select -assert-none t:SB_LUT4 %% t:* %D
diff --git a/tests/arch/intel_alm/.gitignore b/tests/arch/intel_alm/.gitignore
new file mode 100644
index 000000000..ba42e1ee6
--- /dev/null
+++ b/tests/arch/intel_alm/.gitignore
@@ -0,0 +1,2 @@
+/*.log
+/run-test.mk
diff --git a/tests/arch/intel_alm/dffs.ys b/tests/arch/intel_alm/dffs.ys
index cf29ad8e0..149b3121a 100644
--- a/tests/arch/intel_alm/dffs.ys
+++ b/tests/arch/intel_alm/dffs.ys
@@ -17,6 +17,5 @@ equiv_opt -async2sync -assert -map +/intel_alm/common/alm_sim.v -map +/intel_alm
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd dffe # Constrain all select calls below inside the top module
select -assert-count 1 t:MISTRAL_FF
-select -assert-count 1 t:MISTRAL_ALUT3
-select -assert-none t:MISTRAL_FF t:MISTRAL_ALUT3 %% t:* %D
+select -assert-none t:MISTRAL_FF %% t:* %D
diff --git a/tests/arch/intel_alm/fsm.ys b/tests/arch/intel_alm/fsm.ys
index 8bb0ebab2..67965569b 100644
--- a/tests/arch/intel_alm/fsm.ys
+++ b/tests/arch/intel_alm/fsm.ys
@@ -13,6 +13,7 @@ cd fsm # Constrain all select calls below inside the top module
select -assert-count 6 t:MISTRAL_FF
select -assert-max 2 t:MISTRAL_ALUT2 # Clang returns 2, GCC returns 1
+select -assert-count 1 t:MISTRAL_ALUT3
select -assert-count 5 t:MISTRAL_ALUT5
-select -assert-count 1 t:MISTRAL_ALUT6
-select -assert-none t:MISTRAL_FF t:MISTRAL_ALUT2 t:MISTRAL_ALUT5 t:MISTRAL_ALUT6 %% t:* %D
+select -assert-count 2 t:MISTRAL_ALUT6
+select -assert-none t:MISTRAL_FF t:MISTRAL_ALUT2 t:MISTRAL_ALUT3 t:MISTRAL_ALUT5 t:MISTRAL_ALUT6 %% t:* %D
diff --git a/tests/arch/xilinx/abc9_dff.ys b/tests/arch/xilinx/abc9_dff.ys
index b457cefce..210e87477 100644
--- a/tests/arch/xilinx/abc9_dff.ys
+++ b/tests/arch/xilinx/abc9_dff.ys
@@ -1,32 +1,134 @@
+logger -nowarn "Yosys has only limited support for tri-state logic at the moment\. .*"
+
read_verilog <<EOT
module top(input C, D, output [7:0] Q);
-FDRE fd1(.C(C), .CE(1'b1), .D(D), .R(1'b1), .Q(Q[0]));
-FDSE fd2(.C(C), .CE(1'b1), .D(D), .S(1'b1), .Q(Q[1]));
-FDCE fd3(.C(C), .CE(1'b1), .D(D), .CLR(1'b1), .Q(Q[2]));
-FDPE fd4(.C(C), .CE(1'b1), .D(D), .PRE(1'b1), .Q(Q[3]));
-FDRE_1 fd5(.C(C), .CE(1'b1), .D(D), .R(1'b1), .Q(Q[4]));
-FDSE_1 fd6(.C(C), .CE(1'b1), .D(D), .S(1'b1), .Q(Q[5]));
-FDCE_1 fd7(.C(C), .CE(1'b1), .D(D), .CLR(1'b1), .Q(Q[6]));
-FDPE_1 fd8(.C(C), .CE(1'b1), .D(D), .PRE(1'b1), .Q(Q[7]));
+FDRE /*#(.INIT(0))*/ fd1(.C(C), .CE(1'b1), .D(D), .R(1'b1), .Q(Q[0]));
+FDSE #(.INIT(0)) fd2(.C(C), .CE(1'b1), .D(D), .S(1'b1), .Q(Q[1]));
+FDCE #(.INIT(0)) fd3(.C(C), .CE(1'b1), .D(D), .CLR(1'b1), .Q(Q[2]));
+FDPE #(.INIT(0)) fd4(.C(C), .CE(1'b1), .D(D), .PRE(1'b1), .Q(Q[3]));
+FDRE_1 #(.INIT(0)) fd5(.C(C), .CE(1'b1), .D(D), .R(1'b1), .Q(Q[4]));
+FDSE_1 #(.INIT(0)) fd6(.C(C), .CE(1'b1), .D(D), .S(1'b1), .Q(Q[5]));
+FDCE_1 #(.INIT(0)) fd7(.C(C), .CE(1'b1), .D(D), .CLR(1'b1), .Q(Q[6]));
+FDPE_1 #(.INIT(0)) fd8(.C(C), .CE(1'b1), .D(D), .PRE(1'b1), .Q(Q[7]));
endmodule
EOT
equiv_opt -assert -multiclock -map +/xilinx/cells_sim.v synth_xilinx -abc9 -dff -noiopad -noclkbuf
design -load postopt
-select -assert-none t:FD*
+select -assert-count 6 t:FD*
+select -assert-count 6 c:fd2 c:fd3 c:fd4 c:fd6 c:fd7 c:fd8
+
+
+design -reset
+read_verilog <<EOT
+module top(input C, D, output [7:0] Q);
+FDRE #(.INIT(0)) fd1(.C(C), .CE(1'b0), .D(D), .R(1'b0), .Q(Q[0]));
+FDSE #(.INIT(0)) fd2(.C(C), .CE(1'b0), .D(D), .S(1'b0), .Q(Q[1]));
+FDCE #(.INIT(0)) fd3(.C(C), .CE(1'b0), .D(D), .CLR(1'b0), .Q(Q[2]));
+FDPE #(.INIT(0)) fd4(.C(C), .CE(1'b0), .D(D), .PRE(1'b0), .Q(Q[3]));
+FDRE_1 /*#(.INIT(0))*/ fd5(.C(C), .CE(1'b0), .D(D), .R(1'b0), .Q(Q[4]));
+FDSE_1 #(.INIT(0)) fd6(.C(C), .CE(1'b0), .D(D), .S(1'b0), .Q(Q[5]));
+FDCE_1 #(.INIT(0)) fd7(.C(C), .CE(1'b0), .D(D), .CLR(1'b0), .Q(Q[6]));
+FDPE_1 #(.INIT(0)) fd8(.C(C), .CE(1'b0), .D(D), .PRE(1'b0), .Q(Q[7]));
+endmodule
+EOT
+equiv_opt -assert -multiclock -map +/xilinx/cells_sim.v synth_xilinx -abc9 -dff -noiopad -noclkbuf
+design -load postopt
+select -assert-count 4 t:FD*
+select -assert-count 4 c:fd3 c:fd4 c:fd7 c:fd8
+
design -reset
read_verilog <<EOT
module top(input C, D, output [7:0] Q);
-FDRE fd1(.C(C), .CE(1'b0), .D(D), .R(1'b0), .Q(Q[0]));
-FDSE fd2(.C(C), .CE(1'b0), .D(D), .S(1'b0), .Q(Q[1]));
-FDCE fd3(.C(C), .CE(1'b0), .D(D), .CLR(1'b0), .Q(Q[2]));
-FDPE fd4(.C(C), .CE(1'b0), .D(D), .PRE(1'b0), .Q(Q[3]));
-FDRE_1 fd5(.C(C), .CE(1'b0), .D(D), .R(1'b0), .Q(Q[4]));
-FDSE_1 fd6(.C(C), .CE(1'b0), .D(D), .S(1'b0), .Q(Q[5]));
-FDCE_1 fd7(.C(C), .CE(1'b0), .D(D), .CLR(1'b0), .Q(Q[6]));
-FDPE_1 fd8(.C(C), .CE(1'b0), .D(D), .PRE(1'b0), .Q(Q[7]));
+FDRE #(.INIT(1)) fd1(.C(C), .CE(1'b0), .D(D), .R(1'b0), .Q(Q[0]));
+FDSE /*#(.INIT(1))*/ fd2(.C(C), .CE(1'b0), .D(D), .S(1'b0), .Q(Q[1]));
+FDCE #(.INIT(1)) fd3(.C(C), .CE(1'b0), .D(D), .CLR(1'b0), .Q(Q[2]));
+FDPE #(.INIT(1)) fd4(.C(C), .CE(1'b0), .D(D), .PRE(1'b0), .Q(Q[3]));
+FDRE_1 #(.INIT(1)) fd5(.C(C), .CE(1'b0), .D(D), .R(1'b0), .Q(Q[4]));
+FDSE_1 #(.INIT(1)) fd6(.C(C), .CE(1'b0), .D(D), .S(1'b0), .Q(Q[5]));
+FDCE_1 /*#(.INIT(1))*/ fd7(.C(C), .CE(1'b0), .D(D), .CLR(1'b0), .Q(Q[6]));
+FDPE_1 #(.INIT(1)) fd8(.C(C), .CE(1'b0), .D(D), .PRE(1'b0), .Q(Q[7]));
+endmodule
+EOT
+logger -expect warning "Whitebox '\$paramod\\FDRE\\INIT=1' with \(\* abc9_flop \*\) contains a \$dff cell with non-zero initial state -- this is not supported for ABC9 sequential synthesis. Treating as a blackbox\." 1
+logger -expect warning "Whitebox '\$paramod\\FDRE_1\\INIT=1' with \(\* abc9_flop \*\) contains a \$dff cell with non-zero initial state -- this is not supported for ABC9 sequential synthesis. Treating as a blackbox\." 1
+logger -expect warning "Whitebox 'FDSE' with \(\* abc9_flop \*\) contains a \$dff cell with non-zero initial state -- this is not supported for ABC9 sequential synthesis. Treating as a blackbox\." 1
+logger -expect warning "Whitebox '\$paramod\\FDSE_1\\INIT=1' with \(\* abc9_flop \*\) contains a \$dff cell with non-zero initial state -- this is not supported for ABC9 sequential synthesis. Treating as a blackbox\." 1
+equiv_opt -assert -multiclock -map +/xilinx/cells_sim.v synth_xilinx -abc9 -dff -noiopad -noclkbuf
+design -load postopt
+select -assert-count 8 t:FD*
+
+
+design -reset
+read_verilog <<EOT
+module top(input clk, clr, pre, output reg q0 = 1'b0, output reg q1 = 1'b1);
+always @(posedge clk or posedge clr)
+ if (clr)
+ q0 <= 1'b0;
+ else
+ q0 <= ~q0;
+always @(posedge clk or posedge pre)
+ if (pre)
+ q1 <= 1'b1;
+ else
+ q1 <= ~q1;
+endmodule
+EOT
+proc
+equiv_opt -assert -multiclock -map +/xilinx/cells_sim.v synth_xilinx -abc9 -dff -noiopad -noclkbuf
+design -load postopt
+select -assert-count 1 t:FDCE
+select -assert-count 1 t:FDPE
+select -assert-count 2 t:INV
+select -assert-count 0 t:FD* t:INV %% t:* %D
+
+
+design -reset
+read_verilog <<EOT
+module top(input clk, input d, output q);
+reg r;
+always @(posedge clk) begin
+r <= d;
+end
+assign q = ~r;
+endmodule
+EOT
+proc
+equiv_opt -assert -multiclock -map +/xilinx/cells_sim.v synth_xilinx -abc9 -dff -noiopad -noclkbuf
+design -load postopt
+select -assert-count 1 t:FDRE %co w:r %i
+
+
+design -reset
+read_verilog <<EOT
+module top(input clk, input a, b, output reg q1, output q2);
+reg r;
+always @(posedge clk) begin
+ q1 <= a | b;
+ r <= ~(~a & ~b);
+end
+assign q2 = r;
endmodule
EOT
+proc
equiv_opt -assert -multiclock -map +/xilinx/cells_sim.v synth_xilinx -abc9 -dff -noiopad -noclkbuf
design -load postopt
-select -assert-none t:FD*
+select -assert-count 1 t:FDRE %co %a w:r %i
+
+
+design -reset
+read_verilog <<EOT
+module top(input clk, input a, b, output o);
+reg r1, r2;
+always @(posedge clk) begin
+ r1 <= a | b;
+ r2 <= ~(~a & ~b);
+end
+assign o = r1 | r2;
+endmodule
+EOT
+proc
+equiv_opt -assert -multiclock -map +/xilinx/cells_sim.v synth_xilinx -abc9 -dff -noiopad -noclkbuf
+
+
+logger -expect-no-warnings
diff --git a/tests/arch/xilinx/abc9_map.ys b/tests/arch/xilinx/abc9_map.ys
deleted file mode 100644
index 4a7b9384a..000000000
--- a/tests/arch/xilinx/abc9_map.ys
+++ /dev/null
@@ -1,91 +0,0 @@
-read_verilog <<EOT
-module top(input C, CE, D, R, output [1:0] Q);
-FDRE #(.INIT(1'b1)) ff1 (.C(C), .CE(CE), .D(D), .R(R), .Q(Q[0]));
-FDRE_1 #(.INIT(1'b1)) ff2 (.C(C), .CE(CE), .D(D), .R(R), .Q(Q[1]));
-endmodule
-EOT
-design -save gold
-
-techmap -map +/xilinx/abc9_map.v -max_iter 1 -D DFF_MODE
-techmap -map +/xilinx/abc9_unmap.v
-select -assert-count 1 t:FDSE
-select -assert-count 1 t:FDSE_1
-techmap -autoproc -map +/xilinx/cells_sim.v
-design -stash gate
-
-design -import gold -as gold
-design -import gate -as gate
-techmap -autoproc -map +/xilinx/cells_sim.v
-
-miter -equiv -flatten -make_assert -make_outputs gold gate miter
-sat -seq 2 -verify -prove-asserts -show-ports miter
-
-design -reset
-read_verilog <<EOT
-module top(input C, CE, D, S, output [1:0] Q);
-FDSE #(.INIT(1'b1)) ff1 (.C(C), .CE(CE), .D(D), .S(S), .Q(Q[0]));
-FDSE_1 #(.INIT(1'b1)) ff2 (.C(C), .CE(CE), .D(D), .S(S), .Q(Q[1]));
-endmodule
-EOT
-design -save gold
-
-techmap -map +/xilinx/abc9_map.v -max_iter 1 -D DFF_MODE
-techmap -map +/xilinx/abc9_unmap.v
-select -assert-count 1 t:FDRE
-select -assert-count 1 t:FDRE_1
-techmap -autoproc -map +/xilinx/cells_sim.v
-design -stash gate
-
-design -import gold -as gold
-design -import gate -as gate
-techmap -autoproc -map +/xilinx/cells_sim.v
-
-miter -equiv -flatten -make_assert -make_outputs gold gate miter
-sat -seq 2 -set-init-zero -verify -prove-asserts -show-ports miter
-
-design -reset
-read_verilog <<EOT
-module top(input C, CE, D, PRE, output [1:0] Q);
-FDPE #(.INIT(1'b1)) ff1 (.C(C), .CE(CE), .D(D), .PRE(PRE), .Q(Q[0]));
-FDPE_1 #(.INIT(1'b1)) ff2 (.C(C), .CE(CE), .D(D), .PRE(PRE), .Q(Q[1]));
-endmodule
-EOT
-design -save gold
-
-techmap -map +/xilinx/abc9_map.v -max_iter 1 -D DFF_MODE
-techmap -map +/xilinx/abc9_unmap.v
-select -assert-count 1 t:FDCE
-select -assert-count 1 t:FDCE_1
-techmap -autoproc -map +/xilinx/cells_sim.v
-design -stash gate
-
-design -import gold -as gold
-design -import gate -as gate
-techmap -autoproc -map +/xilinx/cells_sim.v
-clk2fflogic
-
-miter -equiv -flatten -make_assert -make_outputs gold gate miter
-sat -seq 2 -set-init-zero -verify -prove-asserts -show-ports miter
-
-design -reset
-read_verilog <<EOT
-module top(input C, CE, D, CLR, output [1:0] Q);
-FDCE #(.INIT(1'b1)) ff1 (.C(C), .CE(CE), .D(D), .CLR(CLR), .Q(Q[0]));
-FDCE_1 #(.INIT(1'b1)) ff2 (.C(C), .CE(CE), .D(D), .CLR(CLR), .Q(Q[1]));
-endmodule
-EOT
-design -save gold
-
-techmap -map +/xilinx/abc9_map.v -max_iter 1 -D DFF_MODE
-techmap -map +/xilinx/abc9_unmap.v
-select -assert-count 1 t:FDPE
-techmap -autoproc -map +/xilinx/cells_sim.v
-design -stash gate
-
-design -import gold -as gold
-design -import gate -as gate
-techmap -autoproc -map +/xilinx/cells_sim.v
-clk2fflogic
-
-miter -equiv -flatten -make_assert -make_outputs gold gate miter
-sat -seq 2 -set-init-zero -verify -prove-asserts -show-ports miter
diff --git a/tests/arch/xilinx/macc.v b/tests/arch/xilinx/macc.v
index e36b2bab1..1645537fd 100644
--- a/tests/arch/xilinx/macc.v
+++ b/tests/arch/xilinx/macc.v
@@ -10,10 +10,10 @@ module macc # (parameter SIZEIN = 16, SIZEOUT = 40) (
output signed [SIZEOUT-1:0] accum_out
);
// Declare registers for intermediate values
-reg signed [SIZEIN-1:0] a_reg, b_reg;
-reg sload_reg;
-reg signed [2*SIZEIN-1:0] mult_reg;
-reg signed [SIZEOUT-1:0] adder_out, old_result;
+reg signed [SIZEIN-1:0] a_reg = 0, b_reg = 0;
+reg sload_reg = 0;
+reg signed [2*SIZEIN-1:0] mult_reg = 0;
+reg signed [SIZEOUT-1:0] adder_out = 0, old_result;
always @* /*(adder_out or sload_reg)*/ begin // Modification necessary to fix sim/synth mismatch
if (sload_reg)
old_result <= 0;
@@ -50,10 +50,10 @@ module macc2 # (parameter SIZEIN = 16, SIZEOUT = 40) (
output overflow
);
// Declare registers for intermediate values
-reg signed [SIZEIN-1:0] a_reg, b_reg, a_reg2, b_reg2;
+reg signed [SIZEIN-1:0] a_reg = 0, b_reg = 0, a_reg2 = 0, b_reg2 = 0;
reg signed [2*SIZEIN-1:0] mult_reg = 0;
reg signed [SIZEOUT:0] adder_out = 0;
-reg overflow_reg;
+reg overflow_reg = 0;
always @(posedge clk) begin
//if (ce)
begin
diff --git a/tests/arch/xilinx/macc.ys b/tests/arch/xilinx/macc.ys
index bf2b36320..61a570f48 100644
--- a/tests/arch/xilinx/macc.ys
+++ b/tests/arch/xilinx/macc.ys
@@ -6,7 +6,7 @@ proc
#equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx -noiopad ### TODO
equiv_opt -run :prove -map +/xilinx/cells_sim.v synth_xilinx -noiopad
miter -equiv -flatten -make_assert -make_outputs gold gate miter
-sat -verify -prove-asserts -seq 10 -show-inputs -show-outputs miter
+sat -verify -prove-asserts -seq 3 -show-inputs -show-outputs miter
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd macc # Constrain all select calls below inside the top module
select -assert-count 1 t:BUFG
@@ -20,7 +20,7 @@ proc
#equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx -noiopad ### TODO
equiv_opt -run :prove -map +/xilinx/cells_sim.v synth_xilinx -noiopad
miter -equiv -flatten -make_assert -make_outputs gold gate miter
-sat -verify -prove-asserts -seq 10 -show-inputs -show-outputs miter
+sat -verify -prove-asserts -seq 4 -show-inputs -show-outputs miter
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd macc2 # Constrain all select calls below inside the top module
diff --git a/tests/arch/xilinx/mux.ys b/tests/arch/xilinx/mux.ys
index 99817738d..1b2788448 100644
--- a/tests/arch/xilinx/mux.ys
+++ b/tests/arch/xilinx/mux.ys
@@ -40,8 +40,10 @@ proc
equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx -noiopad # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd mux16 # Constrain all select calls below inside the top module
-select -assert-min 5 t:LUT6
+select -assert-max 2 t:LUT4
+select -assert-min 4 t:LUT6
select -assert-max 7 t:LUT6
select -assert-max 2 t:MUXF7
+dump
-select -assert-none t:LUT6 t:MUXF7 %% t:* %D
+select -assert-none t:LUT6 t:LUT4 t:MUXF7 %% t:* %D
diff --git a/tests/arch/xilinx/pmgen_xilinx_srl.ys b/tests/arch/xilinx/pmgen_xilinx_srl.ys
index ea2f20487..e76fb20ab 100644
--- a/tests/arch/xilinx/pmgen_xilinx_srl.ys
+++ b/tests/arch/xilinx/pmgen_xilinx_srl.ys
@@ -1,6 +1,6 @@
read_verilog -icells <<EOT
module \$__XILINX_SHREG_ (input C, input D, input [31:0] L, input E, output Q, output SO);
- parameter DEPTH = 1;
+ parameter DEPTH = 2;
parameter [DEPTH-1:0] INIT = 0;
parameter CLKPOL = 1;
parameter ENPOL = 2;
diff --git a/tests/arch/xilinx/xilinx_srl.v b/tests/arch/xilinx/xilinx_srl.v
index bc2a15ab2..29920da41 100644
--- a/tests/arch/xilinx/xilinx_srl.v
+++ b/tests/arch/xilinx/xilinx_srl.v
@@ -29,7 +29,7 @@ endmodule
module $__XILINX_SHREG_(input C, D, E, input [1:0] L, output Q);
parameter CLKPOL = 1;
parameter ENPOL = 1;
-parameter DEPTH = 1;
+parameter DEPTH = 2;
parameter [DEPTH-1:0] INIT = {DEPTH{1'b0}};
reg [DEPTH-1:0] r = INIT;
wire clk = C ^ CLKPOL;
diff --git a/tests/opt/opt_expr_combined_assign.ys b/tests/opt/opt_expr_combined_assign.ys
new file mode 100644
index 000000000..b18923c7b
--- /dev/null
+++ b/tests/opt/opt_expr_combined_assign.ys
@@ -0,0 +1,83 @@
+read_verilog -sv <<EOT
+module opt_expr_or_test(input [3:0] i, input [7:0] j, output [8:0] o);
+wire[8:0] a = 8'b0;
+initial begin
+ a |= i;
+ a |= j;
+end
+ assign o = a;
+endmodule
+EOT
+proc
+equiv_opt -assert opt_expr -fine
+design -load postopt
+
+select -assert-count 1 t:$or r:A_WIDTH=4 r:B_WIDTH=4 r:Y_WIDTH=4 %i %i %i
+
+design -reset
+read_verilog -sv <<EOT
+module opt_expr_add_test(input [3:0] i, input [7:0] j, output [8:0] o);
+wire[8:0] a = 8'b0;
+initial begin
+ a += i;
+ a += j;
+end
+ assign o = a;
+endmodule
+EOT
+proc
+equiv_opt -assert opt_expr -fine
+design -load postopt
+
+select -assert-count 1 t:$add r:A_WIDTH=9 r:B_WIDTH=8 r:Y_WIDTH=9 %i %i %i
+
+design -reset
+read_verilog -sv <<EOT
+module opt_expr_xor_test(input [3:0] i, input [7:0] j, output [8:0] o);
+wire[8:0] a = 8'b0;
+initial begin
+ a ^= i;
+ a ^= j;
+end
+ assign o = a;
+endmodule
+EOT
+proc
+equiv_opt -assert opt_expr -fine
+design -load postopt
+
+select -assert-count 1 t:$xor r:A_WIDTH=4 r:B_WIDTH=4 r:Y_WIDTH=4 %i %i %i
+
+design -reset
+read_verilog -sv <<EOT
+module opt_expr_sub_test(input [3:0] i, input [7:0] j, output [8:0] o);
+wire[8:0] a = 8'b0;
+initial begin
+ a -= i;
+ a -= j;
+end
+ assign o = a;
+endmodule
+EOT
+proc
+equiv_opt -assert opt_expr -fine
+design -load postopt
+
+select -assert-count 1 t:$sub r:A_WIDTH=9 r:B_WIDTH=8 r:Y_WIDTH=9 %i %i %i
+
+design -reset
+read_verilog -sv <<EOT
+module opt_expr_and_test(input [3:0] i, input [7:0] j, output [8:0] o);
+wire[8:0] a = 8'b11111111;
+initial begin
+ a &= i;
+ a &= j;
+end
+ assign o = a;
+endmodule
+EOT
+proc
+equiv_opt -assert opt_expr -fine
+design -load postopt
+
+select -assert-count 1 t:$and r:A_WIDTH=4 r:B_WIDTH=4 r:Y_WIDTH=4 %i %i %i
diff --git a/tests/opt/opt_rmdff.v b/tests/opt/opt_rmdff.v
index b1c06703c..536bf1d4e 100644
--- a/tests/opt/opt_rmdff.v
+++ b/tests/opt/opt_rmdff.v
@@ -1,50 +1,50 @@
module opt_rmdff_test (input C, input D, input E, output [29:0] Q);
\$dffe #(.WIDTH(1), .CLK_POLARITY(1), .EN_POLARITY(1)) remove0 (.CLK(C), .D(D), .EN(1'b0), .Q(Q[0])); // EN is never active
-(* init = "1'b1" *) wire Q1; assign Q[1] = Q1;
+(* init = 1'b1 *) wire Q1; assign Q[1] = Q1;
\$dffe #(.WIDTH(1), .CLK_POLARITY(1), .EN_POLARITY(1)) remove1 (.CLK(C), .D(D), .EN(1'b0), .Q(Q1)); // EN is never active
\$dffe #(.WIDTH(1), .CLK_POLARITY(1), .EN_POLARITY(1)) remove2 (.CLK(C), .D(D), .EN(1'bx), .Q(Q[2])); // EN is don't care
\$dffe #(.WIDTH(1), .CLK_POLARITY(1), .EN_POLARITY(1)) keep3 (.CLK(C), .D(D), .EN(1'b1), .Q(Q[3])); // EN is always active
-(* init = "1'b0" *) wire Q4; assign Q[4] = Q4;
+(* init = 1'b0 *) wire Q4; assign Q[4] = Q4;
\$dffe #(.WIDTH(1), .CLK_POLARITY(0), .EN_POLARITY(1)) keep4 (.CLK(C), .D(D), .EN(1'b1), .Q(Q4)); // EN is always active
\$dffe #(.WIDTH(1), .CLK_POLARITY(1), .EN_POLARITY(0)) remove5 (.CLK(C), .D(D), .EN(1'b1), .Q(Q[5])); // EN is never active
\$dffe #(.WIDTH(1), .CLK_POLARITY(1), .EN_POLARITY(0)) remove6 (.CLK(C), .D(D), .EN(1'bx), .Q(Q[6])); // EN is don't care
-(* init = "1'b0" *) wire Q7; assign Q[7] = Q7;
+(* init = 1'b0 *) wire Q7; assign Q[7] = Q7;
\$dffe #(.WIDTH(1), .CLK_POLARITY(0), .EN_POLARITY(0)) keep7 (.CLK(C), .D(D), .EN(E), .Q(Q7)); // EN is non constant
\$_DFFE_PP_ remove8 (.C(C), .D(D), .E(1'b0), .Q(Q[8])); // EN is never active
-(* init = "1'b1" *) wire Q9; assign Q[9] = Q9;
+(* init = 1'b1 *) wire Q9; assign Q[9] = Q9;
\$_DFFE_PP_ remove9 (.C(C), .D(D), .E(1'b0), .Q(Q9)); // EN is never active
\$_DFFE_PP_ remove10 (.C(C), .D(D), .E(1'bx), .Q(Q[10])); // EN is don't care
\$_DFFE_PP_ keep11 (.C(C), .D(D), .E(1'b1), .Q(Q[11])); // EN is always active
-(* init = "1'b0" *) wire Q12; assign Q[12] = Q12;
+(* init = 1'b0 *) wire Q12; assign Q[12] = Q12;
\$_DFFE_PP_ keep12 (.C(C), .D(D), .E(1'b1), .Q(Q12)); // EN is always active
\$_DFFE_NN_ remove13 (.C(C), .D(D), .E(1'b1), .Q(Q[13])); // EN is never active
-(* init = "1'b1" *) wire Q14; assign Q[14] = Q14;
+(* init = 1'b1 *) wire Q14; assign Q[14] = Q14;
\$_DFFE_NN_ remove14 (.C(C), .D(D), .E(1'b1), .Q(Q14)); // EN is never active
\$_DFFE_NN_ remove15 (.C(C), .D(D), .E(1'bx), .Q(Q[15])); // EN is don't care
\$_DFFE_NN_ keep16 (.C(C), .D(D), .E(1'b0), .Q(Q[16])); // EN is always active
-(* init = "1'b0" *) wire Q17; assign Q[17] = Q17;
+(* init = 1'b0 *) wire Q17; assign Q[17] = Q17;
\$_DFFE_NN_ keep17 (.C(C), .D(D), .E(1'b0), .Q(Q17)); // EN is always active
\$dffe #(.WIDTH(1), .CLK_POLARITY(1), .EN_POLARITY(1)) remove18 (.CLK(1'b0), .D(D), .EN(E), .Q(Q[18])); // CLK is constant
-(* init = "1'b1" *) wire Q19; assign Q[19] = Q19;
+(* init = 1'b1 *) wire Q19; assign Q[19] = Q19;
\$dffe #(.WIDTH(1), .CLK_POLARITY(1), .EN_POLARITY(1)) remove19 (.CLK(1'b1), .D(D), .EN(E), .Q(Q19)); // CLK is constant
\$dffe #(.WIDTH(1), .CLK_POLARITY(1), .EN_POLARITY(1)) remove20 (.CLK(C), .D(1'bx), .EN(E), .Q(Q[20])); // D is undriven, Q has no initial value
-(* init = "1'b0" *) wire Q21; assign Q[21] = Q21;
+(* init = 1'b0 *) wire Q21; assign Q[21] = Q21;
\$dffe #(.WIDTH(1), .CLK_POLARITY(1), .EN_POLARITY(1)) keep21 (.CLK(C), .D(1'bx), .EN(E), .Q(Q21)); // D is undriven, Q has initial value
//\$dffe #(.WIDTH(1), .CLK_POLARITY(0), .EN_POLARITY(1)) remove22 (.CLK(C), .D(1'b0), .EN(1'b1), .Q(Q[22])); // D is constant, no initial Q value, EN is always active
// // (TODO, Q starts with 1'bx and becomes 1'b0)
-(* init = "1'b0" *) wire Q23; assign Q[23] = Q23;
+(* init = 1'b0 *) wire Q23; assign Q[23] = Q23;
\$dffe #(.WIDTH(1), .CLK_POLARITY(1), .EN_POLARITY(1)) noenable23 (.CLK(C), .D(1'b0), .EN(1'b1), .Q(Q23)); // D is constant, initial Q value same as D, EN is always active
-(* init = "1'b1" *) wire Q24; assign Q[24] = Q24;
+(* init = 1'b1 *) wire Q24; assign Q[24] = Q24;
\$dffe #(.WIDTH(1), .CLK_POLARITY(1), .EN_POLARITY(0)) keep24 (.CLK(C), .D(1'b0), .EN(1'b0), .Q(Q24)); // D is constant, initial Q value NOT same as D, EN is always active
-(* init = "1'b1" *) wire Q25; assign Q[25] = Q25;
+(* init = 1'b1 *) wire Q25; assign Q[25] = Q25;
\$dffe #(.WIDTH(1), .CLK_POLARITY(1), .EN_POLARITY(0)) remove25 (.CLK(C), .D(1'b0), .EN(1'b1), .Q(Q25)); // D is constant, EN is never active
\$dffe #(.WIDTH(1), .CLK_POLARITY(1), .EN_POLARITY(1)) remove26 (.CLK(C), .D(Q[26]), .EN(1'b1), .Q(Q[26])); // D is Q, EN is always active
\$dffe #(.WIDTH(1), .CLK_POLARITY(1), .EN_POLARITY(0)) remove27 (.CLK(C), .D(Q[27]), .EN(1'b1), .Q(Q[27])); // D is Q, EN is never active, but no initial value
\$dffe #(.WIDTH(1), .CLK_POLARITY(1), .EN_POLARITY(0)) remove28 (.CLK(C), .D(Q[28]), .EN(E), .Q(Q[28])); // EN is nonconst, but no initial value
-(* init = "1'b1" *) wire Q29; assign Q[29] = Q29;
+(* init = 1'b1 *) wire Q29; assign Q[29] = Q29;
\$dffe #(.WIDTH(1), .CLK_POLARITY(1), .EN_POLARITY(1)) keep29 (.CLK(C), .D(Q[29]), .EN(1'b1), .Q(Q29)); // EN is always active, but with initial value
endmodule
diff --git a/tests/opt/opt_rmdff.ys b/tests/opt/opt_rmdff.ys
index 83a162f44..7e11bc73f 100644
--- a/tests/opt/opt_rmdff.ys
+++ b/tests/opt/opt_rmdff.ys
@@ -1,6 +1,7 @@
read_verilog -icells opt_rmdff.v
prep
design -stash gold
+
read_verilog -icells opt_rmdff.v
proc
opt_rmdff
@@ -14,13 +15,19 @@ design -stash gate
design -import gold -as gold
design -import gate -as gate
-equiv_make gold gate equiv
-hierarchy -top equiv
-equiv_simple -undef
-equiv_status -assert
+cd gold
+# fix up the "EN is don't care" cases, so that the gold output can't
+# become defined by using the properties of an undefined enable. (Both
+# remove6 and remove15 have active-low enables.)
+connect -port remove6 EN 1'b1
+connect -port remove15 E 1'b1
+cd ..
+
+dff2dffe -unmap
+clk2fflogic
+opt_clean
+
+miter -equiv -ignore_gold_x -make_assert -make_outputs -make_outcmp -flatten gold gate miter
+hierarchy -top miter
-#design -load gold
-#stat
-#
-#design -load gate
-#stat
+sat -verify -prove-asserts -enable_undef -set-init-undef -seq 10 -show-public miter
diff --git a/tests/simple/constmuldivmod.v b/tests/simple/constmuldivmod.v
index d1d8be862..5dd8f9295 100644
--- a/tests/simple/constmuldivmod.v
+++ b/tests/simple/constmuldivmod.v
@@ -1,4 +1,4 @@
-module constmuldivmod(input [7:0] A, input [2:0] mode, output reg [7:0] Y);
+module constmuldivmod(input [7:0] A, input [5:0] mode, output reg [7:0] Y);
always @* begin
case (mode)
0: Y = A / 8'd0;
@@ -21,6 +21,46 @@ module constmuldivmod(input [7:0] A, input [2:0] mode, output reg [7:0] Y);
13: Y = A % 8'd8;
14: Y = A * 8'd8;
+ 15: Y = $signed(A) / $signed(8'd0);
+ 16: Y = $signed(A) % $signed(8'd0);
+ 17: Y = $signed(A) * $signed(8'd0);
+
+ 18: Y = $signed(A) / $signed(8'd1);
+ 19: Y = $signed(A) % $signed(8'd1);
+ 20: Y = $signed(A) * $signed(8'd1);
+
+ 21: Y = $signed(A) / $signed(8'd2);
+ 22: Y = $signed(A) % $signed(8'd2);
+ 23: Y = $signed(A) * $signed(8'd2);
+
+ 24: Y = $signed(A) / $signed(8'd4);
+ 25: Y = $signed(A) % $signed(8'd4);
+ 26: Y = $signed(A) * $signed(8'd4);
+
+ 27: Y = $signed(A) / $signed(8'd8);
+ 28: Y = $signed(A) % $signed(8'd8);
+ 29: Y = $signed(A) * $signed(8'd8);
+
+ 30: Y = $signed(A) / $signed(-8'd0);
+ 31: Y = $signed(A) % $signed(-8'd0);
+ 32: Y = $signed(A) * $signed(-8'd0);
+
+ 33: Y = $signed(A) / $signed(-8'd1);
+ 34: Y = $signed(A) % $signed(-8'd1);
+ 35: Y = $signed(A) * $signed(-8'd1);
+
+ 36: Y = $signed(A) / $signed(-8'd2);
+ 37: Y = $signed(A) % $signed(-8'd2);
+ 38: Y = $signed(A) * $signed(-8'd2);
+
+ 39: Y = $signed(A) / $signed(-8'd4);
+ 40: Y = $signed(A) % $signed(-8'd4);
+ 41: Y = $signed(A) * $signed(-8'd4);
+
+ 42: Y = $signed(A) / $signed(-8'd8);
+ 43: Y = $signed(A) % $signed(-8'd8);
+ 44: Y = $signed(A) * $signed(-8'd8);
+
default: Y = 8'd16 * A;
endcase
end
diff --git a/tests/simple_abc9/abc9.box b/tests/simple_abc9/abc9.box
new file mode 100644
index 000000000..b3c88437c
--- /dev/null
+++ b/tests/simple_abc9/abc9.box
@@ -0,0 +1,3 @@
+MUXF8 1 0 3 1
+#I0 I1 S
+0 0 0 # O
diff --git a/tests/simple_abc9/abc9.v b/tests/simple_abc9/abc9.v
index 688b47586..5e969c614 100644
--- a/tests/simple_abc9/abc9.v
+++ b/tests/simple_abc9/abc9.v
@@ -213,7 +213,7 @@ module arbiter (clk, rst, request, acknowledge, grant, grant_valid, grant_encode
input rst;
endmodule
-(* abc9_box, blackbox *)
+(* abc9_box_id=1, blackbox *)
module MUXF8(input I0, I1, S, output O);
specify
(I0 => O) = 0;
diff --git a/tests/simple_abc9/run-test.sh b/tests/simple_abc9/run-test.sh
index 424d8f417..650e42fca 100755
--- a/tests/simple_abc9/run-test.sh
+++ b/tests/simple_abc9/run-test.sh
@@ -25,7 +25,7 @@ exec ${MAKE:-make} -f ../tools/autotest.mk $seed *.v *.sv EXTRA_FLAGS="-n 300 -p
synth -run coarse; \
opt -full; \
techmap; \
- abc9 -lut 4; \
+ abc9 -lut 4 -box ../abc9.box; \
clean; \
check -assert; \
select -assert-none t:${DOLLAR}_NOT_ t:${DOLLAR}_AND_ %%; \
diff --git a/tests/svtypes/logic_rom.sv b/tests/svtypes/logic_rom.sv
new file mode 100644
index 000000000..45fe0a4ca
--- /dev/null
+++ b/tests/svtypes/logic_rom.sv
@@ -0,0 +1,6 @@
+module top(input [3:0] addr, output [7:0] data);
+ logic [7:0] mem[0:15];
+ assign data = mem[addr];
+ integer i;
+ initial for(i = 0; i < 16; i = i + 1) mem[i] = i;
+endmodule
diff --git a/tests/svtypes/logic_rom.ys b/tests/svtypes/logic_rom.ys
new file mode 100644
index 000000000..7b079c136
--- /dev/null
+++ b/tests/svtypes/logic_rom.ys
@@ -0,0 +1,3 @@
+read_verilog -sv logic_rom.sv
+prep -top top
+select -assert-count 1 t:$mem r:SIZE=16 %i r:WIDTH=8 %i
diff --git a/tests/svtypes/static_cast_negative.ys b/tests/svtypes/static_cast_negative.ys
new file mode 100644
index 000000000..4f9e8cf6e
--- /dev/null
+++ b/tests/svtypes/static_cast_negative.ys
@@ -0,0 +1,4 @@
+logger -expect error "Static cast with zero or negative size" 1
+read_verilog -sv <<EOT
+module top; wire [7:0] a = (-1)'(a); endmodule
+EOT
diff --git a/tests/svtypes/static_cast_nonconst.ys b/tests/svtypes/static_cast_nonconst.ys
new file mode 100644
index 000000000..72d8f9910
--- /dev/null
+++ b/tests/svtypes/static_cast_nonconst.ys
@@ -0,0 +1,4 @@
+logger -expect error "Static cast with non constant expression" 1
+read_verilog -sv <<EOT
+module top; wire [7:0] a, b = (a)'(0); endmodule
+EOT
diff --git a/tests/svtypes/static_cast_simple.sv b/tests/svtypes/static_cast_simple.sv
new file mode 100644
index 000000000..2e4ad7d2b
--- /dev/null
+++ b/tests/svtypes/static_cast_simple.sv
@@ -0,0 +1,64 @@
+module top;
+ wire [7:0] a, b, c, d;
+ assign a = 8'd16;
+ assign b = 8'd16;
+ assign c = (a * b) >> 8;
+ assign d = (16'(a) * b) >> 8;
+
+ parameter P = 16;
+
+ wire signed [7:0] s0, s1, s2;
+ wire [7:0] u0, u1, u2, u3, u4, u5, u6;
+ assign s0 = -8'd1;
+ assign s1 = 4'(s0);
+ assign s2 = 4'(unsigned'(s0));
+ assign u0 = -8'd1;
+ assign u1 = 4'(u0);
+ assign u2 = 4'(signed'(u0));
+ assign u3 = 8'(4'(s0));
+ assign u4 = 8'(4'(u0));
+ assign u5 = 8'(4'(signed'(-8'd1)));
+ assign u6 = 8'(4'(unsigned'(-8'd1)));
+
+ wire [8:0] n0, n1, n2, n3, n4, n5, n6, n7, n8, n9;
+ assign n0 = s1;
+ assign n1 = s2;
+ assign n2 = 9'(s1);
+ assign n3 = 9'(s2);
+ assign n4 = 9'(unsigned'(s1));
+ assign n5 = 9'(unsigned'(s2));
+ assign n6 = 9'(u0);
+ assign n7 = 9'(u1);
+ assign n8 = 9'(signed'(u0));
+ assign n9 = 9'(signed'(u1));
+
+ always_comb begin
+ assert(c == 8'b0000_0000);
+ assert(d == 8'b0000_0001);
+
+ assert((P + 1)'(a) == 17'b0_0000_0000_0001_0000);
+ assert((P + 1)'(d - 2) == 17'b1_1111_1111_1111_1111);
+
+ assert(s0 == 8'b1111_1111);
+ assert(s1 == 8'b1111_1111);
+ assert(s2 == 8'b0000_1111);
+ assert(u0 == 8'b1111_1111);
+ assert(u1 == 8'b0000_1111);
+ assert(u2 == 8'b1111_1111);
+ assert(u3 == 8'b1111_1111);
+ assert(u4 == 8'b0000_1111);
+ assert(u5 == 8'b1111_1111);
+ assert(u6 == 8'b0000_1111);
+
+ assert(n0 == 9'b1_1111_1111);
+ assert(n1 == 9'b0_0000_1111);
+ assert(n2 == 9'b1_1111_1111);
+ assert(n3 == 9'b0_0000_1111);
+ assert(n4 == 9'b0_1111_1111);
+ assert(n5 == 9'b0_0000_1111);
+ assert(n6 == 9'b0_1111_1111);
+ assert(n7 == 9'b0_0000_1111);
+ assert(n8 == 9'b1_1111_1111);
+ assert(n9 == 9'b0_0000_1111);
+ end
+endmodule
diff --git a/tests/svtypes/static_cast_verilog.ys b/tests/svtypes/static_cast_verilog.ys
new file mode 100644
index 000000000..fa3680b68
--- /dev/null
+++ b/tests/svtypes/static_cast_verilog.ys
@@ -0,0 +1,4 @@
+logger -expect error "Static cast is only supported in SystemVerilog mode" 1
+read_verilog <<EOT
+module top; wire [7:0] a = 1'(a); endmodule
+EOT
diff --git a/tests/svtypes/static_cast_zero.ys b/tests/svtypes/static_cast_zero.ys
new file mode 100644
index 000000000..d8335ca1b
--- /dev/null
+++ b/tests/svtypes/static_cast_zero.ys
@@ -0,0 +1,4 @@
+logger -expect error "Static cast with zero or negative size" 1
+read_verilog -sv <<EOT
+module top; wire [7:0] a = 0'(a); endmodule
+EOT
diff --git a/tests/svtypes/struct_array.sv b/tests/svtypes/struct_array.sv
new file mode 100644
index 000000000..022ad56c6
--- /dev/null
+++ b/tests/svtypes/struct_array.sv
@@ -0,0 +1,22 @@
+// test for array indexing in structures
+
+module top;
+
+ struct packed {
+ bit [5:0] [7:0] a; // 6 element packed array of bytes
+ bit [15:0] b; // filler for non-zero offset
+ } s;
+
+ initial begin
+ s = '0;
+
+ s.a[2:1] = 16'h1234;
+ s.a[5] = 8'h42;
+
+ s.b = '1;
+ s.b[1:0] = '0;
+ end
+
+ always_comb assert(s==64'h4200_0012_3400_FFFC);
+
+endmodule
diff --git a/tests/svtypes/struct_simple.sv b/tests/svtypes/struct_simple.sv
new file mode 100644
index 000000000..c74289cc3
--- /dev/null
+++ b/tests/svtypes/struct_simple.sv
@@ -0,0 +1,48 @@
+module top;
+ localparam BITS=8;
+
+ struct packed {
+ logic a;
+ logic[BITS-1:0] b;
+ byte c;
+ logic x, y;
+ } s;
+
+ struct packed signed {
+ integer a;
+ logic[15:0] b;
+ logic[7:0] c;
+ bit [7:0] d;
+ } pack1;
+
+ struct packed {
+ byte a;
+ struct packed {
+ byte x, y;
+ } b;
+ } s2;
+
+ assign s.a = '1;
+ assign s.b = '1;
+ assign s.c = 8'hAA;
+ assign s.x = '1;
+ logic[7:0] t;
+ assign t = s.b;
+ assign pack1.a = 42;
+ assign pack1.b = 16'hAAAA;
+ assign pack1.c = '1;
+ assign pack1.d = 8'h55;
+ assign s2.b.x = 'h42;
+
+ always_comb assert(s.a == 1'b1);
+ always_comb assert(s.c == 8'hAA);
+ always_comb assert(s.x == 1'b1);
+ always_comb assert(t == 8'hFF);
+ always_comb assert(pack1.a == 42);
+ always_comb assert(pack1.b == 16'hAAAA);
+ always_comb assert(pack1.c == 8'hFF);
+ always_comb assert(pack1[15:8] == 8'hFF);
+ always_comb assert(pack1.d == 8'h55);
+ always_comb assert(s2.b.x == 'h42);
+
+endmodule
diff --git a/tests/svtypes/typedef_struct.sv b/tests/svtypes/typedef_struct.sv
new file mode 100644
index 000000000..7ae007952
--- /dev/null
+++ b/tests/svtypes/typedef_struct.sv
@@ -0,0 +1,42 @@
+package p;
+
+typedef struct packed {
+ byte a;
+ byte b;
+} p_t;
+
+endpackage
+
+
+module top;
+
+ typedef logic[7:0] t_t;
+
+ typedef struct packed {
+ bit a;
+ logic[7:0] b;
+ t_t t;
+ } s_t;
+
+ s_t s;
+ s_t s1;
+
+ p::p_t ps;
+
+ assign s.a = '1;
+ assign s.b = '1;
+ assign s.t = 8'h55;
+ assign s1 = s;
+ assign ps.a = 8'hAA;
+ assign ps.b = 8'h55;
+
+ always_comb begin
+ assert(s.a == 1'b1);
+ assert(s.b == 8'hFF);
+ assert(s.t == 8'h55);
+ assert(s1.t == 8'h55);
+ assert(ps.a == 8'hAA);
+ assert(ps.b == 8'h55);
+ end
+
+endmodule
diff --git a/tests/svtypes/union_simple.sv b/tests/svtypes/union_simple.sv
new file mode 100644
index 000000000..12e4b376f
--- /dev/null
+++ b/tests/svtypes/union_simple.sv
@@ -0,0 +1,72 @@
+module top;
+
+ typedef struct packed {
+ byte a,b,c,d;
+ } byte4_t;
+
+ typedef union packed {
+ int x;
+ byte4_t y;
+ } w_t;
+
+ w_t w;
+
+ assign w.x = 'h42;
+ always_comb begin
+ assert(w.y.d == 8'h42);
+ end
+
+ typedef logic[4:0] reg_addr_t;
+ typedef logic[6:0] opcode_t;
+
+ typedef struct packed {
+ bit [6:0] func7;
+ reg_addr_t rs2;
+ reg_addr_t rs1;
+ bit [2:0] func3;
+ reg_addr_t rd;
+ opcode_t opcode;
+ } R_t;
+
+ typedef struct packed {
+ bit[11:0] imm;
+ reg_addr_t rs1;
+ bit[2:0] func3;
+ reg_addr_t rd;
+ opcode_t opcode;
+ } I_t;
+
+ typedef struct packed {
+ bit[19:0] imm;
+ reg_addr_t rd;
+ opcode_t opcode;
+ } U_t;
+
+ typedef union packed {
+ R_t r;
+ I_t i;
+ U_t u;
+ } instruction_t;
+
+ instruction_t ir1;
+ assign ir1 = 32'h0AA01EB7; // lui t4,0xAA01
+ always_comb begin
+ assert(ir1.u.opcode == 'h37);
+ assert(ir1.r.opcode == 'h37);
+ assert(ir1.u.rd == 'd29);
+ assert(ir1.r.rd == 'd29);
+ assert(ir1.u.imm == 'hAA01);
+ end
+
+ union packed {
+ int word;
+ struct packed {
+ byte a, b, c, d;
+ } byte4;
+ } u;
+ assign u.word = 'h42;
+ always_comb begin
+ assert(u.byte4.d == 'h42);
+ end
+
+endmodule
diff --git a/tests/techmap/dff2dffs.ys b/tests/techmap/dff2dffs.ys
index 13f1a3cf3..105a89400 100644
--- a/tests/techmap/dff2dffs.ys
+++ b/tests/techmap/dff2dffs.ys
@@ -31,20 +31,20 @@ design -save ref
dff2dffs
clean
-select -assert-count 1 w:q0 %x t:$__DFFS_PP0_ %i
-select -assert-count 1 w:q1 %x t:$__DFFS_PP1_ %i
-select -assert-count 1 w:q2 %x t:$__DFFS_PP0_ %i
-select -assert-count 1 w:q3 %x t:$__DFFS_PP1_ %i
-select -assert-count 1 w:q4 %x t:$__DFFS_PP0_ %i
-select -assert-count 1 w:q5 %x t:$__DFFS_PP1_ %i
+select -assert-count 1 w:q0 %x t:$_SDFF_PP0_ %i
+select -assert-count 1 w:q1 %x t:$_SDFF_PP1_ %i
+select -assert-count 1 w:q2 %x t:$_SDFF_PP0_ %i
+select -assert-count 1 w:q3 %x t:$_SDFF_PP1_ %i
+select -assert-count 1 w:q4 %x t:$_SDFF_PP0_ %i
+select -assert-count 1 w:q5 %x t:$_SDFF_PP1_ %i
design -load ref
dff2dffs -match-init
clean
-select -assert-count 1 w:q0 %x t:$__DFFS_PP0_ %i
-select -assert-count 0 w:q1 %x t:$__DFFS_PP1_ %i
-select -assert-count 0 w:q2 %x t:$__DFFS_PP0_ %i
-select -assert-count 1 w:q3 %x t:$__DFFS_PP1_ %i
-select -assert-count 1 w:q4 %x t:$__DFFS_PP0_ %i
-select -assert-count 1 w:q5 %x t:$__DFFS_PP1_ %i
+select -assert-count 1 w:q0 %x t:$_SDFF_PP0_ %i
+select -assert-count 0 w:q1 %x t:$_SDFF_PP1_ %i
+select -assert-count 0 w:q2 %x t:$_SDFF_PP0_ %i
+select -assert-count 1 w:q3 %x t:$_SDFF_PP1_ %i
+select -assert-count 1 w:q4 %x t:$_SDFF_PP0_ %i
+select -assert-count 1 w:q5 %x t:$_SDFF_PP1_ %i
diff --git a/tests/techmap/dfflegalize_adff.ys b/tests/techmap/dfflegalize_adff.ys
new file mode 100644
index 000000000..a563e8c61
--- /dev/null
+++ b/tests/techmap/dfflegalize_adff.ys
@@ -0,0 +1,103 @@
+read_verilog -icells <<EOT
+
+module adff0(input C, R, D, output [2:0] Q);
+$_DFF_PP0_ ff0 (.C(C), .R(R), .D(D), .Q(Q[0]));
+$_DFF_PN0_ ff1 (.C(C), .R(R), .D(D), .Q(Q[1]));
+$_DFF_NP0_ ff2 (.C(C), .R(R), .D(D), .Q(Q[2]));
+endmodule
+
+module adff1(input C, R, D, output [2:0] Q);
+$_DFF_PP1_ ff0 (.C(C), .R(R), .D(D), .Q(Q[0]));
+$_DFF_PN1_ ff1 (.C(C), .R(R), .D(D), .Q(Q[1]));
+$_DFF_NP1_ ff2 (.C(C), .R(R), .D(D), .Q(Q[2]));
+endmodule
+
+module adffe0(input C, E, R, D, output [3:0] Q);
+$_DFFE_PP0P_ ff0 (.C(C), .R(R), .E(E), .D(D), .Q(Q[0]));
+$_DFFE_PP0N_ ff1 (.C(C), .R(R), .E(E), .D(D), .Q(Q[1]));
+$_DFFE_PN0P_ ff2 (.C(C), .R(R), .E(E), .D(D), .Q(Q[2]));
+$_DFFE_NP0P_ ff3 (.C(C), .R(R), .E(E), .D(D), .Q(Q[3]));
+endmodule
+
+module adffe1(input C, E, R, D, output [3:0] Q);
+$_DFFE_PP1P_ ff0 (.C(C), .R(R), .E(E), .D(D), .Q(Q[0]));
+$_DFFE_PP1N_ ff1 (.C(C), .R(R), .E(E), .D(D), .Q(Q[1]));
+$_DFFE_PN1P_ ff2 (.C(C), .R(R), .E(E), .D(D), .Q(Q[2]));
+$_DFFE_NP1P_ ff3 (.C(C), .R(R), .E(E), .D(D), .Q(Q[3]));
+endmodule
+
+module top(input C, E, R, D, output [13:0] Q);
+adff0 adff0_(.C(C), .R(R), .D(D), .Q(Q[2:0]));
+adff1 adff1_(.C(C), .R(R), .D(D), .Q(Q[5:3]));
+adffe0 adffe0_(.C(C), .R(R), .E(E), .D(D), .Q(Q[9:6]));
+adffe1 adffe1_(.C(C), .R(R), .E(E), .D(D), .Q(Q[13:10]));
+endmodule
+
+EOT
+
+design -save orig
+flatten
+equiv_opt -assert -multiclock -map +/simcells.v dfflegalize -cell $_DFF_PP0_ x
+equiv_opt -assert -multiclock -map +/simcells.v dfflegalize -cell $_DFFE_PP0P_ x
+#equiv_opt -assert -multiclock -map +/simcells.v dfflegalize -cell $_DFFSR_PPP_ x
+#equiv_opt -assert -multiclock -map +/simcells.v dfflegalize -cell $_DFFSRE_PPPP_ x
+
+
+# Convert everything to ADFFs.
+
+design -load orig
+dfflegalize -cell $_DFF_PP0_ x
+
+select -assert-count 2 adff0/t:$_NOT_
+select -assert-count 8 adff1/t:$_NOT_
+select -assert-count 2 adffe0/t:$_NOT_
+select -assert-count 10 adffe1/t:$_NOT_
+select -assert-count 0 adff0/t:$_MUX_
+select -assert-count 0 adff1/t:$_MUX_
+select -assert-count 4 adffe0/t:$_MUX_
+select -assert-count 4 adffe1/t:$_MUX_
+select -assert-count 14 t:$_DFF_PP0_
+select -assert-none t:$_DFF_PP0_ t:$_MUX_ t:$_NOT_ top/* %% %n t:* %i
+
+
+# Convert everything to ADFFEs.
+
+design -load orig
+dfflegalize -cell $_DFFE_PP0P_ x
+
+select -assert-count 2 adff0/t:$_NOT_
+select -assert-count 8 adff1/t:$_NOT_
+select -assert-count 3 adffe0/t:$_NOT_
+select -assert-count 11 adffe1/t:$_NOT_
+select -assert-count 14 t:$_DFFE_PP0P_
+select -assert-none t:$_DFFE_PP0P_ t:$_NOT_ top/* %% %n t:* %i
+
+
+# Convert everything to DFFSRs.
+
+design -load orig
+dfflegalize -cell $_DFFSR_PPP_ x
+
+select -assert-count 2 adff0/t:$_NOT_
+select -assert-count 2 adff1/t:$_NOT_
+select -assert-count 2 adffe0/t:$_NOT_
+select -assert-count 2 adffe1/t:$_NOT_
+select -assert-count 0 adff0/t:$_MUX_
+select -assert-count 0 adff1/t:$_MUX_
+select -assert-count 4 adffe0/t:$_MUX_
+select -assert-count 4 adffe1/t:$_MUX_
+select -assert-count 14 t:$_DFFSR_PPP_
+select -assert-none t:$_DFFSR_PPP_ t:$_MUX_ t:$_NOT_ top/* %% %n t:* %i
+
+
+# Convert everything to DFFSREs.
+
+design -load orig
+dfflegalize -cell $_DFFSRE_PPPP_ x
+
+select -assert-count 2 adff0/t:$_NOT_
+select -assert-count 2 adff1/t:$_NOT_
+select -assert-count 3 adffe0/t:$_NOT_
+select -assert-count 3 adffe1/t:$_NOT_
+select -assert-count 14 t:$_DFFSRE_PPPP_
+select -assert-none t:$_DFFSRE_PPPP_ t:$_NOT_ top/* %% %n t:* %i
diff --git a/tests/techmap/dfflegalize_adff_init.ys b/tests/techmap/dfflegalize_adff_init.ys
new file mode 100644
index 000000000..92f249815
--- /dev/null
+++ b/tests/techmap/dfflegalize_adff_init.ys
@@ -0,0 +1,279 @@
+read_verilog -icells <<EOT
+
+module adff0(input C, R, D, (* init = 3'b000 *) output [2:0] Q);
+$_DFF_PP0_ ff0 (.C(C), .R(R), .D(D), .Q(Q[0]));
+$_DFF_PN0_ ff1 (.C(C), .R(R), .D(D), .Q(Q[1]));
+$_DFF_NP0_ ff2 (.C(C), .R(R), .D(D), .Q(Q[2]));
+endmodule
+
+module adff1(input C, R, D, (* init = 3'b000 *) output [2:0] Q);
+$_DFF_PP1_ ff0 (.C(C), .R(R), .D(D), .Q(Q[0]));
+$_DFF_PN1_ ff1 (.C(C), .R(R), .D(D), .Q(Q[1]));
+$_DFF_NP1_ ff2 (.C(C), .R(R), .D(D), .Q(Q[2]));
+endmodule
+
+module adffe0(input C, E, R, D, (* init = 4'b0000 *) output [3:0] Q);
+$_DFFE_PP0P_ ff0 (.C(C), .R(R), .E(E), .D(D), .Q(Q[0]));
+$_DFFE_PP0N_ ff1 (.C(C), .R(R), .E(E), .D(D), .Q(Q[1]));
+$_DFFE_PN0P_ ff2 (.C(C), .R(R), .E(E), .D(D), .Q(Q[2]));
+$_DFFE_NP0P_ ff3 (.C(C), .R(R), .E(E), .D(D), .Q(Q[3]));
+endmodule
+
+module adffe1(input C, E, R, D, (* init = 4'b0000 *) output [3:0] Q);
+$_DFFE_PP1P_ ff0 (.C(C), .R(R), .E(E), .D(D), .Q(Q[0]));
+$_DFFE_PP1N_ ff1 (.C(C), .R(R), .E(E), .D(D), .Q(Q[1]));
+$_DFFE_PN1P_ ff2 (.C(C), .R(R), .E(E), .D(D), .Q(Q[2]));
+$_DFFE_NP1P_ ff3 (.C(C), .R(R), .E(E), .D(D), .Q(Q[3]));
+endmodule
+
+module top(input C, E, R, D, output [13:0] Q);
+adff0 adff0_(.C(C), .R(R), .D(D), .Q(Q[2:0]));
+adff1 adff1_(.C(C), .R(R), .D(D), .Q(Q[5:3]));
+adffe0 adffe0_(.C(C), .R(R), .E(E), .D(D), .Q(Q[9:6]));
+adffe1 adffe1_(.C(C), .R(R), .E(E), .D(D), .Q(Q[13:10]));
+endmodule
+
+EOT
+
+design -save orig
+flatten
+equiv_opt -assert -multiclock -map +/simcells.v dfflegalize -cell $_DFF_PP0_ 0 -cell $_DLATCH_P_ 0
+equiv_opt -assert -multiclock -map +/simcells.v dfflegalize -cell $_DFF_PP0_ 1 -cell $_DLATCH_P_ 0
+equiv_opt -assert -multiclock -map +/simcells.v dfflegalize -cell $_DFF_PP1_ 0 -cell $_DLATCH_P_ 0
+equiv_opt -assert -multiclock -map +/simcells.v dfflegalize -cell $_DFF_PP1_ 1 -cell $_DLATCH_P_ 0
+equiv_opt -assert -multiclock -map +/simcells.v dfflegalize -cell $_DFFE_PP0P_ 0 -cell $_DLATCH_P_ 1
+equiv_opt -assert -multiclock -map +/simcells.v dfflegalize -cell $_DFFE_PP0P_ 1 -cell $_DLATCH_P_ 1
+equiv_opt -assert -multiclock -map +/simcells.v dfflegalize -cell $_DFFE_PP1P_ 0 -cell $_DLATCH_P_ 1
+equiv_opt -assert -multiclock -map +/simcells.v dfflegalize -cell $_DFFE_PP1P_ 1 -cell $_DLATCH_P_ 1
+#equiv_opt -assert -multiclock -map +/simcells.v dfflegalize -cell $_DFFSR_PPP_ 0
+#equiv_opt -assert -multiclock -map +/simcells.v dfflegalize -cell $_DFFSR_PPP_ 1
+#equiv_opt -assert -multiclock -map +/simcells.v dfflegalize -cell $_DFFSRE_PPPP_ 0
+#equiv_opt -assert -multiclock -map +/simcells.v dfflegalize -cell $_DFFSRE_PPPP_ 1
+
+
+# Convert everything to ADFFs.
+
+design -load orig
+dfflegalize -cell $_DFF_PP0_ 0 -cell $_DLATCH_P_ 0
+
+select -assert-count 2 adff0/t:$_NOT_
+select -assert-count 10 adff1/t:$_NOT_
+select -assert-count 2 adffe0/t:$_NOT_
+select -assert-count 12 adffe1/t:$_NOT_
+select -assert-count 0 adff0/t:$_MUX_
+select -assert-count 3 adff1/t:$_MUX_
+select -assert-count 4 adffe0/t:$_MUX_
+select -assert-count 8 adffe1/t:$_MUX_
+select -assert-count 3 adff0/t:$_DFF_PP0_
+select -assert-count 6 adff1/t:$_DFF_PP0_
+select -assert-count 4 adffe0/t:$_DFF_PP0_
+select -assert-count 8 adffe1/t:$_DFF_PP0_
+select -assert-count 0 adff0/t:$_DLATCH_P_
+select -assert-count 3 adff1/t:$_DLATCH_P_
+select -assert-count 0 adffe0/t:$_DLATCH_P_
+select -assert-count 4 adffe1/t:$_DLATCH_P_
+select -assert-none t:$_DFF_PP0_ t:$_DLATCH_P_ t:$_MUX_ t:$_NOT_ top/* %% %n t:* %i
+
+design -load orig
+dfflegalize -cell $_DFF_PP0_ 1 -cell $_DLATCH_P_ 0
+
+select -assert-count 10 adff0/t:$_NOT_
+select -assert-count 8 adff1/t:$_NOT_
+select -assert-count 12 adffe0/t:$_NOT_
+select -assert-count 10 adffe1/t:$_NOT_
+select -assert-count 3 adff0/t:$_MUX_
+select -assert-count 0 adff1/t:$_MUX_
+select -assert-count 8 adffe0/t:$_MUX_
+select -assert-count 4 adffe1/t:$_MUX_
+select -assert-count 6 adff0/t:$_DFF_PP0_
+select -assert-count 3 adff1/t:$_DFF_PP0_
+select -assert-count 8 adffe0/t:$_DFF_PP0_
+select -assert-count 4 adffe1/t:$_DFF_PP0_
+select -assert-count 3 adff0/t:$_DLATCH_P_
+select -assert-count 0 adff1/t:$_DLATCH_P_
+select -assert-count 4 adffe0/t:$_DLATCH_P_
+select -assert-count 0 adffe1/t:$_DLATCH_P_
+select -assert-none t:$_DFF_PP0_ t:$_DLATCH_P_ t:$_MUX_ t:$_NOT_ top/* %% %n t:* %i
+
+design -load orig
+dfflegalize -cell $_DFF_PP1_ 0 -cell $_DLATCH_P_ 0
+
+select -assert-count 10 adff0/t:$_NOT_
+select -assert-count 2 adff1/t:$_NOT_
+select -assert-count 12 adffe0/t:$_NOT_
+select -assert-count 2 adffe1/t:$_NOT_
+select -assert-count 3 adff0/t:$_MUX_
+select -assert-count 0 adff1/t:$_MUX_
+select -assert-count 8 adffe0/t:$_MUX_
+select -assert-count 4 adffe1/t:$_MUX_
+select -assert-count 6 adff0/t:$_DFF_PP1_
+select -assert-count 3 adff1/t:$_DFF_PP1_
+select -assert-count 8 adffe0/t:$_DFF_PP1_
+select -assert-count 4 adffe1/t:$_DFF_PP1_
+select -assert-count 3 adff0/t:$_DLATCH_P_
+select -assert-count 0 adff1/t:$_DLATCH_P_
+select -assert-count 4 adffe0/t:$_DLATCH_P_
+select -assert-count 0 adffe1/t:$_DLATCH_P_
+select -assert-none t:$_DFF_PP1_ t:$_DLATCH_P_ t:$_MUX_ t:$_NOT_ top/* %% %n t:* %i
+
+design -load orig
+dfflegalize -cell $_DFF_PP1_ 1 -cell $_DLATCH_P_ 0
+
+select -assert-count 8 adff0/t:$_NOT_
+select -assert-count 10 adff1/t:$_NOT_
+select -assert-count 10 adffe0/t:$_NOT_
+select -assert-count 12 adffe1/t:$_NOT_
+select -assert-count 0 adff0/t:$_MUX_
+select -assert-count 3 adff1/t:$_MUX_
+select -assert-count 4 adffe0/t:$_MUX_
+select -assert-count 8 adffe1/t:$_MUX_
+select -assert-count 3 adff0/t:$_DFF_PP1_
+select -assert-count 6 adff1/t:$_DFF_PP1_
+select -assert-count 4 adffe0/t:$_DFF_PP1_
+select -assert-count 8 adffe1/t:$_DFF_PP1_
+select -assert-count 0 adff0/t:$_DLATCH_P_
+select -assert-count 3 adff1/t:$_DLATCH_P_
+select -assert-count 0 adffe0/t:$_DLATCH_P_
+select -assert-count 4 adffe1/t:$_DLATCH_P_
+select -assert-none t:$_DFF_PP1_ t:$_DLATCH_P_ t:$_MUX_ t:$_NOT_ top/* %% %n t:* %i
+
+
+# Convert everything to ADFFEs.
+
+design -load orig
+dfflegalize -cell $_DFFE_PP0P_ 0 -cell $_DLATCH_P_ 1
+
+select -assert-count 2 adff0/t:$_NOT_
+select -assert-count 16 adff1/t:$_NOT_
+select -assert-count 3 adffe0/t:$_NOT_
+select -assert-count 22 adffe1/t:$_NOT_
+select -assert-count 0 adff0/t:$_MUX_
+select -assert-count 3 adff1/t:$_MUX_
+select -assert-count 0 adffe0/t:$_MUX_
+select -assert-count 4 adffe1/t:$_MUX_
+select -assert-count 3 adff0/t:$_DFFE_PP0P_
+select -assert-count 6 adff1/t:$_DFFE_PP0P_
+select -assert-count 4 adffe0/t:$_DFFE_PP0P_
+select -assert-count 8 adffe1/t:$_DFFE_PP0P_
+select -assert-count 0 adff0/t:$_DLATCH_P_
+select -assert-count 3 adff1/t:$_DLATCH_P_
+select -assert-count 0 adffe0/t:$_DLATCH_P_
+select -assert-count 4 adffe1/t:$_DLATCH_P_
+select -assert-none t:$_DFFE_PP0P_ t:$_DLATCH_P_ t:$_MUX_ t:$_NOT_ top/* %% %n t:* %i
+
+design -load orig
+dfflegalize -cell $_DFFE_PP0P_ 1 -cell $_DLATCH_P_ 1
+
+select -assert-count 16 adff0/t:$_NOT_
+select -assert-count 8 adff1/t:$_NOT_
+select -assert-count 22 adffe0/t:$_NOT_
+select -assert-count 11 adffe1/t:$_NOT_
+select -assert-count 3 adff0/t:$_MUX_
+select -assert-count 0 adff1/t:$_MUX_
+select -assert-count 4 adffe0/t:$_MUX_
+select -assert-count 0 adffe1/t:$_MUX_
+select -assert-count 6 adff0/t:$_DFFE_PP0P_
+select -assert-count 3 adff1/t:$_DFFE_PP0P_
+select -assert-count 8 adffe0/t:$_DFFE_PP0P_
+select -assert-count 4 adffe1/t:$_DFFE_PP0P_
+select -assert-count 3 adff0/t:$_DLATCH_P_
+select -assert-count 0 adff1/t:$_DLATCH_P_
+select -assert-count 4 adffe0/t:$_DLATCH_P_
+select -assert-count 0 adffe1/t:$_DLATCH_P_
+select -assert-none t:$_DFFE_PP0P_ t:$_DLATCH_P_ t:$_MUX_ t:$_NOT_ top/* %% %n t:* %i
+
+design -load orig
+dfflegalize -cell $_DFFE_PP1P_ 0 -cell $_DLATCH_P_ 1
+
+select -assert-count 16 adff0/t:$_NOT_
+select -assert-count 2 adff1/t:$_NOT_
+select -assert-count 22 adffe0/t:$_NOT_
+select -assert-count 3 adffe1/t:$_NOT_
+select -assert-count 3 adff0/t:$_MUX_
+select -assert-count 0 adff1/t:$_MUX_
+select -assert-count 4 adffe0/t:$_MUX_
+select -assert-count 0 adffe1/t:$_MUX_
+select -assert-count 6 adff0/t:$_DFFE_PP1P_
+select -assert-count 3 adff1/t:$_DFFE_PP1P_
+select -assert-count 8 adffe0/t:$_DFFE_PP1P_
+select -assert-count 4 adffe1/t:$_DFFE_PP1P_
+select -assert-count 3 adff0/t:$_DLATCH_P_
+select -assert-count 0 adff1/t:$_DLATCH_P_
+select -assert-count 4 adffe0/t:$_DLATCH_P_
+select -assert-count 0 adffe1/t:$_DLATCH_P_
+select -assert-none t:$_DFFE_PP1P_ t:$_DLATCH_P_ t:$_MUX_ t:$_NOT_ top/* %% %n t:* %i
+
+design -load orig
+dfflegalize -cell $_DFFE_PP1P_ 1 -cell $_DLATCH_P_ 1
+
+select -assert-count 8 adff0/t:$_NOT_
+select -assert-count 16 adff1/t:$_NOT_
+select -assert-count 11 adffe0/t:$_NOT_
+select -assert-count 22 adffe1/t:$_NOT_
+select -assert-count 0 adff0/t:$_MUX_
+select -assert-count 3 adff1/t:$_MUX_
+select -assert-count 0 adffe0/t:$_MUX_
+select -assert-count 4 adffe1/t:$_MUX_
+select -assert-count 3 adff0/t:$_DFFE_PP1P_
+select -assert-count 6 adff1/t:$_DFFE_PP1P_
+select -assert-count 4 adffe0/t:$_DFFE_PP1P_
+select -assert-count 8 adffe1/t:$_DFFE_PP1P_
+select -assert-count 0 adff0/t:$_DLATCH_P_
+select -assert-count 3 adff1/t:$_DLATCH_P_
+select -assert-count 0 adffe0/t:$_DLATCH_P_
+select -assert-count 4 adffe1/t:$_DLATCH_P_
+select -assert-none t:$_DFFE_PP1P_ t:$_DLATCH_P_ t:$_MUX_ t:$_NOT_ top/* %% %n t:* %i
+
+
+# Convert everything to DFFSRs.
+
+design -load orig
+dfflegalize -cell $_DFFSR_PPP_ 0
+
+select -assert-count 2 adff0/t:$_NOT_
+select -assert-count 2 adff1/t:$_NOT_
+select -assert-count 2 adffe0/t:$_NOT_
+select -assert-count 2 adffe1/t:$_NOT_
+select -assert-count 0 adff0/t:$_MUX_
+select -assert-count 0 adff1/t:$_MUX_
+select -assert-count 4 adffe0/t:$_MUX_
+select -assert-count 4 adffe1/t:$_MUX_
+select -assert-count 14 t:$_DFFSR_PPP_
+select -assert-none t:$_DFFSR_PPP_ t:$_MUX_ t:$_NOT_ top/* %% %n t:* %i
+
+design -load orig
+dfflegalize -cell $_DFFSR_PPP_ 1
+
+select -assert-count 8 adff0/t:$_NOT_
+select -assert-count 8 adff1/t:$_NOT_
+select -assert-count 10 adffe0/t:$_NOT_
+select -assert-count 10 adffe1/t:$_NOT_
+select -assert-count 0 adff0/t:$_MUX_
+select -assert-count 0 adff1/t:$_MUX_
+select -assert-count 4 adffe0/t:$_MUX_
+select -assert-count 4 adffe1/t:$_MUX_
+select -assert-count 14 t:$_DFFSR_PPP_
+select -assert-none t:$_DFFSR_PPP_ t:$_MUX_ t:$_NOT_ top/* %% %n t:* %i
+
+
+# Convert everything to DFFSREs.
+
+design -load orig
+dfflegalize -cell $_DFFSRE_PPPP_ 0
+
+select -assert-count 2 adff0/t:$_NOT_
+select -assert-count 2 adff1/t:$_NOT_
+select -assert-count 3 adffe0/t:$_NOT_
+select -assert-count 3 adffe1/t:$_NOT_
+select -assert-count 14 t:$_DFFSRE_PPPP_
+select -assert-none t:$_DFFSRE_PPPP_ t:$_NOT_ top/* %% %n t:* %i
+
+design -load orig
+dfflegalize -cell $_DFFSRE_PPPP_ 1
+
+select -assert-count 8 adff0/t:$_NOT_
+select -assert-count 8 adff1/t:$_NOT_
+select -assert-count 11 adffe0/t:$_NOT_
+select -assert-count 11 adffe1/t:$_NOT_
+select -assert-count 14 t:$_DFFSRE_PPPP_
+select -assert-none t:$_DFFSRE_PPPP_ t:$_NOT_ top/* %% %n t:* %i
diff --git a/tests/techmap/dfflegalize_adlatch.ys b/tests/techmap/dfflegalize_adlatch.ys
new file mode 100644
index 000000000..dee17e40c
--- /dev/null
+++ b/tests/techmap/dfflegalize_adlatch.ys
@@ -0,0 +1,51 @@
+read_verilog -icells <<EOT
+
+module adlatch0(input E, R, D, output [2:0] Q);
+$_DLATCH_PP0_ ff0 (.E(E), .R(R), .D(D), .Q(Q[0]));
+$_DLATCH_PN0_ ff1 (.E(E), .R(R), .D(D), .Q(Q[1]));
+$_DLATCH_NP0_ ff2 (.E(E), .R(R), .D(D), .Q(Q[2]));
+endmodule
+
+module adlatch1(input E, R, D, output [2:0] Q);
+$_DLATCH_PP1_ ff0 (.E(E), .R(R), .D(D), .Q(Q[0]));
+$_DLATCH_PN1_ ff1 (.E(E), .R(R), .D(D), .Q(Q[1]));
+$_DLATCH_NP1_ ff2 (.E(E), .R(R), .D(D), .Q(Q[2]));
+endmodule
+
+module top(input C, E, R, D, output [13:0] Q);
+adlatch0 adlatch0_(.E(E), .R(R), .D(D), .Q(Q[2:0]));
+adlatch1 adlatch1_(.E(E), .R(R), .D(D), .Q(Q[5:3]));
+endmodule
+
+EOT
+
+design -save orig
+flatten
+equiv_opt -assert -multiclock -map +/simcells.v dfflegalize -cell $_DLATCH_PP0_ x
+#equiv_opt -assert -multiclock -map +/simcells.v dfflegalize -cell $_DLATCHSR_PPP_ x
+
+
+# Convert everything to ADLATCHs.
+
+design -load orig
+dfflegalize -cell $_DLATCH_PP0_ x
+
+select -assert-count 2 adlatch0/t:$_NOT_
+select -assert-count 8 adlatch1/t:$_NOT_
+select -assert-count 0 adlatch0/t:$_MUX_
+select -assert-count 0 adlatch1/t:$_MUX_
+select -assert-count 6 t:$_DLATCH_PP0_
+select -assert-none t:$_DLATCH_PP0_ t:$_MUX_ t:$_NOT_ top/* %% %n t:* %i
+
+
+# Convert everything to DLATCHSRs.
+
+design -load orig
+dfflegalize -cell $_DLATCHSR_PPP_ x
+
+select -assert-count 2 adlatch0/t:$_NOT_
+select -assert-count 2 adlatch1/t:$_NOT_
+select -assert-count 0 adlatch0/t:$_MUX_
+select -assert-count 0 adlatch1/t:$_MUX_
+select -assert-count 6 t:$_DLATCHSR_PPP_
+select -assert-none t:$_DLATCHSR_PPP_ t:$_MUX_ t:$_NOT_ top/* %% %n t:* %i
diff --git a/tests/techmap/dfflegalize_adlatch_init.ys b/tests/techmap/dfflegalize_adlatch_init.ys
new file mode 100644
index 000000000..c221bbe0e
--- /dev/null
+++ b/tests/techmap/dfflegalize_adlatch_init.ys
@@ -0,0 +1,99 @@
+read_verilog -icells <<EOT
+
+module adlatch0(input E, R, D, (* init = 3'b000 *) output [2:0] Q);
+$_DLATCH_PP0_ ff0 (.E(E), .R(R), .D(D), .Q(Q[0]));
+$_DLATCH_PN0_ ff1 (.E(E), .R(R), .D(D), .Q(Q[1]));
+$_DLATCH_NP0_ ff2 (.E(E), .R(R), .D(D), .Q(Q[2]));
+endmodule
+
+module adlatch1(input E, R, D, (* init = 3'b000 *) output [2:0] Q);
+$_DLATCH_PP1_ ff0 (.E(E), .R(R), .D(D), .Q(Q[0]));
+$_DLATCH_PN1_ ff1 (.E(E), .R(R), .D(D), .Q(Q[1]));
+$_DLATCH_NP1_ ff2 (.E(E), .R(R), .D(D), .Q(Q[2]));
+endmodule
+
+module top(input C, E, R, D, output [13:0] Q);
+adlatch0 adlatch0_(.E(E), .R(R), .D(D), .Q(Q[2:0]));
+adlatch1 adlatch1_(.E(E), .R(R), .D(D), .Q(Q[5:3]));
+endmodule
+
+EOT
+
+design -save orig
+flatten
+equiv_opt -assert -multiclock -map +/simcells.v dfflegalize -cell $_DLATCH_PP0_ 0
+equiv_opt -assert -multiclock -map +/simcells.v dfflegalize -cell $_DLATCH_PP0_ 1
+equiv_opt -assert -multiclock -map +/simcells.v dfflegalize -cell $_DLATCH_PP1_ 0
+equiv_opt -assert -multiclock -map +/simcells.v dfflegalize -cell $_DLATCH_PP1_ 1
+#equiv_opt -assert -multiclock -map +/simcells.v dfflegalize -cell $_DLATCHSR_PPP_ 0
+#equiv_opt -assert -multiclock -map +/simcells.v dfflegalize -cell $_DLATCHSR_PPP_ 1
+
+
+# Convert everything to ADLATCHs.
+
+design -load orig
+dfflegalize -cell $_DLATCH_PP0_ 0
+
+select -assert-count 2 adlatch0/t:$_NOT_
+select -assert-count 10 adlatch1/t:$_NOT_
+select -assert-count 0 adlatch0/t:$_MUX_
+select -assert-count 3 adlatch1/t:$_MUX_
+select -assert-count 3 adlatch0/t:$_DLATCH_PP0_
+select -assert-count 9 adlatch1/t:$_DLATCH_PP0_
+select -assert-none t:$_DLATCH_PP0_ t:$_MUX_ t:$_NOT_ top/* %% %n t:* %i
+
+design -load orig
+dfflegalize -cell $_DLATCH_PP0_ 1
+
+select -assert-count 16 adlatch0/t:$_NOT_
+select -assert-count 8 adlatch1/t:$_NOT_
+select -assert-count 3 adlatch0/t:$_MUX_
+select -assert-count 0 adlatch1/t:$_MUX_
+select -assert-count 9 adlatch0/t:$_DLATCH_PP0_
+select -assert-count 3 adlatch1/t:$_DLATCH_PP0_
+select -assert-none t:$_DLATCH_PP0_ t:$_DLATCH_P_ t:$_MUX_ t:$_NOT_ top/* %% %n t:* %i
+
+design -load orig
+dfflegalize -cell $_DLATCH_PP1_ 0
+
+select -assert-count 10 adlatch0/t:$_NOT_
+select -assert-count 2 adlatch1/t:$_NOT_
+select -assert-count 3 adlatch0/t:$_MUX_
+select -assert-count 0 adlatch1/t:$_MUX_
+select -assert-count 9 adlatch0/t:$_DLATCH_PP1_
+select -assert-count 3 adlatch1/t:$_DLATCH_PP1_
+select -assert-none t:$_DLATCH_PP1_ t:$_MUX_ t:$_NOT_ top/* %% %n t:* %i
+
+design -load orig
+dfflegalize -cell $_DLATCH_PP1_ 1
+
+select -assert-count 8 adlatch0/t:$_NOT_
+select -assert-count 16 adlatch1/t:$_NOT_
+select -assert-count 0 adlatch0/t:$_MUX_
+select -assert-count 3 adlatch1/t:$_MUX_
+select -assert-count 3 adlatch0/t:$_DLATCH_PP1_
+select -assert-count 9 adlatch1/t:$_DLATCH_PP1_
+select -assert-none t:$_DLATCH_PP1_ t:$_MUX_ t:$_NOT_ top/* %% %n t:* %i
+
+
+# Convert everything to DLATCHSRs.
+
+design -load orig
+dfflegalize -cell $_DLATCHSR_PPP_ 0
+
+select -assert-count 2 adlatch0/t:$_NOT_
+select -assert-count 2 adlatch1/t:$_NOT_
+select -assert-count 0 adlatch0/t:$_MUX_
+select -assert-count 0 adlatch1/t:$_MUX_
+select -assert-count 6 t:$_DLATCHSR_PPP_
+select -assert-none t:$_DLATCHSR_PPP_ t:$_MUX_ t:$_NOT_ top/* %% %n t:* %i
+
+design -load orig
+dfflegalize -cell $_DLATCHSR_PPP_ 1
+
+select -assert-count 8 adlatch0/t:$_NOT_
+select -assert-count 8 adlatch1/t:$_NOT_
+select -assert-count 0 adlatch0/t:$_MUX_
+select -assert-count 0 adlatch1/t:$_MUX_
+select -assert-count 6 t:$_DLATCHSR_PPP_
+select -assert-none t:$_DLATCHSR_PPP_ t:$_MUX_ t:$_NOT_ top/* %% %n t:* %i
diff --git a/tests/techmap/dfflegalize_dff.ys b/tests/techmap/dfflegalize_dff.ys
new file mode 100644
index 000000000..d71f4204e
--- /dev/null
+++ b/tests/techmap/dfflegalize_dff.ys
@@ -0,0 +1,306 @@
+read_verilog -icells <<EOT
+
+module dff(input C, D, output [1:0] Q);
+$_DFF_P_ ff0 (.C(C), .D(D), .Q(Q[0]));
+$_DFF_N_ ff1 (.C(C), .D(D), .Q(Q[1]));
+endmodule
+
+module dffe(input C, E, D, output [2:0] Q);
+$_DFFE_PP_ ff0 (.C(C), .E(E), .D(D), .Q(Q[0]));
+$_DFFE_PN_ ff1 (.C(C), .E(E), .D(D), .Q(Q[1]));
+$_DFFE_NP_ ff2 (.C(C), .E(E), .D(D), .Q(Q[2]));
+endmodule
+
+module sdff0(input C, R, D, output [2:0] Q);
+$_SDFF_PP0_ ff0 (.C(C), .R(R), .D(D), .Q(Q[0]));
+$_SDFF_PN0_ ff1 (.C(C), .R(R), .D(D), .Q(Q[1]));
+$_SDFF_NP0_ ff2 (.C(C), .R(R), .D(D), .Q(Q[2]));
+endmodule
+
+module sdff1(input C, R, D, output [2:0] Q);
+$_SDFF_PP1_ ff0 (.C(C), .R(R), .D(D), .Q(Q[0]));
+$_SDFF_PN1_ ff1 (.C(C), .R(R), .D(D), .Q(Q[1]));
+$_SDFF_NP1_ ff2 (.C(C), .R(R), .D(D), .Q(Q[2]));
+endmodule
+
+module sdffe0(input C, E, R, D, output [3:0] Q);
+$_SDFFE_PP0P_ ff0 (.C(C), .R(R), .E(E), .D(D), .Q(Q[0]));
+$_SDFFE_PP0N_ ff1 (.C(C), .R(R), .E(E), .D(D), .Q(Q[1]));
+$_SDFFE_PN0P_ ff2 (.C(C), .R(R), .E(E), .D(D), .Q(Q[2]));
+$_SDFFE_NP0P_ ff3 (.C(C), .R(R), .E(E), .D(D), .Q(Q[3]));
+endmodule
+
+module sdffe1(input C, E, R, D, output [3:0] Q);
+$_SDFFE_PP1P_ ff0 (.C(C), .R(R), .E(E), .D(D), .Q(Q[0]));
+$_SDFFE_PP1N_ ff1 (.C(C), .R(R), .E(E), .D(D), .Q(Q[1]));
+$_SDFFE_PN1P_ ff2 (.C(C), .R(R), .E(E), .D(D), .Q(Q[2]));
+$_SDFFE_NP1P_ ff3 (.C(C), .R(R), .E(E), .D(D), .Q(Q[3]));
+endmodule
+
+module sdffce0(input C, E, R, D, output [3:0] Q);
+$_SDFFCE_PP0P_ ff0 (.C(C), .R(R), .E(E), .D(D), .Q(Q[0]));
+$_SDFFCE_PP0N_ ff1 (.C(C), .R(R), .E(E), .D(D), .Q(Q[1]));
+$_SDFFCE_PN0P_ ff2 (.C(C), .R(R), .E(E), .D(D), .Q(Q[2]));
+$_SDFFCE_NP0P_ ff3 (.C(C), .R(R), .E(E), .D(D), .Q(Q[3]));
+endmodule
+
+module sdffce1(input C, E, R, D, output [3:0] Q);
+$_SDFFCE_PP1P_ ff0 (.C(C), .R(R), .E(E), .D(D), .Q(Q[0]));
+$_SDFFCE_PP1N_ ff1 (.C(C), .R(R), .E(E), .D(D), .Q(Q[1]));
+$_SDFFCE_PN1P_ ff2 (.C(C), .R(R), .E(E), .D(D), .Q(Q[2]));
+$_SDFFCE_NP1P_ ff3 (.C(C), .R(R), .E(E), .D(D), .Q(Q[3]));
+endmodule
+
+module top(input C, E, R, D, output [26:0] Q);
+dff dff_(.C(C), .D(D), .Q(Q[1:0]));
+dffe dffe_(.C(C), .E(E), .D(D), .Q(Q[4:2]));
+sdff0 sdff0_(.C(C), .R(R), .D(D), .Q(Q[7:5]));
+sdff1 sdff1_(.C(C), .R(R), .D(D), .Q(Q[10:8]));
+sdffe0 sdffe0_(.C(C), .R(R), .E(E), .D(D), .Q(Q[14:11]));
+sdffe1 sdffe1_(.C(C), .R(R), .E(E), .D(D), .Q(Q[18:15]));
+sdffce0 sdffce0_(.C(C), .R(R), .E(E), .D(D), .Q(Q[22:19]));
+sdffce1 sdffce1_(.C(C), .R(R), .E(E), .D(D), .Q(Q[26:23]));
+endmodule
+
+EOT
+
+design -save orig
+flatten
+equiv_opt -assert -multiclock -map +/simcells.v dfflegalize -cell $_DFF_P_ x
+equiv_opt -assert -multiclock -map +/simcells.v dfflegalize -cell $_DFFE_PP_ x
+equiv_opt -assert -multiclock -map +/simcells.v dfflegalize -cell $_DFF_PP0_ x
+equiv_opt -assert -multiclock -map +/simcells.v dfflegalize -cell $_DFFE_PP0P_ x
+equiv_opt -assert -multiclock -map +/simcells.v dfflegalize -cell $_DFFSR_PPP_ x
+equiv_opt -assert -multiclock -map +/simcells.v dfflegalize -cell $_DFFSRE_PPPP_ x
+equiv_opt -assert -multiclock -map +/simcells.v dfflegalize -cell $_SDFF_PP0_ x
+equiv_opt -assert -multiclock -map +/simcells.v dfflegalize -cell $_SDFFE_PP0P_ x
+equiv_opt -assert -multiclock -map +/simcells.v dfflegalize -cell $_SDFFCE_PP0P_ x
+
+# Convert everything to DFFs.
+
+design -load orig
+dfflegalize -cell $_DFF_P_ x
+
+select -assert-count 1 dff/t:$_NOT_
+select -assert-count 1 dffe/t:$_NOT_
+select -assert-count 1 sdff0/t:$_NOT_
+select -assert-count 1 sdff1/t:$_NOT_
+select -assert-count 1 sdffe0/t:$_NOT_
+select -assert-count 1 sdffe1/t:$_NOT_
+select -assert-count 1 sdffce0/t:$_NOT_
+select -assert-count 1 sdffce1/t:$_NOT_
+select -assert-count 0 dff/t:$_MUX_
+select -assert-count 3 dffe/t:$_MUX_
+select -assert-count 3 sdff0/t:$_MUX_
+select -assert-count 3 sdff1/t:$_MUX_
+select -assert-count 8 sdffe0/t:$_MUX_
+select -assert-count 8 sdffe1/t:$_MUX_
+select -assert-count 8 sdffce0/t:$_MUX_
+select -assert-count 8 sdffce1/t:$_MUX_
+select -assert-count 27 t:$_DFF_P_
+select -assert-none t:$_DFF_P_ t:$_MUX_ t:$_NOT_ top/* %% %n t:* %i
+
+
+# Convert everything to DFFEs.
+
+design -load orig
+dfflegalize -cell $_DFFE_PP_ x
+
+select -assert-count 1 dff/t:$_NOT_
+select -assert-count 2 dffe/t:$_NOT_
+select -assert-count 1 sdff0/t:$_NOT_
+select -assert-count 1 sdff1/t:$_NOT_
+select -assert-count 1 sdffe0/t:$_NOT_
+select -assert-count 1 sdffe1/t:$_NOT_
+select -assert-count 2 sdffce0/t:$_NOT_
+select -assert-count 2 sdffce1/t:$_NOT_
+select -assert-count 0 dff/t:$_MUX_
+select -assert-count 0 dffe/t:$_MUX_
+select -assert-count 3 sdff0/t:$_MUX_
+select -assert-count 3 sdff1/t:$_MUX_
+select -assert-count 8 sdffe0/t:$_MUX_
+select -assert-count 8 sdffe1/t:$_MUX_
+select -assert-count 4 sdffce0/t:$_MUX_
+select -assert-count 4 sdffce1/t:$_MUX_
+select -assert-count 27 t:$_DFFE_PP_
+select -assert-none t:$_DFFE_PP_ t:$_MUX_ t:$_NOT_ top/* %% %n t:* %i
+
+
+# Convert everything to ADFFs.
+
+design -load orig
+dfflegalize -cell $_DFF_PP0_ x
+
+select -assert-count 1 dff/t:$_NOT_
+select -assert-count 1 dffe/t:$_NOT_
+select -assert-count 1 sdff0/t:$_NOT_
+select -assert-count 1 sdff1/t:$_NOT_
+select -assert-count 1 sdffe0/t:$_NOT_
+select -assert-count 1 sdffe1/t:$_NOT_
+select -assert-count 1 sdffce0/t:$_NOT_
+select -assert-count 1 sdffce1/t:$_NOT_
+select -assert-count 0 dff/t:$_MUX_
+select -assert-count 3 dffe/t:$_MUX_
+select -assert-count 3 sdff0/t:$_MUX_
+select -assert-count 3 sdff1/t:$_MUX_
+select -assert-count 8 sdffe0/t:$_MUX_
+select -assert-count 8 sdffe1/t:$_MUX_
+select -assert-count 8 sdffce0/t:$_MUX_
+select -assert-count 8 sdffce1/t:$_MUX_
+select -assert-count 27 t:$_DFF_PP0_
+select -assert-none t:$_DFF_PP0_ t:$_MUX_ t:$_NOT_ top/* %% %n t:* %i
+
+
+# Convert everything to ADFFEs.
+
+design -load orig
+dfflegalize -cell $_DFFE_PP0P_ x
+
+select -assert-count 1 dff/t:$_NOT_
+select -assert-count 2 dffe/t:$_NOT_
+select -assert-count 1 sdff0/t:$_NOT_
+select -assert-count 1 sdff1/t:$_NOT_
+select -assert-count 1 sdffe0/t:$_NOT_
+select -assert-count 1 sdffe1/t:$_NOT_
+select -assert-count 2 sdffce0/t:$_NOT_
+select -assert-count 2 sdffce1/t:$_NOT_
+select -assert-count 0 dff/t:$_MUX_
+select -assert-count 0 dffe/t:$_MUX_
+select -assert-count 3 sdff0/t:$_MUX_
+select -assert-count 3 sdff1/t:$_MUX_
+select -assert-count 8 sdffe0/t:$_MUX_
+select -assert-count 8 sdffe1/t:$_MUX_
+select -assert-count 4 sdffce0/t:$_MUX_
+select -assert-count 4 sdffce1/t:$_MUX_
+select -assert-count 27 t:$_DFFE_PP0P_
+select -assert-none t:$_DFFE_PP0P_ t:$_MUX_ t:$_NOT_ top/* %% %n t:* %i
+
+
+# Convert everything to DFFSRs.
+
+design -load orig
+dfflegalize -cell $_DFFSR_PPP_ x
+
+select -assert-count 1 dff/t:$_NOT_
+select -assert-count 1 dffe/t:$_NOT_
+select -assert-count 1 sdff0/t:$_NOT_
+select -assert-count 1 sdff1/t:$_NOT_
+select -assert-count 1 sdffe0/t:$_NOT_
+select -assert-count 1 sdffe1/t:$_NOT_
+select -assert-count 1 sdffce0/t:$_NOT_
+select -assert-count 1 sdffce1/t:$_NOT_
+select -assert-count 0 dff/t:$_MUX_
+select -assert-count 3 dffe/t:$_MUX_
+select -assert-count 3 sdff0/t:$_MUX_
+select -assert-count 3 sdff1/t:$_MUX_
+select -assert-count 8 sdffe0/t:$_MUX_
+select -assert-count 8 sdffe1/t:$_MUX_
+select -assert-count 8 sdffce0/t:$_MUX_
+select -assert-count 8 sdffce1/t:$_MUX_
+select -assert-count 27 t:$_DFFSR_PPP_
+select -assert-none t:$_DFFSR_PPP_ t:$_MUX_ t:$_NOT_ top/* %% %n t:* %i
+
+
+# Convert everything to DFFSREs.
+
+design -load orig
+dfflegalize -cell $_DFFSRE_PPPP_ x
+
+select -assert-count 1 dff/t:$_NOT_
+select -assert-count 2 dffe/t:$_NOT_
+select -assert-count 1 sdff0/t:$_NOT_
+select -assert-count 1 sdff1/t:$_NOT_
+select -assert-count 1 sdffe0/t:$_NOT_
+select -assert-count 1 sdffe1/t:$_NOT_
+select -assert-count 2 sdffce0/t:$_NOT_
+select -assert-count 2 sdffce1/t:$_NOT_
+select -assert-count 0 dff/t:$_MUX_
+select -assert-count 0 dffe/t:$_MUX_
+select -assert-count 3 sdff0/t:$_MUX_
+select -assert-count 3 sdff1/t:$_MUX_
+select -assert-count 8 sdffe0/t:$_MUX_
+select -assert-count 8 sdffe1/t:$_MUX_
+select -assert-count 4 sdffce0/t:$_MUX_
+select -assert-count 4 sdffce1/t:$_MUX_
+select -assert-count 27 t:$_DFFSRE_PPPP_
+select -assert-none t:$_DFFSRE_PPPP_ t:$_MUX_ t:$_NOT_ top/* %% %n t:* %i
+
+
+# Convert everything to SDFFs.
+
+design -load orig
+dfflegalize -cell $_SDFF_PP0_ x
+
+select -assert-count 1 dff/t:$_NOT_
+select -assert-count 1 dffe/t:$_NOT_
+select -assert-count 2 sdff0/t:$_NOT_
+select -assert-count 8 sdff1/t:$_NOT_
+select -assert-count 2 sdffe0/t:$_NOT_
+select -assert-count 10 sdffe1/t:$_NOT_
+select -assert-count 2 sdffce0/t:$_NOT_
+select -assert-count 10 sdffce1/t:$_NOT_
+select -assert-count 0 dff/t:$_MUX_
+select -assert-count 3 dffe/t:$_MUX_
+select -assert-count 0 sdff0/t:$_MUX_
+select -assert-count 0 sdff1/t:$_MUX_
+select -assert-count 4 sdffe0/t:$_MUX_
+select -assert-count 4 sdffe1/t:$_MUX_
+select -assert-count 4 sdffce0/t:$_MUX_
+select -assert-count 4 sdffce1/t:$_MUX_
+select -assert-count 0 t:$_AND_ t:$_ORNOT_ t:$_ANDNOT_ %% sdffce0/* sdffce1/* %u %n %i
+select -assert-count 2 sdffce0/t:$_AND_
+select -assert-count 2 sdffce1/t:$_AND_
+select -assert-count 1 sdffce0/t:$_ORNOT_
+select -assert-count 1 sdffce1/t:$_ORNOT_
+select -assert-count 1 sdffce0/t:$_ANDNOT_
+select -assert-count 1 sdffce1/t:$_ANDNOT_
+select -assert-count 27 t:$_SDFF_PP0_
+select -assert-none t:$_SDFF_PP0_ t:$_MUX_ t:$_NOT_ t:$_AND_ t:$_ORNOT_ t:$_ANDNOT_ top/* %% %n t:* %i
+
+
+# Convert everything to SDFFEs.
+
+design -load orig
+dfflegalize -cell $_SDFFE_PP0P_ x
+
+select -assert-count 1 dff/t:$_NOT_
+select -assert-count 2 dffe/t:$_NOT_
+select -assert-count 2 sdff0/t:$_NOT_
+select -assert-count 8 sdff1/t:$_NOT_
+select -assert-count 3 sdffe0/t:$_NOT_
+select -assert-count 11 sdffe1/t:$_NOT_
+select -assert-count 3 sdffce0/t:$_NOT_
+select -assert-count 11 sdffce1/t:$_NOT_
+select -assert-count 0 t:$_AND_ t:$_ORNOT_ t:$_ANDNOT_ %% sdffce0/* sdffce1/* %u %n %i
+select -assert-count 2 sdffce0/t:$_AND_
+select -assert-count 2 sdffce1/t:$_AND_
+select -assert-count 1 sdffce0/t:$_ORNOT_
+select -assert-count 1 sdffce1/t:$_ORNOT_
+select -assert-count 1 sdffce0/t:$_ANDNOT_
+select -assert-count 1 sdffce1/t:$_ANDNOT_
+select -assert-count 27 t:$_SDFFE_PP0P_
+select -assert-none t:$_SDFFE_PP0P_ t:$_NOT_ t:$_AND_ t:$_ORNOT_ t:$_ANDNOT_ top/* %% %n t:* %i
+
+
+# Convert everything to SDFFCEs.
+
+design -load orig
+dfflegalize -cell $_SDFFCE_PP0P_ x
+
+select -assert-count 1 dff/t:$_NOT_
+select -assert-count 2 dffe/t:$_NOT_
+select -assert-count 2 sdff0/t:$_NOT_
+select -assert-count 8 sdff1/t:$_NOT_
+select -assert-count 3 sdffe0/t:$_NOT_
+select -assert-count 11 sdffe1/t:$_NOT_
+select -assert-count 3 sdffce0/t:$_NOT_
+select -assert-count 11 sdffce1/t:$_NOT_
+select -assert-count 0 t:$_OR_ t:$_ORNOT_ t:$_ANDNOT_ %% sdffe0/* sdffe1/* %u %n %i
+select -assert-count 2 sdffe0/t:$_OR_
+select -assert-count 2 sdffe1/t:$_OR_
+select -assert-count 1 sdffe0/t:$_ORNOT_
+select -assert-count 1 sdffe1/t:$_ORNOT_
+select -assert-count 1 sdffe0/t:$_ANDNOT_
+select -assert-count 1 sdffe1/t:$_ANDNOT_
+select -assert-count 27 t:$_SDFFCE_PP0P_
+select -assert-none t:$_SDFFCE_PP0P_ t:$_NOT_ t:$_OR_ t:$_ORNOT_ t:$_ANDNOT_ top/* %% %n t:* %i
diff --git a/tests/techmap/dfflegalize_dff_init.ys b/tests/techmap/dfflegalize_dff_init.ys
new file mode 100644
index 000000000..84848da1f
--- /dev/null
+++ b/tests/techmap/dfflegalize_dff_init.ys
@@ -0,0 +1,786 @@
+read_verilog -icells <<EOT
+
+module dff(input C, D, (* init = 2'b00 *) output [1:0] Q);
+$_DFF_P_ ff0 (.C(C), .D(D), .Q(Q[0]));
+$_DFF_N_ ff1 (.C(C), .D(D), .Q(Q[1]));
+endmodule
+
+module dffe(input C, E, D, (* init = 3'b000 *) output [2:0] Q);
+$_DFFE_PP_ ff0 (.C(C), .E(E), .D(D), .Q(Q[0]));
+$_DFFE_PN_ ff1 (.C(C), .E(E), .D(D), .Q(Q[1]));
+$_DFFE_NP_ ff2 (.C(C), .E(E), .D(D), .Q(Q[2]));
+endmodule
+
+module sdff0(input C, R, D, (* init = 3'b000 *) output [2:0] Q);
+$_SDFF_PP0_ ff0 (.C(C), .R(R), .D(D), .Q(Q[0]));
+$_SDFF_PN0_ ff1 (.C(C), .R(R), .D(D), .Q(Q[1]));
+$_SDFF_NP0_ ff2 (.C(C), .R(R), .D(D), .Q(Q[2]));
+endmodule
+
+module sdff1(input C, R, D, (* init = 3'b000 *) output [2:0] Q);
+$_SDFF_PP1_ ff0 (.C(C), .R(R), .D(D), .Q(Q[0]));
+$_SDFF_PN1_ ff1 (.C(C), .R(R), .D(D), .Q(Q[1]));
+$_SDFF_NP1_ ff2 (.C(C), .R(R), .D(D), .Q(Q[2]));
+endmodule
+
+module sdffe0(input C, E, R, D, (* init = 4'b0000 *) output [3:0] Q);
+$_SDFFE_PP0P_ ff0 (.C(C), .R(R), .E(E), .D(D), .Q(Q[0]));
+$_SDFFE_PP0N_ ff1 (.C(C), .R(R), .E(E), .D(D), .Q(Q[1]));
+$_SDFFE_PN0P_ ff2 (.C(C), .R(R), .E(E), .D(D), .Q(Q[2]));
+$_SDFFE_NP0P_ ff3 (.C(C), .R(R), .E(E), .D(D), .Q(Q[3]));
+endmodule
+
+module sdffe1(input C, E, R, D, (* init = 4'b0000 *) output [3:0] Q);
+$_SDFFE_PP1P_ ff0 (.C(C), .R(R), .E(E), .D(D), .Q(Q[0]));
+$_SDFFE_PP1N_ ff1 (.C(C), .R(R), .E(E), .D(D), .Q(Q[1]));
+$_SDFFE_PN1P_ ff2 (.C(C), .R(R), .E(E), .D(D), .Q(Q[2]));
+$_SDFFE_NP1P_ ff3 (.C(C), .R(R), .E(E), .D(D), .Q(Q[3]));
+endmodule
+
+module sdffce0(input C, E, R, D, (* init = 4'b0000 *) output [3:0] Q);
+$_SDFFCE_PP0P_ ff0 (.C(C), .R(R), .E(E), .D(D), .Q(Q[0]));
+$_SDFFCE_PP0N_ ff1 (.C(C), .R(R), .E(E), .D(D), .Q(Q[1]));
+$_SDFFCE_PN0P_ ff2 (.C(C), .R(R), .E(E), .D(D), .Q(Q[2]));
+$_SDFFCE_NP0P_ ff3 (.C(C), .R(R), .E(E), .D(D), .Q(Q[3]));
+endmodule
+
+module sdffce1(input C, E, R, D, (* init = 4'b0000 *) output [3:0] Q);
+$_SDFFCE_PP1P_ ff0 (.C(C), .R(R), .E(E), .D(D), .Q(Q[0]));
+$_SDFFCE_PP1N_ ff1 (.C(C), .R(R), .E(E), .D(D), .Q(Q[1]));
+$_SDFFCE_PN1P_ ff2 (.C(C), .R(R), .E(E), .D(D), .Q(Q[2]));
+$_SDFFCE_NP1P_ ff3 (.C(C), .R(R), .E(E), .D(D), .Q(Q[3]));
+endmodule
+
+module top(input C, E, R, D, output [26:0] Q);
+dff dff_(.C(C), .D(D), .Q(Q[1:0]));
+dffe dffe_(.C(C), .E(E), .D(D), .Q(Q[4:2]));
+sdff0 sdff0_(.C(C), .R(R), .D(D), .Q(Q[7:5]));
+sdff1 sdff1_(.C(C), .R(R), .D(D), .Q(Q[10:8]));
+sdffe0 sdffe0_(.C(C), .R(R), .E(E), .D(D), .Q(Q[14:11]));
+sdffe1 sdffe1_(.C(C), .R(R), .E(E), .D(D), .Q(Q[18:15]));
+sdffce0 sdffce0_(.C(C), .R(R), .E(E), .D(D), .Q(Q[22:19]));
+sdffce1 sdffce1_(.C(C), .R(R), .E(E), .D(D), .Q(Q[26:23]));
+endmodule
+
+EOT
+
+design -save orig
+flatten
+equiv_opt -assert -multiclock -map +/simcells.v dfflegalize -cell $_DFF_P_ 0
+equiv_opt -assert -multiclock -map +/simcells.v dfflegalize -cell $_DFF_P_ 1
+equiv_opt -assert -multiclock -map +/simcells.v dfflegalize -cell $_DFFE_PP_ 0
+equiv_opt -assert -multiclock -map +/simcells.v dfflegalize -cell $_DFFE_PP_ 1
+equiv_opt -assert -multiclock -map +/simcells.v dfflegalize -cell $_DFF_PP0_ 0
+equiv_opt -assert -multiclock -map +/simcells.v dfflegalize -cell $_DFF_PP0_ 1
+equiv_opt -assert -multiclock -map +/simcells.v dfflegalize -cell $_DFF_PP1_ 0
+equiv_opt -assert -multiclock -map +/simcells.v dfflegalize -cell $_DFF_PP1_ 1
+equiv_opt -assert -multiclock -map +/simcells.v dfflegalize -cell $_DFFE_PP0P_ 0
+equiv_opt -assert -multiclock -map +/simcells.v dfflegalize -cell $_DFFE_PP0P_ 1
+equiv_opt -assert -multiclock -map +/simcells.v dfflegalize -cell $_DFFE_PP1P_ 0
+equiv_opt -assert -multiclock -map +/simcells.v dfflegalize -cell $_DFFE_PP1P_ 1
+equiv_opt -assert -multiclock -map +/simcells.v dfflegalize -cell $_DFFSR_PPP_ 0
+equiv_opt -assert -multiclock -map +/simcells.v dfflegalize -cell $_DFFSR_PPP_ 1
+equiv_opt -assert -multiclock -map +/simcells.v dfflegalize -cell $_DFFSRE_PPPP_ 0
+equiv_opt -assert -multiclock -map +/simcells.v dfflegalize -cell $_DFFSRE_PPPP_ 1
+equiv_opt -assert -multiclock -map +/simcells.v dfflegalize -cell $_SDFF_PP0_ 0
+equiv_opt -assert -multiclock -map +/simcells.v dfflegalize -cell $_SDFF_PP0_ 1
+equiv_opt -assert -multiclock -map +/simcells.v dfflegalize -cell $_SDFF_PP1_ 0
+equiv_opt -assert -multiclock -map +/simcells.v dfflegalize -cell $_SDFF_PP1_ 1
+equiv_opt -assert -multiclock -map +/simcells.v dfflegalize -cell $_SDFFE_PP0P_ 0
+equiv_opt -assert -multiclock -map +/simcells.v dfflegalize -cell $_SDFFE_PP0P_ 1
+equiv_opt -assert -multiclock -map +/simcells.v dfflegalize -cell $_SDFFE_PP1P_ 0
+equiv_opt -assert -multiclock -map +/simcells.v dfflegalize -cell $_SDFFE_PP1P_ 1
+equiv_opt -assert -multiclock -map +/simcells.v dfflegalize -cell $_SDFFCE_PP0P_ 0
+equiv_opt -assert -multiclock -map +/simcells.v dfflegalize -cell $_SDFFCE_PP0P_ 1
+equiv_opt -assert -multiclock -map +/simcells.v dfflegalize -cell $_SDFFCE_PP1P_ 0
+equiv_opt -assert -multiclock -map +/simcells.v dfflegalize -cell $_SDFFCE_PP1P_ 1
+
+# Convert everything to DFFs.
+
+design -load orig
+dfflegalize -cell $_DFF_P_ 0
+
+select -assert-count 1 dff/t:$_NOT_
+select -assert-count 1 dffe/t:$_NOT_
+select -assert-count 1 sdff0/t:$_NOT_
+select -assert-count 1 sdff1/t:$_NOT_
+select -assert-count 1 sdffe0/t:$_NOT_
+select -assert-count 1 sdffe1/t:$_NOT_
+select -assert-count 1 sdffce0/t:$_NOT_
+select -assert-count 1 sdffce1/t:$_NOT_
+select -assert-count 0 dff/t:$_MUX_
+select -assert-count 3 dffe/t:$_MUX_
+select -assert-count 3 sdff0/t:$_MUX_
+select -assert-count 3 sdff1/t:$_MUX_
+select -assert-count 8 sdffe0/t:$_MUX_
+select -assert-count 8 sdffe1/t:$_MUX_
+select -assert-count 8 sdffce0/t:$_MUX_
+select -assert-count 8 sdffce1/t:$_MUX_
+select -assert-count 27 t:$_DFF_P_
+select -assert-none t:$_DFF_P_ t:$_MUX_ t:$_NOT_ top/* %% %n t:* %i
+
+design -load orig
+dfflegalize -cell $_DFF_P_ 1
+
+select -assert-count 5 dff/t:$_NOT_
+select -assert-count 7 dffe/t:$_NOT_
+select -assert-count 7 sdff0/t:$_NOT_
+select -assert-count 7 sdff1/t:$_NOT_
+select -assert-count 9 sdffe0/t:$_NOT_
+select -assert-count 9 sdffe1/t:$_NOT_
+select -assert-count 9 sdffce0/t:$_NOT_
+select -assert-count 9 sdffce1/t:$_NOT_
+select -assert-count 0 dff/t:$_MUX_
+select -assert-count 3 dffe/t:$_MUX_
+select -assert-count 3 sdff0/t:$_MUX_
+select -assert-count 3 sdff1/t:$_MUX_
+select -assert-count 8 sdffe0/t:$_MUX_
+select -assert-count 8 sdffe1/t:$_MUX_
+select -assert-count 8 sdffce0/t:$_MUX_
+select -assert-count 8 sdffce1/t:$_MUX_
+select -assert-count 27 t:$_DFF_P_
+select -assert-none t:$_DFF_P_ t:$_MUX_ t:$_NOT_ top/* %% %n t:* %i
+
+
+# Convert everything to DFFEs.
+
+design -load orig
+dfflegalize -cell $_DFFE_PP_ 0
+
+select -assert-count 1 dff/t:$_NOT_
+select -assert-count 2 dffe/t:$_NOT_
+select -assert-count 1 sdff0/t:$_NOT_
+select -assert-count 1 sdff1/t:$_NOT_
+select -assert-count 1 sdffe0/t:$_NOT_
+select -assert-count 1 sdffe1/t:$_NOT_
+select -assert-count 2 sdffce0/t:$_NOT_
+select -assert-count 2 sdffce1/t:$_NOT_
+select -assert-count 0 dff/t:$_MUX_
+select -assert-count 0 dffe/t:$_MUX_
+select -assert-count 3 sdff0/t:$_MUX_
+select -assert-count 3 sdff1/t:$_MUX_
+select -assert-count 8 sdffe0/t:$_MUX_
+select -assert-count 8 sdffe1/t:$_MUX_
+select -assert-count 4 sdffce0/t:$_MUX_
+select -assert-count 4 sdffce1/t:$_MUX_
+select -assert-count 27 t:$_DFFE_PP_
+select -assert-none t:$_DFFE_PP_ t:$_MUX_ t:$_NOT_ top/* %% %n t:* %i
+
+design -load orig
+dfflegalize -cell $_DFFE_PP_ 1
+
+select -assert-count 5 dff/t:$_NOT_
+select -assert-count 8 dffe/t:$_NOT_
+select -assert-count 7 sdff0/t:$_NOT_
+select -assert-count 7 sdff1/t:$_NOT_
+select -assert-count 9 sdffe0/t:$_NOT_
+select -assert-count 9 sdffe1/t:$_NOT_
+select -assert-count 10 sdffce0/t:$_NOT_
+select -assert-count 10 sdffce1/t:$_NOT_
+select -assert-count 0 dff/t:$_MUX_
+select -assert-count 0 dffe/t:$_MUX_
+select -assert-count 3 sdff0/t:$_MUX_
+select -assert-count 3 sdff1/t:$_MUX_
+select -assert-count 8 sdffe0/t:$_MUX_
+select -assert-count 8 sdffe1/t:$_MUX_
+select -assert-count 4 sdffce0/t:$_MUX_
+select -assert-count 4 sdffce1/t:$_MUX_
+select -assert-count 27 t:$_DFFE_PP_
+select -assert-none t:$_DFFE_PP_ t:$_MUX_ t:$_NOT_ top/* %% %n t:* %i
+
+
+# Convert everything to ADFFs.
+
+design -load orig
+dfflegalize -cell $_DFF_PP0_ 0
+
+select -assert-count 1 dff/t:$_NOT_
+select -assert-count 1 dffe/t:$_NOT_
+select -assert-count 1 sdff0/t:$_NOT_
+select -assert-count 1 sdff1/t:$_NOT_
+select -assert-count 1 sdffe0/t:$_NOT_
+select -assert-count 1 sdffe1/t:$_NOT_
+select -assert-count 1 sdffce0/t:$_NOT_
+select -assert-count 1 sdffce1/t:$_NOT_
+select -assert-count 0 dff/t:$_MUX_
+select -assert-count 3 dffe/t:$_MUX_
+select -assert-count 3 sdff0/t:$_MUX_
+select -assert-count 3 sdff1/t:$_MUX_
+select -assert-count 8 sdffe0/t:$_MUX_
+select -assert-count 8 sdffe1/t:$_MUX_
+select -assert-count 8 sdffce0/t:$_MUX_
+select -assert-count 8 sdffce1/t:$_MUX_
+select -assert-count 27 t:$_DFF_PP0_
+select -assert-none t:$_DFF_PP0_ t:$_MUX_ t:$_NOT_ top/* %% %n t:* %i
+
+design -load orig
+dfflegalize -cell $_DFF_PP0_ 1
+
+select -assert-count 5 dff/t:$_NOT_
+select -assert-count 7 dffe/t:$_NOT_
+select -assert-count 7 sdff0/t:$_NOT_
+select -assert-count 7 sdff1/t:$_NOT_
+select -assert-count 9 sdffe0/t:$_NOT_
+select -assert-count 9 sdffe1/t:$_NOT_
+select -assert-count 9 sdffce0/t:$_NOT_
+select -assert-count 9 sdffce1/t:$_NOT_
+select -assert-count 0 dff/t:$_MUX_
+select -assert-count 3 dffe/t:$_MUX_
+select -assert-count 3 sdff0/t:$_MUX_
+select -assert-count 3 sdff1/t:$_MUX_
+select -assert-count 8 sdffe0/t:$_MUX_
+select -assert-count 8 sdffe1/t:$_MUX_
+select -assert-count 8 sdffce0/t:$_MUX_
+select -assert-count 8 sdffce1/t:$_MUX_
+select -assert-count 27 t:$_DFF_PP0_
+select -assert-none t:$_DFF_PP0_ t:$_MUX_ t:$_NOT_ top/* %% %n t:* %i
+
+design -load orig
+dfflegalize -cell $_DFF_PP1_ 0
+
+select -assert-count 1 dff/t:$_NOT_
+select -assert-count 1 dffe/t:$_NOT_
+select -assert-count 1 sdff0/t:$_NOT_
+select -assert-count 1 sdff1/t:$_NOT_
+select -assert-count 1 sdffe0/t:$_NOT_
+select -assert-count 1 sdffe1/t:$_NOT_
+select -assert-count 1 sdffce0/t:$_NOT_
+select -assert-count 1 sdffce1/t:$_NOT_
+select -assert-count 0 dff/t:$_MUX_
+select -assert-count 3 dffe/t:$_MUX_
+select -assert-count 3 sdff0/t:$_MUX_
+select -assert-count 3 sdff1/t:$_MUX_
+select -assert-count 8 sdffe0/t:$_MUX_
+select -assert-count 8 sdffe1/t:$_MUX_
+select -assert-count 8 sdffce0/t:$_MUX_
+select -assert-count 8 sdffce1/t:$_MUX_
+select -assert-count 27 t:$_DFF_PP1_
+select -assert-none t:$_DFF_PP1_ t:$_MUX_ t:$_NOT_ top/* %% %n t:* %i
+
+design -load orig
+dfflegalize -cell $_DFF_PP1_ 1
+
+select -assert-count 5 dff/t:$_NOT_
+select -assert-count 7 dffe/t:$_NOT_
+select -assert-count 7 sdff0/t:$_NOT_
+select -assert-count 7 sdff1/t:$_NOT_
+select -assert-count 9 sdffe0/t:$_NOT_
+select -assert-count 9 sdffe1/t:$_NOT_
+select -assert-count 9 sdffce0/t:$_NOT_
+select -assert-count 9 sdffce1/t:$_NOT_
+select -assert-count 0 dff/t:$_MUX_
+select -assert-count 3 dffe/t:$_MUX_
+select -assert-count 3 sdff0/t:$_MUX_
+select -assert-count 3 sdff1/t:$_MUX_
+select -assert-count 8 sdffe0/t:$_MUX_
+select -assert-count 8 sdffe1/t:$_MUX_
+select -assert-count 8 sdffce0/t:$_MUX_
+select -assert-count 8 sdffce1/t:$_MUX_
+select -assert-count 27 t:$_DFF_PP1_
+select -assert-none t:$_DFF_PP1_ t:$_MUX_ t:$_NOT_ top/* %% %n t:* %i
+
+
+# Convert everything to ADFFEs.
+
+design -load orig
+dfflegalize -cell $_DFFE_PP0P_ 0
+
+select -assert-count 1 dff/t:$_NOT_
+select -assert-count 2 dffe/t:$_NOT_
+select -assert-count 1 sdff0/t:$_NOT_
+select -assert-count 1 sdff1/t:$_NOT_
+select -assert-count 1 sdffe0/t:$_NOT_
+select -assert-count 1 sdffe1/t:$_NOT_
+select -assert-count 2 sdffce0/t:$_NOT_
+select -assert-count 2 sdffce1/t:$_NOT_
+select -assert-count 0 dff/t:$_MUX_
+select -assert-count 0 dffe/t:$_MUX_
+select -assert-count 3 sdff0/t:$_MUX_
+select -assert-count 3 sdff1/t:$_MUX_
+select -assert-count 8 sdffe0/t:$_MUX_
+select -assert-count 8 sdffe1/t:$_MUX_
+select -assert-count 4 sdffce0/t:$_MUX_
+select -assert-count 4 sdffce1/t:$_MUX_
+select -assert-count 27 t:$_DFFE_PP0P_
+select -assert-none t:$_DFFE_PP0P_ t:$_MUX_ t:$_NOT_ top/* %% %n t:* %i
+
+design -load orig
+dfflegalize -cell $_DFFE_PP0P_ 1
+
+select -assert-count 5 dff/t:$_NOT_
+select -assert-count 8 dffe/t:$_NOT_
+select -assert-count 7 sdff0/t:$_NOT_
+select -assert-count 7 sdff1/t:$_NOT_
+select -assert-count 9 sdffe0/t:$_NOT_
+select -assert-count 9 sdffe1/t:$_NOT_
+select -assert-count 10 sdffce0/t:$_NOT_
+select -assert-count 10 sdffce1/t:$_NOT_
+select -assert-count 0 dff/t:$_MUX_
+select -assert-count 0 dffe/t:$_MUX_
+select -assert-count 3 sdff0/t:$_MUX_
+select -assert-count 3 sdff1/t:$_MUX_
+select -assert-count 8 sdffe0/t:$_MUX_
+select -assert-count 8 sdffe1/t:$_MUX_
+select -assert-count 4 sdffce0/t:$_MUX_
+select -assert-count 4 sdffce1/t:$_MUX_
+select -assert-count 27 t:$_DFFE_PP0P_
+select -assert-none t:$_DFFE_PP0P_ t:$_MUX_ t:$_NOT_ top/* %% %n t:* %i
+
+design -load orig
+dfflegalize -cell $_DFFE_PP1P_ 0
+
+select -assert-count 1 dff/t:$_NOT_
+select -assert-count 2 dffe/t:$_NOT_
+select -assert-count 1 sdff0/t:$_NOT_
+select -assert-count 1 sdff1/t:$_NOT_
+select -assert-count 1 sdffe0/t:$_NOT_
+select -assert-count 1 sdffe1/t:$_NOT_
+select -assert-count 2 sdffce0/t:$_NOT_
+select -assert-count 2 sdffce1/t:$_NOT_
+select -assert-count 0 dff/t:$_MUX_
+select -assert-count 0 dffe/t:$_MUX_
+select -assert-count 3 sdff0/t:$_MUX_
+select -assert-count 3 sdff1/t:$_MUX_
+select -assert-count 8 sdffe0/t:$_MUX_
+select -assert-count 8 sdffe1/t:$_MUX_
+select -assert-count 4 sdffce0/t:$_MUX_
+select -assert-count 4 sdffce1/t:$_MUX_
+select -assert-count 27 t:$_DFFE_PP1P_
+select -assert-none t:$_DFFE_PP1P_ t:$_MUX_ t:$_NOT_ top/* %% %n t:* %i
+
+design -load orig
+dfflegalize -cell $_DFFE_PP1P_ 1
+
+select -assert-count 5 dff/t:$_NOT_
+select -assert-count 8 dffe/t:$_NOT_
+select -assert-count 7 sdff0/t:$_NOT_
+select -assert-count 7 sdff1/t:$_NOT_
+select -assert-count 9 sdffe0/t:$_NOT_
+select -assert-count 9 sdffe1/t:$_NOT_
+select -assert-count 10 sdffce0/t:$_NOT_
+select -assert-count 10 sdffce1/t:$_NOT_
+select -assert-count 0 dff/t:$_MUX_
+select -assert-count 0 dffe/t:$_MUX_
+select -assert-count 3 sdff0/t:$_MUX_
+select -assert-count 3 sdff1/t:$_MUX_
+select -assert-count 8 sdffe0/t:$_MUX_
+select -assert-count 8 sdffe1/t:$_MUX_
+select -assert-count 4 sdffce0/t:$_MUX_
+select -assert-count 4 sdffce1/t:$_MUX_
+select -assert-count 27 t:$_DFFE_PP1P_
+select -assert-none t:$_DFFE_PP1P_ t:$_MUX_ t:$_NOT_ top/* %% %n t:* %i
+
+
+# Convert everything to DFFSRs.
+
+design -load orig
+dfflegalize -cell $_DFFSR_PPP_ 0
+
+select -assert-count 1 dff/t:$_NOT_
+select -assert-count 1 dffe/t:$_NOT_
+select -assert-count 1 sdff0/t:$_NOT_
+select -assert-count 1 sdff1/t:$_NOT_
+select -assert-count 1 sdffe0/t:$_NOT_
+select -assert-count 1 sdffe1/t:$_NOT_
+select -assert-count 1 sdffce0/t:$_NOT_
+select -assert-count 1 sdffce1/t:$_NOT_
+select -assert-count 0 dff/t:$_MUX_
+select -assert-count 3 dffe/t:$_MUX_
+select -assert-count 3 sdff0/t:$_MUX_
+select -assert-count 3 sdff1/t:$_MUX_
+select -assert-count 8 sdffe0/t:$_MUX_
+select -assert-count 8 sdffe1/t:$_MUX_
+select -assert-count 8 sdffce0/t:$_MUX_
+select -assert-count 8 sdffce1/t:$_MUX_
+select -assert-count 27 t:$_DFFSR_PPP_
+select -assert-none t:$_DFFSR_PPP_ t:$_MUX_ t:$_NOT_ top/* %% %n t:* %i
+
+design -load orig
+dfflegalize -cell $_DFFSR_PPP_ 1
+
+select -assert-count 5 dff/t:$_NOT_
+select -assert-count 7 dffe/t:$_NOT_
+select -assert-count 7 sdff0/t:$_NOT_
+select -assert-count 7 sdff1/t:$_NOT_
+select -assert-count 9 sdffe0/t:$_NOT_
+select -assert-count 9 sdffe1/t:$_NOT_
+select -assert-count 9 sdffce0/t:$_NOT_
+select -assert-count 9 sdffce1/t:$_NOT_
+select -assert-count 0 dff/t:$_MUX_
+select -assert-count 3 dffe/t:$_MUX_
+select -assert-count 3 sdff0/t:$_MUX_
+select -assert-count 3 sdff1/t:$_MUX_
+select -assert-count 8 sdffe0/t:$_MUX_
+select -assert-count 8 sdffe1/t:$_MUX_
+select -assert-count 8 sdffce0/t:$_MUX_
+select -assert-count 8 sdffce1/t:$_MUX_
+select -assert-count 27 t:$_DFFSR_PPP_
+select -assert-none t:$_DFFSR_PPP_ t:$_MUX_ t:$_NOT_ top/* %% %n t:* %i
+
+
+# Convert everything to DFFSREs.
+
+design -load orig
+dfflegalize -cell $_DFFSRE_PPPP_ 0
+
+select -assert-count 1 dff/t:$_NOT_
+select -assert-count 2 dffe/t:$_NOT_
+select -assert-count 1 sdff0/t:$_NOT_
+select -assert-count 1 sdff1/t:$_NOT_
+select -assert-count 1 sdffe0/t:$_NOT_
+select -assert-count 1 sdffe1/t:$_NOT_
+select -assert-count 2 sdffce0/t:$_NOT_
+select -assert-count 2 sdffce1/t:$_NOT_
+select -assert-count 0 dff/t:$_MUX_
+select -assert-count 0 dffe/t:$_MUX_
+select -assert-count 3 sdff0/t:$_MUX_
+select -assert-count 3 sdff1/t:$_MUX_
+select -assert-count 8 sdffe0/t:$_MUX_
+select -assert-count 8 sdffe1/t:$_MUX_
+select -assert-count 4 sdffce0/t:$_MUX_
+select -assert-count 4 sdffce1/t:$_MUX_
+select -assert-count 27 t:$_DFFSRE_PPPP_
+select -assert-none t:$_DFFSRE_PPPP_ t:$_MUX_ t:$_NOT_ top/* %% %n t:* %i
+
+design -load orig
+dfflegalize -cell $_DFFSRE_PPPP_ 1
+
+select -assert-count 5 dff/t:$_NOT_
+select -assert-count 8 dffe/t:$_NOT_
+select -assert-count 7 sdff0/t:$_NOT_
+select -assert-count 7 sdff1/t:$_NOT_
+select -assert-count 9 sdffe0/t:$_NOT_
+select -assert-count 9 sdffe1/t:$_NOT_
+select -assert-count 10 sdffce0/t:$_NOT_
+select -assert-count 10 sdffce1/t:$_NOT_
+select -assert-count 0 dff/t:$_MUX_
+select -assert-count 0 dffe/t:$_MUX_
+select -assert-count 3 sdff0/t:$_MUX_
+select -assert-count 3 sdff1/t:$_MUX_
+select -assert-count 8 sdffe0/t:$_MUX_
+select -assert-count 8 sdffe1/t:$_MUX_
+select -assert-count 4 sdffce0/t:$_MUX_
+select -assert-count 4 sdffce1/t:$_MUX_
+select -assert-count 27 t:$_DFFSRE_PPPP_
+select -assert-none t:$_DFFSRE_PPPP_ t:$_MUX_ t:$_NOT_ top/* %% %n t:* %i
+
+
+# Convert everything to SDFFs.
+
+design -load orig
+dfflegalize -cell $_SDFF_PP0_ 0
+
+select -assert-count 1 dff/t:$_NOT_
+select -assert-count 1 dffe/t:$_NOT_
+select -assert-count 2 sdff0/t:$_NOT_
+select -assert-count 1 sdff1/t:$_NOT_
+select -assert-count 2 sdffe0/t:$_NOT_
+select -assert-count 1 sdffe1/t:$_NOT_
+select -assert-count 2 sdffce0/t:$_NOT_
+select -assert-count 1 sdffce1/t:$_NOT_
+select -assert-count 0 dff/t:$_MUX_
+select -assert-count 3 dffe/t:$_MUX_
+select -assert-count 0 sdff0/t:$_MUX_
+select -assert-count 3 sdff1/t:$_MUX_
+select -assert-count 4 sdffe0/t:$_MUX_
+select -assert-count 8 sdffe1/t:$_MUX_
+select -assert-count 4 sdffce0/t:$_MUX_
+select -assert-count 8 sdffce1/t:$_MUX_
+select -assert-count 0 t:$_AND_ t:$_ORNOT_ t:$_ANDNOT_ %% sdffce0/* %n %i
+select -assert-count 2 sdffce0/t:$_AND_
+select -assert-count 1 sdffce0/t:$_ORNOT_
+select -assert-count 1 sdffce0/t:$_ANDNOT_
+select -assert-count 27 t:$_SDFF_PP0_
+select -assert-none t:$_SDFF_PP0_ t:$_MUX_ t:$_NOT_ t:$_AND_ t:$_ORNOT_ t:$_ANDNOT_ top/* %% %n t:* %i
+
+design -load orig
+dfflegalize -cell $_SDFF_PP0_ 1
+
+select -assert-count 5 dff/t:$_NOT_
+select -assert-count 7 dffe/t:$_NOT_
+select -assert-count 7 sdff0/t:$_NOT_
+select -assert-count 8 sdff1/t:$_NOT_
+select -assert-count 9 sdffe0/t:$_NOT_
+select -assert-count 10 sdffe1/t:$_NOT_
+select -assert-count 9 sdffce0/t:$_NOT_
+select -assert-count 10 sdffce1/t:$_NOT_
+select -assert-count 0 dff/t:$_MUX_
+select -assert-count 3 dffe/t:$_MUX_
+select -assert-count 3 sdff0/t:$_MUX_
+select -assert-count 0 sdff1/t:$_MUX_
+select -assert-count 8 sdffe0/t:$_MUX_
+select -assert-count 4 sdffe1/t:$_MUX_
+select -assert-count 8 sdffce0/t:$_MUX_
+select -assert-count 4 sdffce1/t:$_MUX_
+select -assert-count 0 t:$_AND_ t:$_ORNOT_ t:$_ANDNOT_ %% sdffce1/* %n %i
+select -assert-count 2 sdffce1/t:$_AND_
+select -assert-count 1 sdffce1/t:$_ORNOT_
+select -assert-count 1 sdffce1/t:$_ANDNOT_
+select -assert-count 27 t:$_SDFF_PP0_
+select -assert-none t:$_SDFF_PP0_ t:$_MUX_ t:$_NOT_ t:$_AND_ t:$_ORNOT_ t:$_ANDNOT_ top/* %% %n t:* %i
+
+design -load orig
+dfflegalize -cell $_SDFF_PP1_ 0
+
+select -assert-count 1 dff/t:$_NOT_
+select -assert-count 1 dffe/t:$_NOT_
+select -assert-count 1 sdff0/t:$_NOT_
+select -assert-count 2 sdff1/t:$_NOT_
+select -assert-count 1 sdffe0/t:$_NOT_
+select -assert-count 2 sdffe1/t:$_NOT_
+select -assert-count 1 sdffce0/t:$_NOT_
+select -assert-count 2 sdffce1/t:$_NOT_
+select -assert-count 0 dff/t:$_MUX_
+select -assert-count 3 dffe/t:$_MUX_
+select -assert-count 3 sdff0/t:$_MUX_
+select -assert-count 0 sdff1/t:$_MUX_
+select -assert-count 8 sdffe0/t:$_MUX_
+select -assert-count 4 sdffe1/t:$_MUX_
+select -assert-count 8 sdffce0/t:$_MUX_
+select -assert-count 4 sdffce1/t:$_MUX_
+select -assert-count 0 t:$_AND_ t:$_ORNOT_ t:$_ANDNOT_ %% sdffce1/* %n %i
+select -assert-count 2 sdffce1/t:$_AND_
+select -assert-count 1 sdffce1/t:$_ORNOT_
+select -assert-count 1 sdffce1/t:$_ANDNOT_
+select -assert-count 27 t:$_SDFF_PP1_
+select -assert-none t:$_SDFF_PP1_ t:$_MUX_ t:$_NOT_ t:$_AND_ t:$_ORNOT_ t:$_ANDNOT_ top/* %% %n t:* %i
+
+design -load orig
+dfflegalize -cell $_SDFF_PP1_ 1
+
+select -assert-count 5 dff/t:$_NOT_
+select -assert-count 7 dffe/t:$_NOT_
+select -assert-count 8 sdff0/t:$_NOT_
+select -assert-count 7 sdff1/t:$_NOT_
+select -assert-count 10 sdffe0/t:$_NOT_
+select -assert-count 9 sdffe1/t:$_NOT_
+select -assert-count 10 sdffce0/t:$_NOT_
+select -assert-count 9 sdffce1/t:$_NOT_
+select -assert-count 0 dff/t:$_MUX_
+select -assert-count 3 dffe/t:$_MUX_
+select -assert-count 0 sdff0/t:$_MUX_
+select -assert-count 3 sdff1/t:$_MUX_
+select -assert-count 4 sdffe0/t:$_MUX_
+select -assert-count 8 sdffe1/t:$_MUX_
+select -assert-count 4 sdffce0/t:$_MUX_
+select -assert-count 8 sdffce1/t:$_MUX_
+select -assert-count 0 t:$_AND_ t:$_ORNOT_ t:$_ANDNOT_ %% sdffce0/* %n %i
+select -assert-count 2 sdffce0/t:$_AND_
+select -assert-count 1 sdffce0/t:$_ORNOT_
+select -assert-count 1 sdffce0/t:$_ANDNOT_
+select -assert-count 27 t:$_SDFF_PP1_
+select -assert-none t:$_SDFF_PP1_ t:$_MUX_ t:$_NOT_ t:$_AND_ t:$_ORNOT_ t:$_ANDNOT_ top/* %% %n t:* %i
+
+
+# Convert everything to SDFFEs.
+
+design -load orig
+dfflegalize -cell $_SDFFE_PP0P_ 0
+
+select -assert-count 1 dff/t:$_NOT_
+select -assert-count 2 dffe/t:$_NOT_
+select -assert-count 2 sdff0/t:$_NOT_
+select -assert-count 1 sdff1/t:$_NOT_
+select -assert-count 3 sdffe0/t:$_NOT_
+select -assert-count 1 sdffe1/t:$_NOT_
+select -assert-count 3 sdffce0/t:$_NOT_
+select -assert-count 2 sdffce1/t:$_NOT_
+select -assert-count 0 dff/t:$_MUX_
+select -assert-count 0 dffe/t:$_MUX_
+select -assert-count 0 sdff0/t:$_MUX_
+select -assert-count 3 sdff1/t:$_MUX_
+select -assert-count 0 sdffe0/t:$_MUX_
+select -assert-count 8 sdffe1/t:$_MUX_
+select -assert-count 0 sdffce0/t:$_MUX_
+select -assert-count 4 sdffce1/t:$_MUX_
+select -assert-count 0 t:$_AND_ t:$_ORNOT_ t:$_ANDNOT_ %% sdffce0/* %n %i
+select -assert-count 2 sdffce0/t:$_AND_
+select -assert-count 1 sdffce0/t:$_ORNOT_
+select -assert-count 1 sdffce0/t:$_ANDNOT_
+select -assert-count 27 t:$_SDFFE_PP0P_
+select -assert-none t:$_SDFFE_PP0P_ t:$_NOT_ t:$_MUX_ t:$_AND_ t:$_ORNOT_ t:$_ANDNOT_ top/* %% %n t:* %i
+
+design -load orig
+dfflegalize -cell $_SDFFE_PP0P_ 1
+
+select -assert-count 5 dff/t:$_NOT_
+select -assert-count 8 dffe/t:$_NOT_
+select -assert-count 7 sdff0/t:$_NOT_
+select -assert-count 8 sdff1/t:$_NOT_
+select -assert-count 9 sdffe0/t:$_NOT_
+select -assert-count 11 sdffe1/t:$_NOT_
+select -assert-count 10 sdffce0/t:$_NOT_
+select -assert-count 11 sdffce1/t:$_NOT_
+select -assert-count 0 dff/t:$_MUX_
+select -assert-count 0 dffe/t:$_MUX_
+select -assert-count 3 sdff0/t:$_MUX_
+select -assert-count 0 sdff1/t:$_MUX_
+select -assert-count 8 sdffe0/t:$_MUX_
+select -assert-count 0 sdffe1/t:$_MUX_
+select -assert-count 4 sdffce0/t:$_MUX_
+select -assert-count 0 sdffce1/t:$_MUX_
+select -assert-count 0 t:$_AND_ t:$_ORNOT_ t:$_ANDNOT_ %% sdffce1/* %n %i
+select -assert-count 2 sdffce1/t:$_AND_
+select -assert-count 1 sdffce1/t:$_ORNOT_
+select -assert-count 1 sdffce1/t:$_ANDNOT_
+select -assert-count 27 t:$_SDFFE_PP0P_
+select -assert-none t:$_SDFFE_PP0P_ t:$_NOT_ t:$_MUX_ t:$_AND_ t:$_ORNOT_ t:$_ANDNOT_ top/* %% %n t:* %i
+
+design -load orig
+dfflegalize -cell $_SDFFE_PP1P_ 0
+
+select -assert-count 1 dff/t:$_NOT_
+select -assert-count 2 dffe/t:$_NOT_
+select -assert-count 1 sdff0/t:$_NOT_
+select -assert-count 2 sdff1/t:$_NOT_
+select -assert-count 1 sdffe0/t:$_NOT_
+select -assert-count 3 sdffe1/t:$_NOT_
+select -assert-count 2 sdffce0/t:$_NOT_
+select -assert-count 3 sdffce1/t:$_NOT_
+select -assert-count 0 dff/t:$_MUX_
+select -assert-count 0 dffe/t:$_MUX_
+select -assert-count 3 sdff0/t:$_MUX_
+select -assert-count 0 sdff1/t:$_MUX_
+select -assert-count 8 sdffe0/t:$_MUX_
+select -assert-count 0 sdffe1/t:$_MUX_
+select -assert-count 4 sdffce0/t:$_MUX_
+select -assert-count 0 sdffce1/t:$_MUX_
+select -assert-count 0 t:$_AND_ t:$_ORNOT_ t:$_ANDNOT_ %% sdffce1/* %n %i
+select -assert-count 2 sdffce1/t:$_AND_
+select -assert-count 1 sdffce1/t:$_ORNOT_
+select -assert-count 1 sdffce1/t:$_ANDNOT_
+select -assert-count 27 t:$_SDFFE_PP1P_
+select -assert-none t:$_SDFFE_PP1P_ t:$_NOT_ t:$_MUX_ t:$_AND_ t:$_ORNOT_ t:$_ANDNOT_ top/* %% %n t:* %i
+
+design -load orig
+dfflegalize -cell $_SDFFE_PP1P_ 1
+
+select -assert-count 5 dff/t:$_NOT_
+select -assert-count 8 dffe/t:$_NOT_
+select -assert-count 8 sdff0/t:$_NOT_
+select -assert-count 7 sdff1/t:$_NOT_
+select -assert-count 11 sdffe0/t:$_NOT_
+select -assert-count 9 sdffe1/t:$_NOT_
+select -assert-count 11 sdffce0/t:$_NOT_
+select -assert-count 10 sdffce1/t:$_NOT_
+select -assert-count 0 dff/t:$_MUX_
+select -assert-count 0 dffe/t:$_MUX_
+select -assert-count 0 sdff0/t:$_MUX_
+select -assert-count 3 sdff1/t:$_MUX_
+select -assert-count 0 sdffe0/t:$_MUX_
+select -assert-count 8 sdffe1/t:$_MUX_
+select -assert-count 0 sdffce0/t:$_MUX_
+select -assert-count 4 sdffce1/t:$_MUX_
+select -assert-count 0 t:$_AND_ t:$_ORNOT_ t:$_ANDNOT_ %% sdffce0/* %n %i
+select -assert-count 2 sdffce0/t:$_AND_
+select -assert-count 1 sdffce0/t:$_ORNOT_
+select -assert-count 1 sdffce0/t:$_ANDNOT_
+select -assert-count 27 t:$_SDFFE_PP1P_
+select -assert-none t:$_SDFFE_PP1P_ t:$_NOT_ t:$_MUX_ t:$_AND_ t:$_ORNOT_ t:$_ANDNOT_ top/* %% %n t:* %i
+
+
+# Convert everything to SDFFCEs.
+
+design -load orig
+dfflegalize -cell $_SDFFCE_PP0P_ 0
+
+select -assert-count 1 dff/t:$_NOT_
+select -assert-count 2 dffe/t:$_NOT_
+select -assert-count 2 sdff0/t:$_NOT_
+select -assert-count 1 sdff1/t:$_NOT_
+select -assert-count 3 sdffe0/t:$_NOT_
+select -assert-count 1 sdffe1/t:$_NOT_
+select -assert-count 3 sdffce0/t:$_NOT_
+select -assert-count 2 sdffce1/t:$_NOT_
+select -assert-count 0 dff/t:$_MUX_
+select -assert-count 0 dffe/t:$_MUX_
+select -assert-count 0 sdff0/t:$_MUX_
+select -assert-count 3 sdff1/t:$_MUX_
+select -assert-count 0 sdffe0/t:$_MUX_
+select -assert-count 8 sdffe1/t:$_MUX_
+select -assert-count 0 sdffce0/t:$_MUX_
+select -assert-count 4 sdffce1/t:$_MUX_
+select -assert-count 0 t:$_OR_ t:$_ORNOT_ t:$_ANDNOT_ %% sdffe0/* %n %i
+select -assert-count 2 sdffe0/t:$_OR_
+select -assert-count 1 sdffe0/t:$_ORNOT_
+select -assert-count 1 sdffe0/t:$_ANDNOT_
+select -assert-count 27 t:$_SDFFCE_PP0P_
+select -assert-none t:$_SDFFCE_PP0P_ t:$_NOT_ t:$_MUX_ t:$_OR_ t:$_ORNOT_ t:$_ANDNOT_ top/* %% %n t:* %i
+
+design -load orig
+dfflegalize -cell $_SDFFCE_PP0P_ 1
+
+select -assert-count 5 dff/t:$_NOT_
+select -assert-count 8 dffe/t:$_NOT_
+select -assert-count 7 sdff0/t:$_NOT_
+select -assert-count 8 sdff1/t:$_NOT_
+select -assert-count 9 sdffe0/t:$_NOT_
+select -assert-count 11 sdffe1/t:$_NOT_
+select -assert-count 10 sdffce0/t:$_NOT_
+select -assert-count 11 sdffce1/t:$_NOT_
+select -assert-count 0 dff/t:$_MUX_
+select -assert-count 0 dffe/t:$_MUX_
+select -assert-count 3 sdff0/t:$_MUX_
+select -assert-count 0 sdff1/t:$_MUX_
+select -assert-count 8 sdffe0/t:$_MUX_
+select -assert-count 0 sdffe1/t:$_MUX_
+select -assert-count 4 sdffce0/t:$_MUX_
+select -assert-count 0 sdffce1/t:$_MUX_
+select -assert-count 0 t:$_OR_ t:$_ORNOT_ t:$_ANDNOT_ %% sdffe1/* %n %i
+select -assert-count 2 sdffe1/t:$_OR_
+select -assert-count 1 sdffe1/t:$_ORNOT_
+select -assert-count 1 sdffe1/t:$_ANDNOT_
+select -assert-count 27 t:$_SDFFCE_PP0P_
+select -assert-none t:$_SDFFCE_PP0P_ t:$_NOT_ t:$_MUX_ t:$_OR_ t:$_ORNOT_ t:$_ANDNOT_ top/* %% %n t:* %i
+
+design -load orig
+dfflegalize -cell $_SDFFCE_PP1P_ 0
+
+select -assert-count 1 dff/t:$_NOT_
+select -assert-count 2 dffe/t:$_NOT_
+select -assert-count 1 sdff0/t:$_NOT_
+select -assert-count 2 sdff1/t:$_NOT_
+select -assert-count 1 sdffe0/t:$_NOT_
+select -assert-count 3 sdffe1/t:$_NOT_
+select -assert-count 2 sdffce0/t:$_NOT_
+select -assert-count 3 sdffce1/t:$_NOT_
+select -assert-count 0 dff/t:$_MUX_
+select -assert-count 0 dffe/t:$_MUX_
+select -assert-count 3 sdff0/t:$_MUX_
+select -assert-count 0 sdff1/t:$_MUX_
+select -assert-count 8 sdffe0/t:$_MUX_
+select -assert-count 0 sdffe1/t:$_MUX_
+select -assert-count 4 sdffce0/t:$_MUX_
+select -assert-count 0 sdffce1/t:$_MUX_
+select -assert-count 0 t:$_OR_ t:$_ORNOT_ t:$_ANDNOT_ %% sdffe1/* %n %i
+select -assert-count 2 sdffe1/t:$_OR_
+select -assert-count 1 sdffe1/t:$_ORNOT_
+select -assert-count 1 sdffe1/t:$_ANDNOT_
+select -assert-count 27 t:$_SDFFCE_PP1P_
+select -assert-none t:$_SDFFCE_PP1P_ t:$_NOT_ t:$_MUX_ t:$_OR_ t:$_ORNOT_ t:$_ANDNOT_ top/* %% %n t:* %i
+
+design -load orig
+dfflegalize -cell $_SDFFCE_PP1P_ 1
+
+select -assert-count 5 dff/t:$_NOT_
+select -assert-count 8 dffe/t:$_NOT_
+select -assert-count 8 sdff0/t:$_NOT_
+select -assert-count 7 sdff1/t:$_NOT_
+select -assert-count 11 sdffe0/t:$_NOT_
+select -assert-count 9 sdffe1/t:$_NOT_
+select -assert-count 11 sdffce0/t:$_NOT_
+select -assert-count 10 sdffce1/t:$_NOT_
+select -assert-count 0 dff/t:$_MUX_
+select -assert-count 0 dffe/t:$_MUX_
+select -assert-count 0 sdff0/t:$_MUX_
+select -assert-count 3 sdff1/t:$_MUX_
+select -assert-count 0 sdffe0/t:$_MUX_
+select -assert-count 8 sdffe1/t:$_MUX_
+select -assert-count 0 sdffce0/t:$_MUX_
+select -assert-count 4 sdffce1/t:$_MUX_
+select -assert-count 0 t:$_OR_ t:$_ORNOT_ t:$_ANDNOT_ %% sdffe0/* %n %i
+select -assert-count 2 sdffe0/t:$_OR_
+select -assert-count 1 sdffe0/t:$_ORNOT_
+select -assert-count 1 sdffe0/t:$_ANDNOT_
+select -assert-count 27 t:$_SDFFCE_PP1P_
+select -assert-none t:$_SDFFCE_PP1P_ t:$_NOT_ t:$_MUX_ t:$_OR_ t:$_ORNOT_ t:$_ANDNOT_ top/* %% %n t:* %i
diff --git a/tests/techmap/dfflegalize_dffsr.ys b/tests/techmap/dfflegalize_dffsr.ys
new file mode 100644
index 000000000..0cfb4950e
--- /dev/null
+++ b/tests/techmap/dfflegalize_dffsr.ys
@@ -0,0 +1,88 @@
+read_verilog -icells <<EOT
+
+module dffsr(input C, R, S, D, output [3:0] Q);
+$_DFFSR_PPP_ ff0 (.C(C), .R(R), .S(S), .D(D), .Q(Q[0]));
+$_DFFSR_PPN_ ff1 (.C(C), .R(R), .S(S), .D(D), .Q(Q[1]));
+$_DFFSR_PNP_ ff2 (.C(C), .R(R), .S(S), .D(D), .Q(Q[2]));
+$_DFFSR_NPP_ ff3 (.C(C), .R(R), .S(S), .D(D), .Q(Q[3]));
+endmodule
+
+module dffsre(input C, R, S, E, D, output [4:0] Q);
+$_DFFSRE_PPPP_ ff0 (.C(C), .R(R), .S(S), .E(E), .D(D), .Q(Q[0]));
+$_DFFSRE_PPPN_ ff1 (.C(C), .R(R), .S(S), .E(E), .D(D), .Q(Q[1]));
+$_DFFSRE_PPNP_ ff2 (.C(C), .R(R), .S(S), .E(E), .D(D), .Q(Q[2]));
+$_DFFSRE_PNPP_ ff3 (.C(C), .R(R), .S(S), .E(E), .D(D), .Q(Q[3]));
+$_DFFSRE_NPPP_ ff4 (.C(C), .R(R), .S(S), .E(E), .D(D), .Q(Q[4]));
+endmodule
+
+module top(input C, E, R, S, D, output [8:0] Q);
+dffsr dffsr_(.C(C), .R(R), .S(S), .D(D), .Q(Q[3:0]));
+dffsre dffsre_(.C(C), .R(R), .S(S), .E(E), .D(D), .Q(Q[8:4]));
+endmodule
+
+EOT
+
+design -save orig
+flatten
+#equiv_opt -assert -multiclock -map +/simcells.v dfflegalize -cell $_DFF_PP0_ x -cell $_SR_PP_ x
+#equiv_opt -assert -multiclock -map +/simcells.v dfflegalize -cell $_DFFE_PP0P_ x -cell $_SR_PP_ x
+equiv_opt -assert -multiclock -map +/simcells.v dfflegalize -cell $_DFFSR_PPP_ x
+equiv_opt -assert -multiclock -map +/simcells.v dfflegalize -cell $_DFFSRE_PPPP_ x
+
+
+# Convert everything to ADFFs.
+
+design -load orig
+dfflegalize -cell $_DFF_PP0_ x -cell $_SR_PP_ x
+
+select -assert-count 14 dffsr/t:$_NOT_
+select -assert-count 16 dffsre/t:$_NOT_
+select -assert-count 4 dffsr/t:$_MUX_
+select -assert-count 10 dffsre/t:$_MUX_
+select -assert-count 8 dffsr/t:$_DFF_PP0_
+select -assert-count 10 dffsre/t:$_DFF_PP0_
+select -assert-count 4 dffsr/t:$_SR_PP_
+select -assert-count 5 dffsre/t:$_SR_PP_
+select -assert-none t:$_DFF_PP0_ t:$_SR_PP_ t:$_MUX_ t:$_NOT_ top/* %% %n t:* %i
+
+
+# Convert everything to ADFFEs.
+
+design -load orig
+dfflegalize -cell $_DFFE_PP0P_ x -cell $_SR_PP_ x
+
+select -assert-count 14 dffsr/t:$_NOT_
+select -assert-count 18 dffsre/t:$_NOT_
+select -assert-count 4 dffsr/t:$_MUX_
+select -assert-count 5 dffsre/t:$_MUX_
+select -assert-count 8 dffsr/t:$_DFFE_PP0P_
+select -assert-count 10 dffsre/t:$_DFFE_PP0P_
+select -assert-count 4 dffsr/t:$_SR_PP_
+select -assert-count 5 dffsre/t:$_SR_PP_
+select -assert-none t:$_DFFE_PP0P_ t:$_SR_PP_ t:$_MUX_ t:$_NOT_ top/* %% %n t:* %i
+
+
+# Convert everything to DFFSRs.
+
+design -load orig
+dfflegalize -cell $_DFFSR_PPP_ x
+
+select -assert-count 3 dffsr/t:$_NOT_
+select -assert-count 3 dffsre/t:$_NOT_
+select -assert-count 0 dffsr/t:$_MUX_
+select -assert-count 5 dffsre/t:$_MUX_
+select -assert-count 4 dffsr/t:$_DFFSR_PPP_
+select -assert-count 5 dffsre/t:$_DFFSR_PPP_
+select -assert-none t:$_DFFSR_PPP_ t:$_MUX_ t:$_NOT_ top/* %% %n t:* %i
+
+
+# Convert everything to DFFSREs.
+
+design -load orig
+dfflegalize -cell $_DFFSRE_PPPP_ x
+
+select -assert-count 3 dffsr/t:$_NOT_
+select -assert-count 4 dffsre/t:$_NOT_
+select -assert-count 4 dffsr/t:$_DFFSRE_PPPP_
+select -assert-count 5 dffsre/t:$_DFFSRE_PPPP_
+select -assert-none t:$_DFFSRE_PPPP_ t:$_NOT_ top/* %% %n t:* %i
diff --git a/tests/techmap/dfflegalize_dffsr_init.ys b/tests/techmap/dfflegalize_dffsr_init.ys
new file mode 100644
index 000000000..646c086e0
--- /dev/null
+++ b/tests/techmap/dfflegalize_dffsr_init.ys
@@ -0,0 +1,379 @@
+read_verilog -icells <<EOT
+
+module dffsr0(input C, R, S, D, (* init = 4'h0 *) output [3:0] Q);
+$_DFFSR_PPP_ ff0 (.C(C), .R(R), .S(S), .D(D), .Q(Q[0]));
+$_DFFSR_PPN_ ff1 (.C(C), .R(R), .S(S), .D(D), .Q(Q[1]));
+$_DFFSR_PNP_ ff2 (.C(C), .R(R), .S(S), .D(D), .Q(Q[2]));
+$_DFFSR_NPP_ ff3 (.C(C), .R(R), .S(S), .D(D), .Q(Q[3]));
+endmodule
+
+module dffsr1(input C, R, S, D, (* init = 4'hf *) output [3:0] Q);
+$_DFFSR_PPP_ ff0 (.C(C), .R(R), .S(S), .D(D), .Q(Q[0]));
+$_DFFSR_PPN_ ff1 (.C(C), .R(R), .S(S), .D(D), .Q(Q[1]));
+$_DFFSR_PNP_ ff2 (.C(C), .R(R), .S(S), .D(D), .Q(Q[2]));
+$_DFFSR_NPP_ ff3 (.C(C), .R(R), .S(S), .D(D), .Q(Q[3]));
+endmodule
+
+module dffsre0(input C, R, S, E, D, (* init = 5'h0 *) output [4:0] Q);
+$_DFFSRE_PPPP_ ff0 (.C(C), .R(R), .S(S), .E(E), .D(D), .Q(Q[0]));
+$_DFFSRE_PPPN_ ff1 (.C(C), .R(R), .S(S), .E(E), .D(D), .Q(Q[1]));
+$_DFFSRE_PPNP_ ff2 (.C(C), .R(R), .S(S), .E(E), .D(D), .Q(Q[2]));
+$_DFFSRE_PNPP_ ff3 (.C(C), .R(R), .S(S), .E(E), .D(D), .Q(Q[3]));
+$_DFFSRE_NPPP_ ff4 (.C(C), .R(R), .S(S), .E(E), .D(D), .Q(Q[4]));
+endmodule
+
+module dffsre1(input C, R, S, E, D, (* init = 5'h1f *) output [4:0] Q);
+$_DFFSRE_PPPP_ ff0 (.C(C), .R(R), .S(S), .E(E), .D(D), .Q(Q[0]));
+$_DFFSRE_PPPN_ ff1 (.C(C), .R(R), .S(S), .E(E), .D(D), .Q(Q[1]));
+$_DFFSRE_PPNP_ ff2 (.C(C), .R(R), .S(S), .E(E), .D(D), .Q(Q[2]));
+$_DFFSRE_PNPP_ ff3 (.C(C), .R(R), .S(S), .E(E), .D(D), .Q(Q[3]));
+$_DFFSRE_NPPP_ ff4 (.C(C), .R(R), .S(S), .E(E), .D(D), .Q(Q[4]));
+endmodule
+
+module top(input C, E, R, S, D, output [17:0] Q);
+dffsr0 dffsr0_(.C(C), .R(R), .S(S), .D(D), .Q(Q[3:0]));
+dffsr1 dffsr1_(.C(C), .R(R), .S(S), .D(D), .Q(Q[7:4]));
+dffsre0 dffsre0_(.C(C), .R(R), .S(S), .E(E), .D(D), .Q(Q[12:8]));
+dffsre1 dffsre1_(.C(C), .R(R), .S(S), .E(E), .D(D), .Q(Q[17:13]));
+endmodule
+
+EOT
+
+design -save orig
+flatten
+#equiv_opt -assert -multiclock -map +/simcells.v dfflegalize -cell $_DFF_PP0_ 0 -cell $_SR_PP_ 0
+#equiv_opt -assert -multiclock -map +/simcells.v dfflegalize -cell $_DFF_PP0_ 1 -cell $_SR_PP_ 0
+#equiv_opt -assert -multiclock -map +/simcells.v dfflegalize -cell $_DFF_PP1_ 0 -cell $_SR_PP_ 0
+#equiv_opt -assert -multiclock -map +/simcells.v dfflegalize -cell $_DFF_PP1_ 1 -cell $_SR_PP_ 0
+#equiv_opt -assert -multiclock -map +/simcells.v dfflegalize -cell $_DFFE_PP0P_ 0 -cell $_SR_PP_ 0
+#equiv_opt -assert -multiclock -map +/simcells.v dfflegalize -cell $_DFFE_PP0P_ 1 -cell $_SR_PP_ 0
+#equiv_opt -assert -multiclock -map +/simcells.v dfflegalize -cell $_DFFE_PP1P_ 0 -cell $_SR_PP_ 0
+#equiv_opt -assert -multiclock -map +/simcells.v dfflegalize -cell $_DFFE_PP1P_ 1 -cell $_SR_PP_ 0
+equiv_opt -assert -multiclock -map +/simcells.v dfflegalize -cell $_DFFSR_PPP_ 0
+equiv_opt -assert -multiclock -map +/simcells.v dfflegalize -cell $_DFFSR_PPP_ 1
+equiv_opt -assert -multiclock -map +/simcells.v dfflegalize -cell $_DFFSRE_PPPP_ 0
+equiv_opt -assert -multiclock -map +/simcells.v dfflegalize -cell $_DFFSRE_PPPP_ 1
+
+
+# Convert everything to ADFFs.
+
+design -load orig
+dfflegalize -cell $_DFF_PP0_ 0 -cell $_SR_PP_ 0
+
+select -assert-count 14 dffsr0/t:$_NOT_
+select -assert-count 18 dffsr1/t:$_NOT_
+select -assert-count 16 dffsre0/t:$_NOT_
+select -assert-count 21 dffsre1/t:$_NOT_
+select -assert-count 4 dffsr0/t:$_MUX_
+select -assert-count 4 dffsr1/t:$_MUX_
+select -assert-count 10 dffsre0/t:$_MUX_
+select -assert-count 10 dffsre1/t:$_MUX_
+select -assert-count 8 dffsr0/t:$_DFF_PP0_
+select -assert-count 8 dffsr1/t:$_DFF_PP0_
+select -assert-count 10 dffsre0/t:$_DFF_PP0_
+select -assert-count 10 dffsre1/t:$_DFF_PP0_
+select -assert-count 4 dffsr0/t:$_SR_PP_
+select -assert-count 4 dffsr1/t:$_SR_PP_
+select -assert-count 5 dffsre0/t:$_SR_PP_
+select -assert-count 5 dffsre1/t:$_SR_PP_
+select -assert-count 1 dffsr1/t:$_AND_
+select -assert-count 2 dffsr1/t:$_ANDNOT_
+select -assert-count 1 dffsr1/t:$_OR_
+select -assert-count 1 dffsre1/t:$_AND_
+select -assert-count 3 dffsre1/t:$_ANDNOT_
+select -assert-count 1 dffsre1/t:$_OR_
+select -assert-count 0 t:$_AND_ t:$_OR_ t:$_ANDNOT_ %% dffsr1/* dffsre1/* %u %n %i
+select -assert-none t:$_DFF_PP0_ t:$_SR_PP_ t:$_MUX_ t:$_NOT_ t:$_AND_ t:$_ANDNOT_ t:$_OR_ top/* %% %n t:* %i
+
+design -load orig
+dfflegalize -cell $_DFF_PP0_ 1 -cell $_SR_PP_ 0
+
+select -assert-count 18 dffsr0/t:$_NOT_
+select -assert-count 14 dffsr1/t:$_NOT_
+select -assert-count 21 dffsre0/t:$_NOT_
+select -assert-count 16 dffsre1/t:$_NOT_
+select -assert-count 4 dffsr0/t:$_MUX_
+select -assert-count 4 dffsr1/t:$_MUX_
+select -assert-count 10 dffsre0/t:$_MUX_
+select -assert-count 10 dffsre1/t:$_MUX_
+select -assert-count 8 dffsr0/t:$_DFF_PP0_
+select -assert-count 8 dffsr1/t:$_DFF_PP0_
+select -assert-count 10 dffsre0/t:$_DFF_PP0_
+select -assert-count 10 dffsre1/t:$_DFF_PP0_
+select -assert-count 4 dffsr0/t:$_SR_PP_
+select -assert-count 4 dffsr1/t:$_SR_PP_
+select -assert-count 5 dffsre0/t:$_SR_PP_
+select -assert-count 5 dffsre1/t:$_SR_PP_
+select -assert-count 1 dffsr0/t:$_AND_
+select -assert-count 2 dffsr0/t:$_ANDNOT_
+select -assert-count 1 dffsr0/t:$_OR_
+select -assert-count 1 dffsre0/t:$_AND_
+select -assert-count 3 dffsre0/t:$_ANDNOT_
+select -assert-count 1 dffsre0/t:$_OR_
+select -assert-count 0 t:$_AND_ t:$_OR_ t:$_ANDNOT_ %% dffsr0/* dffsre0/* %u %n %i
+select -assert-none t:$_DFF_PP0_ t:$_SR_PP_ t:$_MUX_ t:$_NOT_ t:$_AND_ t:$_ANDNOT_ t:$_OR_ top/* %% %n t:* %i
+
+design -load orig
+dfflegalize -cell $_DFF_PP1_ 0 -cell $_SR_PP_ 0
+
+select -assert-count 18 dffsr0/t:$_NOT_
+select -assert-count 14 dffsr1/t:$_NOT_
+select -assert-count 21 dffsre0/t:$_NOT_
+select -assert-count 16 dffsre1/t:$_NOT_
+select -assert-count 4 dffsr0/t:$_MUX_
+select -assert-count 4 dffsr1/t:$_MUX_
+select -assert-count 10 dffsre0/t:$_MUX_
+select -assert-count 10 dffsre1/t:$_MUX_
+select -assert-count 8 dffsr0/t:$_DFF_PP1_
+select -assert-count 8 dffsr1/t:$_DFF_PP1_
+select -assert-count 10 dffsre0/t:$_DFF_PP1_
+select -assert-count 10 dffsre1/t:$_DFF_PP1_
+select -assert-count 4 dffsr0/t:$_SR_PP_
+select -assert-count 4 dffsr1/t:$_SR_PP_
+select -assert-count 5 dffsre0/t:$_SR_PP_
+select -assert-count 5 dffsre1/t:$_SR_PP_
+select -assert-count 1 dffsr0/t:$_AND_
+select -assert-count 2 dffsr0/t:$_ANDNOT_
+select -assert-count 1 dffsr0/t:$_OR_
+select -assert-count 1 dffsre0/t:$_AND_
+select -assert-count 3 dffsre0/t:$_ANDNOT_
+select -assert-count 1 dffsre0/t:$_OR_
+select -assert-count 0 t:$_AND_ t:$_OR_ t:$_ANDNOT_ %% dffsr0/* dffsre0/* %u %n %i
+select -assert-none t:$_DFF_PP1_ t:$_SR_PP_ t:$_MUX_ t:$_NOT_ t:$_AND_ t:$_ANDNOT_ t:$_OR_ top/* %% %n t:* %i
+
+design -load orig
+dfflegalize -cell $_DFF_PP1_ 1 -cell $_SR_PP_ 0
+
+select -assert-count 14 dffsr0/t:$_NOT_
+select -assert-count 18 dffsr1/t:$_NOT_
+select -assert-count 16 dffsre0/t:$_NOT_
+select -assert-count 21 dffsre1/t:$_NOT_
+select -assert-count 4 dffsr0/t:$_MUX_
+select -assert-count 4 dffsr1/t:$_MUX_
+select -assert-count 10 dffsre0/t:$_MUX_
+select -assert-count 10 dffsre1/t:$_MUX_
+select -assert-count 8 dffsr0/t:$_DFF_PP1_
+select -assert-count 8 dffsr1/t:$_DFF_PP1_
+select -assert-count 10 dffsre0/t:$_DFF_PP1_
+select -assert-count 10 dffsre1/t:$_DFF_PP1_
+select -assert-count 4 dffsr0/t:$_SR_PP_
+select -assert-count 4 dffsr1/t:$_SR_PP_
+select -assert-count 5 dffsre0/t:$_SR_PP_
+select -assert-count 5 dffsre1/t:$_SR_PP_
+select -assert-count 1 dffsr1/t:$_AND_
+select -assert-count 2 dffsr1/t:$_ANDNOT_
+select -assert-count 1 dffsr1/t:$_OR_
+select -assert-count 1 dffsre1/t:$_AND_
+select -assert-count 3 dffsre1/t:$_ANDNOT_
+select -assert-count 1 dffsre1/t:$_OR_
+select -assert-count 0 t:$_AND_ t:$_OR_ t:$_ANDNOT_ %% dffsr1/* dffsre1/* %u %n %i
+select -assert-none t:$_DFF_PP1_ t:$_SR_PP_ t:$_MUX_ t:$_NOT_ t:$_AND_ t:$_ANDNOT_ t:$_OR_ top/* %% %n t:* %i
+
+
+# Convert everything to ADFFEs.
+
+design -load orig
+dfflegalize -cell $_DFFE_PP0P_ 0 -cell $_SR_PP_ 1
+
+select -assert-count 18 dffsr0/t:$_NOT_
+select -assert-count 14 dffsr1/t:$_NOT_
+select -assert-count 23 dffsre0/t:$_NOT_
+select -assert-count 18 dffsre1/t:$_NOT_
+select -assert-count 4 dffsr0/t:$_MUX_
+select -assert-count 4 dffsr1/t:$_MUX_
+select -assert-count 5 dffsre0/t:$_MUX_
+select -assert-count 5 dffsre1/t:$_MUX_
+select -assert-count 8 dffsr0/t:$_DFFE_PP0P_
+select -assert-count 8 dffsr1/t:$_DFFE_PP0P_
+select -assert-count 10 dffsre0/t:$_DFFE_PP0P_
+select -assert-count 10 dffsre1/t:$_DFFE_PP0P_
+select -assert-count 4 dffsr0/t:$_SR_PP_
+select -assert-count 4 dffsr1/t:$_SR_PP_
+select -assert-count 5 dffsre0/t:$_SR_PP_
+select -assert-count 5 dffsre1/t:$_SR_PP_
+select -assert-count 1 dffsr0/t:$_AND_
+select -assert-count 2 dffsr0/t:$_ANDNOT_
+select -assert-count 1 dffsr0/t:$_OR_
+select -assert-count 1 dffsre0/t:$_AND_
+select -assert-count 3 dffsre0/t:$_ANDNOT_
+select -assert-count 1 dffsre0/t:$_OR_
+select -assert-count 0 t:$_AND_ t:$_OR_ t:$_ANDNOT_ %% dffsr0/* dffsre0/* %u %n %i
+select -assert-none t:$_DFFE_PP0P_ t:$_SR_PP_ t:$_MUX_ t:$_NOT_ t:$_AND_ t:$_ANDNOT_ t:$_OR_ top/* %% %n t:* %i
+
+design -load orig
+dfflegalize -cell $_DFFE_PP0P_ 1 -cell $_SR_PP_ 1
+
+select -assert-count 14 dffsr0/t:$_NOT_
+select -assert-count 18 dffsr1/t:$_NOT_
+select -assert-count 18 dffsre0/t:$_NOT_
+select -assert-count 23 dffsre1/t:$_NOT_
+select -assert-count 4 dffsr0/t:$_MUX_
+select -assert-count 4 dffsr1/t:$_MUX_
+select -assert-count 5 dffsre0/t:$_MUX_
+select -assert-count 5 dffsre1/t:$_MUX_
+select -assert-count 8 dffsr0/t:$_DFFE_PP0P_
+select -assert-count 8 dffsr1/t:$_DFFE_PP0P_
+select -assert-count 10 dffsre0/t:$_DFFE_PP0P_
+select -assert-count 10 dffsre1/t:$_DFFE_PP0P_
+select -assert-count 4 dffsr0/t:$_SR_PP_
+select -assert-count 4 dffsr1/t:$_SR_PP_
+select -assert-count 5 dffsre0/t:$_SR_PP_
+select -assert-count 5 dffsre1/t:$_SR_PP_
+select -assert-count 1 dffsr1/t:$_AND_
+select -assert-count 2 dffsr1/t:$_ANDNOT_
+select -assert-count 1 dffsr1/t:$_OR_
+select -assert-count 1 dffsre1/t:$_AND_
+select -assert-count 3 dffsre1/t:$_ANDNOT_
+select -assert-count 1 dffsre1/t:$_OR_
+select -assert-count 0 t:$_AND_ t:$_OR_ t:$_ANDNOT_ %% dffsr1/* dffsre1/* %u %n %i
+select -assert-none t:$_DFFE_PP0P_ t:$_SR_PP_ t:$_MUX_ t:$_NOT_ t:$_AND_ t:$_ANDNOT_ t:$_OR_ top/* %% %n t:* %i
+
+design -load orig
+dfflegalize -cell $_DFFE_PP1P_ 0 -cell $_SR_PP_ 1
+
+select -assert-count 14 dffsr0/t:$_NOT_
+select -assert-count 18 dffsr1/t:$_NOT_
+select -assert-count 18 dffsre0/t:$_NOT_
+select -assert-count 23 dffsre1/t:$_NOT_
+select -assert-count 4 dffsr0/t:$_MUX_
+select -assert-count 4 dffsr1/t:$_MUX_
+select -assert-count 5 dffsre0/t:$_MUX_
+select -assert-count 5 dffsre1/t:$_MUX_
+select -assert-count 8 dffsr0/t:$_DFFE_PP1P_
+select -assert-count 8 dffsr1/t:$_DFFE_PP1P_
+select -assert-count 10 dffsre0/t:$_DFFE_PP1P_
+select -assert-count 10 dffsre1/t:$_DFFE_PP1P_
+select -assert-count 4 dffsr0/t:$_SR_PP_
+select -assert-count 4 dffsr1/t:$_SR_PP_
+select -assert-count 5 dffsre0/t:$_SR_PP_
+select -assert-count 5 dffsre1/t:$_SR_PP_
+select -assert-count 1 dffsr1/t:$_AND_
+select -assert-count 2 dffsr1/t:$_ANDNOT_
+select -assert-count 1 dffsr1/t:$_OR_
+select -assert-count 1 dffsre1/t:$_AND_
+select -assert-count 3 dffsre1/t:$_ANDNOT_
+select -assert-count 1 dffsre1/t:$_OR_
+select -assert-count 0 t:$_AND_ t:$_OR_ t:$_ANDNOT_ %% dffsr1/* dffsre1/* %u %n %i
+select -assert-none t:$_DFFE_PP1P_ t:$_SR_PP_ t:$_MUX_ t:$_NOT_ t:$_AND_ t:$_ANDNOT_ t:$_OR_ top/* %% %n t:* %i
+
+design -load orig
+dfflegalize -cell $_DFFE_PP1P_ 1 -cell $_SR_PP_ 1
+
+select -assert-count 18 dffsr0/t:$_NOT_
+select -assert-count 14 dffsr1/t:$_NOT_
+select -assert-count 23 dffsre0/t:$_NOT_
+select -assert-count 18 dffsre1/t:$_NOT_
+select -assert-count 4 dffsr0/t:$_MUX_
+select -assert-count 4 dffsr1/t:$_MUX_
+select -assert-count 5 dffsre0/t:$_MUX_
+select -assert-count 5 dffsre1/t:$_MUX_
+select -assert-count 8 dffsr0/t:$_DFFE_PP1P_
+select -assert-count 8 dffsr1/t:$_DFFE_PP1P_
+select -assert-count 10 dffsre0/t:$_DFFE_PP1P_
+select -assert-count 10 dffsre1/t:$_DFFE_PP1P_
+select -assert-count 4 dffsr0/t:$_SR_PP_
+select -assert-count 4 dffsr1/t:$_SR_PP_
+select -assert-count 5 dffsre0/t:$_SR_PP_
+select -assert-count 5 dffsre1/t:$_SR_PP_
+select -assert-count 1 dffsr0/t:$_AND_
+select -assert-count 2 dffsr0/t:$_ANDNOT_
+select -assert-count 1 dffsr0/t:$_OR_
+select -assert-count 1 dffsre0/t:$_AND_
+select -assert-count 3 dffsre0/t:$_ANDNOT_
+select -assert-count 1 dffsre0/t:$_OR_
+select -assert-count 0 t:$_AND_ t:$_OR_ t:$_ANDNOT_ %% dffsr0/* dffsre0/* %u %n %i
+select -assert-none t:$_DFFE_PP1P_ t:$_SR_PP_ t:$_MUX_ t:$_NOT_ t:$_AND_ t:$_ANDNOT_ t:$_OR_ top/* %% %n t:* %i
+
+
+# Convert everything to DFFSRs.
+
+design -load orig
+dfflegalize -cell $_DFFSR_PPP_ 0
+
+select -assert-count 3 dffsr0/t:$_NOT_
+select -assert-count 11 dffsr1/t:$_NOT_
+select -assert-count 3 dffsre0/t:$_NOT_
+select -assert-count 13 dffsre1/t:$_NOT_
+select -assert-count 0 dffsr0/t:$_MUX_
+select -assert-count 0 dffsr1/t:$_MUX_
+select -assert-count 5 dffsre0/t:$_MUX_
+select -assert-count 5 dffsre1/t:$_MUX_
+select -assert-count 4 dffsr0/t:$_DFFSR_PPP_
+select -assert-count 4 dffsr1/t:$_DFFSR_PPP_
+select -assert-count 5 dffsre0/t:$_DFFSR_PPP_
+select -assert-count 5 dffsre1/t:$_DFFSR_PPP_
+select -assert-count 1 dffsr1/t:$_AND_
+select -assert-count 2 dffsr1/t:$_ANDNOT_
+select -assert-count 1 dffsr1/t:$_OR_
+select -assert-count 1 dffsre1/t:$_AND_
+select -assert-count 3 dffsre1/t:$_ANDNOT_
+select -assert-count 1 dffsre1/t:$_OR_
+select -assert-count 0 t:$_AND_ t:$_OR_ t:$_ANDNOT_ %% dffsr1/* dffsre1/* %u %n %i
+select -assert-none t:$_DFFSR_PPP_ t:$_MUX_ t:$_NOT_ t:$_AND_ t:$_ANDNOT_ t:$_OR_ top/* %% %n t:* %i
+
+design -load orig
+dfflegalize -cell $_DFFSR_PPP_ 1
+
+select -assert-count 11 dffsr0/t:$_NOT_
+select -assert-count 3 dffsr1/t:$_NOT_
+select -assert-count 13 dffsre0/t:$_NOT_
+select -assert-count 3 dffsre1/t:$_NOT_
+select -assert-count 0 dffsr0/t:$_MUX_
+select -assert-count 0 dffsr1j/t:$_MUX_
+select -assert-count 5 dffsre0/t:$_MUX_
+select -assert-count 5 dffsre1/t:$_MUX_
+select -assert-count 4 dffsr0/t:$_DFFSR_PPP_
+select -assert-count 4 dffsr1/t:$_DFFSR_PPP_
+select -assert-count 5 dffsre0/t:$_DFFSR_PPP_
+select -assert-count 5 dffsre1/t:$_DFFSR_PPP_
+select -assert-count 1 dffsr0/t:$_AND_
+select -assert-count 2 dffsr0/t:$_ANDNOT_
+select -assert-count 1 dffsr0/t:$_OR_
+select -assert-count 1 dffsre0/t:$_AND_
+select -assert-count 3 dffsre0/t:$_ANDNOT_
+select -assert-count 1 dffsre0/t:$_OR_
+select -assert-count 0 t:$_AND_ t:$_OR_ t:$_ANDNOT_ %% dffsr0/* dffsre0/* %u %n %i
+select -assert-none t:$_DFFSR_PPP_ t:$_MUX_ t:$_NOT_ t:$_AND_ t:$_ANDNOT_ t:$_OR_ top/* %% %n t:* %i
+
+
+# Convert everything to DFFSREs.
+
+design -load orig
+dfflegalize -cell $_DFFSRE_PPPP_ 0
+
+select -assert-count 3 dffsr0/t:$_NOT_
+select -assert-count 11 dffsr1/t:$_NOT_
+select -assert-count 4 dffsre0/t:$_NOT_
+select -assert-count 14 dffsre1/t:$_NOT_
+select -assert-count 4 dffsr0/t:$_DFFSRE_PPPP_
+select -assert-count 4 dffsr1/t:$_DFFSRE_PPPP_
+select -assert-count 5 dffsre0/t:$_DFFSRE_PPPP_
+select -assert-count 5 dffsre1/t:$_DFFSRE_PPPP_
+select -assert-count 1 dffsr1/t:$_AND_
+select -assert-count 2 dffsr1/t:$_ANDNOT_
+select -assert-count 1 dffsr1/t:$_OR_
+select -assert-count 1 dffsre1/t:$_AND_
+select -assert-count 3 dffsre1/t:$_ANDNOT_
+select -assert-count 1 dffsre1/t:$_OR_
+select -assert-count 0 t:$_AND_ t:$_OR_ t:$_ANDNOT_ %% dffsr1/* dffsre1/* %u %n %i
+select -assert-none t:$_DFFSRE_PPPP_ t:$_NOT_ t:$_AND_ t:$_ANDNOT_ t:$_OR_ top/* %% %n t:* %i
+
+design -load orig
+dfflegalize -cell $_DFFSRE_PPPP_ 1
+
+select -assert-count 11 dffsr0/t:$_NOT_
+select -assert-count 3 dffsr1/t:$_NOT_
+select -assert-count 14 dffsre0/t:$_NOT_
+select -assert-count 4 dffsre1/t:$_NOT_
+select -assert-count 4 dffsr0/t:$_DFFSRE_PPPP_
+select -assert-count 4 dffsr1/t:$_DFFSRE_PPPP_
+select -assert-count 5 dffsre0/t:$_DFFSRE_PPPP_
+select -assert-count 5 dffsre1/t:$_DFFSRE_PPPP_
+select -assert-count 1 dffsr0/t:$_AND_
+select -assert-count 2 dffsr0/t:$_ANDNOT_
+select -assert-count 1 dffsr0/t:$_OR_
+select -assert-count 1 dffsre0/t:$_AND_
+select -assert-count 3 dffsre0/t:$_ANDNOT_
+select -assert-count 1 dffsre0/t:$_OR_
+select -assert-count 0 t:$_AND_ t:$_OR_ t:$_ANDNOT_ %% dffsr0/* dffsre0/* %u %n %i
+select -assert-none t:$_DFFSRE_PPPP_ t:$_NOT_ t:$_AND_ t:$_ANDNOT_ t:$_OR_ top/* %% %n t:* %i
diff --git a/tests/techmap/dfflegalize_dlatch.ys b/tests/techmap/dfflegalize_dlatch.ys
new file mode 100644
index 000000000..8a5fad0da
--- /dev/null
+++ b/tests/techmap/dfflegalize_dlatch.ys
@@ -0,0 +1,42 @@
+read_verilog -icells <<EOT
+
+module dlatch(input E, D, output [1:0] Q);
+$_DLATCH_P_ ff0 (.E(E), .D(D), .Q(Q[0]));
+$_DLATCH_N_ ff1 (.E(E), .D(D), .Q(Q[1]));
+endmodule
+
+EOT
+
+design -save orig
+equiv_opt -assert -multiclock -map +/simcells.v dfflegalize -cell $_DLATCH_P_ x
+equiv_opt -assert -multiclock -map +/simcells.v dfflegalize -cell $_DLATCH_PP0_ x
+equiv_opt -assert -multiclock -map +/simcells.v dfflegalize -cell $_DLATCHSR_PPP_ x
+
+# Convert everything to DFFs.
+
+design -load orig
+dfflegalize -cell $_DLATCH_P_ x
+
+select -assert-count 1 t:$_NOT_
+select -assert-count 2 t:$_DLATCH_P_
+select -assert-none t:$_DLATCH_P_ t:$_NOT_ %% %n t:* %i
+
+
+# Convert everything to ADLATCHs.
+
+design -load orig
+dfflegalize -cell $_DLATCH_PP0_ x
+
+select -assert-count 1 t:$_NOT_
+select -assert-count 2 t:$_DLATCH_PP0_
+select -assert-none t:$_DLATCH_PP0_ t:$_NOT_ %% %n t:* %i
+
+
+# Convert everything to DLATCHSRs.
+
+design -load orig
+dfflegalize -cell $_DLATCHSR_PPP_ x
+
+select -assert-count 1 t:$_NOT_
+select -assert-count 2 t:$_DLATCHSR_PPP_
+select -assert-none t:$_DLATCHSR_PPP_ t:$_NOT_ %% %n t:* %i
diff --git a/tests/techmap/dfflegalize_dlatch_init.ys b/tests/techmap/dfflegalize_dlatch_init.ys
new file mode 100644
index 000000000..3ec9d9b06
--- /dev/null
+++ b/tests/techmap/dfflegalize_dlatch_init.ys
@@ -0,0 +1,82 @@
+read_verilog -icells <<EOT
+
+module dlatch(input E, D, (* init = 2'h0 *) output [1:0] Q);
+$_DLATCH_P_ ff0 (.E(E), .D(D), .Q(Q[0]));
+$_DLATCH_N_ ff1 (.E(E), .D(D), .Q(Q[1]));
+endmodule
+
+EOT
+
+design -save orig
+equiv_opt -assert -multiclock -map +/simcells.v dfflegalize -cell $_DLATCH_P_ 0
+equiv_opt -assert -multiclock -map +/simcells.v dfflegalize -cell $_DLATCH_P_ 1
+equiv_opt -assert -multiclock -map +/simcells.v dfflegalize -cell $_DLATCH_PP0_ 0
+equiv_opt -assert -multiclock -map +/simcells.v dfflegalize -cell $_DLATCH_PP0_ 1
+equiv_opt -assert -multiclock -map +/simcells.v dfflegalize -cell $_DLATCH_PP1_ 0
+equiv_opt -assert -multiclock -map +/simcells.v dfflegalize -cell $_DLATCH_PP1_ 1
+equiv_opt -assert -multiclock -map +/simcells.v dfflegalize -cell $_DLATCHSR_PPP_ 0
+equiv_opt -assert -multiclock -map +/simcells.v dfflegalize -cell $_DLATCHSR_PPP_ 1
+
+# Convert everything to DFFs.
+
+design -load orig
+dfflegalize -cell $_DLATCH_P_ 0
+
+select -assert-count 1 t:$_NOT_
+select -assert-count 2 t:$_DLATCH_P_
+select -assert-none t:$_DLATCH_P_ t:$_NOT_ %% %n t:* %i
+
+design -load orig
+dfflegalize -cell $_DLATCH_P_ 1
+
+select -assert-count 5 t:$_NOT_
+select -assert-count 2 t:$_DLATCH_P_
+select -assert-none t:$_DLATCH_P_ t:$_NOT_ %% %n t:* %i
+
+
+# Convert everything to ADLATCHs.
+
+design -load orig
+dfflegalize -cell $_DLATCH_PP0_ 0
+
+select -assert-count 1 t:$_NOT_
+select -assert-count 2 t:$_DLATCH_PP0_
+select -assert-none t:$_DLATCH_PP0_ t:$_NOT_ %% %n t:* %i
+
+design -load orig
+dfflegalize -cell $_DLATCH_PP0_ 1
+
+select -assert-count 5 t:$_NOT_
+select -assert-count 2 t:$_DLATCH_PP0_
+select -assert-none t:$_DLATCH_PP0_ t:$_NOT_ %% %n t:* %i
+
+design -load orig
+dfflegalize -cell $_DLATCH_PP1_ 0
+
+select -assert-count 1 t:$_NOT_
+select -assert-count 2 t:$_DLATCH_PP1_
+select -assert-none t:$_DLATCH_PP1_ t:$_NOT_ %% %n t:* %i
+
+design -load orig
+dfflegalize -cell $_DLATCH_PP1_ 1
+
+select -assert-count 5 t:$_NOT_
+select -assert-count 2 t:$_DLATCH_PP1_
+select -assert-none t:$_DLATCH_PP1_ t:$_NOT_ %% %n t:* %i
+
+
+# Convert everything to DLATCHSRs.
+
+design -load orig
+dfflegalize -cell $_DLATCHSR_PPP_ 0
+
+select -assert-count 1 t:$_NOT_
+select -assert-count 2 t:$_DLATCHSR_PPP_
+select -assert-none t:$_DLATCHSR_PPP_ t:$_NOT_ %% %n t:* %i
+
+design -load orig
+dfflegalize -cell $_DLATCHSR_PPP_ 1
+
+select -assert-count 5 t:$_NOT_
+select -assert-count 2 t:$_DLATCHSR_PPP_
+select -assert-none t:$_DLATCHSR_PPP_ t:$_NOT_ %% %n t:* %i
diff --git a/tests/techmap/dfflegalize_dlatchsr.ys b/tests/techmap/dfflegalize_dlatchsr.ys
new file mode 100644
index 000000000..3476c0372
--- /dev/null
+++ b/tests/techmap/dfflegalize_dlatchsr.ys
@@ -0,0 +1,37 @@
+read_verilog -icells <<EOT
+
+module dlatchsr(input E, R, S, D, output [3:0] Q);
+$_DLATCHSR_PPP_ ff0 (.E(E), .R(R), .S(S), .D(D), .Q(Q[0]));
+$_DLATCHSR_PPN_ ff1 (.E(E), .R(R), .S(S), .D(D), .Q(Q[1]));
+$_DLATCHSR_PNP_ ff2 (.E(E), .R(R), .S(S), .D(D), .Q(Q[2]));
+$_DLATCHSR_NPP_ ff3 (.E(E), .R(R), .S(S), .D(D), .Q(Q[3]));
+endmodule
+
+EOT
+
+design -save orig
+#equiv_opt -assert -multiclock -map +/simcells.v dfflegalize -cell $_DLATCH_PP0_ x -cell $_SR_PP_ x
+equiv_opt -assert -multiclock -map +/simcells.v dfflegalize -cell $_DLATCHSR_PPP_ x
+
+
+# Convert everything to ADLATCHs.
+
+design -load orig
+dfflegalize -cell $_DLATCH_PP0_ x -cell $_SR_PP_ x
+
+select -assert-count 14 t:$_NOT_
+select -assert-count 4 t:$_MUX_
+select -assert-count 8 t:$_DLATCH_PP0_
+select -assert-count 4 t:$_SR_PP_
+select -assert-none t:$_DLATCH_PP0_ t:$_SR_PP_ t:$_MUX_ t:$_NOT_ %% %n t:* %i
+
+
+# Convert everything to DLATCHSRs.
+
+design -load orig
+dfflegalize -cell $_DLATCHSR_PPP_ x
+
+select -assert-count 3 t:$_NOT_
+select -assert-count 0 t:$_MUX_
+select -assert-count 4 t:$_DLATCHSR_PPP_
+select -assert-none t:$_DLATCHSR_PPP_ t:$_MUX_ t:$_NOT_ %% %n t:* %i
diff --git a/tests/techmap/dfflegalize_dlatchsr_init.ys b/tests/techmap/dfflegalize_dlatchsr_init.ys
new file mode 100644
index 000000000..e922242d9
--- /dev/null
+++ b/tests/techmap/dfflegalize_dlatchsr_init.ys
@@ -0,0 +1,127 @@
+read_verilog -icells <<EOT
+
+module dlatchsr0(input E, R, S, D, (* init = 4'h0 *) output [3:0] Q);
+$_DLATCHSR_PPP_ ff0 (.E(E), .R(R), .S(S), .D(D), .Q(Q[0]));
+$_DLATCHSR_PPN_ ff1 (.E(E), .R(R), .S(S), .D(D), .Q(Q[1]));
+$_DLATCHSR_PNP_ ff2 (.E(E), .R(R), .S(S), .D(D), .Q(Q[2]));
+$_DLATCHSR_NPP_ ff3 (.E(E), .R(R), .S(S), .D(D), .Q(Q[3]));
+endmodule
+
+module dlatchsr1(input E, R, S, D, (* init = 4'hf *) output [3:0] Q);
+$_DLATCHSR_PPP_ ff0 (.E(E), .R(R), .S(S), .D(D), .Q(Q[0]));
+$_DLATCHSR_PPN_ ff1 (.E(E), .R(R), .S(S), .D(D), .Q(Q[1]));
+$_DLATCHSR_PNP_ ff2 (.E(E), .R(R), .S(S), .D(D), .Q(Q[2]));
+$_DLATCHSR_NPP_ ff3 (.E(E), .R(R), .S(S), .D(D), .Q(Q[3]));
+endmodule
+
+module top(input C, E, R, S, D, output [17:0] Q);
+dlatchsr0 dlatchsr0_(.E(E), .R(R), .S(S), .D(D), .Q(Q[3:0]));
+dlatchsr1 dlatchsr1_(.E(E), .R(R), .S(S), .D(D), .Q(Q[7:4]));
+endmodule
+
+EOT
+
+design -save orig
+flatten
+#equiv_opt -assert -multiclock -map +/simcells.v dfflegalize -cell $_DLATCH_PP0_ 0
+#equiv_opt -assert -multiclock -map +/simcells.v dfflegalize -cell $_DLATCH_PP0_ 1
+#equiv_opt -assert -multiclock -map +/simcells.v dfflegalize -cell $_DLATCH_PP1_ 0
+#equiv_opt -assert -multiclock -map +/simcells.v dfflegalize -cell $_DLATCH_PP1_ 1
+equiv_opt -assert -multiclock -map +/simcells.v dfflegalize -cell $_DLATCHSR_PPP_ 0
+equiv_opt -assert -multiclock -map +/simcells.v dfflegalize -cell $_DLATCHSR_PPP_ 1
+
+
+# Convert everything to ADLATCHs.
+
+design -load orig
+dfflegalize -cell $_DLATCH_PP0_ 0
+
+select -assert-count 14 dlatchsr0/t:$_NOT_
+select -assert-count 18 dlatchsr1/t:$_NOT_
+select -assert-count 4 dlatchsr0/t:$_MUX_
+select -assert-count 4 dlatchsr1/t:$_MUX_
+select -assert-count 12 dlatchsr0/t:$_DLATCH_PP0_
+select -assert-count 12 dlatchsr1/t:$_DLATCH_PP0_
+select -assert-count 1 dlatchsr1/t:$_AND_
+select -assert-count 2 dlatchsr1/t:$_ANDNOT_
+select -assert-count 1 dlatchsr1/t:$_OR_
+select -assert-count 0 t:$_AND_ t:$_OR_ t:$_ANDNOT_ %% dlatchsr1/* %n %i
+select -assert-none t:$_DLATCH_PP0_ t:$_MUX_ t:$_NOT_ t:$_AND_ t:$_ANDNOT_ t:$_OR_ top/* %% %n t:* %i
+
+design -load orig
+dfflegalize -cell $_DLATCH_PP0_ 1
+
+select -assert-count 14 dlatchsr0/t:$_NOT_
+select -assert-count 18 dlatchsr1/t:$_NOT_
+select -assert-count 4 dlatchsr0/t:$_MUX_
+select -assert-count 4 dlatchsr1/t:$_MUX_
+select -assert-count 12 dlatchsr0/t:$_DLATCH_PP0_
+select -assert-count 12 dlatchsr1/t:$_DLATCH_PP0_
+select -assert-count 1 dlatchsr1/t:$_AND_
+select -assert-count 2 dlatchsr1/t:$_ANDNOT_
+select -assert-count 1 dlatchsr1/t:$_OR_
+select -assert-count 0 t:$_AND_ t:$_OR_ t:$_ANDNOT_ %% dlatchsr1/* %n %i
+select -assert-none t:$_DLATCH_PP0_ t:$_MUX_ t:$_NOT_ t:$_AND_ t:$_ANDNOT_ t:$_OR_ top/* %% %n t:* %i
+
+design -load orig
+dfflegalize -cell $_DLATCH_PP1_ 0
+
+select -assert-count 22 dlatchsr0/t:$_NOT_
+select -assert-count 26 dlatchsr1/t:$_NOT_
+select -assert-count 4 dlatchsr0/t:$_MUX_
+select -assert-count 4 dlatchsr1/t:$_MUX_
+select -assert-count 12 dlatchsr0/t:$_DLATCH_PP1_
+select -assert-count 12 dlatchsr1/t:$_DLATCH_PP1_
+select -assert-count 1 dlatchsr1/t:$_AND_
+select -assert-count 2 dlatchsr1/t:$_ANDNOT_
+select -assert-count 1 dlatchsr1/t:$_OR_
+select -assert-count 0 t:$_AND_ t:$_OR_ t:$_ANDNOT_ %% dlatchsr1/* %n %i
+select -assert-none t:$_DLATCH_PP1_ t:$_MUX_ t:$_NOT_ t:$_AND_ t:$_ANDNOT_ t:$_OR_ top/* %% %n t:* %i
+
+design -load orig
+dfflegalize -cell $_DLATCH_PP1_ 1
+
+select -assert-count 22 dlatchsr0/t:$_NOT_
+select -assert-count 26 dlatchsr1/t:$_NOT_
+select -assert-count 4 dlatchsr0/t:$_MUX_
+select -assert-count 4 dlatchsr1/t:$_MUX_
+select -assert-count 12 dlatchsr0/t:$_DLATCH_PP1_
+select -assert-count 12 dlatchsr1/t:$_DLATCH_PP1_
+select -assert-count 1 dlatchsr1/t:$_AND_
+select -assert-count 2 dlatchsr1/t:$_ANDNOT_
+select -assert-count 1 dlatchsr1/t:$_OR_
+select -assert-count 0 t:$_AND_ t:$_OR_ t:$_ANDNOT_ %% dlatchsr1/* %n %i
+select -assert-none t:$_DLATCH_PP1_ t:$_MUX_ t:$_NOT_ t:$_AND_ t:$_ANDNOT_ t:$_OR_ top/* %% %n t:* %i
+
+
+# Convert everything to DLATCHSRs.
+
+design -load orig
+dfflegalize -cell $_DLATCHSR_PPP_ 0
+
+select -assert-count 3 dlatchsr0/t:$_NOT_
+select -assert-count 11 dlatchsr1/t:$_NOT_
+select -assert-count 0 dlatchsr0/t:$_MUX_
+select -assert-count 0 dlatchsr1/t:$_MUX_
+select -assert-count 4 dlatchsr0/t:$_DLATCHSR_PPP_
+select -assert-count 4 dlatchsr1/t:$_DLATCHSR_PPP_
+select -assert-count 1 dlatchsr1/t:$_AND_
+select -assert-count 2 dlatchsr1/t:$_ANDNOT_
+select -assert-count 1 dlatchsr1/t:$_OR_
+select -assert-count 0 t:$_AND_ t:$_OR_ t:$_ANDNOT_ %% dlatchsr1/* %n %i
+select -assert-none t:$_DLATCHSR_PPP_ t:$_MUX_ t:$_NOT_ t:$_AND_ t:$_ANDNOT_ t:$_OR_ top/* %% %n t:* %i
+
+design -load orig
+dfflegalize -cell $_DLATCHSR_PPP_ 1
+
+select -assert-count 11 dlatchsr0/t:$_NOT_
+select -assert-count 3 dlatchsr1/t:$_NOT_
+select -assert-count 0 dlatchsr0/t:$_MUX_
+select -assert-count 0 dlatchsr1j/t:$_MUX_
+select -assert-count 4 dlatchsr0/t:$_DLATCHSR_PPP_
+select -assert-count 4 dlatchsr1/t:$_DLATCHSR_PPP_
+select -assert-count 1 dlatchsr0/t:$_AND_
+select -assert-count 2 dlatchsr0/t:$_ANDNOT_
+select -assert-count 1 dlatchsr0/t:$_OR_
+select -assert-count 0 t:$_AND_ t:$_OR_ t:$_ANDNOT_ %% dlatchsr0/* %n %i
+select -assert-none t:$_DLATCHSR_PPP_ t:$_MUX_ t:$_NOT_ t:$_AND_ t:$_ANDNOT_ t:$_OR_ top/* %% %n t:* %i
diff --git a/tests/techmap/dfflegalize_inv.ys b/tests/techmap/dfflegalize_inv.ys
new file mode 100644
index 000000000..573393e7d
--- /dev/null
+++ b/tests/techmap/dfflegalize_inv.ys
@@ -0,0 +1,178 @@
+# Base test: make sure inverters are applied correctly.
+
+read_verilog -icells <<EOT
+
+module top(input C, E, R, S, D, output [64:0] Q);
+
+$_DFF_P_ ff0 (.C(C), .D(D), .Q(Q[0]));
+$_DFF_N_ ff1 (.C(C), .D(D), .Q(Q[1]));
+
+$_DFFE_PP_ ff2 (.C(C), .E(E), .D(D), .Q(Q[2]));
+$_DFFE_PN_ ff3 (.C(C), .E(E), .D(D), .Q(Q[3]));
+$_DFFE_NP_ ff4 (.C(C), .E(E), .D(D), .Q(Q[4]));
+
+$_DFF_PP0_ ff5 (.C(C), .R(R), .D(D), .Q(Q[5]));
+$_DFF_PN0_ ff6 (.C(C), .R(R), .D(D), .Q(Q[6]));
+$_DFF_NP0_ ff7 (.C(C), .R(R), .D(D), .Q(Q[7]));
+
+$_DFF_PP1_ ff8 (.C(C), .R(R), .D(D), .Q(Q[8]));
+$_DFF_PN1_ ff9 (.C(C), .R(R), .D(D), .Q(Q[9]));
+$_DFF_NP1_ ff10 (.C(C), .R(R), .D(D), .Q(Q[10]));
+
+$_DFFE_PP0P_ ff11 (.C(C), .R(R), .E(E), .D(D), .Q(Q[11]));
+$_DFFE_PP0N_ ff12 (.C(C), .R(R), .E(E), .D(D), .Q(Q[12]));
+$_DFFE_PN0P_ ff13 (.C(C), .R(R), .E(E), .D(D), .Q(Q[13]));
+$_DFFE_NP0P_ ff14 (.C(C), .R(R), .E(E), .D(D), .Q(Q[14]));
+
+$_DFFE_PP1P_ ff15 (.C(C), .R(R), .E(E), .D(D), .Q(Q[15]));
+$_DFFE_PP1N_ ff16 (.C(C), .R(R), .E(E), .D(D), .Q(Q[16]));
+$_DFFE_PN1P_ ff17 (.C(C), .R(R), .E(E), .D(D), .Q(Q[17]));
+$_DFFE_NP1P_ ff18 (.C(C), .R(R), .E(E), .D(D), .Q(Q[18]));
+
+$_DFFSR_PPP_ ff19 (.C(C), .R(R), .S(S), .D(D), .Q(Q[19]));
+$_DFFSR_PPN_ ff20 (.C(C), .R(R), .S(S), .D(D), .Q(Q[20]));
+$_DFFSR_PNP_ ff21 (.C(C), .R(R), .S(S), .D(D), .Q(Q[21]));
+$_DFFSR_NPP_ ff22 (.C(C), .R(R), .S(S), .D(D), .Q(Q[22]));
+
+$_DFFSRE_PPPP_ ff23 (.C(C), .R(R), .S(S), .E(E), .D(D), .Q(Q[23]));
+$_DFFSRE_PPPN_ ff24 (.C(C), .R(R), .S(S), .E(E), .D(D), .Q(Q[24]));
+$_DFFSRE_PPNP_ ff25 (.C(C), .R(R), .S(S), .E(E), .D(D), .Q(Q[25]));
+$_DFFSRE_PNPP_ ff26 (.C(C), .R(R), .S(S), .E(E), .D(D), .Q(Q[26]));
+$_DFFSRE_NPPP_ ff27 (.C(C), .R(R), .S(S), .E(E), .D(D), .Q(Q[27]));
+
+$_SDFF_PP0_ ff28 (.C(C), .R(R), .D(D), .Q(Q[28]));
+$_SDFF_PN0_ ff29 (.C(C), .R(R), .D(D), .Q(Q[29]));
+$_SDFF_NP0_ ff30 (.C(C), .R(R), .D(D), .Q(Q[30]));
+
+$_SDFF_PP1_ ff31 (.C(C), .R(R), .D(D), .Q(Q[31]));
+$_SDFF_PN1_ ff32 (.C(C), .R(R), .D(D), .Q(Q[32]));
+$_SDFF_NP1_ ff33 (.C(C), .R(R), .D(D), .Q(Q[33]));
+
+$_SDFFE_PP0P_ ff34 (.C(C), .R(R), .E(E), .D(D), .Q(Q[34]));
+$_SDFFE_PP0N_ ff35 (.C(C), .R(R), .E(E), .D(D), .Q(Q[35]));
+$_SDFFE_PN0P_ ff36 (.C(C), .R(R), .E(E), .D(D), .Q(Q[36]));
+$_SDFFE_NP0P_ ff37 (.C(C), .R(R), .E(E), .D(D), .Q(Q[37]));
+
+$_SDFFE_PP1P_ ff38 (.C(C), .R(R), .E(E), .D(D), .Q(Q[38]));
+$_SDFFE_PP1N_ ff39 (.C(C), .R(R), .E(E), .D(D), .Q(Q[39]));
+$_SDFFE_PN1P_ ff40 (.C(C), .R(R), .E(E), .D(D), .Q(Q[40]));
+$_SDFFE_NP1P_ ff41 (.C(C), .R(R), .E(E), .D(D), .Q(Q[41]));
+
+$_SDFFCE_PP0P_ ff42 (.C(C), .R(R), .E(E), .D(D), .Q(Q[42]));
+$_SDFFCE_PP0N_ ff43 (.C(C), .R(R), .E(E), .D(D), .Q(Q[43]));
+$_SDFFCE_PN0P_ ff44 (.C(C), .R(R), .E(E), .D(D), .Q(Q[44]));
+$_SDFFCE_NP0P_ ff45 (.C(C), .R(R), .E(E), .D(D), .Q(Q[45]));
+
+$_SDFFCE_PP1P_ ff46 (.C(C), .R(R), .E(E), .D(D), .Q(Q[46]));
+$_SDFFCE_PP1N_ ff47 (.C(C), .R(R), .E(E), .D(D), .Q(Q[47]));
+$_SDFFCE_PN1P_ ff48 (.C(C), .R(R), .E(E), .D(D), .Q(Q[48]));
+$_SDFFCE_NP1P_ ff49 (.C(C), .R(R), .E(E), .D(D), .Q(Q[49]));
+
+$_DLATCH_P_ ff50 (.E(E), .D(D), .Q(Q[50]));
+$_DLATCH_N_ ff51 (.E(E), .D(D), .Q(Q[51]));
+
+$_DLATCH_PP0_ ff52 (.E(E), .R(R), .D(D), .Q(Q[52]));
+$_DLATCH_PN0_ ff53 (.E(E), .R(R), .D(D), .Q(Q[53]));
+$_DLATCH_NP0_ ff54 (.E(E), .R(R), .D(D), .Q(Q[54]));
+
+$_DLATCH_PP1_ ff55 (.E(E), .R(R), .D(D), .Q(Q[55]));
+$_DLATCH_PN1_ ff56 (.E(E), .R(R), .D(D), .Q(Q[56]));
+$_DLATCH_NP1_ ff57 (.E(E), .R(R), .D(D), .Q(Q[57]));
+
+$_DLATCHSR_PPP_ ff58 (.E(E), .R(R), .S(S), .D(D), .Q(Q[58]));
+$_DLATCHSR_PPN_ ff59 (.E(E), .R(R), .S(S), .D(D), .Q(Q[59]));
+$_DLATCHSR_PNP_ ff60 (.E(E), .R(R), .S(S), .D(D), .Q(Q[60]));
+$_DLATCHSR_NPP_ ff61 (.E(E), .R(R), .S(S), .D(D), .Q(Q[61]));
+
+$_SR_PP_ ff62 (.R(R), .S(S), .Q(Q[62]));
+$_SR_PN_ ff63 (.R(R), .S(S), .Q(Q[63]));
+$_SR_NP_ ff64 (.R(R), .S(S), .Q(Q[64]));
+
+endmodule
+
+EOT
+
+design -save orig
+
+equiv_opt -assert -multiclock -map +/simcells.v dfflegalize -cell $_DFF_P_ x -cell $_DFFE_PP_ x -cell $_DFF_PP?_ x -cell $_DFFE_PP?P_ x -cell $_DFFSR_PPP_ x -cell $_DFFSRE_PPPP_ x -cell $_SDFF_PP?_ x -cell $_SDFFE_PP?P_ x -cell $_SDFFCE_PP?P_ x -cell $_DLATCH_P_ x -cell $_DLATCH_PP?_ x -cell $_DLATCHSR_PPP_ x -cell $_SR_PP_ x
+design -load postopt
+
+select -assert-count 46 t:$_NOT_
+select -assert-count 2 t:$_DFF_P_
+select -assert-count 3 t:$_DFFE_PP_
+select -assert-count 3 t:$_DFF_PP0_
+select -assert-count 3 t:$_DFF_PP1_
+select -assert-count 4 t:$_DFFE_PP0P_
+select -assert-count 4 t:$_DFFE_PP1P_
+select -assert-count 4 t:$_DFFSR_PPP_
+select -assert-count 5 t:$_DFFSRE_PPPP_
+select -assert-count 3 t:$_SDFF_PP0_
+select -assert-count 3 t:$_SDFF_PP1_
+select -assert-count 4 t:$_SDFFE_PP0P_
+select -assert-count 4 t:$_SDFFE_PP1P_
+select -assert-count 4 t:$_SDFFCE_PP0P_
+select -assert-count 4 t:$_SDFFCE_PP1P_
+select -assert-count 2 t:$_DLATCH_P_
+select -assert-count 3 t:$_DLATCH_PP0_
+select -assert-count 3 t:$_DLATCH_PP1_
+select -assert-count 4 t:$_DLATCHSR_PPP_
+select -assert-count 3 t:$_SR_PP_
+select -assert-none t:$_DFF_P_ t:$_DFFE_PP_ t:$_DFF_PP?_ t:$_DFFE_PP?P_ t:$_DFFSR_PPP_ t:$_DFFSRE_PPPP_ t:$_SDFF_PP?_ t:$_SDFFE_PP?P_ t:$_SDFFCE_PP?P_ t:$_DLATCH_P_ t:$_DLATCH_PP?_ t:$_DLATCHSR_PPP_ t:$_SR_PP_ t:$_NOT_ %% %n t:* %i
+
+# Now try it again, targetting the opposite cells.
+
+design -load orig
+
+equiv_opt -assert -multiclock -map +/simcells.v dfflegalize -cell $_DFF_N_ x -cell $_DFFE_NN_ x -cell $_DFF_NN?_ x -cell $_DFFE_NN?N_ x -cell $_DFFSR_NNN_ x -cell $_DFFSRE_NNNN_ x -cell $_SDFF_NN?_ x -cell $_SDFFE_NN?N_ x -cell $_SDFFCE_NN?N_ x -cell $_DLATCH_N_ x -cell $_DLATCH_NN?_ x -cell $_DLATCHSR_NNN_ x -cell $_SR_NN_ x
+design -load postopt
+
+select -assert-count 122 t:$_NOT_
+select -assert-count 2 t:$_DFF_N_
+select -assert-count 3 t:$_DFFE_NN_
+select -assert-count 3 t:$_DFF_NN0_
+select -assert-count 3 t:$_DFF_NN1_
+select -assert-count 4 t:$_DFFE_NN0N_
+select -assert-count 4 t:$_DFFE_NN1N_
+select -assert-count 4 t:$_DFFSR_NNN_
+select -assert-count 5 t:$_DFFSRE_NNNN_
+select -assert-count 3 t:$_SDFF_NN0_
+select -assert-count 3 t:$_SDFF_NN1_
+select -assert-count 4 t:$_SDFFE_NN0N_
+select -assert-count 4 t:$_SDFFE_NN1N_
+select -assert-count 4 t:$_SDFFCE_NN0N_
+select -assert-count 4 t:$_SDFFCE_NN1N_
+select -assert-count 2 t:$_DLATCH_N_
+select -assert-count 3 t:$_DLATCH_NN0_
+select -assert-count 3 t:$_DLATCH_NN1_
+select -assert-count 4 t:$_DLATCHSR_NNN_
+select -assert-count 3 t:$_SR_NN_
+select -assert-none t:$_DFF_N_ t:$_DFFE_NN_ t:$_DFF_NN?_ t:$_DFFE_NN?N_ t:$_DFFSR_NNN_ t:$_DFFSRE_NNNN_ t:$_SDFF_NN?_ t:$_SDFFE_NN?N_ t:$_SDFFCE_NN?N_ t:$_DLATCH_N_ t:$_DLATCH_NN?_ t:$_DLATCHSR_NNN_ t:$_SR_NN_ t:$_NOT_ %% %n t:* %i
+
+
+# Second test: make sure set/reset/enable are inverted before clock.
+
+design -reset
+
+read_verilog -icells <<EOT
+
+module top(input C, E, R, S, D, output [3:0] Q);
+
+$_DFFSRE_PPPP_ ff0 (.C(C), .E(E), .R(R), .S(S), .D(D), .Q(Q[0]));
+$_DFFSRE_NPPP_ ff1 (.C(C), .E(E), .R(R), .S(S), .D(D), .Q(Q[1]));
+$_DFFSRE_PNNN_ ff2 (.C(C), .E(E), .R(R), .S(S), .D(D), .Q(Q[2]));
+$_DFFSRE_NNNN_ ff3 (.C(C), .E(E), .R(R), .S(S), .D(D), .Q(Q[3]));
+
+endmodule
+
+EOT
+
+equiv_opt -assert -multiclock -map +/simcells.v dfflegalize -cell $_DFFSRE_NNNN_ x -cell $_DFFSRE_PPPP_ x
+design -load postopt
+
+select -assert-count 6 t:$_NOT_
+select -assert-count 2 t:$_DFFSRE_PPPP_
+select -assert-count 2 t:$_DFFSRE_NNNN_
+select -assert-count 1 t:$_DFFSRE_PPPP_ n:ff0 %i
+select -assert-count 1 t:$_DFFSRE_NNNN_ n:ff1 %i
+select -assert-count 1 t:$_DFFSRE_PPPP_ n:ff2 %i
+select -assert-count 1 t:$_DFFSRE_NNNN_ n:ff3 %i
diff --git a/tests/techmap/dfflegalize_mince.ys b/tests/techmap/dfflegalize_mince.ys
new file mode 100644
index 000000000..75069541b
--- /dev/null
+++ b/tests/techmap/dfflegalize_mince.ys
@@ -0,0 +1,53 @@
+read_verilog -icells <<EOT
+
+module top(input D, C, R, S, input [4:0] E, output [15:0] Q);
+$_DFFE_PP_ ff0(.D(D), .C(C), .E(E[0]), .Q(Q[0]));
+$_DFFE_PP0P_ ff1(.D(D), .C(C), .E(E[0]), .R(R), .Q(Q[1]));
+$_DFFE_PP1P_ ff2(.D(D), .C(C), .E(E[0]), .R(R), .Q(Q[2]));
+$_SDFFE_PP0P_ ff3(.D(D), .C(C), .E(E[0]), .R(R), .Q(Q[3]));
+$_SDFFE_PP1P_ ff4(.D(D), .C(C), .E(E[0]), .R(R), .Q(Q[4]));
+$_SDFFCE_PP0P_ ff5(.D(D), .C(C), .E(E[0]), .R(R), .Q(Q[5]));
+$_SDFFCE_PP1P_ ff6(.D(D), .C(C), .E(E[0]), .R(R), .Q(Q[6]));
+$_DFFSRE_PPPP_ ff7(.D(D), .C(C), .E(E[0]), .R(R), .S(S), .Q(Q[7]));
+$_DFFE_PP_ ff8(.D(D), .C(C), .E(E[1]), .Q(Q[8]));
+$_DFFE_PP0P_ ff9(.D(D), .C(C), .E(E[1]), .R(R), .Q(Q[9]));
+$_DFFE_PP1P_ ff10(.D(D), .C(C), .E(E[2]), .R(R), .Q(Q[10]));
+$_SDFFE_PP0P_ ff11(.D(D), .C(C), .E(E[2]), .R(R), .Q(Q[11]));
+$_SDFFE_PP1P_ ff12(.D(D), .C(C), .E(E[3]), .R(R), .Q(Q[12]));
+$_SDFFCE_PP0P_ ff13(.D(D), .C(C), .E(E[3]), .R(R), .Q(Q[13]));
+$_SDFFCE_PP1P_ ff14(.D(D), .C(C), .E(E[4]), .R(R), .Q(Q[14]));
+$_DFFSRE_PPPP_ ff15(.D(D), .C(C), .E(E[4]), .R(R), .S(S), .Q(Q[15]));
+endmodule
+
+EOT
+
+design -save orig
+equiv_opt -assert -multiclock -map +/simcells.v dfflegalize -cell $_DFFE_PP_ x -cell $_DFFE_PP?P_ x -cell $_DFFSRE_PPPP_ x -cell $_SDFFE_PP?P_ x -cell $_SDFFCE_PP?P_ x -mince 3
+design -load postopt
+
+select -assert-count 4 t:$_DFFE_PP_
+select -assert-count 2 t:$_DFFE_PP0P_
+select -assert-count 2 t:$_DFFE_PP1P_
+select -assert-count 2 t:$_SDFFE_PP0P_
+select -assert-count 2 t:$_SDFFE_PP1P_
+select -assert-count 1 t:$_SDFFCE_PP0P_
+select -assert-count 1 t:$_SDFFCE_PP1P_
+select -assert-count 2 t:$_DFFSRE_PPPP_
+select -assert-count 10 t:$_MUX_
+select -assert-count 0 n:ff0 %ci %ci t:$_MUX_ %i
+select -assert-count 0 n:ff1 %ci %ci t:$_MUX_ %i
+select -assert-count 0 n:ff2 %ci %ci t:$_MUX_ %i
+select -assert-count 0 n:ff3 %ci %ci t:$_MUX_ %i
+select -assert-count 0 n:ff4 %ci %ci t:$_MUX_ %i
+select -assert-count 0 n:ff5 %ci %ci t:$_MUX_ %i
+select -assert-count 0 n:ff6 %ci %ci t:$_MUX_ %i
+select -assert-count 0 n:ff7 %ci %ci t:$_MUX_ %i
+select -assert-count 1 n:ff8 %ci %ci t:$_MUX_ %i
+select -assert-count 1 n:ff9 %ci %ci t:$_MUX_ %i
+select -assert-count 1 n:ff10 %ci %ci t:$_MUX_ %i
+select -assert-count 1 n:ff11 %ci %ci t:$_MUX_ %i
+select -assert-count 1 n:ff12 %ci %ci t:$_MUX_ %i
+select -assert-count 1 n:ff13 %ci %ci t:$_MUX_ %i
+select -assert-count 1 n:ff14 %ci %ci t:$_MUX_ %i
+select -assert-count 1 n:ff15 %ci %ci t:$_MUX_ %i
+select -assert-none n:ff* t:$_MUX_ %% %n t:* %i
diff --git a/tests/techmap/dfflegalize_minsrst.ys b/tests/techmap/dfflegalize_minsrst.ys
new file mode 100644
index 000000000..b9bc3f1b9
--- /dev/null
+++ b/tests/techmap/dfflegalize_minsrst.ys
@@ -0,0 +1,43 @@
+read_verilog -icells <<EOT
+
+module top(input D, C, E, input [3:0] R, output [11:0] Q);
+$_SDFF_PP0_ ff0(.D(D), .C(C), .R(R[0]), .Q(Q[0]));
+$_SDFF_PP1_ ff1(.D(D), .C(C), .R(R[0]), .Q(Q[1]));
+$_SDFFE_PP0P_ ff2(.D(D), .C(C), .R(R[0]), .E(E), .Q(Q[2]));
+$_SDFFE_PP1P_ ff3(.D(D), .C(C), .R(R[0]), .E(E), .Q(Q[3]));
+$_SDFFCE_PP0P_ ff4(.D(D), .C(C), .R(R[0]), .E(E), .Q(Q[4]));
+$_SDFFCE_PP1P_ ff5(.D(D), .C(C), .R(R[0]), .E(E), .Q(Q[5]));
+$_SDFF_PP0_ ff6(.D(D), .C(C), .R(R[1]), .Q(Q[6]));
+$_SDFF_PP1_ ff7(.D(D), .C(C), .R(R[1]), .Q(Q[7]));
+$_SDFFE_PP0P_ ff8(.D(D), .C(C), .R(R[2]), .E(E), .Q(Q[8]));
+$_SDFFE_PP1P_ ff9(.D(D), .C(C), .R(R[2]), .E(E), .Q(Q[9]));
+$_SDFFCE_PP0P_ ff10(.D(D), .C(C), .R(R[3]), .E(E), .Q(Q[10]));
+$_SDFFCE_PP1P_ ff11(.D(D), .C(C), .R(R[3]), .E(E), .Q(Q[11]));
+endmodule
+
+EOT
+
+design -save orig
+equiv_opt -assert -multiclock -map +/simcells.v dfflegalize -cell $_SDFF_PP?_ x -cell $_SDFFE_PP?P_ x -cell $_SDFFCE_PP?P_ x -minsrst 3
+design -load postopt
+
+select -assert-count 5 t:$_SDFF_PP0_
+select -assert-count 1 t:$_SDFF_PP1_
+select -assert-count 3 t:$_SDFFE_PP0P_
+select -assert-count 1 t:$_SDFFE_PP1P_
+select -assert-count 1 t:$_SDFFCE_PP0P_
+select -assert-count 1 t:$_SDFFCE_PP1P_
+select -assert-count 8 t:$_MUX_
+select -assert-count 0 n:ff0 %ci %ci t:$_MUX_ %i
+select -assert-count 0 n:ff1 %ci %ci t:$_MUX_ %i
+select -assert-count 0 n:ff2 %ci %ci t:$_MUX_ %i
+select -assert-count 0 n:ff3 %ci %ci t:$_MUX_ %i
+select -assert-count 0 n:ff4 %ci %ci t:$_MUX_ %i
+select -assert-count 0 n:ff5 %ci %ci t:$_MUX_ %i
+select -assert-count 1 n:ff6 %ci %ci t:$_MUX_ %i
+select -assert-count 1 n:ff7 %ci %ci t:$_MUX_ %i
+select -assert-count 1 n:ff8 %ci %ci t:$_MUX_ %i
+select -assert-count 1 n:ff9 %ci %ci t:$_MUX_ %i
+select -assert-count 1 n:ff10 %ci %ci t:$_MUX_ %i
+select -assert-count 1 n:ff11 %ci %ci t:$_MUX_ %i
+select -assert-none n:ff* t:$_MUX_ %% %n t:* %i
diff --git a/tests/techmap/dfflegalize_sr.ys b/tests/techmap/dfflegalize_sr.ys
new file mode 100644
index 000000000..a75068ae0
--- /dev/null
+++ b/tests/techmap/dfflegalize_sr.ys
@@ -0,0 +1,74 @@
+read_verilog -icells <<EOT
+
+module sr(input R, S, output [2:0] Q);
+$_SR_PP_ ff0 (.R(R), .S(S), .Q(Q[0]));
+$_SR_PN_ ff1 (.R(R), .S(S), .Q(Q[1]));
+$_SR_NP_ ff2 (.R(R), .S(S), .Q(Q[2]));
+endmodule
+
+EOT
+
+design -save orig
+equiv_opt -assert -multiclock -map +/simcells.v dfflegalize -cell $_SR_PP_ x
+equiv_opt -assert -multiclock -map +/simcells.v dfflegalize -cell $_DLATCH_PP0_ x
+equiv_opt -assert -multiclock -map +/simcells.v dfflegalize -cell $_DLATCH_PP1_ x
+equiv_opt -assert -multiclock -map +/simcells.v dfflegalize -cell $_DLATCHSR_PPP_ x
+equiv_opt -assert -multiclock -map +/simcells.v dfflegalize -cell $_DFFSR_PPP_ x
+equiv_opt -assert -multiclock -map +/simcells.v dfflegalize -cell $_DFFSRE_PPPP_ x
+
+
+# Convert everything to SRs.
+
+design -load orig
+dfflegalize -cell $_SR_PP_ x
+
+select -assert-count 2 t:$_NOT_
+select -assert-count 3 t:$_SR_PP_
+select -assert-none t:$_SR_PP_ t:$_NOT_ %% %n t:* %i
+
+
+# Convert everything to ADLATCHs.
+
+design -load orig
+dfflegalize -cell $_DLATCH_PP0_ x
+
+select -assert-count 2 t:$_NOT_
+select -assert-count 3 t:$_DLATCH_PP0_
+select -assert-none t:$_DLATCH_PP0_ t:$_NOT_ %% %n t:* %i
+
+design -load orig
+dfflegalize -cell $_DLATCH_PP1_ x
+
+select -assert-count 8 t:$_NOT_
+select -assert-count 3 t:$_DLATCH_PP1_
+select -assert-none t:$_DLATCH_PP1_ t:$_NOT_ %% %n t:* %i
+
+
+# Convert everything to DLATCHSRs.
+
+design -load orig
+dfflegalize -cell $_DLATCHSR_PPP_ x
+
+select -assert-count 2 t:$_NOT_
+select -assert-count 3 t:$_DLATCHSR_PPP_
+select -assert-none t:$_DLATCHSR_PPP_ t:$_NOT_ %% %n t:* %i
+
+
+# Convert everything to DFFSRs.
+
+design -load orig
+dfflegalize -cell $_DFFSR_PPP_ x
+
+select -assert-count 2 t:$_NOT_
+select -assert-count 3 t:$_DFFSR_PPP_
+select -assert-none t:$_DFFSR_PPP_ t:$_NOT_ %% %n t:* %i
+
+
+# Convert everything to DFFSREs.
+
+design -load orig
+dfflegalize -cell $_DFFSRE_PPPP_ x
+
+select -assert-count 2 t:$_NOT_
+select -assert-count 3 t:$_DFFSRE_PPPP_
+select -assert-none t:$_DFFSRE_PPPP_ t:$_NOT_ %% %n t:* %i
diff --git a/tests/techmap/dfflegalize_sr_init.ys b/tests/techmap/dfflegalize_sr_init.ys
new file mode 100644
index 000000000..39bfdcdcf
--- /dev/null
+++ b/tests/techmap/dfflegalize_sr_init.ys
@@ -0,0 +1,230 @@
+read_verilog -icells <<EOT
+
+module sr0(input R, S, (* init = 3'h0 *) output [2:0] Q);
+$_SR_PP_ ff0 (.R(R), .S(S), .Q(Q[0]));
+$_SR_PN_ ff1 (.R(R), .S(S), .Q(Q[1]));
+$_SR_NP_ ff2 (.R(R), .S(S), .Q(Q[2]));
+endmodule
+
+module sr1(input R, S, (* init = 3'h7 *) output [2:0] Q);
+$_SR_PP_ ff0 (.R(R), .S(S), .Q(Q[0]));
+$_SR_PN_ ff1 (.R(R), .S(S), .Q(Q[1]));
+$_SR_NP_ ff2 (.R(R), .S(S), .Q(Q[2]));
+endmodule
+
+module top(input C, E, R, D, output [5:0] Q);
+sr0 sr0_(.S(S), .R(R), .Q(Q[2:0]));
+sr1 sr1_(.S(S), .R(R), .Q(Q[5:3]));
+endmodule
+
+EOT
+
+design -save orig
+flatten
+equiv_opt -assert -multiclock -map +/simcells.v dfflegalize -cell $_SR_PP_ 0
+equiv_opt -assert -multiclock -map +/simcells.v dfflegalize -cell $_SR_PP_ 1
+equiv_opt -assert -multiclock -map +/simcells.v dfflegalize -cell $_DLATCH_PP0_ 0
+equiv_opt -assert -multiclock -map +/simcells.v dfflegalize -cell $_DLATCH_PP0_ 1
+equiv_opt -assert -multiclock -map +/simcells.v dfflegalize -cell $_DLATCH_PP1_ 0
+equiv_opt -assert -multiclock -map +/simcells.v dfflegalize -cell $_DLATCH_PP1_ 1
+equiv_opt -assert -multiclock -map +/simcells.v dfflegalize -cell $_DLATCHSR_PPP_ 0
+equiv_opt -assert -multiclock -map +/simcells.v dfflegalize -cell $_DLATCHSR_PPP_ 1
+equiv_opt -assert -multiclock -map +/simcells.v dfflegalize -cell $_DFFSR_PPP_ 0
+equiv_opt -assert -multiclock -map +/simcells.v dfflegalize -cell $_DFFSR_PPP_ 1
+equiv_opt -assert -multiclock -map +/simcells.v dfflegalize -cell $_DFFSRE_PPPP_ 0
+equiv_opt -assert -multiclock -map +/simcells.v dfflegalize -cell $_DFFSRE_PPPP_ 1
+
+
+# Convert everything to SRs.
+
+design -load orig
+dfflegalize -cell $_SR_PP_ 0
+
+select -assert-count 2 sr0/t:$_NOT_
+select -assert-count 5 sr1/t:$_NOT_
+select -assert-count 3 sr0/t:$_SR_PP_
+select -assert-count 3 sr1/t:$_SR_PP_
+select -assert-count 0 sr0/t:$_ANDNOT_
+select -assert-count 1 sr1/t:$_ANDNOT_
+select -assert-count 0 sr0/t:$_AND_
+select -assert-count 1 sr1/t:$_AND_
+select -assert-count 0 sr0/t:$_OR_
+select -assert-count 1 sr1/t:$_OR_
+select -assert-none t:$_SR_PP_ t:$_NOT_ t:$_ANDNOT_ t:$_OR_ t:$_AND_ top/* %% %n t:* %i
+
+design -load orig
+dfflegalize -cell $_SR_PP_ 1
+
+select -assert-count 5 sr0/t:$_NOT_
+select -assert-count 2 sr1/t:$_NOT_
+select -assert-count 3 sr0/t:$_SR_PP_
+select -assert-count 3 sr1/t:$_SR_PP_
+select -assert-count 1 sr0/t:$_ANDNOT_
+select -assert-count 0 sr1/t:$_ANDNOT_
+select -assert-count 1 sr0/t:$_AND_
+select -assert-count 0 sr1/t:$_AND_
+select -assert-count 1 sr0/t:$_OR_
+select -assert-count 0 sr1/t:$_OR_
+select -assert-none t:$_SR_PP_ t:$_NOT_ t:$_ANDNOT_ t:$_OR_ t:$_AND_ top/* %% %n t:* %i
+
+
+# Convert everything to ADLATCHs.
+
+design -load orig
+dfflegalize -cell $_DLATCH_PP0_ 0
+
+select -assert-count 2 sr0/t:$_NOT_
+select -assert-count 5 sr1/t:$_NOT_
+select -assert-count 3 sr0/t:$_DLATCH_PP0_
+select -assert-count 3 sr1/t:$_DLATCH_PP0_
+select -assert-count 0 sr0/t:$_ANDNOT_
+select -assert-count 1 sr1/t:$_ANDNOT_
+select -assert-count 0 sr0/t:$_AND_
+select -assert-count 1 sr1/t:$_AND_
+select -assert-count 0 sr0/t:$_OR_
+select -assert-count 1 sr1/t:$_OR_
+select -assert-none t:$_DLATCH_PP0_ t:$_NOT_ t:$_ANDNOT_ t:$_OR_ t:$_AND_ top/* %% %n t:* %i
+
+design -load orig
+dfflegalize -cell $_DLATCH_PP0_ 1
+
+select -assert-count 5 sr0/t:$_NOT_
+select -assert-count 2 sr1/t:$_NOT_
+select -assert-count 3 sr0/t:$_DLATCH_PP0_
+select -assert-count 3 sr1/t:$_DLATCH_PP0_
+select -assert-count 1 sr0/t:$_ANDNOT_
+select -assert-count 0 sr1/t:$_ANDNOT_
+select -assert-count 1 sr0/t:$_AND_
+select -assert-count 0 sr1/t:$_AND_
+select -assert-count 1 sr0/t:$_OR_
+select -assert-count 0 sr1/t:$_OR_
+select -assert-none t:$_DLATCH_PP0_ t:$_NOT_ t:$_ANDNOT_ t:$_OR_ t:$_AND_ top/* %% %n t:* %i
+
+design -load orig
+dfflegalize -cell $_DLATCH_PP1_ 0
+
+select -assert-count 11 sr0/t:$_NOT_
+select -assert-count 8 sr1/t:$_NOT_
+select -assert-count 3 sr0/t:$_DLATCH_PP1_
+select -assert-count 3 sr1/t:$_DLATCH_PP1_
+select -assert-count 1 sr0/t:$_ANDNOT_
+select -assert-count 0 sr1/t:$_ANDNOT_
+select -assert-count 1 sr0/t:$_AND_
+select -assert-count 0 sr1/t:$_AND_
+select -assert-count 1 sr0/t:$_OR_
+select -assert-count 0 sr1/t:$_OR_
+select -assert-none t:$_DLATCH_PP1_ t:$_NOT_ t:$_ANDNOT_ t:$_OR_ t:$_AND_ top/* %% %n t:* %i
+
+design -load orig
+dfflegalize -cell $_DLATCH_PP1_ 1
+
+select -assert-count 8 sr0/t:$_NOT_
+select -assert-count 11 sr1/t:$_NOT_
+select -assert-count 3 sr0/t:$_DLATCH_PP1_
+select -assert-count 3 sr1/t:$_DLATCH_PP1_
+select -assert-count 0 sr0/t:$_ANDNOT_
+select -assert-count 1 sr1/t:$_ANDNOT_
+select -assert-count 0 sr0/t:$_AND_
+select -assert-count 1 sr1/t:$_AND_
+select -assert-count 0 sr0/t:$_OR_
+select -assert-count 1 sr1/t:$_OR_
+select -assert-none t:$_DLATCH_PP1_ t:$_NOT_ t:$_ANDNOT_ t:$_OR_ t:$_AND_ top/* %% %n t:* %i
+
+
+# Convert everything to DLATCHSRs.
+
+design -load orig
+dfflegalize -cell $_DLATCHSR_PPP_ 0
+
+select -assert-count 2 sr0/t:$_NOT_
+select -assert-count 5 sr1/t:$_NOT_
+select -assert-count 3 sr0/t:$_DLATCHSR_PPP_
+select -assert-count 3 sr1/t:$_DLATCHSR_PPP_
+select -assert-count 0 sr0/t:$_ANDNOT_
+select -assert-count 1 sr1/t:$_ANDNOT_
+select -assert-count 0 sr0/t:$_AND_
+select -assert-count 1 sr1/t:$_AND_
+select -assert-count 0 sr0/t:$_OR_
+select -assert-count 1 sr1/t:$_OR_
+select -assert-none t:$_DLATCHSR_PPP_ t:$_NOT_ t:$_ANDNOT_ t:$_OR_ t:$_AND_ top/* %% %n t:* %i
+
+design -load orig
+dfflegalize -cell $_DLATCHSR_PPP_ 1
+
+select -assert-count 5 sr0/t:$_NOT_
+select -assert-count 2 sr1/t:$_NOT_
+select -assert-count 3 sr0/t:$_DLATCHSR_PPP_
+select -assert-count 3 sr1/t:$_DLATCHSR_PPP_
+select -assert-count 1 sr0/t:$_ANDNOT_
+select -assert-count 0 sr1/t:$_ANDNOT_
+select -assert-count 1 sr0/t:$_AND_
+select -assert-count 0 sr1/t:$_AND_
+select -assert-count 1 sr0/t:$_OR_
+select -assert-count 0 sr1/t:$_OR_
+select -assert-none t:$_DLATCHSR_PPP_ t:$_NOT_ t:$_ANDNOT_ t:$_OR_ t:$_AND_ top/* %% %n t:* %i
+
+
+# Convert everything to DFFSRs.
+
+design -load orig
+dfflegalize -cell $_DFFSR_PPP_ 0
+
+select -assert-count 2 sr0/t:$_NOT_
+select -assert-count 5 sr1/t:$_NOT_
+select -assert-count 3 sr0/t:$_DFFSR_PPP_
+select -assert-count 3 sr1/t:$_DFFSR_PPP_
+select -assert-count 0 sr0/t:$_ANDNOT_
+select -assert-count 1 sr1/t:$_ANDNOT_
+select -assert-count 0 sr0/t:$_AND_
+select -assert-count 1 sr1/t:$_AND_
+select -assert-count 0 sr0/t:$_OR_
+select -assert-count 1 sr1/t:$_OR_
+select -assert-none t:$_DFFSR_PPP_ t:$_NOT_ t:$_ANDNOT_ t:$_OR_ t:$_AND_ top/* %% %n t:* %i
+
+design -load orig
+dfflegalize -cell $_DFFSR_PPP_ 1
+
+select -assert-count 5 sr0/t:$_NOT_
+select -assert-count 2 sr1/t:$_NOT_
+select -assert-count 3 sr0/t:$_DFFSR_PPP_
+select -assert-count 3 sr1/t:$_DFFSR_PPP_
+select -assert-count 1 sr0/t:$_ANDNOT_
+select -assert-count 0 sr1/t:$_ANDNOT_
+select -assert-count 1 sr0/t:$_AND_
+select -assert-count 0 sr1/t:$_AND_
+select -assert-count 1 sr0/t:$_OR_
+select -assert-count 0 sr1/t:$_OR_
+select -assert-none t:$_DFFSR_PPP_ t:$_NOT_ t:$_ANDNOT_ t:$_OR_ t:$_AND_ top/* %% %n t:* %i
+
+
+# Convert everything to DFFSREs.
+
+design -load orig
+dfflegalize -cell $_DFFSRE_PPPP_ 0
+
+select -assert-count 2 sr0/t:$_NOT_
+select -assert-count 5 sr1/t:$_NOT_
+select -assert-count 3 sr0/t:$_DFFSRE_PPPP_
+select -assert-count 3 sr1/t:$_DFFSRE_PPPP_
+select -assert-count 0 sr0/t:$_ANDNOT_
+select -assert-count 1 sr1/t:$_ANDNOT_
+select -assert-count 0 sr0/t:$_AND_
+select -assert-count 1 sr1/t:$_AND_
+select -assert-count 0 sr0/t:$_OR_
+select -assert-count 1 sr1/t:$_OR_
+select -assert-none t:$_DFFSRE_PPPP_ t:$_NOT_ t:$_ANDNOT_ t:$_OR_ t:$_AND_ top/* %% %n t:* %i
+
+design -load orig
+dfflegalize -cell $_DFFSRE_PPPP_ 1
+
+select -assert-count 5 sr0/t:$_NOT_
+select -assert-count 2 sr1/t:$_NOT_
+select -assert-count 3 sr0/t:$_DFFSRE_PPPP_
+select -assert-count 3 sr1/t:$_DFFSRE_PPPP_
+select -assert-count 1 sr0/t:$_ANDNOT_
+select -assert-count 0 sr1/t:$_ANDNOT_
+select -assert-count 1 sr0/t:$_AND_
+select -assert-count 0 sr1/t:$_AND_
+select -assert-count 1 sr0/t:$_OR_
+select -assert-count 0 sr1/t:$_OR_
+select -assert-none t:$_DFFSRE_PPPP_ t:$_NOT_ t:$_ANDNOT_ t:$_OR_ t:$_AND_ top/* %% %n t:* %i
diff --git a/tests/techmap/zinit.ys b/tests/techmap/zinit.ys
index d0e41b4d2..3527840b9 100644
--- a/tests/techmap/zinit.ys
+++ b/tests/techmap/zinit.ys
@@ -61,32 +61,32 @@ design -reset
read_verilog -icells <<EOT
module top(input C, R, D, E, (* init = {24{1'b1}} *) output [23:0] Q);
-$__DFFE_NN0 dff0 (.C(C), .D(D), .E(E), .R(R), .Q(Q[0]));
-$__DFFE_NN1 dff1 (.C(C), .D(D), .E(E), .R(R), .Q(Q[1]));
-$__DFFE_NP0 dff2 (.C(C), .D(D), .E(E), .R(R), .Q(Q[2]));
-$__DFFE_NP1 dff3 (.C(C), .D(D), .E(E), .R(R), .Q(Q[3]));
-$__DFFE_PN0 dff4 (.C(C), .D(D), .E(E), .R(R), .Q(Q[4]));
-$__DFFE_PN1 dff5 (.C(C), .D(D), .E(E), .R(R), .Q(Q[5]));
-$__DFFE_PP0 dff6 (.C(C), .D(D), .E(E), .R(R), .Q(Q[6]));
-$__DFFE_PP1 dff7 (.C(C), .D(D), .E(E), .R(R), .Q(Q[7]));
-
-$__DFFS_NN0_ dff8 (.C(C), .D(D[0]), .R(R), .Q(Q[8]));
-$__DFFS_NN1_ dff9 (.C(C), .D(D[0]), .R(R), .Q(Q[9]));
-$__DFFS_NP0_ dff10(.C(C), .D(D[0]), .R(R), .Q(Q[10]));
-$__DFFS_NP1_ dff11(.C(C), .D(D[0]), .R(R), .Q(Q[11]));
-$__DFFS_PN0_ dff12(.C(C), .D(D[0]), .R(R), .Q(Q[12]));
-$__DFFS_PN1_ dff13(.C(C), .D(D[0]), .R(R), .Q(Q[13]));
-$__DFFS_PP0_ dff14(.C(C), .D(D[0]), .R(R), .Q(Q[14]));
-$__DFFS_PP1_ dff15(.C(C), .D(D[0]), .R(R), .Q(Q[15]));
-
-$__DFFSE_NN0 dff16(.C(C), .D(D[0]),.E(E), .R(R), .Q(Q[16]));
-$__DFFSE_NN1 dff17(.C(C), .D(D[0]),.E(E), .R(R), .Q(Q[17]));
-$__DFFSE_NP0 dff18(.C(C), .D(D[0]),.E(E), .R(R), .Q(Q[18]));
-$__DFFSE_NP1 dff19(.C(C), .D(D[0]),.E(E), .R(R), .Q(Q[19]));
-$__DFFSE_PN0 dff20(.C(C), .D(D[0]),.E(E), .R(R), .Q(Q[20]));
-$__DFFSE_PN1 dff21(.C(C), .D(D[0]),.E(E), .R(R), .Q(Q[21]));
-$__DFFSE_PP0 dff22(.C(C), .D(D[0]),.E(E), .R(R), .Q(Q[22]));
-$__DFFSE_PP1 dff23(.C(C), .D(D[0]),.E(E), .R(R), .Q(Q[23]));
+$_DFFE_NN0P_ dff0 (.C(C), .D(D), .E(E), .R(R), .Q(Q[0]));
+$_DFFE_NN1P_ dff1 (.C(C), .D(D), .E(E), .R(R), .Q(Q[1]));
+$_DFFE_NP0P_ dff2 (.C(C), .D(D), .E(E), .R(R), .Q(Q[2]));
+$_DFFE_NP1P_ dff3 (.C(C), .D(D), .E(E), .R(R), .Q(Q[3]));
+$_DFFE_PN0P_ dff4 (.C(C), .D(D), .E(E), .R(R), .Q(Q[4]));
+$_DFFE_PN1P_ dff5 (.C(C), .D(D), .E(E), .R(R), .Q(Q[5]));
+$_DFFE_PP0P_ dff6 (.C(C), .D(D), .E(E), .R(R), .Q(Q[6]));
+$_DFFE_PP1P_ dff7 (.C(C), .D(D), .E(E), .R(R), .Q(Q[7]));
+
+$_SDFF_NN0_ dff8 (.C(C), .D(D[0]), .R(R), .Q(Q[8]));
+$_SDFF_NN1_ dff9 (.C(C), .D(D[0]), .R(R), .Q(Q[9]));
+$_SDFF_NP0_ dff10(.C(C), .D(D[0]), .R(R), .Q(Q[10]));
+$_SDFF_NP1_ dff11(.C(C), .D(D[0]), .R(R), .Q(Q[11]));
+$_SDFF_PN0_ dff12(.C(C), .D(D[0]), .R(R), .Q(Q[12]));
+$_SDFF_PN1_ dff13(.C(C), .D(D[0]), .R(R), .Q(Q[13]));
+$_SDFF_PP0_ dff14(.C(C), .D(D[0]), .R(R), .Q(Q[14]));
+$_SDFF_PP1_ dff15(.C(C), .D(D[0]), .R(R), .Q(Q[15]));
+
+$_SDFFE_NN0P_ dff16(.C(C), .D(D[0]),.E(E), .R(R), .Q(Q[16]));
+$_SDFFE_NN1P_ dff17(.C(C), .D(D[0]),.E(E), .R(R), .Q(Q[17]));
+$_SDFFE_NP0P_ dff18(.C(C), .D(D[0]),.E(E), .R(R), .Q(Q[18]));
+$_SDFFE_NP1P_ dff19(.C(C), .D(D[0]),.E(E), .R(R), .Q(Q[19]));
+$_SDFFE_PN0P_ dff20(.C(C), .D(D[0]),.E(E), .R(R), .Q(Q[20]));
+$_SDFFE_PN1P_ dff21(.C(C), .D(D[0]),.E(E), .R(R), .Q(Q[21]));
+$_SDFFE_PP0P_ dff22(.C(C), .D(D[0]),.E(E), .R(R), .Q(Q[22]));
+$_SDFFE_PP1P_ dff23(.C(C), .D(D[0]),.E(E), .R(R), .Q(Q[23]));
endmodule
EOT
@@ -96,44 +96,44 @@ zinit
select -assert-count 48 t:$_NOT_
select -assert-count 1 w:Q a:init=24'bx %i
-select -assert-count 4 c:dff0 c:dff2 c:dff4 c:dff6 %% t:$__DFFE_??1 %i
-select -assert-count 4 c:dff1 c:dff3 c:dff5 c:dff7 %% t:$__DFFE_??0 %i
-select -assert-count 4 c:dff8 c:dff10 c:dff12 c:dff14 %% t:$__DFFS_??1_ %i
-select -assert-count 4 c:dff9 c:dff11 c:dff13 c:dff15 %% t:$__DFFS_??0_ %i
-select -assert-count 4 c:dff16 c:dff18 c:dff20 c:dff22 %% t:$__DFFSE_??1 %i
-select -assert-count 4 c:dff17 c:dff19 c:dff21 c:dff23 %% t:$__DFFSE_??0 %i
+select -assert-count 4 c:dff0 c:dff2 c:dff4 c:dff6 %% t:$_DFFE_??1P_ %i
+select -assert-count 4 c:dff1 c:dff3 c:dff5 c:dff7 %% t:$_DFFE_??0P_ %i
+select -assert-count 4 c:dff8 c:dff10 c:dff12 c:dff14 %% t:$_SDFF_??1_ %i
+select -assert-count 4 c:dff9 c:dff11 c:dff13 c:dff15 %% t:$_SDFF_??0_ %i
+select -assert-count 4 c:dff16 c:dff18 c:dff20 c:dff22 %% t:$_SDFFE_??1P_ %i
+select -assert-count 4 c:dff17 c:dff19 c:dff21 c:dff23 %% t:$_SDFFE_??0P_ %i
design -reset
read_verilog -icells <<EOT
module top(input C, R, D, E, (* init = {24{1'b0}} *) output [23:0] Q);
-$__DFFE_NN0 dff0 (.C(C), .D(D), .E(E), .R(R), .Q(Q[0]));
-$__DFFE_NN1 dff1 (.C(C), .D(D), .E(E), .R(R), .Q(Q[1]));
-$__DFFE_NP0 dff2 (.C(C), .D(D), .E(E), .R(R), .Q(Q[2]));
-$__DFFE_NP1 dff3 (.C(C), .D(D), .E(E), .R(R), .Q(Q[3]));
-$__DFFE_PN0 dff4 (.C(C), .D(D), .E(E), .R(R), .Q(Q[4]));
-$__DFFE_PN1 dff5 (.C(C), .D(D), .E(E), .R(R), .Q(Q[5]));
-$__DFFE_PP0 dff6 (.C(C), .D(D), .E(E), .R(R), .Q(Q[6]));
-$__DFFE_PP1 dff7 (.C(C), .D(D), .E(E), .R(R), .Q(Q[7]));
-
-$__DFFS_NN0_ dff8 (.C(C), .D(D[0]), .R(R), .Q(Q[8]));
-$__DFFS_NN1_ dff9 (.C(C), .D(D[0]), .R(R), .Q(Q[9]));
-$__DFFS_NP0_ dff10(.C(C), .D(D[0]), .R(R), .Q(Q[10]));
-$__DFFS_NP1_ dff11(.C(C), .D(D[0]), .R(R), .Q(Q[11]));
-$__DFFS_PN0_ dff12(.C(C), .D(D[0]), .R(R), .Q(Q[12]));
-$__DFFS_PN1_ dff13(.C(C), .D(D[0]), .R(R), .Q(Q[13]));
-$__DFFS_PP0_ dff14(.C(C), .D(D[0]), .R(R), .Q(Q[14]));
-$__DFFS_PP1_ dff15(.C(C), .D(D[0]), .R(R), .Q(Q[15]));
-
-$__DFFSE_NN0 dff16(.C(C), .D(D[0]),.E(E), .R(R), .Q(Q[16]));
-$__DFFSE_NN1 dff17(.C(C), .D(D[0]),.E(E), .R(R), .Q(Q[17]));
-$__DFFSE_NP0 dff18(.C(C), .D(D[0]),.E(E), .R(R), .Q(Q[18]));
-$__DFFSE_NP1 dff19(.C(C), .D(D[0]),.E(E), .R(R), .Q(Q[19]));
-$__DFFSE_PN0 dff20(.C(C), .D(D[0]),.E(E), .R(R), .Q(Q[20]));
-$__DFFSE_PN1 dff21(.C(C), .D(D[0]),.E(E), .R(R), .Q(Q[21]));
-$__DFFSE_PP0 dff22(.C(C), .D(D[0]),.E(E), .R(R), .Q(Q[22]));
-$__DFFSE_PP1 dff23(.C(C), .D(D[0]),.E(E), .R(R), .Q(Q[23]));
+$_DFFE_NN0P_ dff0 (.C(C), .D(D), .E(E), .R(R), .Q(Q[0]));
+$_DFFE_NN1P_ dff1 (.C(C), .D(D), .E(E), .R(R), .Q(Q[1]));
+$_DFFE_NP0P_ dff2 (.C(C), .D(D), .E(E), .R(R), .Q(Q[2]));
+$_DFFE_NP1P_ dff3 (.C(C), .D(D), .E(E), .R(R), .Q(Q[3]));
+$_DFFE_PN0P_ dff4 (.C(C), .D(D), .E(E), .R(R), .Q(Q[4]));
+$_DFFE_PN1P_ dff5 (.C(C), .D(D), .E(E), .R(R), .Q(Q[5]));
+$_DFFE_PP0P_ dff6 (.C(C), .D(D), .E(E), .R(R), .Q(Q[6]));
+$_DFFE_PP1P_ dff7 (.C(C), .D(D), .E(E), .R(R), .Q(Q[7]));
+
+$_SDFF_NN0_ dff8 (.C(C), .D(D[0]), .R(R), .Q(Q[8]));
+$_SDFF_NN1_ dff9 (.C(C), .D(D[0]), .R(R), .Q(Q[9]));
+$_SDFF_NP0_ dff10(.C(C), .D(D[0]), .R(R), .Q(Q[10]));
+$_SDFF_NP1_ dff11(.C(C), .D(D[0]), .R(R), .Q(Q[11]));
+$_SDFF_PN0_ dff12(.C(C), .D(D[0]), .R(R), .Q(Q[12]));
+$_SDFF_PN1_ dff13(.C(C), .D(D[0]), .R(R), .Q(Q[13]));
+$_SDFF_PP0_ dff14(.C(C), .D(D[0]), .R(R), .Q(Q[14]));
+$_SDFF_PP1_ dff15(.C(C), .D(D[0]), .R(R), .Q(Q[15]));
+
+$_SDFFE_NN0P_ dff16(.C(C), .D(D[0]),.E(E), .R(R), .Q(Q[16]));
+$_SDFFE_NN1P_ dff17(.C(C), .D(D[0]),.E(E), .R(R), .Q(Q[17]));
+$_SDFFE_NP0P_ dff18(.C(C), .D(D[0]),.E(E), .R(R), .Q(Q[18]));
+$_SDFFE_NP1P_ dff19(.C(C), .D(D[0]),.E(E), .R(R), .Q(Q[19]));
+$_SDFFE_PN0P_ dff20(.C(C), .D(D[0]),.E(E), .R(R), .Q(Q[20]));
+$_SDFFE_PN1P_ dff21(.C(C), .D(D[0]),.E(E), .R(R), .Q(Q[21]));
+$_SDFFE_PP0P_ dff22(.C(C), .D(D[0]),.E(E), .R(R), .Q(Q[22]));
+$_SDFFE_PP1P_ dff23(.C(C), .D(D[0]),.E(E), .R(R), .Q(Q[23]));
endmodule
EOT
@@ -143,9 +143,9 @@ zinit
select -assert-count 0 t:$_NOT_
select -assert-count 1 w:Q a:init=24'bx %i
-select -assert-count 4 c:dff0 c:dff2 c:dff4 c:dff6 %% t:$__DFFE_??0 %i
-select -assert-count 4 c:dff1 c:dff3 c:dff5 c:dff7 %% t:$__DFFE_??1 %i
-select -assert-count 4 c:dff8 c:dff10 c:dff12 c:dff14 %% t:$__DFFS_??0_ %i
-select -assert-count 4 c:dff9 c:dff11 c:dff13 c:dff15 %% t:$__DFFS_??1_ %i
-select -assert-count 4 c:dff16 c:dff18 c:dff20 c:dff22 %% t:$__DFFSE_??0 %i
-select -assert-count 4 c:dff17 c:dff19 c:dff21 c:dff23 %% t:$__DFFSE_??1 %i
+select -assert-count 4 c:dff0 c:dff2 c:dff4 c:dff6 %% t:$_DFFE_??0P_ %i
+select -assert-count 4 c:dff1 c:dff3 c:dff5 c:dff7 %% t:$_DFFE_??1P_ %i
+select -assert-count 4 c:dff8 c:dff10 c:dff12 c:dff14 %% t:$_SDFF_??0_ %i
+select -assert-count 4 c:dff9 c:dff11 c:dff13 c:dff15 %% t:$_SDFF_??1_ %i
+select -assert-count 4 c:dff16 c:dff18 c:dff20 c:dff22 %% t:$_SDFFE_??0P_ %i
+select -assert-count 4 c:dff17 c:dff19 c:dff21 c:dff23 %% t:$_SDFFE_??1P_ %i
diff --git a/tests/various/abc9.ys b/tests/various/abc9.ys
index 6e2415ad7..a9880c722 100644
--- a/tests/various/abc9.ys
+++ b/tests/various/abc9.ys
@@ -45,14 +45,16 @@ sat -seq 10 -verify -prove-asserts -show-ports miter
design -reset
read_verilog -icells <<EOT
module abc9_test036(input clk, d, output q);
-(* keep *) reg w;
-$__ABC9_FF_ ff(.D(d), .Q(w));
-wire \ff.clock = clk;
-wire \ff.init = 1'b0;
+(* keep, init=1'b0 *) wire w;
+$_DFF_P_ ff(.C(clk), .D(d), .Q(w));
assign q = w;
endmodule
EOT
-abc9 -lut 4 -dff
+equiv_opt -assert abc9 -lut 4 -dff
+design -load postopt
+cd abc9_test036
+select -assert-count 1 t:$_DFF_P_
+select -assert-none t:* t:$_DFF_P_ %d
design -reset
@@ -67,8 +69,33 @@ specify
endspecify
endmodule
-module top(input [1:0] i, output o);
+module abc9_test037(input [1:0] i, output o);
LUT2 #(.mask(4'b0)) lut (.i(i), .o(o));
endmodule
EOT
abc9
+
+
+design -reset
+read_verilog -icells <<EOT
+module abc9_test038(input clk, output w, x, y, z);
+(* init=1'b1 *) wire w;
+$_DFF_N_ ff1(.C(clk), .D(1'b1), .Q(w));
+(* init=1'bx *) wire x;
+$_DFF_N_ ff2(.C(clk), .D(1'b0), .Q(x));
+(* init=1'b0 *) wire y;
+$_DFF_N_ ff3(.C(clk), .D(1'b0), .Q(y));
+(* init=1'b0 *) wire z;
+$_DFF_N_ ff4(.C(clk), .D(1'b1), .Q(z));
+endmodule
+EOT
+simplemap
+equiv_opt abc9 -lut 4 -dff
+design -load postopt
+cd abc9_test038
+select -assert-count 3 t:$_DFF_N_
+select -assert-none c:ff1 c:ff2 c:ff4 %% c:* %D
+clean
+select -assert-count 2 a:init
+select -assert-count 1 w:w a:init %i
+select -assert-count 1 c:ff4 %co c:ff4 %d %a a:init %i
diff --git a/tests/various/attrib07_func_call.v b/tests/various/attrib07_func_call.v
index f55ef2316..8c9fb2926 100644
--- a/tests/various/attrib07_func_call.v
+++ b/tests/various/attrib07_func_call.v
@@ -11,7 +11,7 @@ module foo(clk, rst, inp_a, inp_b, out);
input wire rst;
input wire [7:0] inp_a;
input wire [7:0] inp_b;
- output wire [7:0] out;
+ output reg [7:0] out;
always @(posedge clk)
if (rst) out <= 0;
diff --git a/tests/various/const_func.v b/tests/various/const_func.v
new file mode 100644
index 000000000..76cdc385d
--- /dev/null
+++ b/tests/various/const_func.v
@@ -0,0 +1,75 @@
+module Example(outA, outB, outC, outD);
+ parameter OUTPUT = "FOO";
+ output wire [23:0] outA;
+ output wire [23:0] outB;
+ output reg outC, outD;
+ function automatic [23:0] flip;
+ input [23:0] inp;
+ flip = ~inp;
+ endfunction
+
+ generate
+ if (flip(OUTPUT) == flip("BAR"))
+ assign outA = OUTPUT;
+ else
+ assign outA = 0;
+
+ case (flip(OUTPUT))
+ flip("FOO"): assign outB = OUTPUT;
+ flip("BAR"): assign outB = 0;
+ flip("BAZ"): assign outB = "HI";
+ endcase
+
+ genvar i;
+ initial outC = 0;
+ for (i = 0; i != flip(flip(OUTPUT[15:8])); i = i + 1)
+ if (i + 1 == flip(flip("O")))
+ initial outC = 1;
+ endgenerate
+
+ integer j;
+ initial begin
+ outD = 1;
+ for (j = 0; j != flip(flip(OUTPUT[15:8])); j = j + 1)
+ if (j + 1 == flip(flip("O")))
+ outD = 0;
+ end
+endmodule
+
+module top(out);
+ wire [23:0] a1, a2, a3, a4;
+ wire [23:0] b1, b2, b3, b4;
+ wire c1, c2, c3, c4;
+ wire d1, d2, d3, d4;
+ Example e1(a1, b1, c1, d1);
+ Example #("FOO") e2(a2, b2, c2, d2);
+ Example #("BAR") e3(a3, b3, c3, d3);
+ Example #("BAZ") e4(a4, b4, c4, d4);
+
+ output wire [24 * 8 - 1 + 4 :0] out;
+ assign out = {
+ a1, a2, a3, a4,
+ b1, b2, b3, b4,
+ c1, c2, c3, c4,
+ d1, d2, d3, d4};
+
+// `define VERIFY
+`ifdef VERIFY
+ assert property (a1 == 0);
+ assert property (a2 == 0);
+ assert property (a3 == "BAR");
+ assert property (a4 == 0);
+ assert property (b1 == "FOO");
+ assert property (b2 == "FOO");
+ assert property (b3 == 0);
+ assert property (b4 == "HI");
+ assert property (c1 == 1);
+ assert property (c2 == 1);
+ assert property (c3 == 0);
+ assert property (c4 == 0);
+ assert property (d1 == 0);
+ assert property (d2 == 0);
+ assert property (d3 == 1);
+ assert property (d4 == 1);
+`endif
+endmodule
diff --git a/tests/various/const_func.ys b/tests/various/const_func.ys
new file mode 100644
index 000000000..5e3c04105
--- /dev/null
+++ b/tests/various/const_func.ys
@@ -0,0 +1 @@
+read_verilog const_func.v
diff --git a/tests/various/constmsk_testmap.v b/tests/various/constmsk_testmap.v
index fab1b1bbc..b6809c7c0 100644
--- a/tests/various/constmsk_testmap.v
+++ b/tests/various/constmsk_testmap.v
@@ -1,7 +1,7 @@
(* techmap_celltype = "$reduce_or" *)
module my_opt_reduce_or(...);
parameter A_SIGNED = 0;
- parameter A_WIDTH = 1;
+ parameter A_WIDTH = 2;
parameter Y_WIDTH = 1;
input [A_WIDTH-1:0] A;
diff --git a/tests/various/plugin.cc b/tests/various/plugin.cc
index be305fbda..451484c50 100644
--- a/tests/various/plugin.cc
+++ b/tests/various/plugin.cc
@@ -4,7 +4,7 @@ YOSYS_NAMESPACE_BEGIN
struct TestPass : public Pass {
TestPass() : Pass("test", "test") { }
- void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
+ void execute(std::vector<std::string> args, RTLIL::Design *design) override
{
size_t argidx = 1;
extra_args(args, argidx, design);
diff --git a/tests/various/printattr.ys b/tests/various/printattr.ys
new file mode 100644
index 000000000..afc6d8eb6
--- /dev/null
+++ b/tests/various/printattr.ys
@@ -0,0 +1,14 @@
+logger -expect log ".*cells_not_processed=[01]* .*" 1
+logger -expect log ".*src=.<<EOT:1\.1-9\.10. .*" 1
+read_verilog <<EOT
+module mux2(a, b, s, y);
+ input a, b, s;
+ output y;
+
+ wire s_n = ~s;
+ wire t0 = s & a;
+ wire t1 = s_n & b;
+ assign y = t0 | t1;
+endmodule
+EOT
+printattrs
diff --git a/tests/various/shregmap.v b/tests/various/shregmap.v
index 604c2c976..dc828eda7 100644
--- a/tests/various/shregmap.v
+++ b/tests/various/shregmap.v
@@ -13,7 +13,7 @@ assign q = {shift2[3], shift1[3]};
endmodule
module $__SHREG_DFF_P_(input C, D, output Q);
-parameter DEPTH = 1;
+parameter DEPTH = 2;
parameter [DEPTH-1:0] INIT = {DEPTH{1'b0}};
reg [DEPTH-1:0] r = INIT;
always @(posedge C)
@@ -38,7 +38,7 @@ endmodule
module $__XILINX_SHREG_(input C, D, input [1:0] L, output Q);
parameter CLKPOL = 1;
parameter ENPOL = 1;
-parameter DEPTH = 1;
+parameter DEPTH = 2;
parameter [DEPTH-1:0] INIT = {DEPTH{1'b0}};
reg [DEPTH-1:0] r = INIT;
wire clk = C ^ CLKPOL;
diff --git a/tests/various/signed.ys b/tests/various/signed.ys
new file mode 100644
index 000000000..2319a5da1
--- /dev/null
+++ b/tests/various/signed.ys
@@ -0,0 +1,28 @@
+# SV LRM A2.2.1
+
+read_verilog -sv <<EOT
+module test_signed();
+parameter integer signed a = 0;
+parameter integer unsigned b = 0;
+
+endmodule
+EOT
+
+design -reset
+read_verilog -sv <<EOT
+module test_signed();
+parameter logic signed [7:0] a = 0;
+parameter logic unsigned [7:0] b = 0;
+
+endmodule
+EOT
+
+design -reset
+logger -expect error "syntax error, unexpected TOK_INTEGER" 1
+read_verilog -sv <<EOT
+module test_signed();
+parameter signed integer a = 0;
+parameter unsigned integer b = 0;
+
+endmodule
+EOT
diff --git a/tests/various/xaiger.ys b/tests/various/xaiger.ys
new file mode 100644
index 000000000..f612d2e18
--- /dev/null
+++ b/tests/various/xaiger.ys
@@ -0,0 +1,13 @@
+read_verilog <<EOT
+module top(input a, b, output c);
+bb #(1) bb();
+endmodule
+
+module bb(input a, b, output c);
+parameter p = 0;
+assign c = a ^ b;
+endmodule
+EOT
+blackbox bb
+hierarchy
+write_xaiger /dev/null
diff --git a/tests/verilog/bug2037.ys b/tests/verilog/bug2037.ys
new file mode 100644
index 000000000..4b629ba92
--- /dev/null
+++ b/tests/verilog/bug2037.ys
@@ -0,0 +1,58 @@
+logger -expect-no-warnings
+read_verilog <<EOT
+module test ();
+ localparam y = 1;
+ always @(*)
+ if (y) (* foo *) ;
+endmodule
+EOT
+select -assert-none a:* a:src %d
+
+
+design -reset
+logger -expect-no-warnings
+read_verilog <<EOT
+module test ();
+ localparam y = 1;
+ always @(*)
+ if (y) (* foo *) ; else (* bar *) ;
+endmodule
+EOT
+select -assert-none a:* a:src %d
+
+
+design -reset
+logger -expect-no-warnings
+read_verilog <<EOT
+module test ();
+ localparam y = 1;
+ generate if (y) (* foo *) ; endgenerate
+endmodule
+EOT
+select -assert-none a:*
+
+
+design -reset
+logger -expect-no-warnings
+read_verilog <<EOT
+module test ();
+ localparam y = 1;
+ generate if (y) (* foo *) ; else (* bar *); endgenerate
+endmodule
+EOT
+select -assert-none a:*
+
+
+design -reset
+read_verilog <<EOT
+module test ();
+ localparam y = 1;
+ reg x = 1'b0;
+ always @(*) begin
+ if (y)
+ (* foo *) x <= 1'b1;
+ else
+ (* bar *) x = 1'b0;
+ end
+endmodule
+EOT
diff --git a/tests/verilog/bug2042-sv.ys b/tests/verilog/bug2042-sv.ys
index e815d7fc5..91989f412 100644
--- a/tests/verilog/bug2042-sv.ys
+++ b/tests/verilog/bug2042-sv.ys
@@ -2,7 +2,7 @@ read_verilog -sv <<EOT
module Task_Test_Top
(
input a,
-output b
+output reg b
);
task SomeTaskName(a);
diff --git a/tests/verilog/task_attr.ys b/tests/verilog/task_attr.ys
new file mode 100644
index 000000000..d6e75f85f
--- /dev/null
+++ b/tests/verilog/task_attr.ys
@@ -0,0 +1,28 @@
+read_verilog <<EOT
+module top;
+ task foo;
+ endtask
+
+ always @*
+ (* foo *) foo;
+
+ initial
+ if (0) $info("bar");
+endmodule
+EOT
+# Since task enables are not an RTLIL object,
+# any attributes on their AST get dropped
+select -assert-none a:* a:src %d
+
+
+logger -expect error "syntax error, unexpected ATTR_BEGIN" 1
+design -reset
+read_verilog <<EOT
+module top;
+ task foo;
+ endtask
+
+ always @*
+ foo (* foo *);
+endmodule
+EOT