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-rw-r--r--Makefile7
-rw-r--r--backends/cxxrtl/cxxrtl.h29
-rw-r--r--backends/cxxrtl/cxxrtl_backend.cc60
-rw-r--r--backends/cxxrtl/cxxrtl_capi.cc4
-rw-r--r--backends/cxxrtl/cxxrtl_capi.h8
-rw-r--r--frontends/ast/ast.cc1
-rw-r--r--frontends/verific/verific.cc2
-rw-r--r--manual/CHAPTER_Overview.tex4
-rw-r--r--manual/CHAPTER_TextRtlil.tex299
-rw-r--r--manual/manual.tex4
-rw-r--r--passes/sat/freduce.cc1
-rw-r--r--techlibs/nexus/arith_map.v4
12 files changed, 410 insertions, 13 deletions
diff --git a/Makefile b/Makefile
index d352358a0..355b2a25e 100644
--- a/Makefile
+++ b/Makefile
@@ -125,7 +125,7 @@ LDFLAGS += -rdynamic
LDLIBS += -lrt
endif
-YOSYS_VER := 0.9+3710
+YOSYS_VER := 0.9+3715
GIT_REV := $(shell cd $(YOSYS_SRC) && git rev-parse --short HEAD 2> /dev/null || echo UNKNOWN)
OBJS = kernel/version_$(GIT_REV).o
@@ -608,6 +608,11 @@ $(eval $(call add_include_file,backends/cxxrtl/cxxrtl_vcd_capi.cc))
$(eval $(call add_include_file,backends/cxxrtl/cxxrtl_vcd_capi.h))
OBJS += kernel/driver.o kernel/register.o kernel/rtlil.o kernel/log.o kernel/calc.o kernel/yosys.o
+ifeq ($(ENABLE_ABC),1)
+ifneq ($(ABCEXTERNAL),)
+kernel/yosys.o: CXXFLAGS += -DABCEXTERNAL='"$(ABCEXTERNAL)"'
+endif
+endif
OBJS += kernel/cellaigs.o kernel/celledges.o kernel/satgen.o kernel/mem.o
kernel/log.o: CXXFLAGS += -DYOSYS_SRC='"$(YOSYS_SRC)"'
diff --git a/backends/cxxrtl/cxxrtl.h b/backends/cxxrtl/cxxrtl.h
index 7d3a8485c..eb7d7eaeb 100644
--- a/backends/cxxrtl/cxxrtl.h
+++ b/backends/cxxrtl/cxxrtl.h
@@ -110,9 +110,11 @@ struct value : public expr_base<value<Bits>> {
explicit constexpr value(Init ...init) : data{init...} {}
value(const value<Bits> &) = default;
- value(value<Bits> &&) = default;
value<Bits> &operator=(const value<Bits> &) = default;
+ value(value<Bits> &&) = default;
+ value<Bits> &operator=(value<Bits> &&) = default;
+
// A (no-op) helper that forces the cast to value<>.
CXXRTL_ALWAYS_INLINE
const value<Bits> &val() const {
@@ -661,10 +663,16 @@ struct wire {
template<typename... Init>
explicit constexpr wire(Init ...init) : curr{init...}, next{init...} {}
+ // Copying and copy-assigning values is natural. If, however, a value is replaced with a wire,
+ // e.g. because a module is built with a different optimization level, then existing code could
+ // unintentionally copy a wire instead, which would create a subtle but serious bug. To make sure
+ // this doesn't happen, prohibit copying and copy-assigning wires.
wire(const wire<Bits> &) = delete;
- wire(wire<Bits> &&) = default;
wire<Bits> &operator=(const wire<Bits> &) = delete;
+ wire(wire<Bits> &&) = default;
+ wire<Bits> &operator=(wire<Bits> &&) = default;
+
template<class IntegerT>
CXXRTL_ALWAYS_INLINE
IntegerT get() const {
@@ -706,6 +714,9 @@ struct memory {
memory(const memory<Width> &) = delete;
memory<Width> &operator=(const memory<Width> &) = delete;
+ memory(memory<Width> &&) = default;
+ memory<Width> &operator=(memory<Width> &&) = default;
+
// The only way to get the compiler to put the initializer in .rodata and do not copy it on stack is to stuff it
// into a plain array. You'd think an std::initializer_list would work here, but it doesn't, because you can't
// construct an initializer_list in a constexpr (or something) and so if you try to do that the whole thing is
@@ -829,7 +840,7 @@ struct metadata {
typedef std::map<std::string, metadata> metadata_map;
-// Helper class to disambiguate values/wires and their aliases.
+// Tag class to disambiguate values/wires and their aliases.
struct debug_alias {};
// This structure is intended for consumption via foreign function interfaces, like Python's ctypes.
@@ -979,13 +990,25 @@ struct debug_items {
}
};
+// Tag class to disambiguate module move constructor and module constructor that takes black boxes
+// out of another instance of the module.
+struct adopt {};
+
struct module {
module() {}
virtual ~module() {}
+ // Modules with black boxes cannot be copied. Although not all designs include black boxes,
+ // delete the copy constructor and copy assignment operator to make sure that any downstream
+ // code that manipulates modules doesn't accidentally depend on their availability.
module(const module &) = delete;
module &operator=(const module &) = delete;
+ module(module &&) = default;
+ module &operator=(module &&) = default;
+
+ virtual void reset() = 0;
+
virtual bool eval() = 0;
virtual bool commit() = 0;
diff --git a/backends/cxxrtl/cxxrtl_backend.cc b/backends/cxxrtl/cxxrtl_backend.cc
index 23ea57b5a..7efb0aeaf 100644
--- a/backends/cxxrtl/cxxrtl_backend.cc
+++ b/backends/cxxrtl/cxxrtl_backend.cc
@@ -1036,8 +1036,12 @@ struct CxxrtlWorker {
// Edge-sensitive logic
RTLIL::SigBit clk_bit = cell->getPort(ID::CLK)[0];
clk_bit = sigmaps[clk_bit.wire->module](clk_bit);
- f << indent << "if (" << (cell->getParam(ID::CLK_POLARITY).as_bool() ? "posedge_" : "negedge_")
- << mangle(clk_bit) << ") {\n";
+ if (clk_bit.wire) {
+ f << indent << "if (" << (cell->getParam(ID::CLK_POLARITY).as_bool() ? "posedge_" : "negedge_")
+ << mangle(clk_bit) << ") {\n";
+ } else {
+ f << indent << "if (false) {\n";
+ }
inc_indent();
if (cell->hasPort(ID::EN)) {
f << indent << "if (";
@@ -1130,8 +1134,12 @@ struct CxxrtlWorker {
if (cell->getParam(ID::CLK_ENABLE).as_bool()) {
RTLIL::SigBit clk_bit = cell->getPort(ID::CLK)[0];
clk_bit = sigmaps[clk_bit.wire->module](clk_bit);
- f << indent << "if (" << (cell->getParam(ID::CLK_POLARITY).as_bool() ? "posedge_" : "negedge_")
- << mangle(clk_bit) << ") {\n";
+ if (clk_bit.wire) {
+ f << indent << "if (" << (cell->getParam(ID::CLK_POLARITY).as_bool() ? "posedge_" : "negedge_")
+ << mangle(clk_bit) << ") {\n";
+ } else {
+ f << indent << "if (false) {\n";
+ }
inc_indent();
}
RTLIL::Memory *memory = cell->module->memories[cell->getParam(ID::MEMID).decode_string()];
@@ -1869,6 +1877,46 @@ struct CxxrtlWorker {
}
if (has_cells)
f << "\n";
+ f << indent << mangle(module) << "() {}\n";
+ if (has_cells) {
+ f << indent << mangle(module) << "(adopt, " << mangle(module) << " other) :\n";
+ bool first = true;
+ for (auto cell : module->cells()) {
+ if (is_internal_cell(cell->type))
+ continue;
+ if (first) {
+ first = false;
+ } else {
+ f << ",\n";
+ }
+ RTLIL::Module *cell_module = module->design->module(cell->type);
+ if (cell_module->get_bool_attribute(ID(cxxrtl_blackbox))) {
+ f << indent << " " << mangle(cell) << "(std::move(other." << mangle(cell) << "))";
+ } else {
+ f << indent << " " << mangle(cell) << "(adopt {}, std::move(other." << mangle(cell) << "))";
+ }
+ }
+ f << " {\n";
+ inc_indent();
+ for (auto cell : module->cells()) {
+ if (is_internal_cell(cell->type))
+ continue;
+ RTLIL::Module *cell_module = module->design->module(cell->type);
+ if (cell_module->get_bool_attribute(ID(cxxrtl_blackbox)))
+ f << indent << mangle(cell) << "->reset();\n";
+ }
+ dec_indent();
+ f << indent << "}\n";
+ } else {
+ f << indent << mangle(module) << "(adopt, " << mangle(module) << " other) {}\n";
+ }
+ f << "\n";
+ f << indent << "void reset() override {\n";
+ inc_indent();
+ f << indent << "*this = " << mangle(module) << "(adopt {}, std::move(*this));\n";
+ dec_indent();
+ f << indent << "}\n";
+ f << "\n";
f << indent << "bool eval() override;\n";
f << indent << "bool commit() override;\n";
if (debug_info)
@@ -2105,14 +2153,14 @@ struct CxxrtlWorker {
// Various DFF cells are treated like posedge/negedge processes, see above for details.
if (cell->type.in(ID($dff), ID($dffe), ID($adff), ID($adffe), ID($dffsr), ID($dffsre), ID($sdff), ID($sdffe), ID($sdffce))) {
- if (cell->getPort(ID::CLK).is_wire())
+ if (sigmap(cell->getPort(ID::CLK)).is_wire())
register_edge_signal(sigmap, cell->getPort(ID::CLK),
cell->parameters[ID::CLK_POLARITY].as_bool() ? RTLIL::STp : RTLIL::STn);
}
// Similar for memory port cells.
if (cell->type.in(ID($memrd), ID($memwr))) {
if (cell->getParam(ID::CLK_ENABLE).as_bool()) {
- if (cell->getPort(ID::CLK).is_wire())
+ if (sigmap(cell->getPort(ID::CLK)).is_wire())
register_edge_signal(sigmap, cell->getPort(ID::CLK),
cell->parameters[ID::CLK_POLARITY].as_bool() ? RTLIL::STp : RTLIL::STn);
}
diff --git a/backends/cxxrtl/cxxrtl_capi.cc b/backends/cxxrtl/cxxrtl_capi.cc
index b77e4c491..1c3c63e3e 100644
--- a/backends/cxxrtl/cxxrtl_capi.cc
+++ b/backends/cxxrtl/cxxrtl_capi.cc
@@ -43,6 +43,10 @@ void cxxrtl_destroy(cxxrtl_handle handle) {
delete handle;
}
+void cxxrtl_reset(cxxrtl_handle handle) {
+ handle->module->reset();
+}
+
int cxxrtl_eval(cxxrtl_handle handle) {
return handle->module->eval();
}
diff --git a/backends/cxxrtl/cxxrtl_capi.h b/backends/cxxrtl/cxxrtl_capi.h
index 385d6dcf3..662bf2c20 100644
--- a/backends/cxxrtl/cxxrtl_capi.h
+++ b/backends/cxxrtl/cxxrtl_capi.h
@@ -55,6 +55,14 @@ cxxrtl_handle cxxrtl_create(cxxrtl_toplevel design);
// Release all resources used by a design and its handle.
void cxxrtl_destroy(cxxrtl_handle handle);
+// Reinitialize the design, replacing the internal state with the reset values while preserving
+// black boxes.
+//
+// This operation is essentially equivalent to a power-on reset. Values, wires, and memories are
+// returned to their reset state while preserving the state of black boxes and keeping all of
+// the interior pointers obtained with e.g. `cxxrtl_get` valid.
+void cxxrtl_reset(cxxrtl_handle handle);
+
// Evaluate the design, propagating changes on inputs to the `next` value of internal state and
// output wires.
//
diff --git a/frontends/ast/ast.cc b/frontends/ast/ast.cc
index c8183580b..1c0a8b34d 100644
--- a/frontends/ast/ast.cc
+++ b/frontends/ast/ast.cc
@@ -1511,6 +1511,7 @@ RTLIL::IdString AstModule::derive(RTLIL::Design *design, const dict<RTLIL::IdStr
}
} else {
+ modname = new_modname;
log("Found cached RTLIL representation for module `%s'.\n", modname.c_str());
}
diff --git a/frontends/verific/verific.cc b/frontends/verific/verific.cc
index 31c77d39c..cf3bf1070 100644
--- a/frontends/verific/verific.cc
+++ b/frontends/verific/verific.cc
@@ -55,7 +55,7 @@ USING_YOSYS_NAMESPACE
# error "Only Symbiotic EDA flavored Verific is supported. Please contact office@symbioticeda.com for commercial support for Yosys+Verific."
#endif
-#if SYMBIOTIC_VERIFIC_API_VERSION < 20201001
+#if SYMBIOTIC_VERIFIC_API_VERSION < 20201101
# error "Please update your version of Symbiotic EDA flavored Verific."
#endif
diff --git a/manual/CHAPTER_Overview.tex b/manual/CHAPTER_Overview.tex
index ed8b4cd49..83db5aac7 100644
--- a/manual/CHAPTER_Overview.tex
+++ b/manual/CHAPTER_Overview.tex
@@ -230,6 +230,7 @@ generated twice. For modules with only a few parameters, a name directly contain
is generated instead of a hash string.)
\subsection{RTLIL::Cell and RTLIL::Wire}
+\label{sec:rtlil_cell_wire}
A module contains zero to many RTLIL::Cell and RTLIL::Wire objects. Objects of
these types are used to model netlists. Usually the goal of all synthesis efforts is to convert
@@ -275,6 +276,7 @@ The connections of ports to wires are coded by assigning an RTLIL::SigSpec
to each cell port. The RTLIL::SigSpec data type is described in the next section.
\subsection{RTLIL::SigSpec}
+\label{sec:rtlil_sigspec}
A ``signal'' is everything that can be applied to a cell port. I.e.
@@ -295,6 +297,7 @@ RTLIL::SigSpec objects. Such pairs are needed in different locations. Therefore
the type name RTLIL::SigSig was defined for such a pair.
\subsection{RTLIL::Process}
+\label{sec:rtlil_process}
When a high-level HDL frontend processes behavioural code it splits it up into
data path logic (e.g.~the expression {\tt a + b} is replaced by the output of an
@@ -444,6 +447,7 @@ pass calls a series of other passes that together perform this conversion in a w
for most synthesis tasks.
\subsection{RTLIL::Memory}
+\label{sec:rtlil_memory}
For every array (memory) in the HDL code an RTLIL::Memory object is created. A
memory object has the following properties:
diff --git a/manual/CHAPTER_TextRtlil.tex b/manual/CHAPTER_TextRtlil.tex
new file mode 100644
index 000000000..243b56a87
--- /dev/null
+++ b/manual/CHAPTER_TextRtlil.tex
@@ -0,0 +1,299 @@
+\chapter{RTLIL Text Representation}
+\label{chapter:textrtlil}
+
+% Stolen from stackexchange: calculate indent based on given keyword,
+% with some nice hrules added in.
+\newlength{\myl}
+
+\newenvironment{indentgrammar}[1]
+ {\vspace{0.5cm}\hrule
+ \setlength{\myl}{\widthof{#1}+2em}
+ \grammarindent\the\myl
+ \begin{grammar}}
+ {\end{grammar}
+ \hrule}
+
+This appendix documents the text representation of RTLIL in extended Backus-Naur form (EBNF).
+
+The grammar is not meant to represent semantic limitations. That is, the grammar is ``permissive'', and later stages of processing perform more rigorous checks.
+
+The grammar is also not meant to represent the exact grammar used in the RTLIL frontend, since that grammar is specific to processing by lex and yacc, is even more permissive, and is somewhat less understandable than simple EBNF notation.
+
+Finally, note that all statements (rules ending in \texttt{-stmt}) terminate in an end-of-line. Because of this, a statement cannot be broken into multiple lines.
+
+\section{Lexical elements}
+
+\subsection{Characters}
+
+An RTLIL file is a stream of bytes. Strictly speaking, a ``character'' in an RTLIL file is a single byte. The lexer treats multi-byte encoded characters as consecutive single-byte characters. While other encodings \textit{may} work, UTF-8 is known to be safe to use. Byte order marks at the beginning of the file will cause an error.
+
+ASCII spaces (32) and tabs (9) separate lexer tokens.
+
+A \texttt{nonws} character, used in identifiers, is any character whose encoding consists solely of bytes above ASCII space (32).
+
+An \texttt{eol} is one or more consecutive ASCII newlines (10) and carriage returns (13).
+
+\subsection{Identifiers}
+
+There are two types of identifiers in RTLIL:
+
+\begin{itemize}
+ \item Publically visible identifiers
+ \item Auto-generated identifiers
+\end{itemize}
+
+\begin{indentgrammar}{<autogen-id>}
+<id> ::= <public-id> | <autogen-id>
+
+<public-id> ::= "\textbackslash" <nonws>$+$
+
+<autogen-id> ::= "\textdollar" <nonws>$+$
+\end{indentgrammar}
+
+\subsection{Values}
+
+A \textit{value} consists of a width in bits and a bit representation, most significant bit first. Bits may be any of:
+\begin{itemize}
+ \item \texttt{0}: A logic zero value
+ \item \texttt{1}: A logic one value
+ \item \texttt{x}: An unknown logic value (or don't care in case patterns)
+ \item \texttt{z}: A high-impedance value (or don't care in case patterns)
+ \item \texttt{m}: A marked bit (internal use only)
+ \item \texttt{-}: A don't care value
+\end{itemize}
+
+An \textit{integer} is simply a signed integer value in decimal format. \textbf{Warning:} Integer constants are limited to 32 bits. That is, they may only be in the range $[-2147483648, 2147483648)$. Integers outside this range will result in an error.
+
+\begin{indentgrammar}{<binary-digit>}
+<value> ::= <decimal-digit>$+$ \texttt{\textbf{'}} <binary-digit>$*$
+
+<decimal-digit> ::= "0" | "1" | "2" | "3" | "4" | "5" | "6" | "7" | "8" | "9"
+
+<binary-digit> ::= "0" | "1" | "x" | "z" | "m" | "-"
+
+<integer> ::= "-"$?$ <decimal-digit>$+$
+\end{indentgrammar}
+
+\subsection{Strings}
+
+A string is a series of characters delimited by double-quote characters. Within a string, any character except ASCII NUL (0) may be used. In addition, certain escapes can be used:
+
+\begin{itemize}
+ \item \texttt{\textbackslash n}: A newline
+ \item \texttt{\textbackslash t}: A tab
+ \item \texttt{\textbackslash \textit{ooo}}: A character specified as a one, two, or three digit octal value
+\end{itemize}
+
+All other characters may be escaped by a backslash, and become the following character. Thus:
+
+\begin{itemize}
+ \item \texttt{\textbackslash \textbackslash}: A backslash
+ \item \texttt{\textbackslash ''}: A double-quote
+ \item \texttt{\textbackslash r}: An 'r' character
+\end{itemize}
+
+\subsection{Comments}
+
+A comment starts with a \texttt{\textbf{\#}} character and proceeds to the end of the line. All comments are ignored.
+
+\section{File}
+
+A file consists of an optional autoindex statement followed by zero or more modules.
+
+\begin{indentgrammar}{<design>}
+<file> ::= <autoidx-stmt>$?$ <module>*
+\end{indentgrammar}
+
+\subsection{Autoindex statements}
+
+The autoindex statement sets the global autoindex value used by Yosys when it needs to generate a unique name, e.g. \texttt{\textdollar{}flatten\textdollar{}N}. The N part is filled with the value of the global autoindex value, which is subsequently incremented. This global has to be dumped into RTLIL, otherwise e.g. dumping and running a pass would have different properties than just running a pass on a warm design.
+
+\begin{indentgrammar}{<autoidx-stmt>}
+<autoidx-stmt> ::= "autoidx" <integer> <eol>
+\end{indentgrammar}
+
+\subsection{Modules}
+
+Declares a module, with zero or more attributes, consisting of zero or more wires, memories, cells, processes, and connections.
+
+\begin{indentgrammar}{<module-body-stmt>}
+<module> ::= <attr-stmt>$*$ <module-stmt> <module-body> <module-end-stmt>
+
+<module-stmt> ::= "module" <id> <eol>
+
+<module-body> ::=
+(<param-stmt>
+ \alt <wire>
+ \alt <memory>
+ \alt <cell>
+ \alt <process>
+ \alt <conn-stmt>)$*$
+
+<param-stmt> ::= "parameter" <id> <constant>$?$ <eol>
+
+<constant> ::= <value> | <integer> | <string>
+
+<module-end-stmt> ::= "end" <eol>
+\end{indentgrammar}
+
+\subsection{Attribute statements}
+
+Declares an attribute with the given identifier and value.
+
+\begin{indentgrammar}{<attr-stmt>}
+<attr-stmt> ::= "attribute" <id> <constant> <eol>
+\end{indentgrammar}
+
+\subsection{Signal specifications}
+
+A signal is anything that can be applied to a cell port, i.e. a constant value, all bits or a selection of bits from a wire, or concatenations of those.
+
+\textbf{Warning:} When an integer constant is a sigspec, it is always 32 bits wide, 2's complement. For example, a constant of $-1$ is the same as \texttt{32'11111111111111111111111111111111}, while a constant of $1$ is the same as \texttt{32'1}.
+
+See Sec.~\ref{sec:rtlil_sigspec} for an overview of signal specifications.
+
+\begin{indentgrammar}{<sigspec>}
+<sigspec> ::=
+<constant>
+ \alt <wire-id>
+ \alt <sigspec> "[" <integer> (":" <integer>)$?$ "]"
+ \alt "\{" <sigspec>$*$ "\}"
+\end{indentgrammar}
+
+\subsection{Connections}
+
+Declares a connection between the given signals.
+
+\begin{indentgrammar}{<conn-stmt>}
+<conn-stmt> ::= "connect" <sigspec> <sigspec> <eol>
+\end{indentgrammar}
+
+\subsection{Wires}
+
+Declares a wire, with zero or more attributes, with the given identifier and options in the enclosing module.
+
+See Sec.~\ref{sec:rtlil_cell_wire} for an overview of wires.
+
+\begin{indentgrammar}{<wire-option>}
+<wire> ::= <attr-stmt>$*$ <wire-stmt>
+
+<wire-stmt> ::= "wire" <wire-option>$*$ <wire-id> <eol>
+
+<wire-id> ::= <id>
+
+<wire-option> ::=
+"width" <integer>
+ \alt "offset" <integer>
+ \alt "input" <integer>
+ \alt "output" <integer>
+ \alt "inout" <integer>
+ \alt "upto"
+ \alt "signed"
+\end{indentgrammar}
+
+\subsection{Memories}
+
+Declares a memory, with zero or more attributes, with the given identifier and options in the enclosing module.
+
+See Sec.~\ref{sec:rtlil_memory} for an overview of memory cells, and Sec.~\ref{sec:memcells} for details about memory cell types.
+
+\begin{indentgrammar}{<memory-option>}
+<memory> ::= <attr-stmt>$*$ <memory-stmt>
+
+<memory-stmt> ::= "memory" <memory-option>$*$ <id> <eol>
+
+<memory-option> ::=
+"width" <integer>
+ \alt "size" <integer>
+ \alt "offset" <integer>
+\end{indentgrammar}
+
+\subsection{Cells}
+
+Declares a cell, with zero or more attributes, with the given identifier and type in the enclosing module.
+
+Cells perform functions on input signals. See Chap.~\ref{chapter:celllib} for a detailed list of cell types.
+
+\begin{indentgrammar}{<cell-body-stmt>}
+<cell> ::= <attr-stmt>$*$ <cell-stmt> <cell-body-stmt>$*$ <cell-end-stmt>
+
+<cell-stmt> ::= "cell" <cell-id> <cell-type> <eol>
+
+<cell-id> ::= <id>
+
+<cell-type> ::= <id>
+
+<cell-body-stmt> ::=
+"parameter" ("signed" | "real")$?$ <id> <constant> <eol>
+ \alt "connect" <id> <sigspec> <eol>
+
+<cell-end-stmt> ::= "end" <eol>
+\end{indentgrammar}
+
+\subsection{Processes}
+
+Declares a process, with zero or more attributes, with the given identifier in the enclosing module. The body of a process consists of zero or more assignments, exactly one switch, and zero or more syncs.
+
+See Sec.~\ref{sec:rtlil_process} for an overview of processes.
+
+\begin{indentgrammar}{<switch-end-stmt>}
+<process> ::= <attr-stmt>$*$ <proc-stmt> <process-body> <proc-end-stmt>
+
+<proc-stmt> ::= "process" <id> <eol>
+
+<process-body> ::= <assign-stmt>$*$ <switch> <assign-stmt>$*$ <sync>$*$
+
+<assign-stmt> ::= "assign" <dest-sigspec> <src-sigspec> <eol>
+
+<dest-sigspec> ::= <sigspec>
+
+<src-sigspec> ::= <sigspec>
+
+<proc-end-stmt> ::= "end" <eol>
+
+\end{indentgrammar}
+
+\subsection{Switches}
+
+Switches test a signal for equality against a list of cases. Each case specifies a comma-separated list of signals to check against. If there are no signals in the list, then the case is the default case. The body of a case consists of zero or more switches and assignments. Both switches and cases may have zero or more attributes.
+
+\begin{indentgrammar}{<switch-end-stmt>}
+<switch> ::= <switch-stmt> <case>$*$ <switch-end-stmt>
+
+<switch-stmt> := <attr-stmt>$*$ "switch" <sigspec> <eol>
+
+<case> ::= <attr-stmt>$*$ <case-stmt> <case-body>
+
+<case-stmt> ::= "case" <compare>$?$ <eol>
+
+<compare> ::= <sigspec> ("," <sigspec>)$*$
+
+<case-body> ::= (<switch> | <assign-stmt>)$*$
+
+<switch-end-stmt> ::= "end" <eol>
+\end{indentgrammar}
+
+\subsection{Syncs}
+
+Syncs update signals with other signals when an event happens. Such an event may be:
+
+\begin{itemize}
+ \item An edge or level on a signal
+ \item Global clock ticks
+ \item Initialization
+ \item Always
+\end{itemize}
+
+\begin{indentgrammar}{<dest-sigspec>}
+<sync> ::= <sync-stmt> <update-stmt>$*$
+
+<sync-stmt> ::=
+"sync" <sync-type> <sigspec> <eol>
+ \alt "sync" "global" <eol>
+ \alt "sync" "init" <eol>
+ \alt "sync" "always" <eol>
+
+<sync-type> ::= "low" | "high" | "posedge" | "negedge" | "edge"
+
+<update-stmt> ::= "update" <dest-sigspec> <src-sigspec> <eol>
+\end{indentgrammar}
diff --git a/manual/manual.tex b/manual/manual.tex
index 75f087eca..dac8b1000 100644
--- a/manual/manual.tex
+++ b/manual/manual.tex
@@ -75,6 +75,9 @@ bookmarksopen=false%
\usetikzlibrary{through}
\usetikzlibrary{shapes.geometric}
+\usepackage{calc}
+\usepackage[nounderscore]{syntax}
+
\lstset{basicstyle=\ttfamily}
\def\B#1{{\tt\textbackslash{}#1}}
@@ -214,6 +217,7 @@ YOSYS & Yosys Open SYnthesis Suite \\
\label{commandref}
\input{command-reference-manual}
+\include{CHAPTER_TextRtlil}
\include{CHAPTER_Appnotes}
% \include{CHAPTER_StateOfTheArt}
diff --git a/passes/sat/freduce.cc b/passes/sat/freduce.cc
index 762edfdfb..f87b85da9 100644
--- a/passes/sat/freduce.cc
+++ b/passes/sat/freduce.cc
@@ -27,6 +27,7 @@
#include <stdio.h>
#include <string.h>
#include <algorithm>
+#include <limits>
USING_YOSYS_NAMESPACE
PRIVATE_NAMESPACE_BEGIN
diff --git a/techlibs/nexus/arith_map.v b/techlibs/nexus/arith_map.v
index fd9d61be3..ce14a15ea 100644
--- a/techlibs/nexus/arith_map.v
+++ b/techlibs/nexus/arith_map.v
@@ -88,9 +88,9 @@ module _80_nexus_alu (A, B, CI, BI, X, Y, CO);
.COUT(FCO[i+2])
);
- assign CO[i] = (AA[i] && BB[i]) || (((i == 0) ? CI : CO[i-1]) && (AA[i] || BB[i]));
+ assign CO[i] = (AA[i] && BB[i]) || ((Y[i] ^ AA[i] ^ BB[i]) && (AA[i] || BB[i]));
if (i+1 < Y_WIDTH) begin
- assign CO[i+1] = (AA[i+1] && BB[i+1]) || (CO[i] && (AA[i+1] || BB[i+1]));
+ assign CO[i + 1] = (AA[i] && BB[i]) || ((Y[i] ^ AA[i] ^ BB[i]) && (AA[i] || BB[i]));
assign Y[i+1] = Y1[i];
end
end endgenerate
generated by cgit v1.2.3 (git 2.25.1) at 2025-04-03 15:16:05 +0000