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-rw-r--r--frontends/aiger/Makefile.inc3
-rw-r--r--frontends/aiger/aigerparse.cc213
-rw-r--r--frontends/aiger/aigerparse.h31
-rw-r--r--tests/aiger/and.aag5
-rw-r--r--tests/aiger/buffer.aag3
-rw-r--r--tests/aiger/cnt1.aag3
-rw-r--r--tests/aiger/cnt1e.aag8
-rw-r--r--tests/aiger/empty.aag1
-rw-r--r--tests/aiger/false.aag2
-rw-r--r--tests/aiger/halfadder.aag14
-rw-r--r--tests/aiger/inverter.aag3
-rw-r--r--tests/aiger/notcnt1.aag4
-rw-r--r--tests/aiger/notcnt1e.aag8
-rw-r--r--tests/aiger/or.aag5
-rwxr-xr-xtests/aiger/run-test.sh20
-rw-r--r--tests/aiger/toggle-re.aag14
-rw-r--r--tests/aiger/toggle.aag4
-rw-r--r--tests/aiger/true.aag2
-rwxr-xr-xtests/tools/autotest.sh15
19 files changed, 354 insertions, 4 deletions
diff --git a/frontends/aiger/Makefile.inc b/frontends/aiger/Makefile.inc
new file mode 100644
index 000000000..bc1112452
--- /dev/null
+++ b/frontends/aiger/Makefile.inc
@@ -0,0 +1,3 @@
+
+OBJS += frontends/aiger/aigerparse.o
+
diff --git a/frontends/aiger/aigerparse.cc b/frontends/aiger/aigerparse.cc
new file mode 100644
index 000000000..c7a9aecb9
--- /dev/null
+++ b/frontends/aiger/aigerparse.cc
@@ -0,0 +1,213 @@
+/*
+ * yosys -- Yosys Open SYnthesis Suite
+ *
+ * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
+ * Eddie Hung <eddie@fpgeh.com>
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ */
+
+// [[CITE]] The AIGER And-Inverter Graph (AIG) Format Version 20071012
+// Armin Biere. The AIGER And-Inverter Graph (AIG) Format Version 20071012. Technical Report 07/1, October 2011, FMV Reports Series, Institute for Formal Models and Verification, Johannes Kepler University, Altenbergerstr. 69, 4040 Linz, Austria.
+// http://fmv.jku.at/papers/Biere-FMV-TR-07-1.pdf
+
+#include "kernel/yosys.h"
+#include "kernel/sigtools.h"
+#include "aigerparse.h"
+
+YOSYS_NAMESPACE_BEGIN
+
+#define log_debug log
+
+void parse_aiger(RTLIL::Design *design, std::istream &f, std::string clk_name)
+{
+ std::string header;
+ f >> header;
+ if (header != "aag") {
+ log_error("Unsupported AIGER file!\n");
+ return;
+ }
+
+ int M, I, L, O, A;
+ int B=0, C=0, J=0, F=0; // Optional in AIGER 1.9
+ if (!(f >> M >> I >> L >> O >> A)) {
+ log_error("Invalid AIGER header\n");
+ return;
+ }
+ for (auto &i : std::array<std::reference_wrapper<int>,4>{B, C, J, F}) {
+ if (f.peek() != ' ') break;
+ if (!(f >> i)) {
+ log_error("Invalid AIGER header\n");
+ return;
+ }
+ }
+
+ std::string line;
+ std::getline(f, line); // Ignore up to start of next ine, as standard
+ // says anything that follows could be used for
+ // optional sections
+
+ log_debug("M=%d I=%d L=%d O=%d A=%d B=%d C=%d J=%d F=%d\n", M, I, L, O, A, B, C, J, F);
+
+ int line_count = 1;
+ std::stringstream ss;
+
+ auto module = new RTLIL::Module;
+ module->name = RTLIL::escape_id("aig"); // TODO: Name?
+ if (design->module(module->name))
+ log_error("Duplicate definition of module %s in line %d!\n", log_id(module->name), line_count);
+ design->add(module);
+
+ auto createWireIfNotExists = [module](int literal) {
+ const int variable = literal >> 1;
+ const bool invert = literal & 1;
+ RTLIL::IdString wire_name(stringf("\\n%d%s", variable, invert ? "_inv" : "")); // FIXME: is "_inv" the right suffix?
+ RTLIL::Wire *wire = module->wire(wire_name);
+ if (wire) return wire;
+ log_debug("Creating %s\n", wire_name.c_str());
+ wire = module->addWire(wire_name);
+ if (!invert) return wire;
+ RTLIL::IdString wire_inv_name(stringf("\\n%d", variable));
+ RTLIL::Wire *wire_inv = module->wire(wire_inv_name);
+ if (wire_inv) {
+ if (module->cell(wire_inv_name)) return wire;
+ }
+ else {
+ log_debug("Creating %s\n", wire_inv_name.c_str());
+ wire_inv = module->addWire(wire_inv_name);
+ }
+
+ log_debug("Creating %s = ~%s\n", wire_name.c_str(), wire_inv_name.c_str());
+ RTLIL::Cell *inv = module->addCell(stringf("\\n%d_not", variable), "$_NOT_"); // FIXME: is "_not" the right suffix?
+ inv->setPort("\\A", wire_inv);
+ inv->setPort("\\Y", wire);
+
+ return wire;
+ };
+
+ int l1, l2, l3;
+
+ // Parse inputs
+ for (int i = 0; i < I; ++i, ++line_count) {
+ if (!(f >> l1)) {
+ log_error("Line %d cannot be interpreted as an input!\n", line_count);
+ return;
+ }
+ log_debug("%d is an input\n", l1);
+ log_assert(!(l1 & 1)); // TODO: Inputs can't be inverted?
+ RTLIL::Wire *wire = createWireIfNotExists(l1);
+ wire->port_input = true;
+ }
+
+ // Parse latches
+ for (int i = 0; i < L; ++i, ++line_count) {
+ if (!(f >> l1 >> l2)) {
+ log_error("Line %d cannot be interpreted as a latch!\n", line_count);
+ return;
+ }
+ log_debug("%d %d is a latch\n", l1, l2);
+ log_assert(!(l1 & 1)); // TODO: Latch outputs can't be inverted?
+ RTLIL::Wire *q_wire = createWireIfNotExists(l1);
+ RTLIL::Wire *d_wire = createWireIfNotExists(l2);
+ RTLIL::IdString clk_id = RTLIL::escape_id(clk_name.c_str());
+ RTLIL::Wire *clk_wire = module->wire(clk_id);
+ if (!clk_wire) {
+ log_debug("Creating %s\n", clk_id.c_str());
+ clk_wire = module->addWire(clk_id);
+ clk_wire->port_input = true;
+ }
+
+ module->addDff(NEW_ID, clk_wire, d_wire, q_wire);
+ // AIGER latches are assumed to be initialized to zero
+ q_wire->attributes["\\init"] = RTLIL::Const(0);
+ }
+
+ // Parse outputs
+ for (int i = 0; i < O; ++i, ++line_count) {
+ if (!(f >> l1)) {
+ log_error("Line %d cannot be interpreted as an output!\n", line_count);
+ return;
+ }
+
+ log_debug("%d is an output\n", l1);
+ RTLIL::Wire *wire = createWireIfNotExists(l1);
+ wire->port_output = true;
+ }
+ std::getline(f, line); // Ignore up to start of next line
+
+ // TODO: Parse bad state properties
+ for (int i = 0; i < B; ++i, ++line_count)
+ std::getline(f, line); // Ignore up to start of next line
+
+ // TODO: Parse invariant constraints
+ for (int i = 0; i < C; ++i, ++line_count)
+ std::getline(f, line); // Ignore up to start of next line
+
+ // TODO: Parse justice properties
+ for (int i = 0; i < J; ++i, ++line_count)
+ std::getline(f, line); // Ignore up to start of next line
+
+ // TODO: Parse fairness constraints
+ for (int i = 0; i < F; ++i, ++line_count)
+ std::getline(f, line); // Ignore up to start of next line
+
+ // Parse AND
+ for (int i = 0; i < A; ++i, ++line_count) {
+ if (!(f >> l1 >> l2 >> l3)) {
+ log_error("Line %d cannot be interpreted as an AND!\n", line_count);
+ return;
+ }
+
+ log_debug("%d %d %d is an AND\n", l1, l2, l3);
+ log_assert(!(l1 & 1)); // TODO: Output of ANDs can't be inverted?
+ RTLIL::Wire *o_wire = createWireIfNotExists(l1);
+ RTLIL::Wire *i1_wire = createWireIfNotExists(l2);
+ RTLIL::Wire *i2_wire = createWireIfNotExists(l3);
+
+ RTLIL::Cell *and_cell = module->addCell(NEW_ID, "$_AND_");
+ and_cell->setPort("\\A", i1_wire);
+ and_cell->setPort("\\B", i2_wire);
+ and_cell->setPort("\\Y", o_wire);
+ }
+
+ module->fixup_ports();
+}
+
+struct AigerFrontend : public Frontend {
+ AigerFrontend() : Frontend("aiger", "read AIGER file") { }
+ void help() YS_OVERRIDE
+ {
+ // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
+ log("\n");
+ log(" read_aiger [options] [filename]\n");
+ log("\n");
+ log("Load modules from an AIGER file into the current design.\n");
+ log("\n");
+ }
+ void execute(std::istream *&f, std::string filename, std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
+ {
+ log_header(design, "Executing AIGER frontend.\n");
+
+ size_t argidx;
+ for (argidx = 1; argidx < args.size(); argidx++) {
+ std::string arg = args[argidx];
+ break;
+ }
+ extra_args(f, filename, args, argidx);
+
+ parse_aiger(design, *f);
+ }
+} AigerFrontend;
+
+YOSYS_NAMESPACE_END
diff --git a/frontends/aiger/aigerparse.h b/frontends/aiger/aigerparse.h
new file mode 100644
index 000000000..6a250aa67
--- /dev/null
+++ b/frontends/aiger/aigerparse.h
@@ -0,0 +1,31 @@
+/*
+ * yosys -- Yosys Open SYnthesis Suite
+ *
+ * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ */
+
+#ifndef ABC_AIGERPARSE
+#define ABC_AIGERPARSE
+
+#include "kernel/yosys.h"
+
+YOSYS_NAMESPACE_BEGIN
+
+extern void parse_aiger(RTLIL::Design *design, std::istream &f, std::string clk_name="clk");
+
+YOSYS_NAMESPACE_END
+
+#endif
diff --git a/tests/aiger/and.aag b/tests/aiger/and.aag
new file mode 100644
index 000000000..d1ef2c5a5
--- /dev/null
+++ b/tests/aiger/and.aag
@@ -0,0 +1,5 @@
+aag 3 2 0 1 1
+2
+4
+6
+6 2 4
diff --git a/tests/aiger/buffer.aag b/tests/aiger/buffer.aag
new file mode 100644
index 000000000..94a6fb1ed
--- /dev/null
+++ b/tests/aiger/buffer.aag
@@ -0,0 +1,3 @@
+aag 1 1 0 1 0
+2
+2
diff --git a/tests/aiger/cnt1.aag b/tests/aiger/cnt1.aag
new file mode 100644
index 000000000..ce4f28fcb
--- /dev/null
+++ b/tests/aiger/cnt1.aag
@@ -0,0 +1,3 @@
+aag 1 0 1 0 0 1
+2 3
+2
diff --git a/tests/aiger/cnt1e.aag b/tests/aiger/cnt1e.aag
new file mode 100644
index 000000000..6db3f0ffd
--- /dev/null
+++ b/tests/aiger/cnt1e.aag
@@ -0,0 +1,8 @@
+aag 5 1 1 0 3 1
+2
+4 10
+4
+6 5 3
+8 4 2
+10 9 7
+b0 AIGER_NEVER
diff --git a/tests/aiger/empty.aag b/tests/aiger/empty.aag
new file mode 100644
index 000000000..40c0f00cb
--- /dev/null
+++ b/tests/aiger/empty.aag
@@ -0,0 +1 @@
+aag 0 0 0 0 0
diff --git a/tests/aiger/false.aag b/tests/aiger/false.aag
new file mode 100644
index 000000000..421e64a91
--- /dev/null
+++ b/tests/aiger/false.aag
@@ -0,0 +1,2 @@
+aag 0 0 0 1 0
+0
diff --git a/tests/aiger/halfadder.aag b/tests/aiger/halfadder.aag
new file mode 100644
index 000000000..5bf54d38d
--- /dev/null
+++ b/tests/aiger/halfadder.aag
@@ -0,0 +1,14 @@
+aag 7 2 0 2 3
+2
+4
+6
+12
+6 13 15
+12 2 4
+14 3 5
+i0 x
+i1 y
+o0 s
+o1 c
+c
+half adder
diff --git a/tests/aiger/inverter.aag b/tests/aiger/inverter.aag
new file mode 100644
index 000000000..ff7c28542
--- /dev/null
+++ b/tests/aiger/inverter.aag
@@ -0,0 +1,3 @@
+aag 1 1 0 1 0
+2
+3
diff --git a/tests/aiger/notcnt1.aag b/tests/aiger/notcnt1.aag
new file mode 100644
index 000000000..e92815f23
--- /dev/null
+++ b/tests/aiger/notcnt1.aag
@@ -0,0 +1,4 @@
+aag 1 0 1 0 0 1
+2 3
+3
+b0 AIGER_NEVER
diff --git a/tests/aiger/notcnt1e.aag b/tests/aiger/notcnt1e.aag
new file mode 100644
index 000000000..141c864f7
--- /dev/null
+++ b/tests/aiger/notcnt1e.aag
@@ -0,0 +1,8 @@
+aag 5 1 1 0 3 1
+2
+4 10
+5
+6 5 3
+8 4 2
+10 9 7
+b0 AIGER_NEVER
diff --git a/tests/aiger/or.aag b/tests/aiger/or.aag
new file mode 100644
index 000000000..f780e339f
--- /dev/null
+++ b/tests/aiger/or.aag
@@ -0,0 +1,5 @@
+aag 3 2 0 1 1
+2
+4
+7
+6 3 5
diff --git a/tests/aiger/run-test.sh b/tests/aiger/run-test.sh
new file mode 100755
index 000000000..308578f01
--- /dev/null
+++ b/tests/aiger/run-test.sh
@@ -0,0 +1,20 @@
+#!/bin/bash
+
+OPTIND=1
+seed="" # default to no seed specified
+while getopts "S:" opt
+do
+ case "$opt" in
+ S) arg="${OPTARG#"${OPTARG%%[![:space:]]*}"}" # remove leading space
+ seed="SEED=$arg" ;;
+ esac
+done
+shift "$((OPTIND-1))"
+
+# check for Icarus Verilog
+if ! which iverilog > /dev/null ; then
+ echo "$0: Error: Icarus Verilog 'iverilog' not found."
+ exit 1
+fi
+
+exec ${MAKE:-make} -f ../tools/autotest.mk $seed *.aag EXTRA_FLAGS="-f aiger"
diff --git a/tests/aiger/toggle-re.aag b/tests/aiger/toggle-re.aag
new file mode 100644
index 000000000..b662bb386
--- /dev/null
+++ b/tests/aiger/toggle-re.aag
@@ -0,0 +1,14 @@
+aag 7 2 1 2 4
+2
+4
+6 8
+6
+7
+8 4 10
+10 13 15
+12 2 6
+14 3 7
+i0 enable
+i1 reset
+o0 Q
+o1 !Q
diff --git a/tests/aiger/toggle.aag b/tests/aiger/toggle.aag
new file mode 100644
index 000000000..09651012d
--- /dev/null
+++ b/tests/aiger/toggle.aag
@@ -0,0 +1,4 @@
+aag 1 0 1 2 0
+2 3
+2
+3
diff --git a/tests/aiger/true.aag b/tests/aiger/true.aag
new file mode 100644
index 000000000..366893648
--- /dev/null
+++ b/tests/aiger/true.aag
@@ -0,0 +1,2 @@
+aag 0 0 0 1 0
+1
diff --git a/tests/tools/autotest.sh b/tests/tools/autotest.sh
index 800fa3ad5..3e1325b33 100755
--- a/tests/tools/autotest.sh
+++ b/tests/tools/autotest.sh
@@ -88,8 +88,9 @@ shift $((OPTIND - 1))
for fn
do
- bn=${fn%.v}
- if [ "$bn" == "$fn" ]; then
+ bn=${fn%.*}
+ ext=${fn##*.}
+ if [[ "$ext" != "v" ]] && [[ "$ext" != "aag" ]]; then
echo "Invalid argument: $fn" >&2
exit 1
fi
@@ -111,7 +112,12 @@ do
fn=$(basename $fn)
bn=$(basename $bn)
- egrep -v '^\s*`timescale' ../$fn > ${bn}_ref.v
+ if [[ "$ext" == "v" ]]; then
+ egrep -v '^\s*`timescale' ../$fn > ${bn}_ref.${ext}
+ else
+ "$toolsdir"/../../yosys -f "$frontend $include_opts" -b "verilog" -o ${bn}_ref.v ../${fn}
+ frontend="verilog"
+ fi
if [ ! -f ../${bn}_tb.v ]; then
"$toolsdir"/../../yosys -f "$frontend $include_opts" -b "test_autotb $autotb_opts" -o ${bn}_tb.v ${bn}_ref.v
@@ -119,7 +125,8 @@ do
cp ../${bn}_tb.v ${bn}_tb.v
fi
if $genvcd; then sed -i 's,// \$dump,$dump,g' ${bn}_tb.v; fi
- compile_and_run ${bn}_tb_ref ${bn}_out_ref ${bn}_tb.v ${bn}_ref.v $libs
+ compile_and_run ${bn}_tb_ref ${bn}_out_ref ${bn}_tb.v ${bn}_ref.v $libs \
+ "$toolsdir"/../../techlibs/common/simlib.v
if $genvcd; then mv testbench.vcd ${bn}_ref.vcd; fi
test_count=0
generated by cgit v1.2.3 (git 2.25.1) at 2025-05-02 02:30:55 +0000