diff options
41 files changed, 1835 insertions, 149 deletions
@@ -109,7 +109,7 @@ OBJS = kernel/version_$(GIT_REV).o # is just a symlink to your actual ABC working directory, as 'make mrproper' # will remove the 'abc' directory and you do not want to accidentally # delete your work on ABC.. -ABCREV = 14d985a +ABCREV = 2ddc57d ABCPULL = 1 ABCURL ?= https://github.com/berkeley-abc/abc ABCMKARGS = CC="$(CXX)" CXX="$(CXX)" ABC_USE_LIBSTDCXX=1 @@ -359,8 +359,12 @@ ifeq ($(ENABLE_VERIFIC),1) VERIFIC_DIR ?= /usr/local/src/verific_lib_eval VERIFIC_COMPONENTS ?= verilog vhdl database util containers sdf hier_tree CXXFLAGS += $(patsubst %,-I$(VERIFIC_DIR)/%,$(VERIFIC_COMPONENTS)) -DYOSYS_ENABLE_VERIFIC +ifeq ($(OS), Darwin) +LDLIBS += $(patsubst %,$(VERIFIC_DIR)/%/*-mac.a,$(VERIFIC_COMPONENTS)) -lz +else LDLIBS += $(patsubst %,$(VERIFIC_DIR)/%/*-linux.a,$(VERIFIC_COMPONENTS)) -lz endif +endif ifeq ($(ENABLE_PROTOBUF),1) LDLIBS += $(shell pkg-config --cflags --libs protobuf) @@ -595,7 +599,7 @@ vloghtb: $(TARGETS) $(EXTRA_TARGETS) ystests: $(TARGETS) $(EXTRA_TARGETS) rm -rf tests/ystests git clone https://github.com/YosysHQ/yosys-tests.git tests/ystests - +PATH="$$PWD:$$PATH" cd tests/ystests && $(MAKE) + +$(MAKE) PATH="$$PWD:$$PATH" -C tests/ystests @echo "" @echo " Finished \"make ystests\"." @echo "" diff --git a/backends/aiger/aiger.cc b/backends/aiger/aiger.cc index c323691a3..dfe506c66 100644 --- a/backends/aiger/aiger.cc +++ b/backends/aiger/aiger.cc @@ -100,7 +100,7 @@ struct AigerWriter return aig_map.at(bit); } - AigerWriter(Module *module, bool zinit_mode) : module(module), zinit_mode(zinit_mode), sigmap(module) + AigerWriter(Module *module, bool zinit_mode, bool imode, bool omode, bool bmode) : module(module), zinit_mode(zinit_mode), sigmap(module) { pool<SigBit> undriven_bits; pool<SigBit> unused_bits; @@ -293,6 +293,10 @@ struct AigerWriter aig_map[bit] = 2*aig_m; } + if (imode && input_bits.empty()) { + aig_m++, aig_i++; + } + if (zinit_mode) { for (auto it : ff_map) { @@ -371,6 +375,11 @@ struct AigerWriter aig_outputs.push_back(bit2aig(bit)); } + if (omode && output_bits.empty()) { + aig_o++; + aig_outputs.push_back(0); + } + for (auto it : asserts) { aig_b++; int bit_a = bit2aig(it.first); @@ -378,6 +387,11 @@ struct AigerWriter aig_outputs.push_back(mkgate(bit_a^1, bit_en)); } + if (bmode && asserts.empty()) { + aig_b++; + aig_outputs.push_back(0); + } + for (auto it : assumes) { aig_c++; int bit_a = bit2aig(it.first); @@ -689,6 +703,11 @@ struct AigerBackend : public Backend { log(" -vmap <filename>\n"); log(" like -map, but more verbose\n"); log("\n"); + log(" -I, -O, -B\n"); + log(" If the design contains no input/output/assert then create one\n"); + log(" dummy input/output/bad_state pin to make the tools reading the\n"); + log(" AIGER file happy.\n"); + log("\n"); } void execute(std::ostream *&f, std::string filename, std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE { @@ -697,6 +716,9 @@ struct AigerBackend : public Backend { bool miter_mode = false; bool symbols_mode = false; bool verbose_map = false; + bool imode = false; + bool omode = false; + bool bmode = false; std::string map_filename; log_header(design, "Executing AIGER backend.\n"); @@ -729,6 +751,18 @@ struct AigerBackend : public Backend { verbose_map = true; continue; } + if (args[argidx] == "-I") { + imode = true; + continue; + } + if (args[argidx] == "-O") { + omode = true; + continue; + } + if (args[argidx] == "-B") { + bmode = true; + continue; + } break; } extra_args(f, filename, args, argidx); @@ -738,7 +772,7 @@ struct AigerBackend : public Backend { if (top_module == nullptr) log_error("Can't find top module in current design!\n"); - AigerWriter writer(top_module, zinit_mode); + AigerWriter writer(top_module, zinit_mode, imode, omode, bmode); writer.write_aiger(*f, ascii_mode, miter_mode, symbols_mode); if (!map_filename.empty()) { diff --git a/backends/smt2/smt2.cc b/backends/smt2/smt2.cc index e2777ae04..418f8d766 100644 --- a/backends/smt2/smt2.cc +++ b/backends/smt2/smt2.cc @@ -554,7 +554,9 @@ struct Smt2Worker if (cell->type.in("$shift", "$shiftx")) { if (cell->getParam("\\B_SIGNED").as_bool()) { - /* FIXME */ + return export_bvop(cell, stringf("(ite (bvsge B #b%0*d) " + "(bvlshr A B) (bvlshr A (bvneg B)))", + GetSize(cell->getPort("\\B")), 0), 's'); } else { return export_bvop(cell, "(bvlshr A B)", 's'); } diff --git a/backends/smt2/smtbmc.py b/backends/smt2/smtbmc.py index 6af2a5ac1..b944ee004 100644 --- a/backends/smt2/smtbmc.py +++ b/backends/smt2/smtbmc.py @@ -1259,7 +1259,11 @@ elif covermode: smt_assert_antecedent("(|%s_t| s%d s%d)" % (topmod, i-1, i)) smt_assert_consequent(get_constr_expr(constr_assumes, i)) print_msg("Re-solving with appended steps..") - assert smt_check_sat() == "sat" + if smt_check_sat() == "unsat": + print("%s Cannot appended steps without violating assumptions!" % smt.timestamp()) + found_failed_assert = True + retstatus = False + break reached_covers = smt.bv2bin(smt.get("(covers_%d s%d)" % (coveridx, step))) assert len(reached_covers) == len(cover_desc) @@ -1377,7 +1381,11 @@ else: # not tempind, covermode smt_assert_antecedent("(|%s_h| s%d)" % (topmod, i)) smt_assert_antecedent("(|%s_t| s%d s%d)" % (topmod, i-1, i)) smt_assert_consequent(get_constr_expr(constr_assumes, i)) - assert smt_check_sat() == "sat" + print_msg("Re-solving with appended steps..") + if smt_check_sat() == "unsat": + print("%s Cannot appended steps without violating assumptions!" % smt.timestamp()) + retstatus = False + break print_anyconsts(step) for i in range(step, last_check_step+1): print_failed_asserts(i) diff --git a/backends/smt2/smtio.py b/backends/smt2/smtio.py index 3fc823e3e..68783e744 100644 --- a/backends/smt2/smtio.py +++ b/backends/smt2/smtio.py @@ -31,11 +31,19 @@ from threading import Thread # does not run out of stack frames when parsing large expressions if os.name == "posix": smtio_reclimit = 64 * 1024 - smtio_stacksize = 128 * 1024 * 1024 if sys.getrecursionlimit() < smtio_reclimit: sys.setrecursionlimit(smtio_reclimit) - if resource.getrlimit(resource.RLIMIT_STACK)[0] < smtio_stacksize: - resource.setrlimit(resource.RLIMIT_STACK, (smtio_stacksize, -1)) + + current_rlimit_stack = resource.getrlimit(resource.RLIMIT_STACK) + if current_rlimit_stack[0] != resource.RLIM_INFINITY: + smtio_stacksize = 128 * 1024 * 1024 + if os.uname().sysname == "Darwin": + # MacOS has rather conservative stack limits + smtio_stacksize = 16 * 1024 * 1024 + if current_rlimit_stack[1] != resource.RLIM_INFINITY: + smtio_stacksize = min(smtio_stacksize, current_rlimit_stack[1]) + if current_rlimit_stack[0] < smtio_stacksize: + resource.setrlimit(resource.RLIMIT_STACK, (smtio_stacksize, current_rlimit_stack[1])) # currently running solvers (so we can kill them) @@ -158,19 +166,28 @@ class SmtIo: self.unroll = False if self.solver == "yices": - self.popen_vargs = ['yices-smt2', '--incremental'] + self.solver_opts + if self.noincr: + self.popen_vargs = ['yices-smt2'] + self.solver_opts + else: + self.popen_vargs = ['yices-smt2', '--incremental'] + self.solver_opts if self.solver == "z3": self.popen_vargs = ['z3', '-smt2', '-in'] + self.solver_opts if self.solver == "cvc4": - self.popen_vargs = ['cvc4', '--incremental', '--lang', 'smt2.6' if self.logic_dt else 'smt2'] + self.solver_opts + if self.noincr: + self.popen_vargs = ['cvc4', '--lang', 'smt2.6' if self.logic_dt else 'smt2'] + self.solver_opts + else: + self.popen_vargs = ['cvc4', '--incremental', '--lang', 'smt2.6' if self.logic_dt else 'smt2'] + self.solver_opts if self.solver == "mathsat": self.popen_vargs = ['mathsat'] + self.solver_opts if self.solver == "boolector": - self.popen_vargs = ['boolector', '--smt2', '-i'] + self.solver_opts + if self.noincr: + self.popen_vargs = ['boolector', '--smt2'] + self.solver_opts + else: + self.popen_vargs = ['boolector', '--smt2', '-i'] + self.solver_opts self.unroll = True if self.solver == "abc": diff --git a/frontends/ast/ast.cc b/frontends/ast/ast.cc index cc275959a..2c1561552 100644 --- a/frontends/ast/ast.cc +++ b/frontends/ast/ast.cc @@ -172,8 +172,7 @@ bool AstNode::get_bool_attribute(RTLIL::IdString id) AstNode *attr = attributes.at(id); if (attr->type != AST_CONSTANT) - log_file_error(attr->filename, attr->linenum, "Attribute `%s' with non-constant value!\n", - id.c_str()); + log_file_error(attr->filename, attr->linenum, "Attribute `%s' with non-constant value!\n", id.c_str()); return attr->integer != 0; } @@ -969,8 +968,7 @@ static AstModule* process_module(AstNode *ast, bool defer, AstNode *original_ast for (auto &attr : ast->attributes) { if (attr.second->type != AST_CONSTANT) - log_file_error(ast->filename, ast->linenum, "Attribute `%s' with non-constant value!\n", - attr.first.c_str()); + log_file_error(ast->filename, ast->linenum, "Attribute `%s' with non-constant value!\n", attr.first.c_str()); current_module->attributes[attr.first] = attr.second->asAttrConst(); } for (size_t i = 0; i < ast->children.size(); i++) { @@ -1061,8 +1059,7 @@ void AST::process(RTLIL::Design *design, AstNode *ast, bool dump_ast1, bool dump if (design->has((*it)->str)) { RTLIL::Module *existing_mod = design->module((*it)->str); if (!nooverwrite && !overwrite && !existing_mod->get_bool_attribute("\\blackbox")) { - log_file_error((*it)->filename, (*it)->linenum, "Re-definition of module `%s'!\n", - (*it)->str.c_str()); + log_file_error((*it)->filename, (*it)->linenum, "Re-definition of module `%s'!\n", (*it)->str.c_str()); } else if (nooverwrite) { log("Ignoring re-definition of module `%s' at %s:%d.\n", (*it)->str.c_str(), (*it)->filename.c_str(), (*it)->linenum); diff --git a/frontends/ast/genrtlil.cc b/frontends/ast/genrtlil.cc index 59c309665..9531dd356 100644 --- a/frontends/ast/genrtlil.cc +++ b/frontends/ast/genrtlil.cc @@ -55,8 +55,7 @@ static RTLIL::SigSpec uniop2rtlil(AstNode *that, std::string type, int result_wi if (gen_attributes) for (auto &attr : that->attributes) { if (attr.second->type != AST_CONSTANT) - log_file_error(that->filename, that->linenum, "Attribute `%s' with non-constant value!\n", - attr.first.c_str()); + log_file_error(that->filename, that->linenum, "Attribute `%s' with non-constant value!\n", attr.first.c_str()); cell->attributes[attr.first] = attr.second->asAttrConst(); } @@ -89,8 +88,7 @@ static void widthExtend(AstNode *that, RTLIL::SigSpec &sig, int width, bool is_s if (that != NULL) for (auto &attr : that->attributes) { if (attr.second->type != AST_CONSTANT) - log_file_error(that->filename, that->linenum, "Attribute `%s' with non-constant value!\n", - attr.first.c_str()); + log_file_error(that->filename, that->linenum, "Attribute `%s' with non-constant value!\n", attr.first.c_str()); cell->attributes[attr.first] = attr.second->asAttrConst(); } @@ -117,8 +115,7 @@ static RTLIL::SigSpec binop2rtlil(AstNode *that, std::string type, int result_wi for (auto &attr : that->attributes) { if (attr.second->type != AST_CONSTANT) - log_file_error(that->filename, that->linenum, "Attribute `%s' with non-constant value!\n", - attr.first.c_str()); + log_file_error(that->filename, that->linenum, "Attribute `%s' with non-constant value!\n", attr.first.c_str()); cell->attributes[attr.first] = attr.second->asAttrConst(); } @@ -152,8 +149,7 @@ static RTLIL::SigSpec mux2rtlil(AstNode *that, const RTLIL::SigSpec &cond, const for (auto &attr : that->attributes) { if (attr.second->type != AST_CONSTANT) - log_file_error(that->filename, that->linenum, "Attribute `%s' with non-constant value!\n", - attr.first.c_str()); + log_file_error(that->filename, that->linenum, "Attribute `%s' with non-constant value!\n", attr.first.c_str()); cell->attributes[attr.first] = attr.second->asAttrConst(); } @@ -480,8 +476,7 @@ struct AST_INTERNAL::ProcessGenerator for (auto &attr : ast->attributes) { if (attr.second->type != AST_CONSTANT) - log_file_error(ast->filename, ast->linenum, "Attribute `%s' with non-constant value!\n", - attr.first.c_str()); + log_file_error(ast->filename, ast->linenum, "Attribute `%s' with non-constant value!\n", attr.first.c_str()); sw->attributes[attr.first] = attr.second->asAttrConst(); } @@ -648,8 +643,7 @@ void AstNode::detectSignWidthWorker(int &width_hint, bool &sign_hint, bool *foun while (left_at_zero_ast->simplify(true, true, false, 1, -1, false, false)) { } while (right_at_zero_ast->simplify(true, true, false, 1, -1, false, false)) { } if (left_at_zero_ast->type != AST_CONSTANT || right_at_zero_ast->type != AST_CONSTANT) - log_file_error(filename, linenum, "Unsupported expression on dynamic range select on signal `%s'!\n", - str.c_str()); + log_file_error(filename, linenum, "Unsupported expression on dynamic range select on signal `%s'!\n", str.c_str()); this_width = left_at_zero_ast->integer - right_at_zero_ast->integer + 1; delete left_at_zero_ast; delete right_at_zero_ast; @@ -778,7 +772,7 @@ void AstNode::detectSignWidthWorker(int &width_hint, bool &sign_hint, bool *foun while (children[0]->simplify(true, false, false, 1, -1, false, true) == true) { } if (children[0]->type != AST_CONSTANT) log_file_error(filename, linenum, "System function %s called with non-const argument!\n", - RTLIL::unescape_id(str).c_str()); + RTLIL::unescape_id(str).c_str()); width_hint = max(width_hint, int(children[0]->asInt(true))); } break; @@ -799,8 +793,7 @@ void AstNode::detectSignWidthWorker(int &width_hint, bool &sign_hint, bool *foun default: for (auto f : log_files) current_ast->dumpAst(f, "verilog-ast> "); - log_file_error(filename, linenum, "Don't know how to detect sign and width for %s node!\n", - type2str(type).c_str()); + log_file_error(filename, linenum, "Don't know how to detect sign and width for %s node!\n", type2str(type).c_str()); } if (*found_real) @@ -892,11 +885,9 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint) // create an RTLIL::Wire for an AST_WIRE node case AST_WIRE: { if (current_module->wires_.count(str) != 0) - log_file_error(filename, linenum, "Re-definition of signal `%s'!\n", - str.c_str()); + log_file_error(filename, linenum, "Re-definition of signal `%s'!\n", str.c_str()); if (!range_valid) - log_file_error(filename, linenum, "Signal `%s' with non-constant width!\n", - str.c_str()); + log_file_error(filename, linenum, "Signal `%s' with non-constant width!\n", str.c_str()); log_assert(range_left >= range_right || (range_left == -1 && range_right == 0)); @@ -910,8 +901,7 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint) for (auto &attr : attributes) { if (attr.second->type != AST_CONSTANT) - log_file_error(filename, linenum, "Attribute `%s' with non-constant value!\n", - attr.first.c_str()); + log_file_error(filename, linenum, "Attribute `%s' with non-constant value!\n", attr.first.c_str()); wire->attributes[attr.first] = attr.second->asAttrConst(); } } @@ -920,16 +910,14 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint) // create an RTLIL::Memory for an AST_MEMORY node case AST_MEMORY: { if (current_module->memories.count(str) != 0) - log_file_error(filename, linenum, "Re-definition of memory `%s'!\n", - str.c_str()); + log_file_error(filename, linenum, "Re-definition of memory `%s'!\n", str.c_str()); log_assert(children.size() >= 2); log_assert(children[0]->type == AST_RANGE); log_assert(children[1]->type == AST_RANGE); if (!children[0]->range_valid || !children[1]->range_valid) - log_file_error(filename, linenum, "Memory `%s' with non-constant width or size!\n", - str.c_str()); + log_file_error(filename, linenum, "Memory `%s' with non-constant width or size!\n", str.c_str()); RTLIL::Memory *memory = new RTLIL::Memory; memory->attributes["\\src"] = stringf("%s:%d", filename.c_str(), linenum); @@ -946,8 +934,7 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint) for (auto &attr : attributes) { if (attr.second->type != AST_CONSTANT) - log_file_error(filename, linenum, "Attribute `%s' with non-constant value!\n", - attr.first.c_str()); + log_file_error(filename, linenum, "Attribute `%s' with non-constant value!\n", attr.first.c_str()); memory->attributes[attr.first] = attr.second->asAttrConst(); } } @@ -966,8 +953,7 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint) case AST_REALVALUE: { RTLIL::SigSpec sig = realAsConst(width_hint); - log_file_warning(filename, linenum, "converting real value %e to binary %s.\n", - realvalue, log_signal(sig)); + log_file_warning(filename, linenum, "converting real value %e to binary %s.\n", realvalue, log_signal(sig)); return sig; } @@ -994,8 +980,7 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint) } else if (id2ast->type == AST_PARAMETER || id2ast->type == AST_LOCALPARAM) { if (id2ast->children[0]->type != AST_CONSTANT) - log_file_error(filename, linenum, "Parameter %s does not evaluate to constant value!\n", - str.c_str()); + log_file_error(filename, linenum, "Parameter %s does not evaluate to constant value!\n", str.c_str()); chunk = RTLIL::Const(id2ast->children[0]->bits); goto use_const_chunk; } @@ -1010,13 +995,11 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint) is_interface = true; } else { - log_file_error(filename, linenum, "Identifier `%s' doesn't map to any signal!\n", - str.c_str()); + log_file_error(filename, linenum, "Identifier `%s' doesn't map to any signal!\n", str.c_str()); } if (id2ast->type == AST_MEMORY) - log_file_error(filename, linenum, "Identifier `%s' does map to an unexpanded memory!\n", - str.c_str()); + log_file_error(filename, linenum, "Identifier `%s' does map to an unexpanded memory!\n", str.c_str()); // If identifier is an interface, create a RTLIL::SigSpec with a dummy wire with a attribute called 'is_interface' // This makes it possible for the hierarchy pass to see what are interface connections and then replace them @@ -1051,8 +1034,7 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint) while (left_at_zero_ast->simplify(true, true, false, 1, -1, false, false)) { } while (right_at_zero_ast->simplify(true, true, false, 1, -1, false, false)) { } if (left_at_zero_ast->type != AST_CONSTANT || right_at_zero_ast->type != AST_CONSTANT) - log_file_error(filename, linenum, "Unsupported expression on dynamic range select on signal `%s'!\n", - str.c_str()); + log_file_error(filename, linenum, "Unsupported expression on dynamic range select on signal `%s'!\n", str.c_str()); int width = left_at_zero_ast->integer - right_at_zero_ast->integer + 1; AstNode *fake_ast = new AstNode(AST_NONE, clone(), children[0]->children.size() >= 2 ? children[0]->children[1]->clone() : children[0]->children[0]->clone()); @@ -1081,7 +1063,7 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint) if (chunk.offset >= source_width || chunk.offset + chunk.width < 0) { if (chunk.width == 1) log_file_warning(filename, linenum, "Range select out of bounds on signal `%s': Setting result bit to undef.\n", - str.c_str()); + str.c_str()); else log_file_warning(filename, linenum, "Range select [%d:%d] out of bounds on signal `%s': Setting all %d result bits to undef.\n", children[0]->range_left, children[0]->range_right, str.c_str(), chunk.width); @@ -1098,10 +1080,10 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint) } if (add_undef_bits_lsb) log_file_warning(filename, linenum, "Range [%d:%d] select out of bounds on signal `%s': Setting %d LSB bits to undef.\n", - children[0]->range_left, children[0]->range_right, str.c_str(), add_undef_bits_lsb); + children[0]->range_left, children[0]->range_right, str.c_str(), add_undef_bits_lsb); if (add_undef_bits_msb) log_file_warning(filename, linenum, "Range [%d:%d] select out of bounds on signal `%s': Setting %d MSB bits to undef.\n", - children[0]->range_left, children[0]->range_right, str.c_str(), add_undef_bits_msb); + children[0]->range_left, children[0]->range_right, str.c_str(), add_undef_bits_msb); } } } @@ -1436,8 +1418,7 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint) for (auto &attr : attributes) { if (attr.second->type != AST_CONSTANT) - log_file_error(filename, linenum, "Attribute `%s' with non-constant value!\n", - attr.first.c_str()); + log_file_error(filename, linenum, "Attribute `%s' with non-constant value!\n", attr.first.c_str()); cell->attributes[attr.first] = attr.second->asAttrConst(); } @@ -1459,9 +1440,9 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint) new_right.append(right[i]); } log_file_warning(filename, linenum, "Ignoring assignment to constant bits:\n" - " old assignment: %s = %s\n new assignment: %s = %s.\n", - log_signal(left), log_signal(right), - log_signal(new_left), log_signal(new_right)); + " old assignment: %s = %s\n new assignment: %s = %s.\n", + log_signal(left), log_signal(right), + log_signal(new_left), log_signal(new_right)); left = new_left; right = new_right; } @@ -1494,14 +1475,14 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint) IdString paraname = child->str.empty() ? stringf("$%d", ++para_counter) : child->str; if (child->children[0]->type == AST_REALVALUE) { log_file_warning(filename, linenum, "Replacing floating point parameter %s.%s = %f with string.\n", - log_id(cell), log_id(paraname), child->children[0]->realvalue); + log_id(cell), log_id(paraname), child->children[0]->realvalue); auto strnode = AstNode::mkconst_str(stringf("%f", child->children[0]->realvalue)); strnode->cloneInto(child->children[0]); delete strnode; } if (child->children[0]->type != AST_CONSTANT) log_file_error(filename, linenum, "Parameter %s.%s with non-constant value!\n", - log_id(cell), log_id(paraname)); + log_id(cell), log_id(paraname)); cell->parameters[paraname] = child->children[0]->asParaConst(); continue; } @@ -1522,8 +1503,7 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint) } for (auto &attr : attributes) { if (attr.second->type != AST_CONSTANT) - log_file_error(filename, linenum, "Attribute `%s' with non-constant value!\n", - attr.first.c_str()); + log_file_error(filename, linenum, "Attribute `%s' with non-constant value!\n", attr.first.c_str()); cell->attributes[attr.first] = attr.second->asAttrConst(); } } @@ -1551,18 +1531,17 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint) if (GetSize(children) > 1) log_file_error(filename, linenum, "System function %s got %d arguments, expected 1 or 0.\n", - RTLIL::unescape_id(str).c_str(), GetSize(children)); + RTLIL::unescape_id(str).c_str(), GetSize(children)); if (GetSize(children) == 1) { if (children[0]->type != AST_CONSTANT) log_file_error(filename, linenum, "System function %s called with non-const argument!\n", - RTLIL::unescape_id(str).c_str()); + RTLIL::unescape_id(str).c_str()); width = children[0]->asInt(true); } if (width <= 0) - log_file_error(filename, linenum, "Failed to detect width of %s!\n", - RTLIL::unescape_id(str).c_str()); + log_file_error(filename, linenum, "Failed to detect width of %s!\n", RTLIL::unescape_id(str).c_str()); Cell *cell = current_module->addCell(myid, str.substr(1)); cell->attributes["\\src"] = stringf("%s:%d", filename.c_str(), linenum); @@ -1589,8 +1568,7 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint) for (auto f : log_files) current_ast->dumpAst(f, "verilog-ast> "); type_name = type2str(type); - log_file_error(filename, linenum, "Don't know how to generate RTLIL code for %s node!\n", - type_name.c_str()); + log_file_error(filename, linenum, "Don't know how to generate RTLIL code for %s node!\n", type_name.c_str()); } return RTLIL::SigSpec(); diff --git a/frontends/ast/simplify.cc b/frontends/ast/simplify.cc index e56a62563..bb4c9735d 100644 --- a/frontends/ast/simplify.cc +++ b/frontends/ast/simplify.cc @@ -196,7 +196,7 @@ bool AstNode::simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage, int nargs = GetSize(children); if (nargs < 1) log_file_error(filename, linenum, "System task `%s' got %d arguments, expected >= 1.\n", - str.c_str(), int(children.size())); + str.c_str(), int(children.size())); // First argument is the format string AstNode *node_string = children[0]; @@ -240,7 +240,7 @@ bool AstNode::simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage, case 'X': if (next_arg >= GetSize(children)) log_file_error(filename, linenum, "Missing argument for %%%c format specifier in system task `%s'.\n", - cformat, str.c_str()); + cformat, str.c_str()); node_arg = children[next_arg++]; while (node_arg->simplify(true, false, false, stage, width_hint, sign_hint, false)) { } @@ -450,8 +450,21 @@ bool AstNode::simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage, children[0]->id2ast->is_reg = true; // if logic type is used in a block asignment if ((type == AST_ASSIGN_LE || type == AST_ASSIGN_EQ) && !children[0]->id2ast->is_reg) log_warning("wire '%s' is assigned in a block at %s:%d.\n", children[0]->str.c_str(), filename.c_str(), linenum); - if (type == AST_ASSIGN && children[0]->id2ast->is_reg) - log_warning("reg '%s' is assigned in a continuous assignment at %s:%d.\n", children[0]->str.c_str(), filename.c_str(), linenum); + if (type == AST_ASSIGN && children[0]->id2ast->is_reg) { + bool is_rand_reg = false; + if (children[1]->type == AST_FCALL) { + if (children[1]->str == "\\$anyconst") + is_rand_reg = true; + if (children[1]->str == "\\$anyseq") + is_rand_reg = true; + if (children[1]->str == "\\$allconst") + is_rand_reg = true; + if (children[1]->str == "\\$allseq") + is_rand_reg = true; + } + if (!is_rand_reg) + log_warning("reg '%s' is assigned in a continuous assignment at %s:%d.\n", children[0]->str.c_str(), filename.c_str(), linenum); + } children[0]->was_checked = true; } break; @@ -732,7 +745,7 @@ bool AstNode::simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage, if (current_scope.at(modname)->type != AST_CELL) log_file_error(filename, linenum, "Defparam argument `%s . %s` does not match a cell!\n", - RTLIL::unescape_id(modname).c_str(), RTLIL::unescape_id(paramname).c_str()); + RTLIL::unescape_id(modname).c_str(), RTLIL::unescape_id(paramname).c_str()); AstNode *paraset = new AstNode(AST_PARASET, children[1]->clone(), GetSize(children) > 2 ? children[2]->clone() : NULL); paraset->str = paramname; @@ -880,7 +893,7 @@ bool AstNode::simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage, if (children[0]->type == AST_REALVALUE) { RTLIL::Const constvalue = children[0]->realAsConst(width); log_file_warning(filename, linenum, "converting real value %e to binary %s.\n", - children[0]->realvalue, log_signal(constvalue)); + children[0]->realvalue, log_signal(constvalue)); delete children[0]; children[0] = mkconst_bits(constvalue.bits, sign_hint); did_something = true; @@ -1299,8 +1312,7 @@ bool AstNode::simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage, if (type == AST_PRIMITIVE) { if (children.size() < 2) - log_file_error(filename, linenum, "Insufficient number of arguments for primitive `%s'!\n", - str.c_str()); + log_file_error(filename, linenum, "Insufficient number of arguments for primitive `%s'!\n", str.c_str()); std::vector<AstNode*> children_list; for (auto child : children) { @@ -1315,8 +1327,7 @@ bool AstNode::simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage, if (str == "bufif0" || str == "bufif1" || str == "notif0" || str == "notif1") { if (children_list.size() != 3) - log_file_error(filename, linenum, "Invalid number of arguments for primitive `%s'!\n", - str.c_str()); + log_file_error(filename, linenum, "Invalid number of arguments for primitive `%s'!\n", str.c_str()); std::vector<RTLIL::State> z_const(1, RTLIL::State::Sz); @@ -1403,8 +1414,7 @@ bool AstNode::simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage, while (left_at_zero_ast->simplify(true, true, false, stage, -1, false, false)) { } while (right_at_zero_ast->simplify(true, true, false, stage, -1, false, false)) { } if (left_at_zero_ast->type != AST_CONSTANT || right_at_zero_ast->type != AST_CONSTANT) - log_file_error(filename, linenum, "Unsupported expression on dynamic range select on signal `%s'!\n", - str.c_str()); + log_file_error(filename, linenum, "Unsupported expression on dynamic range select on signal `%s'!\n", str.c_str()); result_width = abs(int(left_at_zero_ast->integer - right_at_zero_ast->integer)) + 1; } did_something = true; @@ -1775,11 +1785,11 @@ skip_dynamic_range_lvalue_expansion:; if (GetSize(children) != 1 && GetSize(children) != 2) log_file_error(filename, linenum, "System function %s got %d arguments, expected 1 or 2.\n", - RTLIL::unescape_id(str).c_str(), int(children.size())); + RTLIL::unescape_id(str).c_str(), int(children.size())); if (!current_always_clocked) log_file_error(filename, linenum, "System function %s is only allowed in clocked blocks.\n", - RTLIL::unescape_id(str).c_str()); + RTLIL::unescape_id(str).c_str()); if (GetSize(children) == 2) { @@ -1844,11 +1854,11 @@ skip_dynamic_range_lvalue_expansion:; { if (GetSize(children) != 1) log_file_error(filename, linenum, "System function %s got %d arguments, expected 1.\n", - RTLIL::unescape_id(str).c_str(), int(children.size())); + RTLIL::unescape_id(str).c_str(), int(children.size())); if (!current_always_clocked) log_file_error(filename, linenum, "System function %s is only allowed in clocked blocks.\n", - RTLIL::unescape_id(str).c_str()); + RTLIL::unescape_id(str).c_str()); AstNode *present = children.at(0)->clone(); AstNode *past = clone(); @@ -1861,10 +1871,14 @@ skip_dynamic_range_lvalue_expansion:; newNode = new AstNode(AST_NE, past, present); else if (str == "\\$rose") - newNode = new AstNode(AST_LOGIC_AND, new AstNode(AST_LOGIC_NOT, past), present); + newNode = new AstNode(AST_LOGIC_AND, + new AstNode(AST_LOGIC_NOT, new AstNode(AST_BIT_AND, past, mkconst_int(1,false))), + new AstNode(AST_BIT_AND, present, mkconst_int(1,false))); else if (str == "\\$fell") - newNode = new AstNode(AST_LOGIC_AND, past, new AstNode(AST_LOGIC_NOT, present)); + newNode = new AstNode(AST_LOGIC_AND, + new AstNode(AST_BIT_AND, past, mkconst_int(1,false)), + new AstNode(AST_LOGIC_NOT, new AstNode(AST_BIT_AND, present, mkconst_int(1,false)))); else log_abort(); @@ -1882,7 +1896,7 @@ skip_dynamic_range_lvalue_expansion:; { if (children.size() != 1) log_file_error(filename, linenum, "System function %s got %d arguments, expected 1.\n", - RTLIL::unescape_id(str).c_str(), int(children.size())); + RTLIL::unescape_id(str).c_str(), int(children.size())); AstNode *buf = children[0]->clone(); while (buf->simplify(true, false, false, stage, width_hint, sign_hint, false)) { } @@ -1907,11 +1921,11 @@ skip_dynamic_range_lvalue_expansion:; { if (str == "\\$bits" && children.size() != 1) log_file_error(filename, linenum, "System function %s got %d arguments, expected 1.\n", - RTLIL::unescape_id(str).c_str(), int(children.size())); + RTLIL::unescape_id(str).c_str(), int(children.size())); if (str == "\\$size" && children.size() != 1 && children.size() != 2) log_file_error(filename, linenum, "System function %s got %d arguments, expected 1 or 2.\n", - RTLIL::unescape_id(str).c_str(), int(children.size())); + RTLIL::unescape_id(str).c_str(), int(children.size())); int dim = 1; if (str == "\\$size" && children.size() == 2) { @@ -1985,18 +1999,18 @@ skip_dynamic_range_lvalue_expansion:; if (func_with_two_arguments) { if (children.size() != 2) log_file_error(filename, linenum, "System function %s got %d arguments, expected 2.\n", - RTLIL::unescape_id(str).c_str(), int(children.size())); + RTLIL::unescape_id(str).c_str(), int(children.size())); } else { if (children.size() != 1) log_file_error(filename, linenum, "System function %s got %d arguments, expected 1.\n", - RTLIL::unescape_id(str).c_str(), int(children.size())); + RTLIL::unescape_id(str).c_str(), int(children.size())); } if (children.size() >= 1) { while (children[0]->simplify(true, false, false, stage, width_hint, sign_hint, false)) { } if (!children[0]->isConst()) log_file_error(filename, linenum, "Failed to evaluate system function `%s' with non-constant argument.\n", - RTLIL::unescape_id(str).c_str()); + RTLIL::unescape_id(str).c_str()); int child_width_hint = width_hint; bool child_sign_hint = sign_hint; children[0]->detectSignWidth(child_width_hint, child_sign_hint); @@ -2007,7 +2021,7 @@ skip_dynamic_range_lvalue_expansion:; while (children[1]->simplify(true, false, false, stage, width_hint, sign_hint, false)) { } if (!children[1]->isConst()) log_file_error(filename, linenum, "Failed to evaluate system function `%s' with non-constant argument.\n", - RTLIL::unescape_id(str).c_str()); + RTLIL::unescape_id(str).c_str()); int child_width_hint = width_hint; bool child_sign_hint = sign_hint; children[1]->detectSignWidth(child_width_hint, child_sign_hint); @@ -2095,7 +2109,7 @@ skip_dynamic_range_lvalue_expansion:; { if (GetSize(children) < 2 || GetSize(children) > 4) log_file_error(filename, linenum, "System function %s got %d arguments, expected 2-4.\n", - RTLIL::unescape_id(str).c_str(), int(children.size())); + RTLIL::unescape_id(str).c_str(), int(children.size())); AstNode *node_filename = children[0]->clone(); while (node_filename->simplify(true, false, false, stage, width_hint, sign_hint, false)) { } @@ -3259,12 +3273,12 @@ void AstNode::replace_variables(std::map<std::string, AstNode::varinfo_t> &varia if (!children.empty()) { if (children.size() != 1 || children.at(0)->type != AST_RANGE) log_file_error(filename, linenum, "Memory access in constant function is not supported\n%s:%d: ...called from here.\n", - fcall->filename.c_str(), fcall->linenum); + fcall->filename.c_str(), fcall->linenum); children.at(0)->replace_variables(variables, fcall); while (simplify(true, false, false, 1, -1, false, true)) { } if (!children.at(0)->range_valid) log_file_error(filename, linenum, "Non-constant range\n%s:%d: ... called from here.\n", - fcall->filename.c_str(), fcall->linenum); + fcall->filename.c_str(), fcall->linenum); offset = min(children.at(0)->range_left, children.at(0)->range_right); width = min(std::abs(children.at(0)->range_left - children.at(0)->range_right) + 1, width); } @@ -3304,7 +3318,7 @@ AstNode *AstNode::eval_const_function(AstNode *fcall) while (child->simplify(true, false, false, 1, -1, false, true)) { } if (!child->range_valid) log_file_error(child->filename, child->linenum, "Can't determine size of variable %s\n%s:%d: ... called from here.\n", - child->str.c_str(), fcall->filename.c_str(), fcall->linenum); + child->str.c_str(), fcall->filename.c_str(), fcall->linenum); variables[child->str].val = RTLIL::Const(RTLIL::State::Sx, abs(child->range_left - child->range_right)+1); variables[child->str].offset = min(child->range_left, child->range_right); variables[child->str].is_signed = child->is_signed; @@ -3348,15 +3362,15 @@ AstNode *AstNode::eval_const_function(AstNode *fcall) if (stmt->children.at(1)->type != AST_CONSTANT) log_file_error(stmt->filename, stmt->linenum, "Non-constant expression in constant function\n%s:%d: ... called from here. X\n", - fcall->filename.c_str(), fcall->linenum); + fcall->filename.c_str(), fcall->linenum); if (stmt->children.at(0)->type != AST_IDENTIFIER) log_file_error(stmt->filename, stmt->linenum, "Unsupported composite left hand side in constant function\n%s:%d: ... called from here.\n", - fcall->filename.c_str(), fcall->linenum); + fcall->filename.c_str(), fcall->linenum); if (!variables.count(stmt->children.at(0)->str)) log_file_error(stmt->filename, stmt->linenum, "Assignment to non-local variable in constant function\n%s:%d: ... called from here.\n", - fcall->filename.c_str(), fcall->linenum); + fcall->filename.c_str(), fcall->linenum); if (stmt->children.at(0)->children.empty()) { variables[stmt->children.at(0)->str].val = stmt->children.at(1)->bitsAsConst(variables[stmt->children.at(0)->str].val.bits.size()); @@ -3364,7 +3378,7 @@ AstNode *AstNode::eval_const_function(AstNode *fcall) AstNode *range = stmt->children.at(0)->children.at(0); if (!range->range_valid) log_file_error(range->filename, range->linenum, "Non-constant range\n%s:%d: ... called from here.\n", - fcall->filename.c_str(), fcall->linenum); + fcall->filename.c_str(), fcall->linenum); int offset = min(range->range_left, range->range_right); int width = std::abs(range->range_left - range->range_right) + 1; varinfo_t &v = variables[stmt->children.at(0)->str]; @@ -3396,7 +3410,7 @@ AstNode *AstNode::eval_const_function(AstNode *fcall) if (cond->type != AST_CONSTANT) log_file_error(stmt->filename, stmt->linenum, "Non-constant expression in constant function\n%s:%d: ... called from here.\n", - fcall->filename.c_str(), fcall->linenum); + fcall->filename.c_str(), fcall->linenum); if (cond->asBool()) { block->children.insert(block->children.begin(), stmt->children.at(1)->clone()); @@ -3417,7 +3431,7 @@ AstNode *AstNode::eval_const_function(AstNode *fcall) if (num->type != AST_CONSTANT) log_file_error(stmt->filename, stmt->linenum, "Non-constant expression in constant function\n%s:%d: ... called from here.\n", - fcall->filename.c_str(), fcall->linenum); + fcall->filename.c_str(), fcall->linenum); block->children.erase(block->children.begin()); for (int i = 0; i < num->bitsAsConst().as_int(); i++) @@ -3455,7 +3469,7 @@ AstNode *AstNode::eval_const_function(AstNode *fcall) if (cond->type != AST_CONSTANT) log_file_error(stmt->filename, stmt->linenum, "Non-constant expression in constant function\n%s:%d: ... called from here.\n", - fcall->filename.c_str(), fcall->linenum); + fcall->filename.c_str(), fcall->linenum); found_match = cond->asBool(); delete cond; @@ -3485,7 +3499,7 @@ AstNode *AstNode::eval_const_function(AstNode *fcall) } log_file_error(stmt->filename, stmt->linenum, "Unsupported language construct in constant function\n%s:%d: ... called from here.\n", - fcall->filename.c_str(), fcall->linenum); + fcall->filename.c_str(), fcall->linenum); log_abort(); } diff --git a/frontends/liberty/liberty.cc b/frontends/liberty/liberty.cc index 66db43baf..4acfbf1cb 100644 --- a/frontends/liberty/liberty.cc +++ b/frontends/liberty/liberty.cc @@ -36,7 +36,8 @@ static RTLIL::SigSpec parse_func_identifier(RTLIL::Module *module, const char *& int id_len = 0; while (('a' <= expr[id_len] && expr[id_len] <= 'z') || ('A' <= expr[id_len] && expr[id_len] <= 'Z') || - ('0' <= expr[id_len] && expr[id_len] <= '9') || expr[id_len] == '.' || expr[id_len] == '_') id_len++; + ('0' <= expr[id_len] && expr[id_len] <= '9') || expr[id_len] == '.' || + expr[id_len] == '_' || expr[id_len] == '[' || expr[id_len] == ']') id_len++; if (id_len == 0) log_error("Expected identifier at `%s'.\n", expr); diff --git a/frontends/verific/verific.cc b/frontends/verific/verific.cc index dba3b0f0c..971f0b24a 100644 --- a/frontends/verific/verific.cc +++ b/frontends/verific/verific.cc @@ -1835,6 +1835,7 @@ struct VerificPass : public Pass { Message::RegisterCallBackMsg(msg_func); RuntimeFlags::SetVar("db_preserve_user_nets", 1); RuntimeFlags::SetVar("db_allow_external_nets", 1); + RuntimeFlags::SetVar("vhdl_support_variable_slice", 1); RuntimeFlags::SetVar("vhdl_ignore_assertion_statements", 0); RuntimeFlags::SetVar("veri_extract_dualport_rams", 0); RuntimeFlags::SetVar("veri_extract_multiport_rams", 1); diff --git a/frontends/verilog/verilog_parser.y b/frontends/verilog/verilog_parser.y index 4dbe028a0..5ab1b62df 100644 --- a/frontends/verilog/verilog_parser.y +++ b/frontends/verilog/verilog_parser.y @@ -125,7 +125,7 @@ static void free_attr(std::map<std::string, AstNode*> *al) %type <ast> range range_or_multirange non_opt_range non_opt_multirange range_or_signed_int %type <ast> wire_type expr basic_expr concat_list rvalue lvalue lvalue_concat_list %type <string> opt_label tok_prim_wrapper hierarchical_id -%type <boolean> opt_signed unique_case_attr +%type <boolean> opt_signed opt_property unique_case_attr %type <al> attr case_attr // operator precedence from low to high @@ -305,7 +305,7 @@ module_arg_opt_assignment: else ast_stack.back()->children.push_back(new AstNode(AST_ASSIGN, wire, $2)); } else - frontend_verilog_yyerror("Syntax error."); + frontend_verilog_yyerror("SystemVerilog interface in module port list cannot have a default value."); } | /* empty */; @@ -672,7 +672,7 @@ task_func_port: astbuf2 = $3; if (astbuf1->range_left >= 0 && astbuf1->range_right >= 0) { if (astbuf2) { - frontend_verilog_yyerror("Syntax error."); + frontend_verilog_yyerror("integer/genvar types cannot have packed dimensions (task/function arguments)"); } else { astbuf2 = new AstNode(AST_RANGE); astbuf2->children.push_back(AstNode::mkconst_int(astbuf1->range_left, true)); @@ -680,7 +680,7 @@ task_func_port: } } if (astbuf2 && astbuf2->children.size() != 2) - frontend_verilog_yyerror("Syntax error."); + frontend_verilog_yyerror("task/function argument range must be of the form: [<expr>:<expr>], [<expr>+:<expr>], or [<expr>-:<expr>]"); } wire_name | wire_name; task_func_body: @@ -883,7 +883,7 @@ param_signed: param_integer: TOK_INTEGER { if (astbuf1->children.size() != 1) - frontend_verilog_yyerror("Syntax error."); + frontend_verilog_yyerror("Internal error in param_integer - should not happen?"); astbuf1->children.push_back(new AstNode(AST_RANGE)); astbuf1->children.back()->children.push_back(AstNode::mkconst_int(31, true)); astbuf1->children.back()->children.push_back(AstNode::mkconst_int(0, true)); @@ -893,7 +893,7 @@ param_integer: param_real: TOK_REAL { if (astbuf1->children.size() != 1) - frontend_verilog_yyerror("Syntax error."); + frontend_verilog_yyerror("Parameter already declared as integer, cannot set to real."); astbuf1->children.push_back(new AstNode(AST_REALVALUE)); } | /* empty */; @@ -901,7 +901,7 @@ param_range: range { if ($1 != NULL) { if (astbuf1->children.size() != 1) - frontend_verilog_yyerror("Syntax error."); + frontend_verilog_yyerror("integer/real parameters should not have a range."); astbuf1->children.push_back($1); } }; @@ -930,7 +930,7 @@ single_param_decl: AstNode *node; if (astbuf1 == nullptr) { if (!sv_mode) - frontend_verilog_yyerror("syntax error"); + frontend_verilog_yyerror("In pure Verilog (not SystemVerilog), parameter/localparam with an initializer must use the parameter/localparam keyword"); node = new AstNode(AST_PARAMETER); node->children.push_back(AstNode::mkconst_int(0, true)); } else { @@ -966,7 +966,7 @@ wire_decl: astbuf2 = $3; if (astbuf1->range_left >= 0 && astbuf1->range_right >= 0) { if (astbuf2) { - frontend_verilog_yyerror("Syntax error."); + frontend_verilog_yyerror("integer/genvar types cannot have packed dimensions."); } else { astbuf2 = new AstNode(AST_RANGE); astbuf2->children.push_back(AstNode::mkconst_int(astbuf1->range_left, true)); @@ -974,7 +974,7 @@ wire_decl: } } if (astbuf2 && astbuf2->children.size() != 2) - frontend_verilog_yyerror("Syntax error."); + frontend_verilog_yyerror("wire/reg/logic packed dimension must be of the form: [<expr>:<expr>], [<expr>+:<expr>], or [<expr>-:<expr>]"); } wire_name_list { delete astbuf1; if (astbuf2 != NULL) @@ -1068,7 +1068,7 @@ wire_name_and_opt_assign: wire_name: TOK_ID range_or_multirange { if (astbuf1 == nullptr) - frontend_verilog_yyerror("Syntax error."); + frontend_verilog_yyerror("Internal error - should not happen - no AST_WIRE node."); AstNode *node = astbuf1->clone(); node->str = *$1; append_attr_clone(node, albuf); @@ -1076,7 +1076,7 @@ wire_name: node->children.push_back(astbuf2->clone()); if ($2 != NULL) { if (node->is_input || node->is_output) - frontend_verilog_yyerror("Syntax error."); + frontend_verilog_yyerror("input/output/inout ports cannot have unpacked dimensions."); if (!astbuf2) { AstNode *rng = new AstNode(AST_RANGE); rng->children.push_back(AstNode::mkconst_int(0, true)); @@ -1320,7 +1320,12 @@ opt_label: }; opt_property: - TOK_PROPERTY | /* empty */; + TOK_PROPERTY { + $$ = true; + } | + /* empty */ { + $$ = false; + }; opt_stmt_label: TOK_ID ':' | /* empty */; @@ -1399,12 +1404,16 @@ assert: delete $5; else ast_stack.back()->children.push_back(new AstNode(AST_ASSUME, $5)); + if (!$3) + log_file_warning(current_filename, get_line_num(), "SystemVerilog does not allow \"restrict\" without \"property\".\n"); } | opt_stmt_label TOK_RESTRICT opt_property '(' TOK_EVENTUALLY expr ')' ';' { if (norestrict_mode) delete $6; else ast_stack.back()->children.push_back(new AstNode(AST_FAIR, $6)); + if (!$3) + log_file_warning(current_filename, get_line_num(), "SystemVerilog does not allow \"restrict\" without \"property\".\n"); }; assert_property: @@ -1478,7 +1487,7 @@ behavioral_stmt: node->str = *$3; } behavioral_stmt_list TOK_END opt_label { if ($3 != NULL && $7 != NULL && *$3 != *$7) - frontend_verilog_yyerror("Syntax error."); + frontend_verilog_yyerror("Begin label (%s) and end label (%s) don't match.", $3->c_str()+1, $7->c_str()+1); if ($3 != NULL) delete $3; if ($7 != NULL) @@ -1794,7 +1803,7 @@ basic_expr: } | '(' expr ')' TOK_CONSTVAL { if ($4->substr(0, 1) != "'") - frontend_verilog_yyerror("Syntax error."); + frontend_verilog_yyerror("Cast operation must be applied on sized constants e.g. (<expr>)<constval> , while %s is not a sized constant.", $4->c_str()); AstNode *bits = $2; AstNode *val = const2ast(*$4, case_type_stack.size() == 0 ? 0 : case_type_stack.back(), !lib_mode); if (val == NULL) @@ -1804,7 +1813,7 @@ basic_expr: } | hierarchical_id TOK_CONSTVAL { if ($2->substr(0, 1) != "'") - frontend_verilog_yyerror("Syntax error."); + frontend_verilog_yyerror("Cast operation must be applied on sized constants, e.g. <ID>\'d0, while %s is not a sized constant.", $2->c_str()); AstNode *bits = new AstNode(AST_IDENTIFIER); bits->str = *$1; AstNode *val = const2ast(*$2, case_type_stack.size() == 0 ? 0 : case_type_stack.back(), !lib_mode); diff --git a/kernel/celltypes.h b/kernel/celltypes.h index 6041168bb..8b8a56111 100644 --- a/kernel/celltypes.h +++ b/kernel/celltypes.h @@ -257,7 +257,7 @@ struct CellTypes return v; } - static RTLIL::Const eval(RTLIL::IdString type, const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len) + static RTLIL::Const eval(RTLIL::IdString type, const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len, bool *errp = nullptr) { if (type == "$sshr" && !signed1) type = "$shr"; @@ -329,10 +329,15 @@ struct CellTypes if (type == "$_ORNOT_") return const_or(arg1, eval_not(arg2), false, false, 1); + if (errp != nullptr) { + *errp = true; + return State::Sm; + } + log_abort(); } - static RTLIL::Const eval(RTLIL::Cell *cell, const RTLIL::Const &arg1, const RTLIL::Const &arg2) + static RTLIL::Const eval(RTLIL::Cell *cell, const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool *errp = nullptr) { if (cell->type == "$slice") { RTLIL::Const ret; @@ -415,10 +420,10 @@ struct CellTypes bool signed_a = cell->parameters.count("\\A_SIGNED") > 0 && cell->parameters["\\A_SIGNED"].as_bool(); bool signed_b = cell->parameters.count("\\B_SIGNED") > 0 && cell->parameters["\\B_SIGNED"].as_bool(); int result_len = cell->parameters.count("\\Y_WIDTH") > 0 ? cell->parameters["\\Y_WIDTH"].as_int() : -1; - return eval(cell->type, arg1, arg2, signed_a, signed_b, result_len); + return eval(cell->type, arg1, arg2, signed_a, signed_b, result_len, errp); } - static RTLIL::Const eval(RTLIL::Cell *cell, const RTLIL::Const &arg1, const RTLIL::Const &arg2, const RTLIL::Const &arg3) + static RTLIL::Const eval(RTLIL::Cell *cell, const RTLIL::Const &arg1, const RTLIL::Const &arg2, const RTLIL::Const &arg3, bool *errp = nullptr) { if (cell->type.in("$mux", "$pmux", "$_MUX_")) { RTLIL::Const ret = arg1; @@ -436,10 +441,10 @@ struct CellTypes return eval_not(const_and(const_or(arg1, arg2, false, false, 1), arg3, false, false, 1)); log_assert(arg3.bits.size() == 0); - return eval(cell, arg1, arg2); + return eval(cell, arg1, arg2, errp); } - static RTLIL::Const eval(RTLIL::Cell *cell, const RTLIL::Const &arg1, const RTLIL::Const &arg2, const RTLIL::Const &arg3, const RTLIL::Const &arg4) + static RTLIL::Const eval(RTLIL::Cell *cell, const RTLIL::Const &arg1, const RTLIL::Const &arg2, const RTLIL::Const &arg3, const RTLIL::Const &arg4, bool *errp = nullptr) { if (cell->type == "$_AOI4_") return eval_not(const_or(const_and(arg1, arg2, false, false, 1), const_and(arg3, arg4, false, false, 1), false, false, 1)); @@ -447,7 +452,7 @@ struct CellTypes return eval_not(const_and(const_or(arg1, arg2, false, false, 1), const_and(arg3, arg4, false, false, 1), false, false, 1)); log_assert(arg4.bits.size() == 0); - return eval(cell, arg1, arg2, arg3); + return eval(cell, arg1, arg2, arg3, errp); } }; diff --git a/kernel/consteval.h b/kernel/consteval.h index 0229f5045..154373a8d 100644 --- a/kernel/consteval.h +++ b/kernel/consteval.h @@ -321,8 +321,13 @@ struct ConstEval if (sig_d.size() > 0 && !eval(sig_d, undef, cell)) return false; - set(sig_y, CellTypes::eval(cell, sig_a.as_const(), sig_b.as_const(), - sig_c.as_const(), sig_d.as_const())); + bool eval_err = false; + RTLIL::Const eval_ret = CellTypes::eval(cell, sig_a.as_const(), sig_b.as_const(), sig_c.as_const(), sig_d.as_const(), &eval_err); + + if (eval_err) + return false; + + set(sig_y, eval_ret); } return true; diff --git a/kernel/yosys.cc b/kernel/yosys.cc index ad032899c..f002955ad 100644 --- a/kernel/yosys.cc +++ b/kernel/yosys.cc @@ -799,7 +799,7 @@ static void handle_label(std::string &command, bool &from_to_active, const std:: while (pos < GetSize(command) && command[pos] != ' ' && command[pos] != '\t' && command[pos] != '\r' && command[pos] != '\n') label += command[pos++]; - if (label.back() == ':' && GetSize(label) > 1) + if (GetSize(label) > 1 && label.back() == ':') { label = label.substr(0, GetSize(label)-1); command = command.substr(pos); @@ -821,7 +821,7 @@ void run_frontend(std::string filename, std::string command, std::string *backen command = "verilog"; else if (filename.size() > 2 && filename.substr(filename.size()-3) == ".sv") command = "verilog -sv"; - else if (filename.size() > 2 && filename.substr(filename.size()-4) == ".vhd") + else if (filename.size() > 3 && filename.substr(filename.size()-4) == ".vhd") command = "vhdl"; else if (filename.size() > 4 && filename.substr(filename.size()-5) == ".blif") command = "blif"; @@ -833,7 +833,7 @@ void run_frontend(std::string filename, std::string command, std::string *backen command = "ilang"; else if (filename.size() > 3 && filename.substr(filename.size()-3) == ".ys") command = "script"; - else if (filename.size() > 2 && filename.substr(filename.size()-4) == ".tcl") + else if (filename.size() > 3 && filename.substr(filename.size()-4) == ".tcl") command = "tcl"; else if (filename == "-") command = "script"; diff --git a/passes/opt/opt_muxtree.cc b/passes/opt/opt_muxtree.cc index 87c7ce9b2..375697dc8 100644 --- a/passes/opt/opt_muxtree.cc +++ b/passes/opt/opt_muxtree.cc @@ -36,6 +36,7 @@ struct OptMuxtreeWorker RTLIL::Module *module; SigMap assign_map; int removed_count; + int glob_abort_cnt = 100000; struct bitinfo_t { bool seen_non_mux; @@ -293,6 +294,9 @@ struct OptMuxtreeWorker void eval_mux_port(knowledge_t &knowledge, int mux_idx, int port_idx, bool do_replace_known, bool do_enable_ports, int abort_count) { + if (glob_abort_cnt == 0) + return; + muxinfo_t &muxinfo = mux2info[mux_idx]; if (do_enable_ports) @@ -315,7 +319,7 @@ struct OptMuxtreeWorker knowledge.visited_muxes[m] = true; parent_muxes.push_back(m); } - for (int m : parent_muxes) + for (int m : parent_muxes) { if (root_enable_muxes.at(m)) continue; else if (root_muxes.at(m)) { @@ -327,6 +331,9 @@ struct OptMuxtreeWorker eval_mux(knowledge, m, false, do_enable_ports, abort_count - 1); } else eval_mux(knowledge, m, do_replace_known, do_enable_ports, abort_count); + if (glob_abort_cnt == 0) + return; + } for (int m : parent_muxes) knowledge.visited_muxes[m] = false; @@ -390,6 +397,12 @@ struct OptMuxtreeWorker void eval_mux(knowledge_t &knowledge, int mux_idx, bool do_replace_known, bool do_enable_ports, int abort_count) { + if (glob_abort_cnt == 0) { + log(" Giving up (too many iterations)\n"); + return; + } + glob_abort_cnt--; + muxinfo_t &muxinfo = mux2info[mux_idx]; // set input ports to constants if we find known active or inactive signals @@ -433,6 +446,9 @@ struct OptMuxtreeWorker if (knowledge.known_inactive.at(portinfo.ctrl_sig)) continue; eval_mux_port(knowledge, mux_idx, port_idx, do_replace_known, do_enable_ports, abort_count); + + if (glob_abort_cnt == 0) + return; } } diff --git a/passes/techmap/dfflibmap.cc b/passes/techmap/dfflibmap.cc index 416ed2bd5..b0528d473 100644 --- a/passes/techmap/dfflibmap.cc +++ b/passes/techmap/dfflibmap.cc @@ -100,6 +100,18 @@ static bool parse_pin(LibertyAst *cell, LibertyAst *attr, std::string &pin_name, for (auto child : cell->children) if (child->id == "pin" && child->args.size() == 1 && child->args[0] == pin_name) return true; + + /* If we end up here, the pin specified in the attribute does not exist, which is an error, + or, the attribute contains an expression which we do not yet support. + For now, we'll simply produce a warning to let the user know something is up. + */ + if (pin_name.find_first_of("^*|&") == std::string::npos) { + log_warning("Malformed liberty file - cannot find pin '%s' in cell '%s' - skipping.\n", pin_name.c_str(), cell->args[0].c_str()); + } + else { + log_warning("Found unsupported expression '%s' in pin attribute of cell '%s' - skipping.\n", pin_name.c_str(), cell->args[0].c_str()); + } + return false; } diff --git a/passes/techmap/libparse.cc b/passes/techmap/libparse.cc index d3b1ff02f..3927a657b 100644 --- a/passes/techmap/libparse.cc +++ b/passes/techmap/libparse.cc @@ -90,11 +90,11 @@ int LibertyParser::lexer(std::string &str) c = f.get(); } while (c == ' ' || c == '\t' || c == '\r'); - if (('a' <= c && c <= 'z') || ('A' <= c && c <= 'Z') || ('0' <= c && c <= '9') || c == '_' || c == '-' || c == '+' || c == '.') { + if (('a' <= c && c <= 'z') || ('A' <= c && c <= 'Z') || ('0' <= c && c <= '9') || c == '_' || c == '-' || c == '+' || c == '.' || c == '[' || c == ']') { str = c; while (1) { c = f.get(); - if (('a' <= c && c <= 'z') || ('A' <= c && c <= 'Z') || ('0' <= c && c <= '9') || c == '_' || c == '-' || c == '+' || c == '.') + if (('a' <= c && c <= 'z') || ('A' <= c && c <= 'Z') || ('0' <= c && c <= '9') || c == '_' || c == '-' || c == '+' || c == '.' || c == '[' || c == ']') str += c; else break; @@ -159,7 +159,7 @@ int LibertyParser::lexer(std::string &str) if (c == '\n') { line++; - return ';'; + return 'n'; } // if (c >= 32 && c < 255) @@ -175,7 +175,7 @@ LibertyAst *LibertyParser::parse() int tok = lexer(str); - while (tok == ';') + while (tok == 'n') tok = lexer(str); if (tok == '}' || tok < 0) @@ -194,6 +194,9 @@ LibertyAst *LibertyParser::parse() if (tok == ';') break; + if (tok == 'n') + continue; + if (tok == ':' && ast->value.empty()) { tok = lexer(ast->value); if (tok != 'v') @@ -249,14 +252,14 @@ LibertyAst *LibertyParser::parse() void LibertyParser::error() { - log_error("Syntax error in line %d.\n", line); + log_error("Syntax error in liberty file on line %d.\n", line); } #else void LibertyParser::error() { - fprintf(stderr, "Syntax error in line %d.\n", line); + fprintf(stderr, "Syntax error in liberty file on line %d.\n", line); exit(1); } diff --git a/techlibs/ecp5/Makefile.inc b/techlibs/ecp5/Makefile.inc index 9b6f061bd..b23d5c70e 100644 --- a/techlibs/ecp5/Makefile.inc +++ b/techlibs/ecp5/Makefile.inc @@ -3,6 +3,7 @@ OBJS += techlibs/ecp5/synth_ecp5.o $(eval $(call add_share_file,share/ecp5,techlibs/ecp5/cells_map.v)) $(eval $(call add_share_file,share/ecp5,techlibs/ecp5/cells_sim.v)) +$(eval $(call add_share_file,share/ecp5,techlibs/ecp5/cells_bb.v)) $(eval $(call add_share_file,share/ecp5,techlibs/ecp5/drams_map.v)) $(eval $(call add_share_file,share/ecp5,techlibs/ecp5/dram.txt)) $(eval $(call add_share_file,share/ecp5,techlibs/ecp5/brams_map.v)) diff --git a/techlibs/ecp5/cells_bb.v b/techlibs/ecp5/cells_bb.v new file mode 100644 index 000000000..057f9d737 --- /dev/null +++ b/techlibs/ecp5/cells_bb.v @@ -0,0 +1,514 @@ +// ECP5 Blackbox cells +// FIXME: Create sim models + +(* blackbox *) +module MULT18X18D( + input A0, A1, A2, A3, A4, A5, A6, A7, A8, A9, A10, A11, A12, A13, A14, A15, A16, A17, + input B0, B1, B2, B3, B4, B5, B6, B7, B8, B9, B10, B11, B12, B13, B14, B15, B16, B17, + input C0, C1, C2, C3, C4, C5, C6, C7, C8, C9, C10, C11, C12, C13, C14, C15, C16, C17, + input SIGNEDA, SIGNEDB, SOURCEA, SOURCEB, + input CLK0, CLK1, CLK2, CLK3, + input CE0, CE1, CE2, CE3, + input RST0, RST1, RST2, RST3, + input SRIA0, SRIA1, SRIA2, SRIA3, SRIA4, SRIA5, SRIA6, SRIA7, SRIA8, SRIA9, SRIA10, SRIA11, SRIA12, SRIA13, SRIA14, SRIA15, SRIA16, SRIA17, + input SRIB0, SRIB1, SRIB2, SRIB3, SRIB4, SRIB5, SRIB6, SRIB7, SRIB8, SRIB9, SRIB10, SRIB11, SRIB12, SRIB13, SRIB14, SRIB15, SRIB16, SRIB17, + output SROA0, SROA1, SROA2, SROA3, SROA4, SROA5, SROA6, SROA7, SROA8, SROA9, SROA10, SROA11, SROA12, SROA13, SROA14, SROA15, SROA16, SROA17, + output SROB0, SROB1, SROB2, SROB3, SROB4, SROB5, SROB6, SROB7, SROB8, SROB9, SROB10, SROB11, SROB12, SROB13, SROB14, SROB15, SROB16, SROB17, + output ROA0, ROA1, ROA2, ROA3, ROA4, ROA5, ROA6, ROA7, ROA8, ROA9, ROA10, ROA11, ROA12, ROA13, ROA14, ROA15, ROA16, ROA17, + output ROB0, ROB1, ROB2, ROB3, ROB4, ROB5, ROB6, ROB7, ROB8, ROB9, ROB10, ROB11, ROB12, ROB13, ROB14, ROB15, ROB16, ROB17, + output ROC0, ROC1, ROC2, ROC3, ROC4, ROC5, ROC6, ROC7, ROC8, ROC9, ROC10, ROC11, ROC12, ROC13, ROC14, ROC15, ROC16, ROC17, + output P0, P1, P2, P3, P4, P5, P6, P7, P8, P9, P10, P11, P12, P13, P14, P15, P16, P17, P18, P19, P20, P21, P22, P23, P24, P25, P26, P27, P28, P29, P30, P31, P32, P33, P34, P35, + output SIGNEDP +); + parameter REG_INPUTA_CLK = "NONE"; + parameter REG_INPUTA_CE = "CE0"; + parameter REG_INPUTA_RST = "RST0"; + parameter REG_INPUTB_CLK = "NONE"; + parameter REG_INPUTB_CE = "CE0"; + parameter REG_INPUTB_RST = "RST0"; + parameter REG_INPUTC_CLK = "NONE"; + parameter REG_PIPELINE_CLK = "NONE"; + parameter REG_PIPELINE_CE = "CE0"; + parameter REG_PIPELINE_RST = "RST0"; + parameter REG_OUTPUT_CLK = "NONE"; + parameter [127:0] CLK0_DIV = "ENABLED"; + parameter [127:0] CLK1_DIV = "ENABLED"; + parameter [127:0] CLK2_DIV = "ENABLED"; + parameter [127:0] CLK3_DIV = "ENABLED"; + parameter [127:0] GSR = "ENABLED"; + parameter [127:0] SOURCEB_MODE = "B_SHIFT"; + parameter [127:0] RESETMODE = "SYNC"; +endmodule + +(* blackbox *) +module ALU54B( + input CLK0, CLK1, CLK2, CLK3, + input CE0, CE1, CE2, CE3, + input RST0, RST1, RST2, RST3, + input SIGNEDIA, SIGNEDIB, SIGNEDCIN, + input A0, A1, A2, A3, A4, A5, A6, A7, A8, A9, A10, A11, A12, A13, A14, A15, A16, A17, A18, A19, A20, A21, A22, A23, A24, A25, A26, A27, A28, A29, A30, A31, A32, A33, A34, A35, + input B0, B1, B2, B3, B4, B5, B6, B7, B8, B9, B10, B11, B12, B13, B14, B15, B16, B17, B18, B19, B20, B21, B22, B23, B24, B25, B26, B27, B28, B29, B30, B31, B32, B33, B34, B35, + input C0, C1, C2, C3, C4, C5, C6, C7, C8, C9, C10, C11, C12, C13, C14, C15, C16, C17, C18, C19, C20, C21, C22, C23, C24, C25, C26, C27, C28, C29, C30, C31, C32, C33, C34, C35, C36, C37, C38, C39, C40, C41, C42, C43, C44, C45, C46, C47, C48, C49, C50, C51, C52, C53, + input CFB0, CFB1, CFB2, CFB3, CFB4, CFB5, CFB6, CFB7, CFB8, CFB9, CFB10, CFB11, CFB12, CFB13, CFB14, CFB15, CFB16, CFB17, CFB18, CFB19, CFB20, CFB21, CFB22, CFB23, CFB24, CFB25, CFB26, CFB27, CFB28, CFB29, CFB30, CFB31, CFB32, CFB33, CFB34, CFB35, CFB36, CFB37, CFB38, CFB39, CFB40, CFB41, CFB42, CFB43, CFB44, CFB45, CFB46, CFB47, CFB48, CFB49, CFB50, CFB51, CFB52, CFB53, + input MA0, MA1, MA2, MA3, MA4, MA5, MA6, MA7, MA8, MA9, MA10, MA11, MA12, MA13, MA14, MA15, MA16, MA17, MA18, MA19, MA20, MA21, MA22, MA23, MA24, MA25, MA26, MA27, MA28, MA29, MA30, MA31, MA32, MA33, MA34, MA35, + input MB0, MB1, MB2, MB3, MB4, MB5, MB6, MB7, MB8, MB9, MB10, MB11, MB12, MB13, MB14, MB15, MB16, MB17, MB18, MB19, MB20, MB21, MB22, MB23, MB24, MB25, MB26, MB27, MB28, MB29, MB30, MB31, MB32, MB33, MB34, MB35, + input CIN0, CIN1, CIN2, CIN3, CIN4, CIN5, CIN6, CIN7, CIN8, CIN9, CIN10, CIN11, CIN12, CIN13, CIN14, CIN15, CIN16, CIN17, CIN18, CIN19, CIN20, CIN21, CIN22, CIN23, CIN24, CIN25, CIN26, CIN27, CIN28, CIN29, CIN30, CIN31, CIN32, CIN33, CIN34, CIN35, CIN36, CIN37, CIN38, CIN39, CIN40, CIN41, CIN42, CIN43, CIN44, CIN45, CIN46, CIN47, CIN48, CIN49, CIN50, CIN51, CIN52, CIN53, + input OP0, OP1, OP2, OP3, OP4, OP5, OP6, OP7, OP8, OP9, OP10, + output R0, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, R13, R14, R15, R16, R17, R18, R19, R20, R21, R22, R23, R24, R25, R26, R27, R28, R29, R30, R31, R32, R33, R34, R35, R36, R37, R38, R39, R40, R41, R42, R43, R44, R45, R46, R47, R48, R49, R50, R51, R52, R53, + output CO0, CO1, CO2, CO3, CO4, CO5, CO6, CO7, CO8, CO9, CO10, CO11, CO12, CO13, CO14, CO15, CO16, CO17, CO18, CO19, CO20, CO21, CO22, CO23, CO24, CO25, CO26, CO27, CO28, CO29, CO30, CO31, CO32, CO33, CO34, CO35, CO36, CO37, CO38, CO39, CO40, CO41, CO42, CO43, CO44, CO45, CO46, CO47, CO48, CO49, CO50, CO51, CO52, CO53, + output EQZ, EQZM, EQOM, EQPAT, EQPATB, + output OVER, UNDER, OVERUNDER, + output SIGNEDR +); + parameter REG_INPUTC0_CLK = "NONE"; + parameter REG_INPUTC1_CLK = "NONE"; + parameter REG_OPCODEOP0_0_CLK = "NONE"; + parameter REG_OPCODEOP0_0_CE = "CE0"; + parameter REG_OPCODEOP0_0_RST = "RST0"; + parameter REG_OPCODEOP1_0_CLK = "NONE"; + parameter REG_OPCODEOP0_1_CLK = "NONE"; + parameter REG_OPCODEOP0_1_CE = "CE0"; + parameter REG_OPCODEOP0_1_RST = "RST0"; + parameter REG_OPCODEIN_0_CLK = "NONE"; + parameter REG_OPCODEIN_0_CE = "CE0"; + parameter REG_OPCODEIN_0_RST = "RST0"; + parameter REG_OPCODEIN_1_CLK = "NONE"; + parameter REG_OPCODEIN_1_CE = "CE0"; + parameter REG_OPCODEIN_1_RST = "RST0"; + parameter REG_OUTPUT0_CLK = "NONE"; + parameter REG_OUTPUT1_CLK = "NONE"; + parameter REG_FLAG_CLK = "NONE"; + parameter [127:0] MCPAT_SOURCE = "STATIC"; + parameter [127:0] MASKPAT_SOURCE = "STATIC"; + parameter MASK01 = "0x00000000000000"; + parameter [127:0] CLK0_DIV = "ENABLED"; + parameter [127:0] CLK1_DIV = "ENABLED"; + parameter [127:0] CLK2_DIV = "ENABLED"; + parameter [127:0] CLK3_DIV = "ENABLED"; + parameter MCPAT = "0x00000000000000"; + parameter MASKPAT = "0x00000000000000"; + parameter RNDPAT = "0x00000000000000"; + parameter [127:0] GSR = "ENABLED"; + parameter [127:0] RESETMODE = "SYNC"; + parameter FORCE_ZERO_BARREL_SHIFT = "DISABLED"; + parameter LEGACY = "DISABLED"; +endmodule + +(* blackbox *) +module EHXPLLL ( + input CLKI, CLKFB, + input PHASESEL1, PHASESEL0, PHASEDIR, PHASESTEP, PHASELOADREG, + input STDBY, PLLWAKESYNC, + input RST, ENCLKOP, ENCLKOS, ENCLKOS2, ENCLKOS3, + output CLKOP, CLKOS, CLKOS2, CLKOS3, + output LOCK, INTLOCK, + output REFCLK, CLKINTFB +); + parameter CLKI_DIV = 1; + parameter CLKFB_DIV = 1; + parameter CLKOP_DIV = 8; + parameter CLKOS_DIV = 8; + parameter CLKOS2_DIV = 8; + parameter CLKOS3_DIV = 8; + parameter CLKOP_ENABLE = "ENABLED"; + parameter CLKOS_ENABLE = "DISABLED"; + parameter CLKOS2_ENABLE = "DISABLED"; + parameter CLKOS3_ENABLE = "DISABLED"; + parameter CLKOP_CPHASE = 0; + parameter CLKOS_CPHASE = 0; + parameter CLKOS2_CPHASE = 0; + parameter CLKOS3_CPHASE = 0; + parameter CLKOP_FPHASE = 0; + parameter CLKOS_FPHASE = 0; + parameter CLKOS2_FPHASE = 0; + parameter CLKOS3_FPHASE = 0; + parameter FEEDBK_PATH = "CLKOP"; + parameter CLKOP_TRIM_POL = "RISING"; + parameter CLKOP_TRIM_DELAY = 0; + parameter CLKOS_TRIM_POL = "RISING"; + parameter CLKOS_TRIM_DELAY = 0; + parameter OUTDIVIDER_MUXA = "DIVA"; + parameter OUTDIVIDER_MUXB = "DIVB"; + parameter OUTDIVIDER_MUXC = "DIVC"; + parameter OUTDIVIDER_MUXD = "DIVD"; + parameter PLL_LOCK_MODE = 0; + parameter PLL_LOCK_DELAY = 200; + parameter STDBY_ENABLE = "DISABLED"; + parameter REFIN_RESET = "DISABLED"; + parameter SYNC_ENABLE = "DISABLED"; + parameter INT_LOCK_STICKY = "ENABLED"; + parameter DPHASE_SOURCE = "DISABLED"; + parameter PLLRST_ENA = "DISABLED"; + parameter INTFB_WAKE = "DISABLED"; +endmodule + +(* blackbox *) +module DTR( + input STARTPULSE, + output DTROUT7, DTROUT6, DTROUT5, DTROUT4, DTROUT3, DTROUT2, DTROUT1, DTROUT0 +); +endmodule + +(* blackbox *) +module OSCG( + output OSC +); +parameter DIV = 128; +endmodule + +(* blackbox *) +module IDDRX1F( + input D, SCLK, RST, + output Q0, Q1 +); + parameter GSR = "ENABLED"; +endmodule + +(* blackbox *) +module ODDRX1F( + input SCLK, RST, D0, D1, + output Q +); + parameter GSR = "ENABLED"; +endmodule + +(* blackbox *) +module CLKDIVF( + input CLKI, RST, ALIGNWD, + output CDIVX +); + parameter GSR = "DISABLED"; + parameter DIV = "2.0"; +endmodule + +(* blackbox *) +module DCCA( + input CLKI, CE, + output CLKO +); +endmodule + +(* blackbox *) (* keep *) +module DCUA( + input CH0_HDINP, CH1_HDINP, CH0_HDINN, CH1_HDINN, + input D_TXBIT_CLKP_FROM_ND, D_TXBIT_CLKN_FROM_ND, D_SYNC_ND, D_TXPLL_LOL_FROM_ND, + input CH0_RX_REFCLK, CH1_RX_REFCLK, CH0_FF_RXI_CLK, CH1_FF_RXI_CLK, CH0_FF_TXI_CLK, CH1_FF_TXI_CLK, CH0_FF_EBRD_CLK, CH1_FF_EBRD_CLK, + input CH0_FF_TX_D_0, CH1_FF_TX_D_0, CH0_FF_TX_D_1, CH1_FF_TX_D_1, CH0_FF_TX_D_2, CH1_FF_TX_D_2, CH0_FF_TX_D_3, CH1_FF_TX_D_3, + input CH0_FF_TX_D_4, CH1_FF_TX_D_4, CH0_FF_TX_D_5, CH1_FF_TX_D_5, CH0_FF_TX_D_6, CH1_FF_TX_D_6, CH0_FF_TX_D_7, CH1_FF_TX_D_7, + input CH0_FF_TX_D_8, CH1_FF_TX_D_8, CH0_FF_TX_D_9, CH1_FF_TX_D_9, CH0_FF_TX_D_10, CH1_FF_TX_D_10, CH0_FF_TX_D_11, CH1_FF_TX_D_11, + input CH0_FF_TX_D_12, CH1_FF_TX_D_12, CH0_FF_TX_D_13, CH1_FF_TX_D_13, CH0_FF_TX_D_14, CH1_FF_TX_D_14, CH0_FF_TX_D_15, CH1_FF_TX_D_15, + input CH0_FF_TX_D_16, CH1_FF_TX_D_16, CH0_FF_TX_D_17, CH1_FF_TX_D_17, CH0_FF_TX_D_18, CH1_FF_TX_D_18, CH0_FF_TX_D_19, CH1_FF_TX_D_19, + input CH0_FF_TX_D_20, CH1_FF_TX_D_20, CH0_FF_TX_D_21, CH1_FF_TX_D_21, CH0_FF_TX_D_22, CH1_FF_TX_D_22, CH0_FF_TX_D_23, CH1_FF_TX_D_23, + input CH0_FFC_EI_EN, CH1_FFC_EI_EN, CH0_FFC_PCIE_DET_EN, CH1_FFC_PCIE_DET_EN, CH0_FFC_PCIE_CT, CH1_FFC_PCIE_CT, CH0_FFC_SB_INV_RX, CH1_FFC_SB_INV_RX, + input CH0_FFC_ENABLE_CGALIGN, CH1_FFC_ENABLE_CGALIGN, CH0_FFC_SIGNAL_DETECT, CH1_FFC_SIGNAL_DETECT, CH0_FFC_FB_LOOPBACK, CH1_FFC_FB_LOOPBACK, CH0_FFC_SB_PFIFO_LP, CH1_FFC_SB_PFIFO_LP, + input CH0_FFC_PFIFO_CLR, CH1_FFC_PFIFO_CLR, CH0_FFC_RATE_MODE_RX, CH1_FFC_RATE_MODE_RX, CH0_FFC_RATE_MODE_TX, CH1_FFC_RATE_MODE_TX, CH0_FFC_DIV11_MODE_RX, CH1_FFC_DIV11_MODE_RX, CH0_FFC_RX_GEAR_MODE, CH1_FFC_RX_GEAR_MODE, CH0_FFC_TX_GEAR_MODE, CH1_FFC_TX_GEAR_MODE, + input CH0_FFC_DIV11_MODE_TX, CH1_FFC_DIV11_MODE_TX, CH0_FFC_LDR_CORE2TX_EN, CH1_FFC_LDR_CORE2TX_EN, CH0_FFC_LANE_TX_RST, CH1_FFC_LANE_TX_RST, CH0_FFC_LANE_RX_RST, CH1_FFC_LANE_RX_RST, + input CH0_FFC_RRST, CH1_FFC_RRST, CH0_FFC_TXPWDNB, CH1_FFC_TXPWDNB, CH0_FFC_RXPWDNB, CH1_FFC_RXPWDNB, CH0_LDR_CORE2TX, CH1_LDR_CORE2TX, + input D_SCIWDATA0, D_SCIWDATA1, D_SCIWDATA2, D_SCIWDATA3, D_SCIWDATA4, D_SCIWDATA5, D_SCIWDATA6, D_SCIWDATA7, + input D_SCIADDR0, D_SCIADDR1, D_SCIADDR2, D_SCIADDR3, D_SCIADDR4, D_SCIADDR5, D_SCIENAUX, D_SCISELAUX, + input CH0_SCIEN, CH1_SCIEN, CH0_SCISEL, CH1_SCISEL, D_SCIRD, D_SCIWSTN, D_CYAWSTN, D_FFC_SYNC_TOGGLE, + input D_FFC_DUAL_RST, D_FFC_MACRO_RST, D_FFC_MACROPDB, D_FFC_TRST, CH0_FFC_CDR_EN_BITSLIP, CH1_FFC_CDR_EN_BITSLIP, D_SCAN_ENABLE, D_SCAN_IN_0, + input D_SCAN_IN_1, D_SCAN_IN_2, D_SCAN_IN_3, D_SCAN_IN_4, D_SCAN_IN_5, D_SCAN_IN_6, D_SCAN_IN_7, D_SCAN_MODE, + input D_SCAN_RESET, D_CIN0, D_CIN1, D_CIN2, D_CIN3, D_CIN4, D_CIN5, D_CIN6,D_CIN7, D_CIN8, D_CIN9, D_CIN10, D_CIN11, + output CH0_HDOUTP, CH1_HDOUTP, CH0_HDOUTN, CH1_HDOUTN, D_TXBIT_CLKP_TO_ND, D_TXBIT_CLKN_TO_ND, D_SYNC_PULSE2ND, D_TXPLL_LOL_TO_ND, + output CH0_FF_RX_F_CLK, CH1_FF_RX_F_CLK, CH0_FF_RX_H_CLK, CH1_FF_RX_H_CLK, CH0_FF_TX_F_CLK, CH1_FF_TX_F_CLK, CH0_FF_TX_H_CLK, CH1_FF_TX_H_CLK, + output CH0_FF_RX_PCLK, CH1_FF_RX_PCLK, CH0_FF_TX_PCLK, CH1_FF_TX_PCLK, CH0_FF_RX_D_0, CH1_FF_RX_D_0, CH0_FF_RX_D_1, CH1_FF_RX_D_1, + output CH0_FF_RX_D_2, CH1_FF_RX_D_2, CH0_FF_RX_D_3, CH1_FF_RX_D_3, CH0_FF_RX_D_4, CH1_FF_RX_D_4, CH0_FF_RX_D_5, CH1_FF_RX_D_5, + output CH0_FF_RX_D_6, CH1_FF_RX_D_6, CH0_FF_RX_D_7, CH1_FF_RX_D_7, CH0_FF_RX_D_8, CH1_FF_RX_D_8, CH0_FF_RX_D_9, CH1_FF_RX_D_9, + output CH0_FF_RX_D_10, CH1_FF_RX_D_10, CH0_FF_RX_D_11, CH1_FF_RX_D_11, CH0_FF_RX_D_12, CH1_FF_RX_D_12, CH0_FF_RX_D_13, CH1_FF_RX_D_13, + output CH0_FF_RX_D_14, CH1_FF_RX_D_14, CH0_FF_RX_D_15, CH1_FF_RX_D_15, CH0_FF_RX_D_16, CH1_FF_RX_D_16, CH0_FF_RX_D_17, CH1_FF_RX_D_17, + output CH0_FF_RX_D_18, CH1_FF_RX_D_18, CH0_FF_RX_D_19, CH1_FF_RX_D_19, CH0_FF_RX_D_20, CH1_FF_RX_D_20, CH0_FF_RX_D_21, CH1_FF_RX_D_21, + output CH0_FF_RX_D_22, CH1_FF_RX_D_22, CH0_FF_RX_D_23, CH1_FF_RX_D_23, CH0_FFS_PCIE_DONE, CH1_FFS_PCIE_DONE, CH0_FFS_PCIE_CON, CH1_FFS_PCIE_CON, + output CH0_FFS_RLOS, CH1_FFS_RLOS, CH0_FFS_LS_SYNC_STATUS, CH1_FFS_LS_SYNC_STATUS, CH0_FFS_CC_UNDERRUN, CH1_FFS_CC_UNDERRUN, CH0_FFS_CC_OVERRUN, CH1_FFS_CC_OVERRUN, + output CH0_FFS_RXFBFIFO_ERROR, CH1_FFS_RXFBFIFO_ERROR, CH0_FFS_TXFBFIFO_ERROR, CH1_FFS_TXFBFIFO_ERROR, CH0_FFS_RLOL, CH1_FFS_RLOL, CH0_FFS_SKP_ADDED, CH1_FFS_SKP_ADDED, + output CH0_FFS_SKP_DELETED, CH1_FFS_SKP_DELETED, CH0_LDR_RX2CORE, CH1_LDR_RX2CORE, D_SCIRDATA0, D_SCIRDATA1, D_SCIRDATA2, D_SCIRDATA3, + output D_SCIRDATA4, D_SCIRDATA5, D_SCIRDATA6, D_SCIRDATA7, D_SCIINT, D_SCAN_OUT_0, D_SCAN_OUT_1, D_SCAN_OUT_2, D_SCAN_OUT_3, D_SCAN_OUT_4, D_SCAN_OUT_5, D_SCAN_OUT_6, D_SCAN_OUT_7, + output D_COUT0, D_COUT1, D_COUT2, D_COUT3, D_COUT4, D_COUT5, D_COUT6, D_COUT7, D_COUT8, D_COUT9, D_COUT10, D_COUT11, D_COUT12, D_COUT13, D_COUT14, D_COUT15, D_COUT16, D_COUT17, D_COUT18, D_COUT19, + + input D_REFCLKI, + output D_FFS_PLOL +); + parameter CH0_AUTO_CALIB_EN = "0b0"; + parameter CH0_AUTO_FACQ_EN = "0b0"; + parameter CH0_BAND_THRESHOLD = "0b000000"; + parameter CH0_CALIB_CK_MODE = "0b0"; + parameter CH0_CC_MATCH_1 = "0b0000000000"; + parameter CH0_CC_MATCH_2 = "0b0000000000"; + parameter CH0_CC_MATCH_3 = "0b0000000000"; + parameter CH0_CC_MATCH_4 = "0b0000000000"; + parameter CH0_CDR_CNT4SEL = "0b00"; + parameter CH0_CDR_CNT8SEL = "0b00"; + parameter CH0_CTC_BYPASS = "0b0"; + parameter CH0_DCOATDCFG = "0b00"; + parameter CH0_DCOATDDLY = "0b00"; + parameter CH0_DCOBYPSATD = "0b0"; + parameter CH0_DCOCALDIV = "0b000"; + parameter CH0_DCOCTLGI = "0b000"; + parameter CH0_DCODISBDAVOID = "0b0"; + parameter CH0_DCOFLTDAC = "0b00"; + parameter CH0_DCOFTNRG = "0b000"; + parameter CH0_DCOIOSTUNE = "0b000"; + parameter CH0_DCOITUNE = "0b00"; + parameter CH0_DCOITUNE4LSB = "0b000"; + parameter CH0_DCOIUPDNX2 = "0b0"; + parameter CH0_DCONUOFLSB = "0b000"; + parameter CH0_DCOSCALEI = "0b00"; + parameter CH0_DCOSTARTVAL = "0b000"; + parameter CH0_DCOSTEP = "0b00"; + parameter CH0_DEC_BYPASS = "0b0"; + parameter CH0_ENABLE_CG_ALIGN = "0b0"; + parameter CH0_ENC_BYPASS = "0b0"; + parameter CH0_FF_RX_F_CLK_DIS = "0b0"; + parameter CH0_FF_RX_H_CLK_EN = "0b0"; + parameter CH0_FF_TX_F_CLK_DIS = "0b0"; + parameter CH0_FF_TX_H_CLK_EN = "0b0"; + parameter CH0_GE_AN_ENABLE = "0b0"; + parameter CH0_INVERT_RX = "0b0"; + parameter CH0_INVERT_TX = "0b0"; + parameter CH0_LDR_CORE2TX_SEL = "0b0"; + parameter CH0_LDR_RX2CORE_SEL = "0b0"; + parameter CH0_LEQ_OFFSET_SEL = "0b0"; + parameter CH0_LEQ_OFFSET_TRIM = "0b000"; + parameter CH0_LSM_DISABLE = "0b0"; + parameter CH0_MATCH_2_ENABLE = "0b0"; + parameter CH0_MATCH_4_ENABLE = "0b0"; + parameter CH0_MIN_IPG_CNT = "0b00"; + parameter CH0_PCIE_EI_EN = "0b0"; + parameter CH0_PCIE_MODE = "0b0"; + parameter CH0_PCS_DET_TIME_SEL = "0b00"; + parameter CH0_PDEN_SEL = "0b0"; + parameter CH0_PRBS_ENABLE = "0b0"; + parameter CH0_PRBS_LOCK = "0b0"; + parameter CH0_PRBS_SELECTION = "0b0"; + parameter CH0_RATE_MODE_RX = "0b0"; + parameter CH0_RATE_MODE_TX = "0b0"; + parameter CH0_RCV_DCC_EN = "0b0"; + parameter CH0_REG_BAND_OFFSET = "0b0000"; + parameter CH0_REG_BAND_SEL = "0b000000"; + parameter CH0_REG_IDAC_EN = "0b0"; + parameter CH0_REG_IDAC_SEL = "0b0000000000"; + parameter CH0_REQ_EN = "0b0"; + parameter CH0_REQ_LVL_SET = "0b00"; + parameter CH0_RIO_MODE = "0b0"; + parameter CH0_RLOS_SEL = "0b0"; + parameter CH0_RPWDNB = "0b0"; + parameter CH0_RTERM_RX = "0b00000"; + parameter CH0_RTERM_TX = "0b00000"; + parameter CH0_RXIN_CM = "0b00"; + parameter CH0_RXTERM_CM = "0b00"; + parameter CH0_RX_DCO_CK_DIV = "0b000"; + parameter CH0_RX_DIV11_SEL = "0b0"; + parameter CH0_RX_GEAR_BYPASS = "0b0"; + parameter CH0_RX_GEAR_MODE = "0b0"; + parameter CH0_RX_LOS_CEQ = "0b00"; + parameter CH0_RX_LOS_EN = "0b0"; + parameter CH0_RX_LOS_HYST_EN = "0b0"; + parameter CH0_RX_LOS_LVL = "0b000"; + parameter CH0_RX_RATE_SEL = "0b0000"; + parameter CH0_RX_SB_BYPASS = "0b0"; + parameter CH0_SB_BYPASS = "0b0"; + parameter CH0_SEL_SD_RX_CLK = "0b0"; + parameter CH0_TDRV_DAT_SEL = "0b00"; + parameter CH0_TDRV_POST_EN = "0b0"; + parameter CH0_TDRV_PRE_EN = "0b0"; + parameter CH0_TDRV_SLICE0_CUR = "0b000"; + parameter CH0_TDRV_SLICE0_SEL = "0b00"; + parameter CH0_TDRV_SLICE1_CUR = "0b000"; + parameter CH0_TDRV_SLICE1_SEL = "0b00"; + parameter CH0_TDRV_SLICE2_CUR = "0b00"; + parameter CH0_TDRV_SLICE2_SEL = "0b00"; + parameter CH0_TDRV_SLICE3_CUR = "0b00"; + parameter CH0_TDRV_SLICE3_SEL = "0b00"; + parameter CH0_TDRV_SLICE4_CUR = "0b00"; + parameter CH0_TDRV_SLICE4_SEL = "0b00"; + parameter CH0_TDRV_SLICE5_CUR = "0b00"; + parameter CH0_TDRV_SLICE5_SEL = "0b00"; + parameter CH0_TPWDNB = "0b0"; + parameter CH0_TX_CM_SEL = "0b00"; + parameter CH0_TX_DIV11_SEL = "0b0"; + parameter CH0_TX_GEAR_BYPASS = "0b0"; + parameter CH0_TX_GEAR_MODE = "0b0"; + parameter CH0_TX_POST_SIGN = "0b0"; + parameter CH0_TX_PRE_SIGN = "0b0"; + parameter CH0_UC_MODE = "0b0"; + parameter CH0_UDF_COMMA_A = "0b0000000000"; + parameter CH0_UDF_COMMA_B = "0b0000000000"; + parameter CH0_UDF_COMMA_MASK = "0b0000000000"; + parameter CH0_WA_BYPASS = "0b0"; + parameter CH0_WA_MODE = "0b0"; + parameter CH1_AUTO_CALIB_EN = "0b0"; + parameter CH1_AUTO_FACQ_EN = "0b0"; + parameter CH1_BAND_THRESHOLD = "0b000000"; + parameter CH1_CALIB_CK_MODE = "0b0"; + parameter CH1_CC_MATCH_1 = "0b0000000000"; + parameter CH1_CC_MATCH_2 = "0b0000000000"; + parameter CH1_CC_MATCH_3 = "0b0000000000"; + parameter CH1_CC_MATCH_4 = "0b0000000000"; + parameter CH1_CDR_CNT4SEL = "0b00"; + parameter CH1_CDR_CNT8SEL = "0b00"; + parameter CH1_CTC_BYPASS = "0b0"; + parameter CH1_DCOATDCFG = "0b00"; + parameter CH1_DCOATDDLY = "0b00"; + parameter CH1_DCOBYPSATD = "0b0"; + parameter CH1_DCOCALDIV = "0b000"; + parameter CH1_DCOCTLGI = "0b000"; + parameter CH1_DCODISBDAVOID = "0b0"; + parameter CH1_DCOFLTDAC = "0b00"; + parameter CH1_DCOFTNRG = "0b000"; + parameter CH1_DCOIOSTUNE = "0b000"; + parameter CH1_DCOITUNE = "0b00"; + parameter CH1_DCOITUNE4LSB = "0b000"; + parameter CH1_DCOIUPDNX2 = "0b0"; + parameter CH1_DCONUOFLSB = "0b000"; + parameter CH1_DCOSCALEI = "0b00"; + parameter CH1_DCOSTARTVAL = "0b000"; + parameter CH1_DCOSTEP = "0b00"; + parameter CH1_DEC_BYPASS = "0b0"; + parameter CH1_ENABLE_CG_ALIGN = "0b0"; + parameter CH1_ENC_BYPASS = "0b0"; + parameter CH1_FF_RX_F_CLK_DIS = "0b0"; + parameter CH1_FF_RX_H_CLK_EN = "0b0"; + parameter CH1_FF_TX_F_CLK_DIS = "0b0"; + parameter CH1_FF_TX_H_CLK_EN = "0b0"; + parameter CH1_GE_AN_ENABLE = "0b0"; + parameter CH1_INVERT_RX = "0b0"; + parameter CH1_INVERT_TX = "0b0"; + parameter CH1_LDR_CORE2TX_SEL = "0b0"; + parameter CH1_LDR_RX2CORE_SEL = "0b0"; + parameter CH1_LEQ_OFFSET_SEL = "0b0"; + parameter CH1_LEQ_OFFSET_TRIM = "0b000"; + parameter CH1_LSM_DISABLE = "0b0"; + parameter CH1_MATCH_2_ENABLE = "0b0"; + parameter CH1_MATCH_4_ENABLE = "0b0"; + parameter CH1_MIN_IPG_CNT = "0b00"; + parameter CH1_PCIE_EI_EN = "0b0"; + parameter CH1_PCIE_MODE = "0b0"; + parameter CH1_PCS_DET_TIME_SEL = "0b00"; + parameter CH1_PDEN_SEL = "0b0"; + parameter CH1_PRBS_ENABLE = "0b0"; + parameter CH1_PRBS_LOCK = "0b0"; + parameter CH1_PRBS_SELECTION = "0b0"; + parameter CH1_RATE_MODE_RX = "0b0"; + parameter CH1_RATE_MODE_TX = "0b0"; + parameter CH1_RCV_DCC_EN = "0b0"; + parameter CH1_REG_BAND_OFFSET = "0b0000"; + parameter CH1_REG_BAND_SEL = "0b000000"; + parameter CH1_REG_IDAC_EN = "0b0"; + parameter CH1_REG_IDAC_SEL = "0b0000000000"; + parameter CH1_REQ_EN = "0b0"; + parameter CH1_REQ_LVL_SET = "0b00"; + parameter CH1_RIO_MODE = "0b0"; + parameter CH1_RLOS_SEL = "0b0"; + parameter CH1_RPWDNB = "0b0"; + parameter CH1_RTERM_RX = "0b00000"; + parameter CH1_RTERM_TX = "0b00000"; + parameter CH1_RXIN_CM = "0b00"; + parameter CH1_RXTERM_CM = "0b00"; + parameter CH1_RX_DCO_CK_DIV = "0b000"; + parameter CH1_RX_DIV11_SEL = "0b0"; + parameter CH1_RX_GEAR_BYPASS = "0b0"; + parameter CH1_RX_GEAR_MODE = "0b0"; + parameter CH1_RX_LOS_CEQ = "0b00"; + parameter CH1_RX_LOS_EN = "0b0"; + parameter CH1_RX_LOS_HYST_EN = "0b0"; + parameter CH1_RX_LOS_LVL = "0b000"; + parameter CH1_RX_RATE_SEL = "0b0000"; + parameter CH1_RX_SB_BYPASS = "0b0"; + parameter CH1_SB_BYPASS = "0b0"; + parameter CH1_SEL_SD_RX_CLK = "0b0"; + parameter CH1_TDRV_DAT_SEL = "0b00"; + parameter CH1_TDRV_POST_EN = "0b0"; + parameter CH1_TDRV_PRE_EN = "0b0"; + parameter CH1_TDRV_SLICE0_CUR = "0b000"; + parameter CH1_TDRV_SLICE0_SEL = "0b00"; + parameter CH1_TDRV_SLICE1_CUR = "0b000"; + parameter CH1_TDRV_SLICE1_SEL = "0b00"; + parameter CH1_TDRV_SLICE2_CUR = "0b00"; + parameter CH1_TDRV_SLICE2_SEL = "0b00"; + parameter CH1_TDRV_SLICE3_CUR = "0b00"; + parameter CH1_TDRV_SLICE3_SEL = "0b00"; + parameter CH1_TDRV_SLICE4_CUR = "0b00"; + parameter CH1_TDRV_SLICE4_SEL = "0b00"; + parameter CH1_TDRV_SLICE5_CUR = "0b00"; + parameter CH1_TDRV_SLICE5_SEL = "0b00"; + parameter CH1_TPWDNB = "0b0"; + parameter CH1_TX_CM_SEL = "0b00"; + parameter CH1_TX_DIV11_SEL = "0b0"; + parameter CH1_TX_GEAR_BYPASS = "0b0"; + parameter CH1_TX_GEAR_MODE = "0b0"; + parameter CH1_TX_POST_SIGN = "0b0"; + parameter CH1_TX_PRE_SIGN = "0b0"; + parameter CH1_UC_MODE = "0b0"; + parameter CH1_UDF_COMMA_A = "0b0000000000"; + parameter CH1_UDF_COMMA_B = "0b0000000000"; + parameter CH1_UDF_COMMA_MASK = "0b0000000000"; + parameter CH1_WA_BYPASS = "0b0"; + parameter CH1_WA_MODE = "0b0"; + parameter D_BITCLK_FROM_ND_EN = "0b0"; + parameter D_BITCLK_LOCAL_EN = "0b0"; + parameter D_BITCLK_ND_EN = "0b0"; + parameter D_BUS8BIT_SEL = "0b0"; + parameter D_CDR_LOL_SET = "0b00"; + parameter D_CMUSETBIASI = "0b00"; + parameter D_CMUSETI4CPP = "0b0000"; + parameter D_CMUSETI4CPZ = "0b0000"; + parameter D_CMUSETI4VCO = "0b00"; + parameter D_CMUSETICP4P = "0b00"; + parameter D_CMUSETICP4Z = "0b000"; + parameter D_CMUSETINITVCT = "0b00"; + parameter D_CMUSETISCL4VCO = "0b000"; + parameter D_CMUSETP1GM = "0b000"; + parameter D_CMUSETP2AGM = "0b000"; + parameter D_CMUSETZGM = "0b000"; + parameter D_DCO_CALIB_TIME_SEL = "0b00"; + parameter D_HIGH_MARK = "0b0000"; + parameter D_IB_PWDNB = "0b0"; + parameter D_ISETLOS = "0b00000000"; + parameter D_LOW_MARK = "0b0000"; + parameter D_MACROPDB = "0b0"; + parameter D_PD_ISET = "0b00"; + parameter D_PLL_LOL_SET = "0b00"; + parameter D_REFCK_MODE = "0b000"; + parameter D_REQ_ISET = "0b000"; + parameter D_RG_EN = "0b0"; + parameter D_RG_SET = "0b00"; + parameter D_SETICONST_AUX = "0b00"; + parameter D_SETICONST_CH = "0b00"; + parameter D_SETIRPOLY_AUX = "0b00"; + parameter D_SETIRPOLY_CH = "0b00"; + parameter D_SETPLLRC = "0b000000"; + parameter D_SYNC_LOCAL_EN = "0b0"; + parameter D_SYNC_ND_EN = "0b0"; + parameter D_TXPLL_PWDNB = "0b0"; + parameter D_TX_VCO_CK_DIV = "0b000"; + parameter D_XGE_MODE = "0b0"; + +// These parameters don't do anything but are +// needed for compatability with Diamond + parameter D_TX_MAX_RATE = "2.5"; + parameter D_RX_MAX_RATE = "2.5"; + parameter CH0_TXAMPLITUDE = "0d1300"; + parameter CH1_TXAMPLITUDE = "0d1300"; + parameter CH0_PROTOCOL = "8B10B"; + parameter CH1_PROTOCOL = "8B10B"; + parameter CH0_CDR_MAX_RATE = "2.5"; + parameter CH1_CDR_MAX_RATE = "2.5"; +endmodule + +(* blackbox *) +module EXTREFB ( + input REFCLKP, REFCLKN, + output REFCLKO +); + parameter REFCK_PWDNB = "0b0"; + parameter REFCK_RTERM = "0b0"; + parameter REFCK_DCBIAS_EN = "0b0"; +endmodule + +(* blackbox *) +module PCSCLKDIV ( + input CLKI, RST, SEL2, SEL1, SEL0, + output CDIV1, CDIVX +); + parameter GSR = "DISABLED"; +endmodule diff --git a/techlibs/ecp5/cells_sim.v b/techlibs/ecp5/cells_sim.v index 6e4b0a5ac..507ab1beb 100644 --- a/techlibs/ecp5/cells_sim.v +++ b/techlibs/ecp5/cells_sim.v @@ -257,7 +257,7 @@ assign O = I; endmodule // --------------------------------------- - +(* keep *) module TRELLIS_IO( inout B, input I, diff --git a/techlibs/ecp5/synth_ecp5.cc b/techlibs/ecp5/synth_ecp5.cc index cb6a4c3d8..825e131c4 100644 --- a/techlibs/ecp5/synth_ecp5.cc +++ b/techlibs/ecp5/synth_ecp5.cc @@ -203,7 +203,7 @@ struct SynthEcp5Pass : public ScriptPass { if (check_label("begin")) { - run("read_verilog -lib +/ecp5/cells_sim.v"); + run("read_verilog -lib +/ecp5/cells_sim.v +/ecp5/cells_bb.v"); run(stringf("hierarchy -check %s", help_mode ? "-top <top>" : top_opt.c_str())); } diff --git a/techlibs/sf2/Makefile.inc b/techlibs/sf2/Makefile.inc new file mode 100644 index 000000000..cade49f37 --- /dev/null +++ b/techlibs/sf2/Makefile.inc @@ -0,0 +1,7 @@ + +OBJS += techlibs/sf2/synth_sf2.o + +$(eval $(call add_share_file,share/sf2,techlibs/sf2/arith_map.v)) +$(eval $(call add_share_file,share/sf2,techlibs/sf2/cells_map.v)) +$(eval $(call add_share_file,share/sf2,techlibs/sf2/cells_sim.v)) + diff --git a/techlibs/sf2/arith_map.v b/techlibs/sf2/arith_map.v new file mode 100644 index 000000000..462d3ce50 --- /dev/null +++ b/techlibs/sf2/arith_map.v @@ -0,0 +1,21 @@ +/* + * yosys -- Yosys Open SYnthesis Suite + * + * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at> + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + * + */ + + +// nothing here yet diff --git a/techlibs/sf2/cells_map.v b/techlibs/sf2/cells_map.v new file mode 100644 index 000000000..5b8888294 --- /dev/null +++ b/techlibs/sf2/cells_map.v @@ -0,0 +1,68 @@ +// module \$_DFF_N_ (input D, C, output Q); SB_DFFN _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C)); endmodule + +module \$_DFF_P_ (input D, C, output Q); + SLE _TECHMAP_REPLACE_ ( + .D(D), + .CLK(C), + .EN(1'b1), + .ALn(1'b1), + .ADn(1'b1), + .SLn(1'b1), + .SD(1'b0), + .LAT(1'b0), + .Q(Q) + ); +endmodule + +// module \$_DFFE_NN_ (input D, C, E, output Q); SB_DFFNE _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .E(!E)); endmodule +// module \$_DFFE_PN_ (input D, C, E, output Q); SB_DFFE _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .E(!E)); endmodule +// +// module \$_DFFE_NP_ (input D, C, E, output Q); SB_DFFNE _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .E(E)); endmodule +// module \$_DFFE_PP_ (input D, C, E, output Q); SB_DFFE _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .E(E)); endmodule +// +// module \$_DFF_NN0_ (input D, C, R, output Q); SB_DFFNR _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .R(!R)); endmodule +// module \$_DFF_NN1_ (input D, C, R, output Q); SB_DFFNS _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .S(!R)); endmodule +// module \$_DFF_PN0_ (input D, C, R, output Q); SB_DFFR _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .R(!R)); endmodule +// module \$_DFF_PN1_ (input D, C, R, output Q); SB_DFFS _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .S(!R)); endmodule +// +// module \$_DFF_NP0_ (input D, C, R, output Q); SB_DFFNR _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .R(R)); endmodule +// module \$_DFF_NP1_ (input D, C, R, output Q); SB_DFFNS _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .S(R)); endmodule +// module \$_DFF_PP0_ (input D, C, R, output Q); SB_DFFR _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .R(R)); endmodule +// module \$_DFF_PP1_ (input D, C, R, output Q); SB_DFFS _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .S(R)); endmodule +// +// module \$__DFFE_NN0 (input D, C, E, R, output Q); SB_DFFNER _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .E(E), .R(!R)); endmodule +// module \$__DFFE_NN1 (input D, C, E, R, output Q); SB_DFFNES _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .E(E), .S(!R)); endmodule +// module \$__DFFE_PN0 (input D, C, E, R, output Q); SB_DFFER _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .E(E), .R(!R)); endmodule +// module \$__DFFE_PN1 (input D, C, E, R, output Q); SB_DFFES _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .E(E), .S(!R)); endmodule +// +// module \$__DFFE_NP0 (input D, C, E, R, output Q); SB_DFFNER _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .E(E), .R(R)); endmodule +// module \$__DFFE_NP1 (input D, C, E, R, output Q); SB_DFFNES _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .E(E), .S(R)); endmodule +// module \$__DFFE_PP0 (input D, C, E, R, output Q); SB_DFFER _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .E(E), .R(R)); endmodule +// module \$__DFFE_PP1 (input D, C, E, R, output Q); SB_DFFES _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .E(E), .S(R)); endmodule + +`ifndef NO_LUT +module \$lut (A, Y); + parameter WIDTH = 0; + parameter LUT = 0; + + input [WIDTH-1:0] A; + output Y; + + generate + if (WIDTH == 1) begin + CFG1 #(.INIT(LUT)) _TECHMAP_REPLACE_ (.Y(Y), .A(A[0])); + end else + if (WIDTH == 2) begin + CFG2 #(.INIT(LUT)) _TECHMAP_REPLACE_ (.Y(Y), .A(A[0]), .B(A[1])); + end else + if (WIDTH == 3) begin + CFG3 #(.INIT(LUT)) _TECHMAP_REPLACE_ (.Y(Y), .A(A[0]), .B(A[1]), .C(A[2])); + end else + if (WIDTH == 4) begin + CFG4 #(.INIT(LUT)) _TECHMAP_REPLACE_ (.Y(Y), .A(A[0]), .B(A[1]), .C(A[2]), .D(A[3])); + end else begin + wire _TECHMAP_FAIL_ = 1; + end + endgenerate +endmodule +`endif diff --git a/techlibs/sf2/cells_sim.v b/techlibs/sf2/cells_sim.v new file mode 100644 index 000000000..b03b2c750 --- /dev/null +++ b/techlibs/sf2/cells_sim.v @@ -0,0 +1,75 @@ +module SLE ( + output Q, + input ADn, + input ALn, + input CLK, + input D, + input LAT, + input SD, + input EN, + input SLn +); + reg q_latch, q_ff; + + always @(posedge CLK, negedge ALn) begin + if (!ALn) begin + q_ff <= !ADn; + end else if (EN) begin + if (!SLn) + q_ff <= SD; + else + q_ff <= D; + end + end + + always @* begin + if (!ALn) begin + q_latch <= !ADn; + end else if (CLK && EN) begin + if (!SLn) + q_ff <= SD; + else + q_ff <= D; + end + end + + assign Q = LAT ? q_latch : q_ff; +endmodule + +module CFG1 ( + output Y, + input A +); + parameter [1:0] INIT = 2'h0; + assign Y = INIT >> A; +endmodule + +module CFG2 ( + output Y, + input A, + input B +); + parameter [3:0] INIT = 4'h0; + assign Y = INIT >> {B, A}; +endmodule + +module CFG3 ( + output Y, + input A, + input B, + input C +); + parameter [7:0] INIT = 8'h0; + assign Y = INIT >> {C, B, A}; +endmodule + +module CFG4 ( + output Y, + input A, + input B, + input C, + input D +); + parameter [15:0] INIT = 16'h0; + assign Y = INIT >> {D, C, B, A}; +endmodule diff --git a/techlibs/sf2/synth_sf2.cc b/techlibs/sf2/synth_sf2.cc new file mode 100644 index 000000000..2676ea657 --- /dev/null +++ b/techlibs/sf2/synth_sf2.cc @@ -0,0 +1,206 @@ +/* + * yosys -- Yosys Open SYnthesis Suite + * + * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at> + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + * + */ + +#include "kernel/register.h" +#include "kernel/celltypes.h" +#include "kernel/rtlil.h" +#include "kernel/log.h" + +USING_YOSYS_NAMESPACE +PRIVATE_NAMESPACE_BEGIN + +struct SynthSf2Pass : public ScriptPass +{ + SynthSf2Pass() : ScriptPass("synth_sf2", "synthesis for SmartFusion2 and IGLOO2 FPGAs") { } + + void help() YS_OVERRIDE + { + // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| + log("\n"); + log(" synth_sf2 [options]\n"); + log("\n"); + log("This command runs synthesis for SmartFusion2 and IGLOO2 FPGAs.\n"); + log("\n"); + log(" -top <module>\n"); + log(" use the specified module as top module\n"); + log("\n"); + log(" -edif <file>\n"); + log(" write the design to the specified EDIF file. writing of an output file\n"); + log(" is omitted if this parameter is not specified.\n"); + log("\n"); + log(" -json <file>\n"); + log(" write the design to the specified JSON file. writing of an output file\n"); + log(" is omitted if this parameter is not specified.\n"); + log("\n"); + log(" -run <from_label>:<to_label>\n"); + log(" only run the commands between the labels (see below). an empty\n"); + log(" from label is synonymous to 'begin', and empty to label is\n"); + log(" synonymous to the end of the command list.\n"); + log("\n"); + log(" -noflatten\n"); + log(" do not flatten design before synthesis\n"); + log("\n"); + log(" -retime\n"); + log(" run 'abc' with -dff option\n"); + log("\n"); + log("\n"); + log("The following commands are executed by this synthesis command:\n"); + help_script(); + log("\n"); + } + + string top_opt, edif_file, json_file; + bool flatten, retime; + + void clear_flags() YS_OVERRIDE + { + top_opt = "-auto-top"; + edif_file = ""; + json_file = ""; + flatten = true; + retime = false; + } + + void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE + { + string run_from, run_to; + clear_flags(); + + size_t argidx; + for (argidx = 1; argidx < args.size(); argidx++) + { + if (args[argidx] == "-top" && argidx+1 < args.size()) { + top_opt = "-top " + args[++argidx]; + continue; + } + if (args[argidx] == "-edif" && argidx+1 < args.size()) { + edif_file = args[++argidx]; + continue; + } + if (args[argidx] == "-json" && argidx+1 < args.size()) { + json_file = args[++argidx]; + continue; + } + if (args[argidx] == "-run" && argidx+1 < args.size()) { + size_t pos = args[argidx+1].find(':'); + if (pos == std::string::npos) + break; + run_from = args[++argidx].substr(0, pos); + run_to = args[argidx].substr(pos+1); + continue; + } + if (args[argidx] == "-noflatten") { + flatten = false; + continue; + } + if (args[argidx] == "-retime") { + retime = true; + continue; + } + break; + } + extra_args(args, argidx, design); + + if (!design->full_selection()) + log_cmd_error("This comannd only operates on fully selected designs!\n"); + + log_header(design, "Executing SYNTH_SF2 pass.\n"); + log_push(); + + run_script(design, run_from, run_to); + + log_pop(); + } + + void script() YS_OVERRIDE + { + if (check_label("begin")) + { + run("read_verilog -lib +/sf2/cells_sim.v"); + run(stringf("hierarchy -check %s", help_mode ? "-top <top>" : top_opt.c_str())); + } + + if (flatten && check_label("flatten", "(unless -noflatten)")) + { + run("proc"); + run("flatten"); + run("tribuf -logic"); + run("deminout"); + } + + if (check_label("coarse")) + { + run("synth -run coarse"); + } + + if (check_label("fine")) + { + run("opt -fast -mux_undef -undriven -fine"); + run("memory_map"); + run("opt -undriven -fine"); + run("techmap -map +/techmap.v -map +/sf2/arith_map.v"); + if (retime || help_mode) + run("abc -dff", "(only if -retime)"); + } + + if (check_label("map_ffs")) + { + run("dffsr2dff"); + run("techmap -D NO_LUT -map +/sf2/cells_map.v"); + run("opt_expr -mux_undef"); + run("simplemap"); + // run("sf2_ffinit"); + // run("sf2_ffssr"); + // run("sf2_opt -full"); + } + + if (check_label("map_luts")) + { + run("abc -lut 4"); + run("clean"); + } + + if (check_label("map_cells")) + { + run("techmap -map +/sf2/cells_map.v"); + run("clean"); + } + + if (check_label("check")) + { + run("hierarchy -check"); + run("stat"); + run("check -noinit"); + } + + if (check_label("edif")) + { + if (!edif_file.empty() || help_mode) + run(stringf("write_edif %s", help_mode ? "<file-name>" : edif_file.c_str())); + } + + if (check_label("json")) + { + if (!json_file.empty() || help_mode) + run(stringf("write_json %s", help_mode ? "<file-name>" : json_file.c_str())); + } + } +} SynthSf2Pass; + +PRIVATE_NAMESPACE_END diff --git a/techlibs/xilinx/cells_xtra.sh b/techlibs/xilinx/cells_xtra.sh index e7c7d17bf..0480410f5 100644 --- a/techlibs/xilinx/cells_xtra.sh +++ b/techlibs/xilinx/cells_xtra.sh @@ -112,6 +112,7 @@ function xtract_cell_decl() xtract_cell_decl PHY_CONTROL xtract_cell_decl PLLE2_ADV xtract_cell_decl PLLE2_BASE + xtract_cell_decl PS7 xtract_cell_decl PULLDOWN xtract_cell_decl PULLUP # xtract_cell_decl RAM128X1D diff --git a/techlibs/xilinx/cells_xtra.v b/techlibs/xilinx/cells_xtra.v index 69e54233a..8d8b91ddc 100644 --- a/techlibs/xilinx/cells_xtra.v +++ b/techlibs/xilinx/cells_xtra.v @@ -3057,6 +3057,629 @@ module PLLE2_BASE (...); input RST; endmodule +module PS7 (...); + output DMA0DAVALID; + output DMA0DRREADY; + output DMA0RSTN; + output DMA1DAVALID; + output DMA1DRREADY; + output DMA1RSTN; + output DMA2DAVALID; + output DMA2DRREADY; + output DMA2RSTN; + output DMA3DAVALID; + output DMA3DRREADY; + output DMA3RSTN; + output EMIOCAN0PHYTX; + output EMIOCAN1PHYTX; + output EMIOENET0GMIITXEN; + output EMIOENET0GMIITXER; + output EMIOENET0MDIOMDC; + output EMIOENET0MDIOO; + output EMIOENET0MDIOTN; + output EMIOENET0PTPDELAYREQRX; + output EMIOENET0PTPDELAYREQTX; + output EMIOENET0PTPPDELAYREQRX; + output EMIOENET0PTPPDELAYREQTX; + output EMIOENET0PTPPDELAYRESPRX; + output EMIOENET0PTPPDELAYRESPTX; + output EMIOENET0PTPSYNCFRAMERX; + output EMIOENET0PTPSYNCFRAMETX; + output EMIOENET0SOFRX; + output EMIOENET0SOFTX; + output EMIOENET1GMIITXEN; + output EMIOENET1GMIITXER; + output EMIOENET1MDIOMDC; + output EMIOENET1MDIOO; + output EMIOENET1MDIOTN; + output EMIOENET1PTPDELAYREQRX; + output EMIOENET1PTPDELAYREQTX; + output EMIOENET1PTPPDELAYREQRX; + output EMIOENET1PTPPDELAYREQTX; + output EMIOENET1PTPPDELAYRESPRX; + output EMIOENET1PTPPDELAYRESPTX; + output EMIOENET1PTPSYNCFRAMERX; + output EMIOENET1PTPSYNCFRAMETX; + output EMIOENET1SOFRX; + output EMIOENET1SOFTX; + output EMIOI2C0SCLO; + output EMIOI2C0SCLTN; + output EMIOI2C0SDAO; + output EMIOI2C0SDATN; + output EMIOI2C1SCLO; + output EMIOI2C1SCLTN; + output EMIOI2C1SDAO; + output EMIOI2C1SDATN; + output EMIOPJTAGTDO; + output EMIOPJTAGTDTN; + output EMIOSDIO0BUSPOW; + output EMIOSDIO0CLK; + output EMIOSDIO0CMDO; + output EMIOSDIO0CMDTN; + output EMIOSDIO0LED; + output EMIOSDIO1BUSPOW; + output EMIOSDIO1CLK; + output EMIOSDIO1CMDO; + output EMIOSDIO1CMDTN; + output EMIOSDIO1LED; + output EMIOSPI0MO; + output EMIOSPI0MOTN; + output EMIOSPI0SCLKO; + output EMIOSPI0SCLKTN; + output EMIOSPI0SO; + output EMIOSPI0SSNTN; + output EMIOSPI0STN; + output EMIOSPI1MO; + output EMIOSPI1MOTN; + output EMIOSPI1SCLKO; + output EMIOSPI1SCLKTN; + output EMIOSPI1SO; + output EMIOSPI1SSNTN; + output EMIOSPI1STN; + output EMIOTRACECTL; + output EMIOUART0DTRN; + output EMIOUART0RTSN; + output EMIOUART0TX; + output EMIOUART1DTRN; + output EMIOUART1RTSN; + output EMIOUART1TX; + output EMIOUSB0VBUSPWRSELECT; + output EMIOUSB1VBUSPWRSELECT; + output EMIOWDTRSTO; + output EVENTEVENTO; + output MAXIGP0ARESETN; + output MAXIGP0ARVALID; + output MAXIGP0AWVALID; + output MAXIGP0BREADY; + output MAXIGP0RREADY; + output MAXIGP0WLAST; + output MAXIGP0WVALID; + output MAXIGP1ARESETN; + output MAXIGP1ARVALID; + output MAXIGP1AWVALID; + output MAXIGP1BREADY; + output MAXIGP1RREADY; + output MAXIGP1WLAST; + output MAXIGP1WVALID; + output SAXIACPARESETN; + output SAXIACPARREADY; + output SAXIACPAWREADY; + output SAXIACPBVALID; + output SAXIACPRLAST; + output SAXIACPRVALID; + output SAXIACPWREADY; + output SAXIGP0ARESETN; + output SAXIGP0ARREADY; + output SAXIGP0AWREADY; + output SAXIGP0BVALID; + output SAXIGP0RLAST; + output SAXIGP0RVALID; + output SAXIGP0WREADY; + output SAXIGP1ARESETN; + output SAXIGP1ARREADY; + output SAXIGP1AWREADY; + output SAXIGP1BVALID; + output SAXIGP1RLAST; + output SAXIGP1RVALID; + output SAXIGP1WREADY; + output SAXIHP0ARESETN; + output SAXIHP0ARREADY; + output SAXIHP0AWREADY; + output SAXIHP0BVALID; + output SAXIHP0RLAST; + output SAXIHP0RVALID; + output SAXIHP0WREADY; + output SAXIHP1ARESETN; + output SAXIHP1ARREADY; + output SAXIHP1AWREADY; + output SAXIHP1BVALID; + output SAXIHP1RLAST; + output SAXIHP1RVALID; + output SAXIHP1WREADY; + output SAXIHP2ARESETN; + output SAXIHP2ARREADY; + output SAXIHP2AWREADY; + output SAXIHP2BVALID; + output SAXIHP2RLAST; + output SAXIHP2RVALID; + output SAXIHP2WREADY; + output SAXIHP3ARESETN; + output SAXIHP3ARREADY; + output SAXIHP3AWREADY; + output SAXIHP3BVALID; + output SAXIHP3RLAST; + output SAXIHP3RVALID; + output SAXIHP3WREADY; + output [11:0] MAXIGP0ARID; + output [11:0] MAXIGP0AWID; + output [11:0] MAXIGP0WID; + output [11:0] MAXIGP1ARID; + output [11:0] MAXIGP1AWID; + output [11:0] MAXIGP1WID; + output [1:0] DMA0DATYPE; + output [1:0] DMA1DATYPE; + output [1:0] DMA2DATYPE; + output [1:0] DMA3DATYPE; + output [1:0] EMIOUSB0PORTINDCTL; + output [1:0] EMIOUSB1PORTINDCTL; + output [1:0] EVENTSTANDBYWFE; + output [1:0] EVENTSTANDBYWFI; + output [1:0] MAXIGP0ARBURST; + output [1:0] MAXIGP0ARLOCK; + output [1:0] MAXIGP0ARSIZE; + output [1:0] MAXIGP0AWBURST; + output [1:0] MAXIGP0AWLOCK; + output [1:0] MAXIGP0AWSIZE; + output [1:0] MAXIGP1ARBURST; + output [1:0] MAXIGP1ARLOCK; + output [1:0] MAXIGP1ARSIZE; + output [1:0] MAXIGP1AWBURST; + output [1:0] MAXIGP1AWLOCK; + output [1:0] MAXIGP1AWSIZE; + output [1:0] SAXIACPBRESP; + output [1:0] SAXIACPRRESP; + output [1:0] SAXIGP0BRESP; + output [1:0] SAXIGP0RRESP; + output [1:0] SAXIGP1BRESP; + output [1:0] SAXIGP1RRESP; + output [1:0] SAXIHP0BRESP; + output [1:0] SAXIHP0RRESP; + output [1:0] SAXIHP1BRESP; + output [1:0] SAXIHP1RRESP; + output [1:0] SAXIHP2BRESP; + output [1:0] SAXIHP2RRESP; + output [1:0] SAXIHP3BRESP; + output [1:0] SAXIHP3RRESP; + output [28:0] IRQP2F; + output [2:0] EMIOSDIO0BUSVOLT; + output [2:0] EMIOSDIO1BUSVOLT; + output [2:0] EMIOSPI0SSON; + output [2:0] EMIOSPI1SSON; + output [2:0] EMIOTTC0WAVEO; + output [2:0] EMIOTTC1WAVEO; + output [2:0] MAXIGP0ARPROT; + output [2:0] MAXIGP0AWPROT; + output [2:0] MAXIGP1ARPROT; + output [2:0] MAXIGP1AWPROT; + output [2:0] SAXIACPBID; + output [2:0] SAXIACPRID; + output [2:0] SAXIHP0RACOUNT; + output [2:0] SAXIHP1RACOUNT; + output [2:0] SAXIHP2RACOUNT; + output [2:0] SAXIHP3RACOUNT; + output [31:0] EMIOTRACEDATA; + output [31:0] FTMTP2FDEBUG; + output [31:0] MAXIGP0ARADDR; + output [31:0] MAXIGP0AWADDR; + output [31:0] MAXIGP0WDATA; + output [31:0] MAXIGP1ARADDR; + output [31:0] MAXIGP1AWADDR; + output [31:0] MAXIGP1WDATA; + output [31:0] SAXIGP0RDATA; + output [31:0] SAXIGP1RDATA; + output [3:0] EMIOSDIO0DATAO; + output [3:0] EMIOSDIO0DATATN; + output [3:0] EMIOSDIO1DATAO; + output [3:0] EMIOSDIO1DATATN; + output [3:0] FCLKCLK; + output [3:0] FCLKRESETN; + output [3:0] FTMTF2PTRIGACK; + output [3:0] FTMTP2FTRIG; + output [3:0] MAXIGP0ARCACHE; + output [3:0] MAXIGP0ARLEN; + output [3:0] MAXIGP0ARQOS; + output [3:0] MAXIGP0AWCACHE; + output [3:0] MAXIGP0AWLEN; + output [3:0] MAXIGP0AWQOS; + output [3:0] MAXIGP0WSTRB; + output [3:0] MAXIGP1ARCACHE; + output [3:0] MAXIGP1ARLEN; + output [3:0] MAXIGP1ARQOS; + output [3:0] MAXIGP1AWCACHE; + output [3:0] MAXIGP1AWLEN; + output [3:0] MAXIGP1AWQOS; + output [3:0] MAXIGP1WSTRB; + output [5:0] SAXIGP0BID; + output [5:0] SAXIGP0RID; + output [5:0] SAXIGP1BID; + output [5:0] SAXIGP1RID; + output [5:0] SAXIHP0BID; + output [5:0] SAXIHP0RID; + output [5:0] SAXIHP0WACOUNT; + output [5:0] SAXIHP1BID; + output [5:0] SAXIHP1RID; + output [5:0] SAXIHP1WACOUNT; + output [5:0] SAXIHP2BID; + output [5:0] SAXIHP2RID; + output [5:0] SAXIHP2WACOUNT; + output [5:0] SAXIHP3BID; + output [5:0] SAXIHP3RID; + output [5:0] SAXIHP3WACOUNT; + output [63:0] EMIOGPIOO; + output [63:0] EMIOGPIOTN; + output [63:0] SAXIACPRDATA; + output [63:0] SAXIHP0RDATA; + output [63:0] SAXIHP1RDATA; + output [63:0] SAXIHP2RDATA; + output [63:0] SAXIHP3RDATA; + output [7:0] EMIOENET0GMIITXD; + output [7:0] EMIOENET1GMIITXD; + output [7:0] SAXIHP0RCOUNT; + output [7:0] SAXIHP0WCOUNT; + output [7:0] SAXIHP1RCOUNT; + output [7:0] SAXIHP1WCOUNT; + output [7:0] SAXIHP2RCOUNT; + output [7:0] SAXIHP2WCOUNT; + output [7:0] SAXIHP3RCOUNT; + output [7:0] SAXIHP3WCOUNT; + inout DDRCASB; + inout DDRCKE; + inout DDRCKN; + inout DDRCKP; + inout DDRCSB; + inout DDRDRSTB; + inout DDRODT; + inout DDRRASB; + inout DDRVRN; + inout DDRVRP; + inout DDRWEB; + inout PSCLK; + inout PSPORB; + inout PSSRSTB; + inout [14:0] DDRA; + inout [2:0] DDRBA; + inout [31:0] DDRDQ; + inout [3:0] DDRDM; + inout [3:0] DDRDQSN; + inout [3:0] DDRDQSP; + inout [53:0] MIO; + input DMA0ACLK; + input DMA0DAREADY; + input DMA0DRLAST; + input DMA0DRVALID; + input DMA1ACLK; + input DMA1DAREADY; + input DMA1DRLAST; + input DMA1DRVALID; + input DMA2ACLK; + input DMA2DAREADY; + input DMA2DRLAST; + input DMA2DRVALID; + input DMA3ACLK; + input DMA3DAREADY; + input DMA3DRLAST; + input DMA3DRVALID; + input EMIOCAN0PHYRX; + input EMIOCAN1PHYRX; + input EMIOENET0EXTINTIN; + input EMIOENET0GMIICOL; + input EMIOENET0GMIICRS; + input EMIOENET0GMIIRXCLK; + input EMIOENET0GMIIRXDV; + input EMIOENET0GMIIRXER; + input EMIOENET0GMIITXCLK; + input EMIOENET0MDIOI; + input EMIOENET1EXTINTIN; + input EMIOENET1GMIICOL; + input EMIOENET1GMIICRS; + input EMIOENET1GMIIRXCLK; + input EMIOENET1GMIIRXDV; + input EMIOENET1GMIIRXER; + input EMIOENET1GMIITXCLK; + input EMIOENET1MDIOI; + input EMIOI2C0SCLI; + input EMIOI2C0SDAI; + input EMIOI2C1SCLI; + input EMIOI2C1SDAI; + input EMIOPJTAGTCK; + input EMIOPJTAGTDI; + input EMIOPJTAGTMS; + input EMIOSDIO0CDN; + input EMIOSDIO0CLKFB; + input EMIOSDIO0CMDI; + input EMIOSDIO0WP; + input EMIOSDIO1CDN; + input EMIOSDIO1CLKFB; + input EMIOSDIO1CMDI; + input EMIOSDIO1WP; + input EMIOSPI0MI; + input EMIOSPI0SCLKI; + input EMIOSPI0SI; + input EMIOSPI0SSIN; + input EMIOSPI1MI; + input EMIOSPI1SCLKI; + input EMIOSPI1SI; + input EMIOSPI1SSIN; + input EMIOSRAMINTIN; + input EMIOTRACECLK; + input EMIOUART0CTSN; + input EMIOUART0DCDN; + input EMIOUART0DSRN; + input EMIOUART0RIN; + input EMIOUART0RX; + input EMIOUART1CTSN; + input EMIOUART1DCDN; + input EMIOUART1DSRN; + input EMIOUART1RIN; + input EMIOUART1RX; + input EMIOUSB0VBUSPWRFAULT; + input EMIOUSB1VBUSPWRFAULT; + input EMIOWDTCLKI; + input EVENTEVENTI; + input FPGAIDLEN; + input FTMDTRACEINCLOCK; + input FTMDTRACEINVALID; + input MAXIGP0ACLK; + input MAXIGP0ARREADY; + input MAXIGP0AWREADY; + input MAXIGP0BVALID; + input MAXIGP0RLAST; + input MAXIGP0RVALID; + input MAXIGP0WREADY; + input MAXIGP1ACLK; + input MAXIGP1ARREADY; + input MAXIGP1AWREADY; + input MAXIGP1BVALID; + input MAXIGP1RLAST; + input MAXIGP1RVALID; + input MAXIGP1WREADY; + input SAXIACPACLK; + input SAXIACPARVALID; + input SAXIACPAWVALID; + input SAXIACPBREADY; + input SAXIACPRREADY; + input SAXIACPWLAST; + input SAXIACPWVALID; + input SAXIGP0ACLK; + input SAXIGP0ARVALID; + input SAXIGP0AWVALID; + input SAXIGP0BREADY; + input SAXIGP0RREADY; + input SAXIGP0WLAST; + input SAXIGP0WVALID; + input SAXIGP1ACLK; + input SAXIGP1ARVALID; + input SAXIGP1AWVALID; + input SAXIGP1BREADY; + input SAXIGP1RREADY; + input SAXIGP1WLAST; + input SAXIGP1WVALID; + input SAXIHP0ACLK; + input SAXIHP0ARVALID; + input SAXIHP0AWVALID; + input SAXIHP0BREADY; + input SAXIHP0RDISSUECAP1EN; + input SAXIHP0RREADY; + input SAXIHP0WLAST; + input SAXIHP0WRISSUECAP1EN; + input SAXIHP0WVALID; + input SAXIHP1ACLK; + input SAXIHP1ARVALID; + input SAXIHP1AWVALID; + input SAXIHP1BREADY; + input SAXIHP1RDISSUECAP1EN; + input SAXIHP1RREADY; + input SAXIHP1WLAST; + input SAXIHP1WRISSUECAP1EN; + input SAXIHP1WVALID; + input SAXIHP2ACLK; + input SAXIHP2ARVALID; + input SAXIHP2AWVALID; + input SAXIHP2BREADY; + input SAXIHP2RDISSUECAP1EN; + input SAXIHP2RREADY; + input SAXIHP2WLAST; + input SAXIHP2WRISSUECAP1EN; + input SAXIHP2WVALID; + input SAXIHP3ACLK; + input SAXIHP3ARVALID; + input SAXIHP3AWVALID; + input SAXIHP3BREADY; + input SAXIHP3RDISSUECAP1EN; + input SAXIHP3RREADY; + input SAXIHP3WLAST; + input SAXIHP3WRISSUECAP1EN; + input SAXIHP3WVALID; + input [11:0] MAXIGP0BID; + input [11:0] MAXIGP0RID; + input [11:0] MAXIGP1BID; + input [11:0] MAXIGP1RID; + input [19:0] IRQF2P; + input [1:0] DMA0DRTYPE; + input [1:0] DMA1DRTYPE; + input [1:0] DMA2DRTYPE; + input [1:0] DMA3DRTYPE; + input [1:0] MAXIGP0BRESP; + input [1:0] MAXIGP0RRESP; + input [1:0] MAXIGP1BRESP; + input [1:0] MAXIGP1RRESP; + input [1:0] SAXIACPARBURST; + input [1:0] SAXIACPARLOCK; + input [1:0] SAXIACPARSIZE; + input [1:0] SAXIACPAWBURST; + input [1:0] SAXIACPAWLOCK; + input [1:0] SAXIACPAWSIZE; + input [1:0] SAXIGP0ARBURST; + input [1:0] SAXIGP0ARLOCK; + input [1:0] SAXIGP0ARSIZE; + input [1:0] SAXIGP0AWBURST; + input [1:0] SAXIGP0AWLOCK; + input [1:0] SAXIGP0AWSIZE; + input [1:0] SAXIGP1ARBURST; + input [1:0] SAXIGP1ARLOCK; + input [1:0] SAXIGP1ARSIZE; + input [1:0] SAXIGP1AWBURST; + input [1:0] SAXIGP1AWLOCK; + input [1:0] SAXIGP1AWSIZE; + input [1:0] SAXIHP0ARBURST; + input [1:0] SAXIHP0ARLOCK; + input [1:0] SAXIHP0ARSIZE; + input [1:0] SAXIHP0AWBURST; + input [1:0] SAXIHP0AWLOCK; + input [1:0] SAXIHP0AWSIZE; + input [1:0] SAXIHP1ARBURST; + input [1:0] SAXIHP1ARLOCK; + input [1:0] SAXIHP1ARSIZE; + input [1:0] SAXIHP1AWBURST; + input [1:0] SAXIHP1AWLOCK; + input [1:0] SAXIHP1AWSIZE; + input [1:0] SAXIHP2ARBURST; + input [1:0] SAXIHP2ARLOCK; + input [1:0] SAXIHP2ARSIZE; + input [1:0] SAXIHP2AWBURST; + input [1:0] SAXIHP2AWLOCK; + input [1:0] SAXIHP2AWSIZE; + input [1:0] SAXIHP3ARBURST; + input [1:0] SAXIHP3ARLOCK; + input [1:0] SAXIHP3ARSIZE; + input [1:0] SAXIHP3AWBURST; + input [1:0] SAXIHP3AWLOCK; + input [1:0] SAXIHP3AWSIZE; + input [2:0] EMIOTTC0CLKI; + input [2:0] EMIOTTC1CLKI; + input [2:0] SAXIACPARID; + input [2:0] SAXIACPARPROT; + input [2:0] SAXIACPAWID; + input [2:0] SAXIACPAWPROT; + input [2:0] SAXIACPWID; + input [2:0] SAXIGP0ARPROT; + input [2:0] SAXIGP0AWPROT; + input [2:0] SAXIGP1ARPROT; + input [2:0] SAXIGP1AWPROT; + input [2:0] SAXIHP0ARPROT; + input [2:0] SAXIHP0AWPROT; + input [2:0] SAXIHP1ARPROT; + input [2:0] SAXIHP1AWPROT; + input [2:0] SAXIHP2ARPROT; + input [2:0] SAXIHP2AWPROT; + input [2:0] SAXIHP3ARPROT; + input [2:0] SAXIHP3AWPROT; + input [31:0] FTMDTRACEINDATA; + input [31:0] FTMTF2PDEBUG; + input [31:0] MAXIGP0RDATA; + input [31:0] MAXIGP1RDATA; + input [31:0] SAXIACPARADDR; + input [31:0] SAXIACPAWADDR; + input [31:0] SAXIGP0ARADDR; + input [31:0] SAXIGP0AWADDR; + input [31:0] SAXIGP0WDATA; + input [31:0] SAXIGP1ARADDR; + input [31:0] SAXIGP1AWADDR; + input [31:0] SAXIGP1WDATA; + input [31:0] SAXIHP0ARADDR; + input [31:0] SAXIHP0AWADDR; + input [31:0] SAXIHP1ARADDR; + input [31:0] SAXIHP1AWADDR; + input [31:0] SAXIHP2ARADDR; + input [31:0] SAXIHP2AWADDR; + input [31:0] SAXIHP3ARADDR; + input [31:0] SAXIHP3AWADDR; + input [3:0] DDRARB; + input [3:0] EMIOSDIO0DATAI; + input [3:0] EMIOSDIO1DATAI; + input [3:0] FCLKCLKTRIGN; + input [3:0] FTMDTRACEINATID; + input [3:0] FTMTF2PTRIG; + input [3:0] FTMTP2FTRIGACK; + input [3:0] SAXIACPARCACHE; + input [3:0] SAXIACPARLEN; + input [3:0] SAXIACPARQOS; + input [3:0] SAXIACPAWCACHE; + input [3:0] SAXIACPAWLEN; + input [3:0] SAXIACPAWQOS; + input [3:0] SAXIGP0ARCACHE; + input [3:0] SAXIGP0ARLEN; + input [3:0] SAXIGP0ARQOS; + input [3:0] SAXIGP0AWCACHE; + input [3:0] SAXIGP0AWLEN; + input [3:0] SAXIGP0AWQOS; + input [3:0] SAXIGP0WSTRB; + input [3:0] SAXIGP1ARCACHE; + input [3:0] SAXIGP1ARLEN; + input [3:0] SAXIGP1ARQOS; + input [3:0] SAXIGP1AWCACHE; + input [3:0] SAXIGP1AWLEN; + input [3:0] SAXIGP1AWQOS; + input [3:0] SAXIGP1WSTRB; + input [3:0] SAXIHP0ARCACHE; + input [3:0] SAXIHP0ARLEN; + input [3:0] SAXIHP0ARQOS; + input [3:0] SAXIHP0AWCACHE; + input [3:0] SAXIHP0AWLEN; + input [3:0] SAXIHP0AWQOS; + input [3:0] SAXIHP1ARCACHE; + input [3:0] SAXIHP1ARLEN; + input [3:0] SAXIHP1ARQOS; + input [3:0] SAXIHP1AWCACHE; + input [3:0] SAXIHP1AWLEN; + input [3:0] SAXIHP1AWQOS; + input [3:0] SAXIHP2ARCACHE; + input [3:0] SAXIHP2ARLEN; + input [3:0] SAXIHP2ARQOS; + input [3:0] SAXIHP2AWCACHE; + input [3:0] SAXIHP2AWLEN; + input [3:0] SAXIHP2AWQOS; + input [3:0] SAXIHP3ARCACHE; + input [3:0] SAXIHP3ARLEN; + input [3:0] SAXIHP3ARQOS; + input [3:0] SAXIHP3AWCACHE; + input [3:0] SAXIHP3AWLEN; + input [3:0] SAXIHP3AWQOS; + input [4:0] SAXIACPARUSER; + input [4:0] SAXIACPAWUSER; + input [5:0] SAXIGP0ARID; + input [5:0] SAXIGP0AWID; + input [5:0] SAXIGP0WID; + input [5:0] SAXIGP1ARID; + input [5:0] SAXIGP1AWID; + input [5:0] SAXIGP1WID; + input [5:0] SAXIHP0ARID; + input [5:0] SAXIHP0AWID; + input [5:0] SAXIHP0WID; + input [5:0] SAXIHP1ARID; + input [5:0] SAXIHP1AWID; + input [5:0] SAXIHP1WID; + input [5:0] SAXIHP2ARID; + input [5:0] SAXIHP2AWID; + input [5:0] SAXIHP2WID; + input [5:0] SAXIHP3ARID; + input [5:0] SAXIHP3AWID; + input [5:0] SAXIHP3WID; + input [63:0] EMIOGPIOI; + input [63:0] SAXIACPWDATA; + input [63:0] SAXIHP0WDATA; + input [63:0] SAXIHP1WDATA; + input [63:0] SAXIHP2WDATA; + input [63:0] SAXIHP3WDATA; + input [7:0] EMIOENET0GMIIRXD; + input [7:0] EMIOENET1GMIIRXD; + input [7:0] SAXIACPWSTRB; + input [7:0] SAXIHP0WSTRB; + input [7:0] SAXIHP1WSTRB; + input [7:0] SAXIHP2WSTRB; + input [7:0] SAXIHP3WSTRB; +endmodule + module PULLDOWN (...); output O; endmodule diff --git a/tests/errors/syntax_err01.v b/tests/errors/syntax_err01.v new file mode 100644 index 000000000..68e9b1d50 --- /dev/null +++ b/tests/errors/syntax_err01.v @@ -0,0 +1,4 @@ +module a; +integer [31:0]w; +endmodule + diff --git a/tests/errors/syntax_err02.v b/tests/errors/syntax_err02.v new file mode 100644 index 000000000..c72e976a8 --- /dev/null +++ b/tests/errors/syntax_err02.v @@ -0,0 +1,7 @@ +module a; +task to ( + input integer [3:0]x +); +endtask +endmodule + diff --git a/tests/errors/syntax_err03.v b/tests/errors/syntax_err03.v new file mode 100644 index 000000000..6eec44ade --- /dev/null +++ b/tests/errors/syntax_err03.v @@ -0,0 +1,7 @@ +module a; +task to ( + input [3]x +); +endtask +endmodule + diff --git a/tests/errors/syntax_err04.v b/tests/errors/syntax_err04.v new file mode 100644 index 000000000..d488e5dbb --- /dev/null +++ b/tests/errors/syntax_err04.v @@ -0,0 +1,4 @@ +module a; +wire [3]x; +endmodule + diff --git a/tests/errors/syntax_err05.v b/tests/errors/syntax_err05.v new file mode 100644 index 000000000..8a1f11532 --- /dev/null +++ b/tests/errors/syntax_err05.v @@ -0,0 +1,4 @@ +module a; +input x[2:0]; +endmodule + diff --git a/tests/errors/syntax_err06.v b/tests/errors/syntax_err06.v new file mode 100644 index 000000000..b35a1dea2 --- /dev/null +++ b/tests/errors/syntax_err06.v @@ -0,0 +1,6 @@ +module a; +initial +begin : label1 +end: label2 +endmodule + diff --git a/tests/errors/syntax_err07.v b/tests/errors/syntax_err07.v new file mode 100644 index 000000000..62bcc6b3e --- /dev/null +++ b/tests/errors/syntax_err07.v @@ -0,0 +1,6 @@ +module a; +wire [5:0]x; +wire [3:0]y; +assign y = (4)55; +endmodule + diff --git a/tests/errors/syntax_err08.v b/tests/errors/syntax_err08.v new file mode 100644 index 000000000..d41bfd6c9 --- /dev/null +++ b/tests/errors/syntax_err08.v @@ -0,0 +1,6 @@ +module a; +wire [5:0]x; +wire [3:0]y; +assign y = x 55; +endmodule + diff --git a/tests/errors/syntax_err09.v b/tests/errors/syntax_err09.v new file mode 100644 index 000000000..1e472eb94 --- /dev/null +++ b/tests/errors/syntax_err09.v @@ -0,0 +1,3 @@ +module a(input wire x = 1'b0); +endmodule + diff --git a/tests/errors/syntax_err10.v b/tests/errors/syntax_err10.v new file mode 100644 index 000000000..d3280405c --- /dev/null +++ b/tests/errors/syntax_err10.v @@ -0,0 +1,3 @@ +module a; +parameter integer [2:0]x=0; +endmodule diff --git a/tests/errors/syntax_err11.v b/tests/errors/syntax_err11.v new file mode 100644 index 000000000..f3cde9dfc --- /dev/null +++ b/tests/errors/syntax_err11.v @@ -0,0 +1,3 @@ +module a; +parameter integer real x=0; +endmodule diff --git a/tests/errors/syntax_err12.v b/tests/errors/syntax_err12.v new file mode 100644 index 000000000..f9b5d5b0b --- /dev/null +++ b/tests/errors/syntax_err12.v @@ -0,0 +1,7 @@ +interface iface; +endinterface + +module a ( + iface x = 1'b0 +); +endmodule diff --git a/tests/errors/syntax_err13.v b/tests/errors/syntax_err13.v new file mode 100644 index 000000000..b5c942fca --- /dev/null +++ b/tests/errors/syntax_err13.v @@ -0,0 +1,4 @@ +module a #(p = 0) +(); +endmodule + |