diff options
| -rw-r--r-- | Makefile | 2 | ||||
| -rw-r--r-- | backends/verilog/verilog_backend.cc | 38 | ||||
| -rw-r--r-- | frontends/ast/ast.cc | 18 | ||||
| -rw-r--r-- | frontends/ast/ast.h | 2 | ||||
| -rw-r--r-- | frontends/liberty/liberty.cc | 32 | ||||
| -rw-r--r-- | frontends/verilog/verilog_frontend.cc | 23 | ||||
| -rw-r--r-- | frontends/verilog/verilog_lexer.l | 10 | ||||
| -rw-r--r-- | passes/techmap/techmap.cc | 4 | ||||
| -rw-r--r-- | techlibs/intel/synth_intel.cc | 13 |
9 files changed, 117 insertions, 25 deletions
@@ -102,7 +102,7 @@ OBJS = kernel/version_$(GIT_REV).o # is just a symlink to your actual ABC working directory, as 'make mrproper' # will remove the 'abc' directory and you do not want to accidentally # delete your work on ABC.. -ABCREV = a2d59be +ABCREV = f23ea8e ABCPULL = 1 ABCURL ?= https://github.com/berkeley-abc/abc ABCMKARGS = CC="$(CXX)" CXX="$(CXX)" ABC_USE_LIBSTDCXX=1 diff --git a/backends/verilog/verilog_backend.cc b/backends/verilog/verilog_backend.cc index bdf705056..b50dc12af 100644 --- a/backends/verilog/verilog_backend.cc +++ b/backends/verilog/verilog_backend.cc @@ -897,6 +897,42 @@ bool dump_cell_expr(std::ostream &f, std::string indent, RTLIL::Cell *cell) return true; } + if (cell->type == "$dlatch") + { + RTLIL::SigSpec sig_en; + bool pol_en = false; + + sig_en = cell->getPort("\\EN"); + pol_en = cell->parameters["\\EN_POLARITY"].as_bool(); + + std::string reg_name = cellname(cell); + bool out_is_reg_wire = is_reg_wire(cell->getPort("\\Q"), reg_name); + + if (!out_is_reg_wire) { + f << stringf("%s" "reg [%d:0] %s", indent.c_str(), cell->parameters["\\WIDTH"].as_int()-1, reg_name.c_str()); + dump_reg_init(f, cell->getPort("\\Q")); + f << ";\n"; + } + + f << stringf("%s" "always @*\n", indent.c_str()); + + f << stringf("%s" " if (%s", indent.c_str(), pol_en ? "" : "!"); + dump_sigspec(f, sig_en); + f << stringf(")\n"); + + f << stringf("%s" " %s = ", indent.c_str(), reg_name.c_str()); + dump_cell_expr_port(f, cell, "D", false); + f << stringf(";\n"); + + if (!out_is_reg_wire) { + f << stringf("%s" "assign ", indent.c_str()); + dump_sigspec(f, cell->getPort("\\Q")); + f << stringf(" = %s;\n", reg_name.c_str()); + } + + return true; + } + if (cell->type == "$mem") { RTLIL::IdString memid = cell->parameters["\\MEMID"].decode_string(); @@ -1537,6 +1573,8 @@ struct VerilogBackend : public Backend { reg_ct.insert("$dff"); reg_ct.insert("$adff"); + reg_ct.insert("$dffe"); + reg_ct.insert("$dlatch"); reg_ct.insert("$_DFF_N_"); reg_ct.insert("$_DFF_P_"); diff --git a/frontends/ast/ast.cc b/frontends/ast/ast.cc index 037a9f3ee..999202b47 100644 --- a/frontends/ast/ast.cc +++ b/frontends/ast/ast.cc @@ -1003,7 +1003,7 @@ static AstModule* process_module(AstNode *ast, bool defer) // create AstModule instances for all modules in the AST tree and add them to 'design' void AST::process(RTLIL::Design *design, AstNode *ast, bool dump_ast1, bool dump_ast2, bool dump_vlog, bool dump_rtlil, - bool nolatches, bool nomeminit, bool nomem2reg, bool mem2reg, bool lib, bool noopt, bool icells, bool ignore_redef, bool defer, bool autowire) + bool nolatches, bool nomeminit, bool nomem2reg, bool mem2reg, bool lib, bool noopt, bool icells, bool nooverwrite, bool overwrite, bool defer, bool autowire) { current_ast = ast; flag_dump_ast1 = dump_ast1; @@ -1042,12 +1042,20 @@ void AST::process(RTLIL::Design *design, AstNode *ast, bool dump_ast1, bool dump (*it)->str = "$abstract" + (*it)->str; if (design->has((*it)->str)) { - if (!ignore_redef) + RTLIL::Module *existing_mod = design->module((*it)->str); + if (!nooverwrite && !overwrite && !existing_mod->get_bool_attribute("\\blackbox")) { log_error("Re-definition of module `%s' at %s:%d!\n", (*it)->str.c_str(), (*it)->filename.c_str(), (*it)->linenum); - log("Ignoring re-definition of module `%s' at %s:%d!\n", - (*it)->str.c_str(), (*it)->filename.c_str(), (*it)->linenum); - continue; + } else if (nooverwrite) { + log("Ignoring re-definition of module `%s' at %s:%d.\n", + (*it)->str.c_str(), (*it)->filename.c_str(), (*it)->linenum); + continue; + } else { + log("Replacing existing%s module `%s' at %s:%d.\n", + existing_mod->get_bool_attribute("\\blackbox") ? " blackbox" : "", + (*it)->str.c_str(), (*it)->filename.c_str(), (*it)->linenum); + design->remove(existing_mod); + } } design->add(process_module(*it, defer)); diff --git a/frontends/ast/ast.h b/frontends/ast/ast.h index d1e2c78d1..756629aca 100644 --- a/frontends/ast/ast.h +++ b/frontends/ast/ast.h @@ -275,7 +275,7 @@ namespace AST // process an AST tree (ast must point to an AST_DESIGN node) and generate RTLIL code void process(RTLIL::Design *design, AstNode *ast, bool dump_ast1, bool dump_ast2, bool dump_vlog, bool dump_rtlil, bool nolatches, bool nomeminit, - bool nomem2reg, bool mem2reg, bool lib, bool noopt, bool icells, bool ignore_redef, bool defer, bool autowire); + bool nomem2reg, bool mem2reg, bool lib, bool noopt, bool icells, bool nooverwrite, bool overwrite, bool defer, bool autowire); // parametric modules are supported directly by the AST library // therefore we need our own derivate of RTLIL::Module with overloaded virtual functions diff --git a/frontends/liberty/liberty.cc b/frontends/liberty/liberty.cc index af80c2921..877b1883e 100644 --- a/frontends/liberty/liberty.cc +++ b/frontends/liberty/liberty.cc @@ -463,9 +463,13 @@ struct LibertyFrontend : public Frontend { log(" -lib\n"); log(" only create empty blackbox modules\n"); log("\n"); - log(" -ignore_redef\n"); + log(" -nooverwrite\n"); log(" ignore re-definitions of modules. (the default behavior is to\n"); - log(" create an error message.)\n"); + log(" create an error message if the existing module is not a blackbox\n"); + log(" module, and overwrite the existing module if it is a blackbox module.)\n"); + log("\n"); + log(" -overwrite\n"); + log(" overwrite existing modules with the same name\n"); log("\n"); log(" -ignore_miss_func\n"); log(" ignore cells with missing function specification of outputs\n"); @@ -484,7 +488,8 @@ struct LibertyFrontend : public Frontend { virtual void execute(std::istream *&f, std::string filename, std::vector<std::string> args, RTLIL::Design *design) { bool flag_lib = false; - bool flag_ignore_redef = false; + bool flag_nooverwrite = false; + bool flag_overwrite = false; bool flag_ignore_miss_func = false; bool flag_ignore_miss_dir = false; bool flag_ignore_miss_data_latch = false; @@ -499,8 +504,14 @@ struct LibertyFrontend : public Frontend { flag_lib = true; continue; } - if (arg == "-ignore_redef") { - flag_ignore_redef = true; + if (arg == "-ignore_redef" || arg == "-nooverwrite") { + flag_nooverwrite = true; + flag_overwrite = false; + continue; + } + if (arg == "-overwrite") { + flag_nooverwrite = false; + flag_overwrite = true; continue; } if (arg == "-ignore_miss_func") { @@ -537,9 +548,16 @@ struct LibertyFrontend : public Frontend { std::string cell_name = RTLIL::escape_id(cell->args.at(0)); if (design->has(cell_name)) { - if (flag_ignore_redef) + Module *existing_mod = design->module(cell_name); + if (!flag_nooverwrite && !flag_overwrite && !existing_mod->get_bool_attribute("\\blackbox")) { + log_error("Re-definition of of cell/module %s!\n", log_id(cell_name)); + } else if (flag_nooverwrite) { + log("Ignoring re-definition of module %s.\n", log_id(cell_name)); continue; - log_error("Duplicate definition of cell/module %s.\n", RTLIL::unescape_id(cell_name).c_str()); + } else { + log("Replacing existing%s module %s.\n", existing_mod->get_bool_attribute("\\blackbox") ? " blackbox" : "", log_id(cell_name)); + design->remove(existing_mod); + } } // log("Processing cell type %s.\n", RTLIL::unescape_id(cell_name).c_str()); diff --git a/frontends/verilog/verilog_frontend.cc b/frontends/verilog/verilog_frontend.cc index e5917b97e..505c94619 100644 --- a/frontends/verilog/verilog_frontend.cc +++ b/frontends/verilog/verilog_frontend.cc @@ -137,9 +137,13 @@ struct VerilogFrontend : public Frontend { log(" -icells\n"); log(" interpret cell types starting with '$' as internal cell types\n"); log("\n"); - log(" -ignore_redef\n"); + log(" -nooverwrite\n"); log(" ignore re-definitions of modules. (the default behavior is to\n"); - log(" create an error message.)\n"); + log(" create an error message if the existing module is not a black box\n"); + log(" module, and overwrite the existing module otherwise.)\n"); + log("\n"); + log(" -overwrite\n"); + log(" overwrite existing modules with the same name\n"); log("\n"); log(" -defer\n"); log(" only read the abstract syntax tree and defer actual compilation\n"); @@ -191,7 +195,8 @@ struct VerilogFrontend : public Frontend { bool flag_nodpi = false; bool flag_noopt = false; bool flag_icells = false; - bool flag_ignore_redef = false; + bool flag_nooverwrite = false; + bool flag_overwrite = false; bool flag_defer = false; std::map<std::string, std::string> defines_map; std::list<std::string> include_dirs; @@ -289,8 +294,14 @@ struct VerilogFrontend : public Frontend { flag_icells = true; continue; } - if (arg == "-ignore_redef") { - flag_ignore_redef = true; + if (arg == "-ignore_redef" || arg == "-nooverwrite") { + flag_nooverwrite = true; + flag_overwrite = false; + continue; + } + if (arg == "-overwrite") { + flag_nooverwrite = false; + flag_overwrite = true; continue; } if (arg == "-defer") { @@ -370,7 +381,7 @@ struct VerilogFrontend : public Frontend { if (flag_nodpi) error_on_dpi_function(current_ast); - AST::process(design, current_ast, flag_dump_ast1, flag_dump_ast2, flag_dump_vlog, flag_dump_rtlil, flag_nolatches, flag_nomeminit, flag_nomem2reg, flag_mem2reg, lib_mode, flag_noopt, flag_icells, flag_ignore_redef, flag_defer, default_nettype_wire); + AST::process(design, current_ast, flag_dump_ast1, flag_dump_ast2, flag_dump_vlog, flag_dump_rtlil, flag_nolatches, flag_nomeminit, flag_nomem2reg, flag_mem2reg, lib_mode, flag_noopt, flag_icells, flag_nooverwrite, flag_overwrite, flag_defer, default_nettype_wire); if (!flag_nopp) delete lexin; diff --git a/frontends/verilog/verilog_lexer.l b/frontends/verilog/verilog_lexer.l index 32d7738cf..d12c9ee4e 100644 --- a/frontends/verilog/verilog_lexer.l +++ b/frontends/verilog/verilog_lexer.l @@ -241,10 +241,18 @@ YOSYS_NAMESPACE_END while (yystr[i]) { if (yystr[i] == '\\' && yystr[i + 1]) { i++; - if (yystr[i] == 'n') + if (yystr[i] == 'a') + yystr[i] = '\a'; + else if (yystr[i] == 'f') + yystr[i] = '\f'; + else if (yystr[i] == 'n') yystr[i] = '\n'; + else if (yystr[i] == 'r') + yystr[i] = '\r'; else if (yystr[i] == 't') yystr[i] = '\t'; + else if (yystr[i] == 'v') + yystr[i] = '\v'; else if ('0' <= yystr[i] && yystr[i] <= '7') { yystr[i] = yystr[i] - '0'; if ('0' <= yystr[i + 1] && yystr[i + 1] <= '7') { diff --git a/passes/techmap/techmap.cc b/passes/techmap/techmap.cc index 02d0d47e8..1908ae8b5 100644 --- a/passes/techmap/techmap.cc +++ b/passes/techmap/techmap.cc @@ -933,7 +933,7 @@ struct TechmapPass : public Pass { log(" -D <define>, -I <incdir>\n"); log(" this options are passed as-is to the Verilog frontend for loading the\n"); log(" map file. Note that the Verilog frontend is also called with the\n"); - log(" '-ignore_redef' option set.\n"); + log(" '-nooverwrite' option set.\n"); log("\n"); log("When a module in the map file has the 'techmap_celltype' attribute set, it will\n"); log("match cells with a type that match the text value of this attribute. Otherwise\n"); @@ -1031,7 +1031,7 @@ struct TechmapPass : public Pass { simplemap_get_mappers(worker.simplemap_mappers); std::vector<std::string> map_files; - std::string verilog_frontend = "verilog -ignore_redef"; + std::string verilog_frontend = "verilog -nooverwrite"; int max_iter = -1; size_t argidx; diff --git a/techlibs/intel/synth_intel.cc b/techlibs/intel/synth_intel.cc index dfed7a285..c51949bd4 100644 --- a/techlibs/intel/synth_intel.cc +++ b/techlibs/intel/synth_intel.cc @@ -59,6 +59,9 @@ struct SynthIntelPass : public ScriptPass { log(" from label is synonymous to 'begin', and empty to label is\n"); log(" synonymous to the end of the command list.\n"); log("\n"); + log(" -noiopads\n"); + log(" do not use altsyncram cells in output netlist\n"); + log("\n"); log(" -nobram\n"); log(" do not use altsyncram cells in output netlist\n"); log("\n"); @@ -74,7 +77,7 @@ struct SynthIntelPass : public ScriptPass { } string top_opt, family_opt, vout_file, blif_file; - bool retime, flatten, nobram; + bool retime, flatten, nobram, noiopads; virtual void clear_flags() YS_OVERRIDE { @@ -85,6 +88,7 @@ struct SynthIntelPass : public ScriptPass { retime = false; flatten = true; nobram = false; + noiopads = false; } virtual void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE @@ -119,6 +123,10 @@ struct SynthIntelPass : public ScriptPass { run_to = args[argidx].substr(pos+1); continue; } + if (args[argidx] == "-noiopads") { + noiopads = true; + continue; + } if (args[argidx] == "-nobram") { nobram = true; continue; @@ -216,7 +224,8 @@ struct SynthIntelPass : public ScriptPass { if (check_label("map_cells")) { - run("iopadmap -bits -outpad $__outpad I:O -inpad $__inpad O:I"); + if (!noiopads) + run("iopadmap -bits -outpad $__outpad I:O -inpad $__inpad O:I", "(unless -noiopads)"); if(family_opt=="max10") run("techmap -map +/intel/max10/cells_map.v"); else if(family_opt=="a10gx") |