diff options
| -rw-r--r-- | backends/aiger/xaiger.cc | 2 | ||||
| -rw-r--r-- | passes/techmap/abc9_ops.cc | 4 |
2 files changed, 3 insertions, 3 deletions
diff --git a/backends/aiger/xaiger.cc b/backends/aiger/xaiger.cc index c2d076c86..66ddbde33 100644 --- a/backends/aiger/xaiger.cc +++ b/backends/aiger/xaiger.cc @@ -318,7 +318,7 @@ struct XAigerWriter RTLIL::Module* box_module = module->design->module(cell->type); log_assert(box_module); - log_assert(box_module->attributes.count("\\abc9_box_id")); + log_assert(box_module->attributes.count("\\abc9_box_id") || box_module->get_bool_attribute("\\abc9_flop")); auto r = box_ports.insert(cell->type); if (r.second) { diff --git a/passes/techmap/abc9_ops.cc b/passes/techmap/abc9_ops.cc index 4d05b5afb..fd2759ae5 100644 --- a/passes/techmap/abc9_ops.cc +++ b/passes/techmap/abc9_ops.cc @@ -117,7 +117,7 @@ void check(RTLIL::Design *design) if (wire->port_output) num_outputs++; } if (num_outputs != 1) - log_error("Module '%s' with (* abc_flop *) has %d outputs (expect 1).\n", log_id(m), num_outputs); + log_error("Module '%s' with (* abc9_flop *) has %d outputs (expect 1).\n", log_id(m), num_outputs); } } } @@ -333,7 +333,7 @@ void prep_xaiger(RTLIL::Module *module, bool dff) log_assert(cell); RTLIL::Module* box_module = design->module(cell->type); - if (!box_module || !box_module->attributes.count("\\abc9_box_id")) + if (!box_module || (!box_module->attributes.count("\\abc9_box_id") && !box_module->get_bool_attribute("\\abc9_flop"))) continue; cell->attributes["\\abc9_box_seq"] = box_count++; |