diff options
| -rw-r--r-- | Makefile | 6 | ||||
| -rw-r--r-- | README.md | 4 | ||||
| -rw-r--r-- | frontends/ast/ast.cc | 7 | ||||
| -rw-r--r-- | passes/hierarchy/hierarchy.cc | 24 | ||||
| -rw-r--r-- | passes/techmap/techmap.cc | 44 | ||||
| -rwxr-xr-x | tests/simple/run-test.sh | 2 | ||||
| -rwxr-xr-x | tests/simple_abc9/run-test.sh | 2 | ||||
| -rw-r--r-- | tests/various/hierarchy_defer.ys | 27 |
8 files changed, 103 insertions, 13 deletions
@@ -88,7 +88,7 @@ ifeq ($(OS), Darwin) PLUGIN_LDFLAGS += -undefined dynamic_lookup # homebrew search paths -ifneq ($(shell which brew),) +ifneq ($(shell :; command -v brew),) BREW_PREFIX := $(shell brew --prefix)/opt $(info $$BREW_PREFIX is [${BREW_PREFIX}]) ifeq ($(ENABLE_PYOSYS),1) @@ -102,8 +102,8 @@ PKG_CONFIG_PATH := $(BREW_PREFIX)/tcl-tk/lib/pkgconfig:$(PKG_CONFIG_PATH) export PATH := $(BREW_PREFIX)/bison/bin:$(BREW_PREFIX)/gettext/bin:$(BREW_PREFIX)/flex/bin:$(PATH) # macports search paths -else ifneq ($(shell which port),) -PORT_PREFIX := $(patsubst %/bin/port,%,$(shell which port)) +else ifneq ($(shell :; command -v port),) +PORT_PREFIX := $(patsubst %/bin/port,%,$(shell :; command -v port)) CXXFLAGS += -I$(PORT_PREFIX)/include LDFLAGS += -L$(PORT_PREFIX)/lib PKG_CONFIG_PATH := $(PORT_PREFIX)/lib/pkgconfig:$(PKG_CONFIG_PATH) @@ -332,6 +332,10 @@ Verilog Attributes and non-standard features that represent module parameters or localparams (when the HDL front-end is run in ``-pwires`` mode). +- Wires marked with the ``hierconn`` attribute are connected to wires with the + same name (format ``cell_name.identifier``) when they are imported from + sub-modules by ``flatten``. + - The ``clkbuf_driver`` attribute can be set on an output port of a blackbox module to mark it as a clock buffer output, and thus prevent ``clkbufmap`` from inserting another clock buffer on a net driven by such output. diff --git a/frontends/ast/ast.cc b/frontends/ast/ast.cc index 82283fb5b..a3a78e414 100644 --- a/frontends/ast/ast.cc +++ b/frontends/ast/ast.cc @@ -1099,6 +1099,13 @@ static AstModule* process_module(AstNode *ast, bool defer, AstNode *original_ast ignoreThisSignalsInInitial = RTLIL::SigSpec(); } + else { + for (auto &attr : ast->attributes) { + if (attr.second->type != AST_CONSTANT) + continue; + current_module->attributes[attr.first] = attr.second->asAttrConst(); + } + } if (ast->type == AST_INTERFACE) current_module->set_bool_attribute("\\is_interface"); diff --git a/passes/hierarchy/hierarchy.cc b/passes/hierarchy/hierarchy.cc index fd95b94b2..d8a628448 100644 --- a/passes/hierarchy/hierarchy.cc +++ b/passes/hierarchy/hierarchy.cc @@ -808,6 +808,30 @@ struct HierarchyPass : public Pass { if (mod_it.second->get_bool_attribute("\\top")) top_mod = mod_it.second; + if (top_mod != nullptr && top_mod->name.begins_with("$abstract")) { + IdString top_name = top_mod->name.substr(strlen("$abstract")); + + dict<RTLIL::IdString, RTLIL::Const> top_parameters; + for (auto ¶ : parameters) { + SigSpec sig_value; + if (!RTLIL::SigSpec::parse(sig_value, NULL, para.second)) + log_cmd_error("Can't decode value '%s'!\n", para.second.c_str()); + top_parameters[RTLIL::escape_id(para.first)] = sig_value.as_const(); + } + + top_mod = design->module(top_mod->derive(design, top_parameters)); + + if (top_mod != nullptr && top_mod->name != top_name) { + Module *m = top_mod->clone(); + m->name = top_name; + Module *old_mod = design->module(top_name); + if (old_mod) + design->remove(old_mod); + design->add(m); + top_mod = m; + } + } + if (top_mod == nullptr && auto_top_mode) { log_header(design, "Finding top of design hierarchy..\n"); dict<Module*, int> db; diff --git a/passes/techmap/techmap.cc b/passes/techmap/techmap.cc index c4496f76f..5ce1bf7d6 100644 --- a/passes/techmap/techmap.cc +++ b/passes/techmap/techmap.cc @@ -205,20 +205,38 @@ struct TechmapWorker } std::map<RTLIL::IdString, RTLIL::IdString> positional_ports; + dict<Wire*, IdString> temp_renamed_wires; for (auto &it : tpl->wires_) { if (it.second->port_id > 0) positional_ports[stringf("$%d", it.second->port_id)] = it.first; IdString w_name = it.second->name; apply_prefix(cell->name, w_name); - RTLIL::Wire *w = module->addWire(w_name, it.second); - w->port_input = false; - w->port_output = false; - w->port_id = 0; - if (it.second->get_bool_attribute(ID(_techmap_special_))) - w->attributes.clear(); - if (w->attributes.count(ID(src))) - w->add_strpool_attribute(ID(src), extra_src_attrs); + RTLIL::Wire *w = module->wire(w_name); + if (w != nullptr) { + if (!flatten_mode || !w->get_bool_attribute(ID(hierconn))) { + temp_renamed_wires[w] = w->name; + module->rename(w, NEW_ID); + w = nullptr; + } else { + w->attributes.erase(ID(hierconn)); + if (GetSize(w) < GetSize(it.second)) { + log_warning("Widening signal %s.%s to match size of %s.%s (via %s.%s).\n", log_id(module), log_id(w), + log_id(tpl), log_id(it.second), log_id(module), log_id(cell)); + w->width = GetSize(it.second); + } + } + } + if (w == nullptr) { + w = module->addWire(w_name, it.second); + w->port_input = false; + w->port_output = false; + w->port_id = 0; + if (it.second->get_bool_attribute(ID(_techmap_special_))) + w->attributes.clear(); + if (w->attributes.count(ID(src))) + w->add_strpool_attribute(ID(src), extra_src_attrs); + } design->select(module, w); } @@ -380,6 +398,16 @@ struct TechmapWorker } module->remove(cell); + + for (auto &it : temp_renamed_wires) + { + Wire *w = it.first; + IdString name = it.second; + IdString altname = module->uniquify(name); + Wire *other_w = module->wire(name); + module->rename(other_w, altname); + module->rename(w, name); + } } bool techmap_module(RTLIL::Design *design, RTLIL::Module *module, RTLIL::Design *map, std::set<RTLIL::Cell*> &handled_cells, diff --git a/tests/simple/run-test.sh b/tests/simple/run-test.sh index 967ac49f2..f20fd0d30 100755 --- a/tests/simple/run-test.sh +++ b/tests/simple/run-test.sh @@ -12,7 +12,7 @@ done shift "$((OPTIND-1))" # check for Icarus Verilog -if ! which iverilog > /dev/null ; then +if ! command -v iverilog > /dev/null ; then echo "$0: Error: Icarus Verilog 'iverilog' not found." exit 1 fi diff --git a/tests/simple_abc9/run-test.sh b/tests/simple_abc9/run-test.sh index 8df6994e3..0d4262005 100755 --- a/tests/simple_abc9/run-test.sh +++ b/tests/simple_abc9/run-test.sh @@ -12,7 +12,7 @@ done shift "$((OPTIND-1))" # check for Icarus Verilog -if ! which iverilog > /dev/null ; then +if ! command -v iverilog > /dev/null ; then echo "$0: Error: Icarus Verilog 'iverilog' not found." exit 1 fi diff --git a/tests/various/hierarchy_defer.ys b/tests/various/hierarchy_defer.ys new file mode 100644 index 000000000..70f5b70a3 --- /dev/null +++ b/tests/various/hierarchy_defer.ys @@ -0,0 +1,27 @@ +read -noverific +read -vlog2k <<EOT +module first; +endmodule + +(* top *) +module top(input i, output o); +sub s0(i, o); +endmodule + +(* constant_expression=1+1?2*2:3/3 *) +module sub(input i, output o); +assign o = ~i; +endmodule +EOT +design -save read + +hierarchy -auto-top +select -assert-any top +select -assert-any sub +select -assert-none foo + +design -load read +hierarchy +select -assert-any top +select -assert-any sub +select -assert-none foo |