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-rw-r--r--CHANGELOG9
-rw-r--r--Makefile4
-rw-r--r--frontends/verific/verific.cc17
-rw-r--r--kernel/rtlil.cc10
-rw-r--r--kernel/rtlil.h4
-rw-r--r--manual/command-reference-manual.tex8
-rw-r--r--passes/cmds/select.cc3
-rw-r--r--passes/cmds/stat.cc9
-rw-r--r--passes/fsm/fsmdata.h4
-rw-r--r--passes/opt/wreduce.cc10
-rw-r--r--passes/sat/fmcombine.cc3
11 files changed, 63 insertions, 18 deletions
diff --git a/CHANGELOG b/CHANGELOG
index c26f389fc..e32d9d053 100644
--- a/CHANGELOG
+++ b/CHANGELOG
@@ -2,8 +2,14 @@
List of major changes and improvements between releases
=======================================================
-Yosys 0.17 .. Yosys 0.17-dev
+Yosys 0.18 .. Yosys 0.18-dev
--------------------------
+
+Yosys 0.17 .. Yosys 0.18
+--------------------------
+ * Various
+ - Migrated most flows to use memory_libmap based memory inference
+
* New commands and options
- Added "memory_libmap" pass
- Added "memory_bmux2rom" pass - converts muxes to ROMs
@@ -30,6 +36,7 @@ Yosys 0.17 .. Yosys 0.17-dev
* Verific support
- Proper file location for readmem commands
+ - Added "-vlog-libext" option to specify search extension for libraries
Yosys 0.16 .. Yosys 0.17
--------------------------
diff --git a/Makefile b/Makefile
index 120e3076e..dd9eaad92 100644
--- a/Makefile
+++ b/Makefile
@@ -129,7 +129,7 @@ LDFLAGS += -rdynamic
LDLIBS += -lrt
endif
-YOSYS_VER := 0.17+87
+YOSYS_VER := 0.18+0
# Note: We arrange for .gitcommit to contain the (short) commit hash in
# tarballs generated with git-archive(1) using .gitattributes. The git repo
@@ -145,7 +145,7 @@ endif
OBJS = kernel/version_$(GIT_REV).o
bumpversion:
- sed -i "/^YOSYS_VER := / s/+[0-9][0-9]*$$/+`git log --oneline 6f9602b.. | wc -l`/;" Makefile
+ sed -i "/^YOSYS_VER := / s/+[0-9][0-9]*$$/+`git log --oneline 19ce3b4.. | wc -l`/;" Makefile
# set 'ABCREV = default' to use abc/ as it is
#
diff --git a/frontends/verific/verific.cc b/frontends/verific/verific.cc
index a9adb5a17..6351483db 100644
--- a/frontends/verific/verific.cc
+++ b/frontends/verific/verific.cc
@@ -86,7 +86,7 @@ bool verific_import_pending;
string verific_error_msg;
int verific_sva_fsm_limit;
-vector<string> verific_incdirs, verific_libdirs;
+vector<string> verific_incdirs, verific_libdirs, verific_libexts;
void msg_func(msg_type_t msg_type, const char *message_id, linefile_type linefile, const char *msg, va_list args)
{
@@ -2323,6 +2323,7 @@ void verific_import(Design *design, const std::map<std::string,std::string> &par
LineFile::DeleteAllLineFiles();
verific_incdirs.clear();
verific_libdirs.clear();
+ verific_libexts.clear();
verific_import_pending = false;
if (!verific_error_msg.empty())
@@ -2433,6 +2434,11 @@ struct VerificPass : public Pass {
log("find undefined modules.\n");
log("\n");
log("\n");
+ log(" verific -vlog-libext <extension>..\n");
+ log("\n");
+ log("Add Verilog library extensions, used when searching in library directories.\n");
+ log("\n");
+ log("\n");
log(" verific -vlog-define <macro>[=<value>]..\n");
log("\n");
log("Add Verilog defines.\n");
@@ -2716,6 +2722,12 @@ struct VerificPass : public Pass {
goto check_error;
}
+ if (GetSize(args) > argidx && args[argidx] == "-vlog-libext") {
+ for (argidx++; argidx < GetSize(args); argidx++)
+ verific_libexts.push_back(args[argidx]);
+ goto check_error;
+ }
+
if (GetSize(args) > argidx && args[argidx] == "-vlog-define") {
for (argidx++; argidx < GetSize(args); argidx++) {
string name = args[argidx];
@@ -2856,6 +2868,8 @@ struct VerificPass : public Pass {
veri_file::AddIncludeDir(dir.c_str());
for (auto &dir : verific_libdirs)
veri_file::AddYDir(dir.c_str());
+ for (auto &ext : verific_libexts)
+ veri_file::AddLibExt(ext.c_str());
while (argidx < GetSize(args))
file_names.Insert(args[argidx++].c_str());
@@ -3345,6 +3359,7 @@ struct VerificPass : public Pass {
LineFile::DeleteAllLineFiles();
verific_incdirs.clear();
verific_libdirs.clear();
+ verific_libexts.clear();
verific_import_pending = false;
goto check_error;
}
diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc
index 72dcb89af..8346b56e0 100644
--- a/kernel/rtlil.cc
+++ b/kernel/rtlil.cc
@@ -204,7 +204,7 @@ RTLIL::Const::Const()
flags = RTLIL::CONST_FLAG_NONE;
}
-RTLIL::Const::Const(std::string str)
+RTLIL::Const::Const(const std::string &str)
{
flags = RTLIL::CONST_FLAG_STRING;
bits.reserve(str.size() * 8);
@@ -243,14 +243,6 @@ RTLIL::Const::Const(const std::vector<bool> &bits)
this->bits.emplace_back(b ? State::S1 : State::S0);
}
-RTLIL::Const::Const(const RTLIL::Const &c)
-{
- flags = c.flags;
- this->bits.reserve(c.size());
- for (const auto &b : c.bits)
- this->bits.push_back(b);
-}
-
bool RTLIL::Const::operator <(const RTLIL::Const &other) const
{
if (bits.size() != other.bits.size())
diff --git a/kernel/rtlil.h b/kernel/rtlil.h
index d8300f159..7a0b6b9c7 100644
--- a/kernel/rtlil.h
+++ b/kernel/rtlil.h
@@ -636,12 +636,12 @@ struct RTLIL::Const
std::vector<RTLIL::State> bits;
Const();
- Const(std::string str);
+ Const(const std::string &str);
Const(int val, int width = 32);
Const(RTLIL::State bit, int width = 1);
Const(const std::vector<RTLIL::State> &bits) : bits(bits) { flags = CONST_FLAG_NONE; }
Const(const std::vector<bool> &bits);
- Const(const RTLIL::Const &c);
+ Const(const RTLIL::Const &c) = default;
RTLIL::Const &operator =(const RTLIL::Const &other) = default;
bool operator <(const RTLIL::Const &other) const;
diff --git a/manual/command-reference-manual.tex b/manual/command-reference-manual.tex
index 4108527d8..edc8af6e6 100644
--- a/manual/command-reference-manual.tex
+++ b/manual/command-reference-manual.tex
@@ -7838,6 +7838,11 @@ Add Verilog library directories. Verific will search in this directories to
find undefined modules.
+ verific -vlog-libext <extension>..
+
+Add Verilog library extensions, used when searching in library directories.
+
+
verific -vlog-define <macro>[=<value>]..
Add Verilog defines.
@@ -8057,6 +8062,9 @@ Options:
Do not change the width of memory address ports. Use this options in
flows that use the 'memory_memx' pass.
+ -mux_undef
+ remove 'undef' inputs from $mux, $pmux and $_MUX_ cells
+
-keepdc
Do not optimize explicit don't-care values.
\end{lstlisting}
diff --git a/passes/cmds/select.cc b/passes/cmds/select.cc
index d609c8d0f..b112b145c 100644
--- a/passes/cmds/select.cc
+++ b/passes/cmds/select.cc
@@ -1456,7 +1456,10 @@ struct SelectPass : public Pass {
}
}
if (count_mode)
+ {
+ design->scratchpad_set_int("select.count", total_count);
log("%d objects.\n", total_count);
+ }
if (f != nullptr)
fclose(f);
#undef LOG_OBJECT
diff --git a/passes/cmds/stat.cc b/passes/cmds/stat.cc
index fffdda48e..c858c8631 100644
--- a/passes/cmds/stat.cc
+++ b/passes/cmds/stat.cc
@@ -381,6 +381,15 @@ struct StatPass : public Pass {
log("\n");
data.log_data(top_mod->name, true);
+ design->scratchpad_set_int("stat.num_wires", data.num_wires);
+ design->scratchpad_set_int("stat.num_wire_bits", data.num_wire_bits);
+ design->scratchpad_set_int("stat.num_pub_wires", data.num_pub_wires);
+ design->scratchpad_set_int("stat.num_pub_wire_bits", data.num_pub_wire_bits);
+ design->scratchpad_set_int("stat.num_memories", data.num_memories);
+ design->scratchpad_set_int("stat.num_memory_bits", data.num_memory_bits);
+ design->scratchpad_set_int("stat.num_processes", data.num_processes);
+ design->scratchpad_set_int("stat.num_cells", data.num_cells);
+ design->scratchpad_set_int("stat.area", data.area);
}
log("\n");
diff --git a/passes/fsm/fsmdata.h b/passes/fsm/fsmdata.h
index 4ba3b4e4f..97371efab 100644
--- a/passes/fsm/fsmdata.h
+++ b/passes/fsm/fsmdata.h
@@ -91,8 +91,8 @@ struct FsmData
if (reset_state < 0 || reset_state >= state_num)
reset_state = -1;
- RTLIL::Const state_table = cell->parameters[ID::STATE_TABLE];
- RTLIL::Const trans_table = cell->parameters[ID::TRANS_TABLE];
+ const RTLIL::Const &state_table = cell->parameters[ID::STATE_TABLE];
+ const RTLIL::Const &trans_table = cell->parameters[ID::TRANS_TABLE];
for (int i = 0; i < state_num; i++) {
RTLIL::Const state_code;
diff --git a/passes/opt/wreduce.cc b/passes/opt/wreduce.cc
index aaad28ef0..08ab6de6f 100644
--- a/passes/opt/wreduce.cc
+++ b/passes/opt/wreduce.cc
@@ -30,6 +30,7 @@ struct WreduceConfig
{
pool<IdString> supported_cell_types;
bool keepdc = false;
+ bool mux_undef = false;
WreduceConfig()
{
@@ -83,7 +84,7 @@ struct WreduceWorker
SigBit ref = sig_a[i];
for (int k = 0; k < GetSize(sig_s); k++) {
- if ((config->keepdc || (ref != State::Sx && sig_b[k*GetSize(sig_a) + i] != State::Sx)) && ref != sig_b[k*GetSize(sig_a) + i])
+ if ((config->keepdc || !config->mux_undef || (ref != State::Sx && sig_b[k*GetSize(sig_a) + i] != State::Sx)) && ref != sig_b[k*GetSize(sig_a) + i])
goto no_match_ab;
if (sig_b[k*GetSize(sig_a) + i] != State::Sx)
ref = sig_b[k*GetSize(sig_a) + i];
@@ -479,6 +480,9 @@ struct WreducePass : public Pass {
log(" Do not change the width of memory address ports. Use this options in\n");
log(" flows that use the 'memory_memx' pass.\n");
log("\n");
+ log(" -mux_undef\n");
+ log(" remove 'undef' inputs from $mux, $pmux and $_MUX_ cells\n");
+ log("\n");
log(" -keepdc\n");
log(" Do not optimize explicit don't-care values.\n");
log("\n");
@@ -500,6 +504,10 @@ struct WreducePass : public Pass {
config.keepdc = true;
continue;
}
+ if (args[argidx] == "-mux_undef") {
+ config.mux_undef = true;
+ continue;
+ }
break;
}
extra_args(args, argidx, design);
diff --git a/passes/sat/fmcombine.cc b/passes/sat/fmcombine.cc
index e15bdf6a8..220cf5c52 100644
--- a/passes/sat/fmcombine.cc
+++ b/passes/sat/fmcombine.cc
@@ -64,6 +64,9 @@ struct FmcombineWorker
c->parameters = cell->parameters;
c->attributes = cell->attributes;
+ if (cell->is_mem_cell())
+ c->parameters[ID::MEMID] = cell->parameters[ID::MEMID].decode_string() + suffix;
+
for (auto &conn : cell->connections())
c->setPort(conn.first, import_sig(conn.second, suffix));
generated by cgit v1.2.3 (git 2.25.1) at 2025-04-19 03:56:15 +0000