diff options
| -rw-r--r-- | frontends/ast/genrtlil.cc | 1 | ||||
| -rw-r--r-- | frontends/ast/simplify.cc | 8 | ||||
| -rw-r--r-- | tests/various/const_arg_loop.v | 10 | ||||
| -rw-r--r-- | tests/various/port_sign_extend.v | 13 |
4 files changed, 28 insertions, 4 deletions
diff --git a/frontends/ast/genrtlil.cc b/frontends/ast/genrtlil.cc index 500ccf8c0..b8bfdf65e 100644 --- a/frontends/ast/genrtlil.cc +++ b/frontends/ast/genrtlil.cc @@ -141,6 +141,7 @@ static RTLIL::SigSpec mux2rtlil(AstNode *that, const RTLIL::SigSpec &cond, const RTLIL::Wire *wire = current_module->addWire(cell->name.str() + "_Y", left.size()); wire->attributes[ID::src] = stringf("%s:%d.%d-%d.%d", that->filename.c_str(), that->location.first_line, that->location.first_column, that->location.last_line, that->location.last_column); + wire->is_signed = that->is_signed; for (auto &attr : that->attributes) { if (attr.second->type != AST_CONSTANT) diff --git a/frontends/ast/simplify.cc b/frontends/ast/simplify.cc index 8e205cb76..5fa4ac83b 100644 --- a/frontends/ast/simplify.cc +++ b/frontends/ast/simplify.cc @@ -3342,6 +3342,14 @@ skip_dynamic_range_lvalue_expansion:; wire->type = AST_LOCALPARAM; wire->attributes.erase(ID::nosync); wire->children.insert(wire->children.begin(), arg->clone()); + // args without a range implicitly have width 1 + if (wire->children.back()->type != AST_RANGE) { + AstNode* range = new AstNode(); + range->type = AST_RANGE; + wire->children.push_back(range); + range->children.push_back(mkconst_int(0, true)); + range->children.push_back(mkconst_int(0, true)); + } continue; } AstNode *wire_id = new AstNode(AST_IDENTIFIER); diff --git a/tests/various/const_arg_loop.v b/tests/various/const_arg_loop.v index 76cc67abb..ed15aa135 100644 --- a/tests/various/const_arg_loop.v +++ b/tests/various/const_arg_loop.v @@ -44,6 +44,12 @@ module top; end endfunction + function automatic [16:0] operation4; + input [15:0] a; + input b; + operation4 = {a, b}; + endfunction + wire [31:0] a; assign a = 2; @@ -61,6 +67,9 @@ module top; wire [31:0] x3; assign x3 = operation3(A, a); + wire [16:0] x4; + assign x4 = operation4(a[15:0], 0); + // `define VERIFY `ifdef VERIFY assert property (a == 2); @@ -69,5 +78,6 @@ module top; assert property (x1b == 16); assert property (x2 == 4); assert property (x3 == 16); + assert property (x4 == a << 1); `endif endmodule diff --git a/tests/various/port_sign_extend.v b/tests/various/port_sign_extend.v index 055f20ad8..446268268 100644 --- a/tests/various/port_sign_extend.v +++ b/tests/various/port_sign_extend.v @@ -24,8 +24,8 @@ module PassThrough(a, b); assign b = a; endmodule -module act(o1, o2, o3, o4, o5, yay1, nay1, yay2, nay2); - output wire [3:0] o1, o2, o3, o4, o5; +module act(o1, o2, o3, o4, o5, o6, yay1, nay1, yay2, nay2); + output wire [3:0] o1, o2, o3, o4, o5, o6; // unsigned constant PassThrough pt1(1'b1, o1); @@ -48,6 +48,10 @@ module act(o1, o2, o3, o4, o5, yay1, nay1, yay2, nay2); wire signed [1:0] tmp5b = 2'b01; PassThrough pt5(tmp5a ^ tmp5b, o5); + wire signed [2:0] tmp6a = 3'b100; + wire signed [2:0] tmp6b = 3'b001; + PassThrough pt6(tmp6a ? tmp6a : tmp6b, o6); + output wire [2:0] yay1, nay1; GeneratorSigned1 os1(yay1); GeneratorUnsigned1 ou1(nay1); @@ -57,14 +61,15 @@ module act(o1, o2, o3, o4, o5, yay1, nay1, yay2, nay2); GeneratorUnsigned2 ou2(nay2); endmodule -module ref(o1, o2, o3, o4, o5, yay1, nay1, yay2, nay2); - output wire [3:0] o1, o2, o3, o4, o5; +module ref(o1, o2, o3, o4, o5, o6, yay1, nay1, yay2, nay2); + output wire [3:0] o1, o2, o3, o4, o5, o6; assign o1 = 4'b0001; assign o2 = 4'b0001; assign o3 = 4'b1111; assign o4 = 4'b1111; assign o5 = 4'b1110; + assign o6 = 4'b1100; output wire [2:0] yay1, nay1; assign yay1 = 3'b111; |