diff options
| -rw-r--r-- | Makefile | 2 | ||||
| -rw-r--r-- | frontends/verific/verific.cc | 77 | ||||
| -rw-r--r-- | kernel/yosys.h | 2 | ||||
| -rw-r--r-- | passes/techmap/flatten.cc | 7 |
4 files changed, 81 insertions, 7 deletions
@@ -129,7 +129,7 @@ LDFLAGS += -rdynamic LDLIBS += -lrt endif -YOSYS_VER := 0.10+63 +YOSYS_VER := 0.10+71 GIT_REV := $(shell git -C $(YOSYS_SRC) rev-parse --short HEAD 2> /dev/null || echo UNKNOWN) OBJS = kernel/version_$(GIT_REV).o diff --git a/frontends/verific/verific.cc b/frontends/verific/verific.cc index eb9f37678..5a75b52af 100644 --- a/frontends/verific/verific.cc +++ b/frontends/verific/verific.cc @@ -2498,6 +2498,13 @@ struct VerificPass : public Pass { log(" WARNING: Templates only available in commercial build.\n"); log("\n"); #endif + log("\n"); + log("\n"); + log(" verific -cfg [<name> [<value>]]\n"); + log("\n"); + log("Get/set Verific runtime flags.\n"); + log("\n"); + log("\n"); log("Use YosysHQ Tabby CAD Suite if you need Yosys+Verific.\n"); log("https://www.yosyshq.com/\n"); log("\n"); @@ -2526,7 +2533,10 @@ struct VerificPass : public Pass { Message::SetConsoleOutput(0); Message::RegisterCallBackMsg(msg_func); + RuntimeFlags::SetVar("db_preserve_user_instances", 1); RuntimeFlags::SetVar("db_preserve_user_nets", 1); + RuntimeFlags::SetVar("db_preserve_x", 1); + RuntimeFlags::SetVar("db_allow_external_nets", 1); RuntimeFlags::SetVar("db_infer_wide_operators", 1); RuntimeFlags::SetVar("db_infer_set_reset_registers", 0); @@ -2542,10 +2552,12 @@ struct VerificPass : public Pass { RuntimeFlags::SetVar("vhdl_ignore_assertion_statements", 0); RuntimeFlags::SetVar("vhdl_preserve_assignments", 1); - //RuntimeFlags::SetVar("vhdl_preserve_comments",1); + //RuntimeFlags::SetVar("vhdl_preserve_comments", 1); + RuntimeFlags::SetVar("vhdl_preserve_drivers", 1); #endif RuntimeFlags::SetVar("veri_preserve_assignments", 1); - RuntimeFlags::SetVar("veri_preserve_comments",1); + RuntimeFlags::SetVar("veri_preserve_comments", 1); + RuntimeFlags::SetVar("veri_preserve_drivers", 1); // Workaround for VIPER #13851 RuntimeFlags::SetVar("veri_create_name_for_unnamed_gen_block", 1); @@ -2556,6 +2568,8 @@ struct VerificPass : public Pass { // https://github.com/YosysHQ/yosys/issues/1055 RuntimeFlags::SetVar("veri_elaborate_top_level_modules_having_interface_ports", 1) ; + RuntimeFlags::SetVar("verific_produce_verbose_syntax_error_message", 1); + #ifndef DB_PRESERVE_INITIAL_VALUE # warning Verific was built without DB_PRESERVE_INITIAL_VALUE. #endif @@ -3200,6 +3214,65 @@ struct VerificPass : public Pass { goto check_error; } + if (argidx < GetSize(args) && args[argidx] == "-cfg") + { + if (argidx+1 == GetSize(args)) { + MapIter mi; + const char *k, *s; + unsigned long v; + pool<std::string> lines; + FOREACH_MAP_ITEM(RuntimeFlags::GetVarMap(), mi, &k, &v) { + lines.insert(stringf("%s %lu", k, v)); + } + FOREACH_MAP_ITEM(RuntimeFlags::GetStringVarMap(), mi, &k, &s) { + if (s == nullptr) + lines.insert(stringf("%s NULL", k)); + else + lines.insert(stringf("%s \"%s\"", k, s)); + } + lines.sort(); + for (auto &line : lines) + log("verific -cfg %s\n", line.c_str()); + goto check_error; + } + + if (argidx+2 == GetSize(args)) { + const char *k = args[argidx+1].c_str(); + if (RuntimeFlags::HasUnsignedVar(k)) { + log("verific -cfg %s %lu\n", k, RuntimeFlags::GetVar(k)); + goto check_error; + } + if (RuntimeFlags::HasStringVar(k)) { + const char *s = RuntimeFlags::GetStringVar(k); + if (s == nullptr) + log("verific -cfg %s NULL\n", k); + else + log("verific -cfg %s \"%s\"\n", k, s); + goto check_error; + } + log_cmd_error("Can't find Verific Runtime flag '%s'.\n", k); + } + + if (argidx+3 == GetSize(args)) { + const auto &k = args[argidx+1], &v = args[argidx+2]; + if (v == "NULL") { + RuntimeFlags::SetStringVar(k.c_str(), nullptr); + goto check_error; + } + if (v[0] == '"') { + std::string s = v.substr(1, GetSize(v)-2); + RuntimeFlags::SetStringVar(k.c_str(), v.c_str()); + goto check_error; + } + char *endptr; + unsigned long n = strtol(v.c_str(), &endptr, 0); + if (*endptr == 0) { + RuntimeFlags::SetVar(k.c_str(), n); + goto check_error; + } + } + } + cmd_error(args, argidx, "Missing or unsupported mode parameter.\n"); check_error: diff --git a/kernel/yosys.h b/kernel/yosys.h index 013c3308f..7fe8dc4f4 100644 --- a/kernel/yosys.h +++ b/kernel/yosys.h @@ -148,7 +148,7 @@ extern Tcl_Obj *Tcl_ObjSetVar2(Tcl_Interp *interp, Tcl_Obj *part1Ptr, Tcl_Obj *p #endif #if __cplusplus >= 201703L -# define YS_MAYBE_UNUSED [[maybe_unused]]; +# define YS_MAYBE_UNUSED [[maybe_unused]] #elif defined(__GNUC__) || defined(__clang__) # define YS_MAYBE_UNUSED __attribute__((__unused__)) #else diff --git a/passes/techmap/flatten.cc b/passes/techmap/flatten.cc index 616fee3f5..7e6df5d2c 100644 --- a/passes/techmap/flatten.cc +++ b/passes/techmap/flatten.cc @@ -77,7 +77,7 @@ struct FlattenWorker { bool ignore_wb = false; - void flatten_cell(RTLIL::Design *design, RTLIL::Module *module, RTLIL::Cell *cell, RTLIL::Module *tpl, std::vector<RTLIL::Cell*> &new_cells) + void flatten_cell(RTLIL::Design *design, RTLIL::Module *module, RTLIL::Cell *cell, RTLIL::Module *tpl, SigMap &sigmap, std::vector<RTLIL::Cell*> &new_cells) { // Copy the contents of the flattened cell @@ -165,7 +165,6 @@ struct FlattenWorker for (auto bit : tpl_conn.first) tpl_driven.insert(bit); - SigMap sigmap(module); for (auto &port_it : cell->connections()) { IdString port_name = port_it.first; @@ -218,6 +217,7 @@ struct FlattenWorker log_id(module), log_id(cell), log_id(port_it.first), log_signal(new_conn.first), log_signal(new_conn.second)); module->connect(new_conn); + sigmap.add(new_conn.first, new_conn.second); } module->remove(cell); @@ -228,6 +228,7 @@ struct FlattenWorker if (!design->selected(module) || module->get_blackbox_attribute(ignore_wb)) return; + SigMap sigmap(module); std::vector<RTLIL::Cell*> worklist = module->selected_cells(); while (!worklist.empty()) { @@ -251,7 +252,7 @@ struct FlattenWorker // If a design is fully selected and has a top module defined, topological sorting ensures that all cells // added during flattening are black boxes, and flattening is finished in one pass. However, when flattening // individual modules, this isn't the case, and the newly added cells might have to be flattened further. - flatten_cell(design, module, cell, tpl, worklist); + flatten_cell(design, module, cell, tpl, sigmap, worklist); } } }; |