diff options
| -rw-r--r-- | Makefile | 5 | ||||
| -rw-r--r-- | README.md | 4 | ||||
| -rw-r--r-- | backends/btor/btor.cc | 10 | ||||
| -rw-r--r-- | backends/cxxrtl/Makefile.inc | 2 | ||||
| -rw-r--r-- | backends/cxxrtl/cxxrtl.h | 160 | ||||
| -rw-r--r-- | backends/cxxrtl/cxxrtl_backend.cc (renamed from backends/cxxrtl/cxxrtl.cc) | 246 | ||||
| -rw-r--r-- | backends/cxxrtl/cxxrtl_capi.cc | 60 | ||||
| -rw-r--r-- | backends/cxxrtl/cxxrtl_capi.h | 152 | ||||
| -rw-r--r-- | backends/cxxrtl/cxxrtl_vcd.h | 224 | ||||
| -rw-r--r-- | backends/cxxrtl/cxxrtl_vcd_capi.cc | 83 | ||||
| -rw-r--r-- | backends/cxxrtl/cxxrtl_vcd_capi.h | 107 | ||||
| -rw-r--r-- | backends/smt2/smtio.py | 2 | ||||
| -rw-r--r-- | frontends/ast/simplify.cc | 143 | ||||
| -rw-r--r-- | frontends/verilog/verilog_parser.y | 10 | ||||
| -rw-r--r-- | kernel/register.h | 2 | ||||
| -rw-r--r-- | kernel/rtlil.cc | 44 | ||||
| -rw-r--r-- | kernel/rtlil.h | 7 | ||||
| -rw-r--r-- | manual/CHAPTER_Overview.tex | 7 | ||||
| -rw-r--r-- | passes/cmds/select.cc | 33 | ||||
| -rw-r--r-- | passes/fsm/fsm_extract.cc | 2 | ||||
| -rw-r--r-- | passes/hierarchy/hierarchy.cc | 19 | ||||
| -rw-r--r-- | passes/techmap/Makefile.inc | 1 | ||||
| -rw-r--r-- | passes/techmap/flatten.cc | 333 | ||||
| -rw-r--r-- | passes/techmap/techmap.cc | 494 | ||||
| -rw-r--r-- | tests/svtypes/struct_array.sv | 22 |
25 files changed, 1708 insertions, 464 deletions
@@ -588,6 +588,11 @@ $(eval $(call add_include_file,passes/fsm/fsmdata.h)) $(eval $(call add_include_file,frontends/ast/ast.h)) $(eval $(call add_include_file,backends/ilang/ilang_backend.h)) $(eval $(call add_include_file,backends/cxxrtl/cxxrtl.h)) +$(eval $(call add_include_file,backends/cxxrtl/cxxrtl_vcd.h)) +$(eval $(call add_include_file,backends/cxxrtl/cxxrtl_capi.cc)) +$(eval $(call add_include_file,backends/cxxrtl/cxxrtl_capi.h)) +$(eval $(call add_include_file,backends/cxxrtl/cxxrtl_vcd_capi.cc)) +$(eval $(call add_include_file,backends/cxxrtl/cxxrtl_vcd_capi.h)) OBJS += kernel/driver.o kernel/register.o kernel/rtlil.o kernel/log.o kernel/calc.o kernel/yosys.o OBJS += kernel/cellaigs.o kernel/celledges.o @@ -309,7 +309,9 @@ Verilog Attributes and non-standard features that have ports with a width that depends on a parameter. - The ``hdlname`` attribute is used by some passes to document the original - (HDL) name of a module when renaming a module. + (HDL) name of a module when renaming a module. It should contain a single + name, or, when describing a hierarchical name in a flattened design, multiple + names separated by a single space character. - The ``keep`` attribute on cells and wires is used to mark objects that should never be removed by the optimizer. This is used for example for cells that diff --git a/backends/btor/btor.cc b/backends/btor/btor.cc index bbdcfb70a..9ac312480 100644 --- a/backends/btor/btor.cc +++ b/backends/btor/btor.cc @@ -1355,13 +1355,13 @@ struct BtorBackend : public Backend { log(" -i <filename>\n"); log(" Create additional info file with auxiliary information\n"); log("\n"); - log(" -n\n"); - log(" Don't identify internal netnames\n"); + log(" -x\n"); + log(" Output symbols for internal netnames (starting with '$')\n"); log("\n"); } void execute(std::ostream *&f, std::string filename, std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE { - bool verbose = false, single_bad = false, cover_mode = false, print_internal_names = true; + bool verbose = false, single_bad = false, cover_mode = false, print_internal_names = false; string info_filename; log_header(design, "Executing BTOR backend.\n"); @@ -1385,8 +1385,8 @@ struct BtorBackend : public Backend { info_filename = args[++argidx]; continue; } - if (args[argidx] == "-n") { - print_internal_names = false; + if (args[argidx] == "-x") { + print_internal_names = true; continue; } break; diff --git a/backends/cxxrtl/Makefile.inc b/backends/cxxrtl/Makefile.inc index f93e65f85..aaa304502 100644 --- a/backends/cxxrtl/Makefile.inc +++ b/backends/cxxrtl/Makefile.inc @@ -1,2 +1,2 @@ -OBJS += backends/cxxrtl/cxxrtl.o +OBJS += backends/cxxrtl/cxxrtl_backend.o diff --git a/backends/cxxrtl/cxxrtl.h b/backends/cxxrtl/cxxrtl.h index 701510b7f..c988c9e80 100644 --- a/backends/cxxrtl/cxxrtl.h +++ b/backends/cxxrtl/cxxrtl.h @@ -33,13 +33,15 @@ #include <memory> #include <sstream> -// The cxxrtl support library implements compile time specialized arbitrary width arithmetics, as well as provides +#include <backends/cxxrtl/cxxrtl_capi.h> + +// The CXXRTL support library implements compile time specialized arbitrary width arithmetics, as well as provides // composite lvalues made out of bit slices and concatenations of lvalues. This allows the `write_cxxrtl` pass // to perform a straightforward translation of RTLIL structures to readable C++, relying on the C++ compiler // to unwrap the abstraction and generate efficient code. namespace cxxrtl { -// All arbitrary-width values in cxxrtl are backed by arrays of unsigned integers called chunks. The chunk size +// All arbitrary-width values in CXXRTL are backed by arrays of unsigned integers called chunks. The chunk size // is the same regardless of the value width to simplify manipulating values via FFI interfaces, e.g. driving // and introspecting the simulation in Python. // @@ -49,6 +51,8 @@ namespace cxxrtl { // invisible to the compiler, (b) we often operate on non-power-of-2 values and have to clear the high bits anyway. // Therefore, using relatively wide chunks and clearing the high bits explicitly and only when we know they may be // clobbered results in simpler generated code. +typedef uint32_t chunk_t; + template<typename T> struct chunk_traits { static_assert(std::is_integral<T>::value && std::is_unsigned<T>::value, @@ -65,7 +69,7 @@ template<size_t Bits> struct value : public expr_base<value<Bits>> { static constexpr size_t bits = Bits; - using chunk = chunk_traits<uint32_t>; + using chunk = chunk_traits<chunk_t>; static constexpr chunk::type msb_mask = (Bits % chunk::bits == 0) ? chunk::mask : chunk::mask >> (chunk::bits - (Bits % chunk::bits)); @@ -712,6 +716,69 @@ struct metadata { typedef std::map<std::string, metadata> metadata_map; +// This structure is intended for consumption via foreign function interfaces, like Python's ctypes. +// Because of this it uses a C-style layout that is easy to parse rather than more idiomatic C++. +// +// To avoid violating strict aliasing rules, this structure has to be a subclass of the one used +// in the C API, or it would not be possible to cast between the pointers to these. +struct debug_item : ::cxxrtl_object { + enum : uint32_t { + VALUE = CXXRTL_VALUE, + WIRE = CXXRTL_WIRE, + MEMORY = CXXRTL_MEMORY, + }; + + debug_item(const ::cxxrtl_object &object) : cxxrtl_object(object) {} + + template<size_t Bits> + debug_item(value<Bits> &item) { + static_assert(sizeof(item) == value<Bits>::chunks * sizeof(chunk_t), + "value<Bits> is not compatible with C layout"); + type = VALUE; + width = Bits; + depth = 1; + curr = item.data; + next = item.data; + } + + template<size_t Bits> + debug_item(const value<Bits> &item) { + static_assert(sizeof(item) == value<Bits>::chunks * sizeof(chunk_t), + "value<Bits> is not compatible with C layout"); + type = VALUE; + width = Bits; + depth = 1; + curr = const_cast<uint32_t*>(item.data); + next = nullptr; + } + + template<size_t Bits> + debug_item(wire<Bits> &item) { + static_assert(sizeof(item.curr) == value<Bits>::chunks * sizeof(chunk_t) && + sizeof(item.next) == value<Bits>::chunks * sizeof(chunk_t), + "wire<Bits> is not compatible with C layout"); + type = WIRE; + width = Bits; + depth = 1; + curr = item.curr.data; + next = item.next.data; + } + + template<size_t Width> + debug_item(memory<Width> &item) { + static_assert(sizeof(item.data[0]) == value<Width>::chunks * sizeof(chunk_t), + "memory<Width> is not compatible with C layout"); + type = MEMORY; + width = Width; + depth = item.data.size(); + curr = item.data.empty() ? nullptr : item.data[0].data; + next = nullptr; + } +}; +static_assert(std::is_standard_layout<debug_item>::value, "debug_item is not compatible with C layout"); + +typedef std::map<std::string, debug_item> debug_items; + struct module { module() {} virtual ~module() {} @@ -731,11 +798,18 @@ struct module { } while (commit() && !converged); return deltas; } + + virtual void debug_info(debug_items &items, std::string path = "") {} }; } // namespace cxxrtl -// Definitions of internal Yosys cells. Other than the functions in this namespace, cxxrtl is fully generic +// Internal structure used to communicate with the implementation of the C interface. +typedef struct _cxxrtl_toplevel { + std::unique_ptr<cxxrtl::module> module; +} *cxxrtl_toplevel; + +// Definitions of internal Yosys cells. Other than the functions in this namespace, CXXRTL is fully generic // and indepenent of Yosys implementation details. // // The `write_cxxrtl` pass translates internal cells (cells with names that start with `$`) to calls of these @@ -755,73 +829,55 @@ constexpr T max(const T &a, const T &b) { // Logic operations template<size_t BitsY, size_t BitsA> -value<BitsY> not_u(const value<BitsA> &a) { - return a.template zcast<BitsY>().bit_not(); -} - -template<size_t BitsY, size_t BitsA> -value<BitsY> not_s(const value<BitsA> &a) { - return a.template scast<BitsY>().bit_not(); -} - -template<size_t BitsY, size_t BitsA> -value<BitsY> logic_not_u(const value<BitsA> &a) { +value<BitsY> logic_not(const value<BitsA> &a) { return value<BitsY> { a ? 0u : 1u }; } -template<size_t BitsY, size_t BitsA> -value<BitsY> logic_not_s(const value<BitsA> &a) { - return value<BitsY> { a ? 0u : 1u }; +template<size_t BitsY, size_t BitsA, size_t BitsB> +value<BitsY> logic_and(const value<BitsA> &a, const value<BitsB> &b) { + return value<BitsY> { (bool(a) & bool(b)) ? 1u : 0u }; } -template<size_t BitsY, size_t BitsA> -value<BitsY> reduce_and_u(const value<BitsA> &a) { - return value<BitsY> { a.bit_not().is_zero() ? 1u : 0u }; +template<size_t BitsY, size_t BitsA, size_t BitsB> +value<BitsY> logic_or(const value<BitsA> &a, const value<BitsB> &b) { + return value<BitsY> { (bool(a) | bool(b)) ? 1u : 0u }; } +// Reduction operations template<size_t BitsY, size_t BitsA> -value<BitsY> reduce_and_s(const value<BitsA> &a) { +value<BitsY> reduce_and(const value<BitsA> &a) { return value<BitsY> { a.bit_not().is_zero() ? 1u : 0u }; } template<size_t BitsY, size_t BitsA> -value<BitsY> reduce_or_u(const value<BitsA> &a) { - return value<BitsY> { a ? 1u : 0u }; -} - -template<size_t BitsY, size_t BitsA> -value<BitsY> reduce_or_s(const value<BitsA> &a) { +value<BitsY> reduce_or(const value<BitsA> &a) { return value<BitsY> { a ? 1u : 0u }; } template<size_t BitsY, size_t BitsA> -value<BitsY> reduce_xor_u(const value<BitsA> &a) { - return value<BitsY> { (a.ctpop() % 2) ? 1u : 0u }; -} - -template<size_t BitsY, size_t BitsA> -value<BitsY> reduce_xor_s(const value<BitsA> &a) { +value<BitsY> reduce_xor(const value<BitsA> &a) { return value<BitsY> { (a.ctpop() % 2) ? 1u : 0u }; } template<size_t BitsY, size_t BitsA> -value<BitsY> reduce_xnor_u(const value<BitsA> &a) { +value<BitsY> reduce_xnor(const value<BitsA> &a) { return value<BitsY> { (a.ctpop() % 2) ? 0u : 1u }; } template<size_t BitsY, size_t BitsA> -value<BitsY> reduce_xnor_s(const value<BitsA> &a) { - return value<BitsY> { (a.ctpop() % 2) ? 0u : 1u }; +value<BitsY> reduce_bool(const value<BitsA> &a) { + return value<BitsY> { a ? 1u : 0u }; } +// Bitwise operations template<size_t BitsY, size_t BitsA> -value<BitsY> reduce_bool_u(const value<BitsA> &a) { - return value<BitsY> { a ? 1u : 0u }; +value<BitsY> not_u(const value<BitsA> &a) { + return a.template zcast<BitsY>().bit_not(); } template<size_t BitsY, size_t BitsA> -value<BitsY> reduce_bool_s(const value<BitsA> &a) { - return value<BitsY> { a ? 1u : 0u }; +value<BitsY> not_s(const value<BitsA> &a) { + return a.template scast<BitsY>().bit_not(); } template<size_t BitsY, size_t BitsA, size_t BitsB> @@ -865,26 +921,6 @@ value<BitsY> xnor_ss(const value<BitsA> &a, const value<BitsB> &b) { } template<size_t BitsY, size_t BitsA, size_t BitsB> -value<BitsY> logic_and_uu(const value<BitsA> &a, const value<BitsB> &b) { - return value<BitsY> { (bool(a) & bool(b)) ? 1u : 0u }; -} - -template<size_t BitsY, size_t BitsA, size_t BitsB> -value<BitsY> logic_and_ss(const value<BitsA> &a, const value<BitsB> &b) { - return value<BitsY> { (bool(a) & bool(b)) ? 1u : 0u }; -} - -template<size_t BitsY, size_t BitsA, size_t BitsB> -value<BitsY> logic_or_uu(const value<BitsA> &a, const value<BitsB> &b) { - return value<BitsY> { (bool(a) | bool(b)) ? 1u : 0u }; -} - -template<size_t BitsY, size_t BitsA, size_t BitsB> -value<BitsY> logic_or_ss(const value<BitsA> &a, const value<BitsB> &b) { - return value<BitsY> { (bool(a) | bool(b)) ? 1u : 0u }; -} - -template<size_t BitsY, size_t BitsA, size_t BitsB> value<BitsY> shl_uu(const value<BitsA> &a, const value<BitsB> &b) { return a.template zcast<BitsY>().template shl(b); } @@ -921,7 +957,7 @@ value<BitsY> sshr_uu(const value<BitsA> &a, const value<BitsB> &b) { template<size_t BitsY, size_t BitsA, size_t BitsB> value<BitsY> sshr_su(const value<BitsA> &a, const value<BitsB> &b) { - return a.template shr(b).template scast<BitsY>(); + return a.template sshr(b).template scast<BitsY>(); } template<size_t BitsY, size_t BitsA, size_t BitsB> diff --git a/backends/cxxrtl/cxxrtl.cc b/backends/cxxrtl/cxxrtl_backend.cc index 0cceecbba..4c04a2f14 100644 --- a/backends/cxxrtl/cxxrtl.cc +++ b/backends/cxxrtl/cxxrtl_backend.cc @@ -192,6 +192,13 @@ bool is_binary_cell(RTLIL::IdString type) ID($add), ID($sub), ID($mul), ID($div), ID($mod)); } +bool is_extending_cell(RTLIL::IdString type) +{ + return !type.in( + ID($logic_not), ID($logic_and), ID($logic_or), + ID($reduce_and), ID($reduce_or), ID($reduce_xor), ID($reduce_xnor), ID($reduce_bool)); +} + bool is_elidable_cell(RTLIL::IdString type) { return is_unary_cell(type) || is_binary_cell(type) || type.in( @@ -359,10 +366,10 @@ struct FlowGraph { // // eliminating the unnecessary delta cycle. Conceptually, the CELL_SYNC node type is a series of // connections of the form `connect \lhs \cell.\sync_output`; the right-hand side of these is not - // as a wire in RTLIL. If it was expressible, then `\cell.\sync_output` would have a sync def, - // and this node would be an ordinary CONNECT node, with `\lhs` having a comb def. Because it isn't, - // a special node type is used, the right-hand side does not appear anywhere, and the left-hand - // side has a comb def. + // expressible as a wire in RTLIL. If it was expressible, then `\cell.\sync_output` would have + // a sync def, and this node would be an ordinary CONNECT node, with `\lhs` having a comb def. + // Because it isn't, a special node type is used, the right-hand side does not appear anywhere, + // and the left-hand side has a comb def. for (auto conn : cell->connections()) if (cell->output(conn.first)) if (is_cxxrtl_sync_port(cell, conn.first)) { @@ -467,14 +474,16 @@ std::vector<std::string> split_by(const std::string &str, const std::string &sep std::vector<std::string> result; size_t prev = 0; while (true) { - size_t curr = str.find_first_of(sep, prev + 1); - if (curr > str.size()) - curr = str.size(); - if (curr > prev + 1) - result.push_back(str.substr(prev, curr - prev)); - if (curr == str.size()) + size_t curr = str.find_first_of(sep, prev); + if (curr == std::string::npos) { + std::string part = str.substr(prev); + if (!part.empty()) result.push_back(part); break; - prev = curr; + } else { + std::string part = str.substr(prev, curr - prev); + if (!part.empty()) result.push_back(part); + prev = curr + 1; + } } return result; } @@ -502,6 +511,15 @@ std::string escape_cxx_string(const std::string &input) return output; } +template<class T> +std::string get_hdl_name(T *object) +{ + if (object->has_attribute(ID::hdlname)) + return object->get_string_attribute(ID::hdlname); + else + return object->name.str().substr(1); +} + struct CxxrtlWorker { bool split_intf = false; std::string intf_filename; @@ -516,6 +534,8 @@ struct CxxrtlWorker { bool run_proc_flatten = false; bool max_opt_level = false; + bool debug_info = false; + std::ostringstream f; std::string indent; int temporary = 0; @@ -528,6 +548,8 @@ struct CxxrtlWorker { dict<const RTLIL::Wire*, FlowGraph::Node> elided_wires; dict<const RTLIL::Module*, std::vector<FlowGraph::Node>> schedule; pool<const RTLIL::Wire*> localized_wires; + dict<const RTLIL::Wire*, const RTLIL::Wire*> debug_alias_wires; + dict<const RTLIL::Wire*, RTLIL::Const> debug_const_wires; dict<const RTLIL::Module*, pool<std::string>> blackbox_specializations; dict<const RTLIL::Module*, bool> eval_converges; @@ -894,17 +916,19 @@ struct CxxrtlWorker { { // Unary cells if (is_unary_cell(cell->type)) { - f << cell->type.substr(1) << '_' << - (cell->getParam(ID::A_SIGNED).as_bool() ? 's' : 'u') << - "<" << cell->getParam(ID::Y_WIDTH).as_int() << ">("; + f << cell->type.substr(1); + if (is_extending_cell(cell->type)) + f << '_' << (cell->getParam(ID::A_SIGNED).as_bool() ? 's' : 'u'); + f << "<" << cell->getParam(ID::Y_WIDTH).as_int() << ">("; dump_sigspec_rhs(cell->getPort(ID::A)); f << ")"; // Binary cells } else if (is_binary_cell(cell->type)) { - f << cell->type.substr(1) << '_' << - (cell->getParam(ID::A_SIGNED).as_bool() ? 's' : 'u') << - (cell->getParam(ID::B_SIGNED).as_bool() ? 's' : 'u') << - "<" << cell->getParam(ID::Y_WIDTH).as_int() << ">("; + f << cell->type.substr(1); + if (is_extending_cell(cell->type)) + f << '_' << (cell->getParam(ID::A_SIGNED).as_bool() ? 's' : 'u') << + (cell->getParam(ID::B_SIGNED).as_bool() ? 's' : 'u'); + f << "<" << cell->getParam(ID::Y_WIDTH).as_int() << ">("; dump_sigspec_rhs(cell->getPort(ID::A)); f << ", "; dump_sigspec_rhs(cell->getPort(ID::B)); @@ -1593,6 +1617,61 @@ struct CxxrtlWorker { dec_indent(); } + void dump_debug_info_method(RTLIL::Module *module) + { + size_t count_const_wires = 0; + size_t count_alias_wires = 0; + size_t count_member_wires = 0; + size_t count_skipped_wires = 0; + inc_indent(); + f << indent << "assert(path.empty() || path[path.size() - 1] == ' ');\n"; + for (auto wire : module->wires()) { + if (wire->name[0] != '\\') + continue; + if (debug_const_wires.count(wire)) { + // Wire tied to a constant + f << indent << "static const value<" << wire->width << "> const_" << mangle(wire) << " = "; + dump_const(debug_const_wires[wire]); + f << ";\n"; + f << indent << "items.emplace(path + " << escape_cxx_string(get_hdl_name(wire)); + f << ", debug_item(const_" << mangle(wire) << "));\n"; + count_const_wires++; + } else if (debug_alias_wires.count(wire)) { + // Alias of a member wire + f << indent << "items.emplace(path + " << escape_cxx_string(get_hdl_name(wire)); + f << ", debug_item(" << mangle(debug_alias_wires[wire]) << "));\n"; + count_alias_wires++; + } else if (!localized_wires.count(wire)) { + // Member wire + f << indent << "items.emplace(path + " << escape_cxx_string(get_hdl_name(wire)); + f << ", debug_item(" << mangle(wire) << "));\n"; + count_member_wires++; + } else { + count_skipped_wires++; + } + } + for (auto &memory_it : module->memories) { + if (memory_it.first[0] != '\\') + continue; + f << indent << "items.emplace(path + " << escape_cxx_string(get_hdl_name(memory_it.second)); + f << ", debug_item(" << mangle(memory_it.second) << "));\n"; + } + for (auto cell : module->cells()) { + if (is_internal_cell(cell->type)) + continue; + const char *access = is_cxxrtl_blackbox_cell(cell) ? "->" : "."; + f << indent << mangle(cell) << access << "debug_info(items, "; + f << "path + " << escape_cxx_string(get_hdl_name(cell) + ' ') << ");\n"; + } + dec_indent(); + + log_debug("Debug information statistics for module %s:\n", log_id(module)); + log_debug(" Const wires: %zu\n", count_const_wires); + log_debug(" Alias wires: %zu\n", count_alias_wires); + log_debug(" Member wires: %zu\n", count_member_wires); + log_debug(" Other wires: %zu (no debug information)\n", count_skipped_wires); + } + void dump_metadata_map(const dict<RTLIL::IdString, RTLIL::Const> &metadata_map) { if (metadata_map.empty()) { @@ -1641,6 +1720,12 @@ struct CxxrtlWorker { dump_commit_method(module); f << indent << "}\n"; f << "\n"; + if (debug_info) { + f << indent << "void debug_info(debug_items &items, std::string path = \"\") override {\n"; + dump_debug_info_method(module); + f << indent << "}\n"; + f << "\n"; + } f << indent << "static std::unique_ptr<" << mangle(module); f << template_params(module, /*is_decl=*/false) << "> "; f << "create(std::string name, metadata_map parameters, metadata_map attributes);\n"; @@ -1689,7 +1774,7 @@ struct CxxrtlWorker { if (cell_module->get_bool_attribute(ID(cxxrtl_blackbox))) { f << indent << "std::unique_ptr<" << mangle(cell_module) << template_args(cell) << "> "; f << mangle(cell) << " = " << mangle(cell_module) << template_args(cell); - f << "::create(" << escape_cxx_string(cell->name.str()) << ", "; + f << "::create(" << escape_cxx_string(get_hdl_name(cell)) << ", "; dump_metadata_map(cell->parameters); f << ", "; dump_metadata_map(cell->attributes); @@ -1703,6 +1788,8 @@ struct CxxrtlWorker { f << "\n"; f << indent << "bool eval() override;\n"; f << indent << "bool commit() override;\n"; + if (debug_info) + f << indent << "void debug_info(debug_items &items, std::string path = \"\") override;\n"; dec_indent(); f << indent << "}; // struct " << mangle(module) << "\n"; f << "\n"; @@ -1721,10 +1808,17 @@ struct CxxrtlWorker { dump_commit_method(module); f << indent << "}\n"; f << "\n"; + if (debug_info) { + f << indent << "void " << mangle(module) << "::debug_info(debug_items &items, std::string path) {\n"; + dump_debug_info_method(module); + f << indent << "}\n"; + f << "\n"; + } } void dump_design(RTLIL::Design *design) { + RTLIL::Module *top_module = nullptr; std::vector<RTLIL::Module*> modules; TopoSort<RTLIL::Module*> topo_design; for (auto module : design->modules()) { @@ -1734,6 +1828,8 @@ struct CxxrtlWorker { modules.push_back(module); // cxxrtl blackboxes first if (module->get_blackbox_attribute() || module->get_bool_attribute(ID(cxxrtl_blackbox))) continue; + if (module->get_bool_attribute(ID::top)) + top_module = module; topo_design.node(module); for (auto cell : module->cells()) { @@ -1755,6 +1851,25 @@ struct CxxrtlWorker { f << "#ifndef " << include_guard << "\n"; f << "#define " << include_guard << "\n"; f << "\n"; + if (top_module != nullptr && debug_info) { + f << "#include <backends/cxxrtl/cxxrtl_capi.h>\n"; + f << "\n"; + f << "#ifdef __cplusplus\n"; + f << "extern \"C\" {\n"; + f << "#endif\n"; + f << "\n"; + f << "cxxrtl_toplevel " << design_ns << "_create();\n"; + f << "\n"; + f << "#ifdef __cplusplus\n"; + f << "}\n"; + f << "#endif\n"; + f << "\n"; + } else { + f << "// The CXXRTL C API is not available because the design is built without debug information.\n"; + f << "\n"; + } + f << "#ifdef __cplusplus\n"; + f << "\n"; f << "#include <backends/cxxrtl/cxxrtl.h>\n"; f << "\n"; f << "using namespace cxxrtl;\n"; @@ -1765,6 +1880,8 @@ struct CxxrtlWorker { dump_module_intf(module); f << "} // namespace " << design_ns << "\n"; f << "\n"; + f << "#endif // __cplusplus\n"; + f << "\n"; f << "#endif\n"; *intf_f << f.str(); f.str(""); } @@ -1774,6 +1891,15 @@ struct CxxrtlWorker { else f << "#include <backends/cxxrtl/cxxrtl.h>\n"; f << "\n"; + f << "#if defined(CXXRTL_INCLUDE_CAPI_IMPL) || \\\n"; + f << " defined(CXXRTL_INCLUDE_VCD_CAPI_IMPL)\n"; + f << "#include <backends/cxxrtl/cxxrtl_capi.cc>\n"; + f << "#endif\n"; + f << "\n"; + f << "#if defined(CXXRTL_INCLUDE_VCD_CAPI_IMPL)\n"; + f << "#include <backends/cxxrtl/cxxrtl_vcd_capi.cc>\n"; + f << "#endif\n"; + f << "\n"; f << "using namespace cxxrtl_yosys;\n"; f << "\n"; f << "namespace " << design_ns << " {\n"; @@ -1784,6 +1910,17 @@ struct CxxrtlWorker { dump_module_impl(module); } f << "} // namespace " << design_ns << "\n"; + f << "\n"; + if (top_module != nullptr && debug_info) { + f << "cxxrtl_toplevel " << design_ns << "_create() {\n"; + inc_indent(); + f << indent << "return new _cxxrtl_toplevel { "; + f << "std::make_unique<" << design_ns << "::" << mangle(top_module) << ">()"; + f << " };\n"; + dec_indent(); + f << "}\n"; + } + *impl_f << f.str(); f.str(""); } @@ -2044,6 +2181,44 @@ struct CxxrtlWorker { } eval_converges[module] = feedback_wires.empty() && buffered_wires.empty(); + + if (debug_info) { + // Find wires that alias other wires or are tied to a constant; debug information can be enriched with these + // at essentially zero additional cost. + // + // Note that the information collected here can't be used for optimizing the netlist: debug information queries + // are pure and run on a design in a stable state, which allows assumptions that do not otherwise hold. + for (auto wire : module->wires()) { + if (wire->name[0] != '\\') + continue; + if (!localized_wires[wire]) + continue; + const RTLIL::Wire *wire_it = wire; + while (1) { + if (!(flow.wire_def_elidable.count(wire_it) && flow.wire_def_elidable[wire_it])) + break; // not an alias: complex def + log_assert(flow.wire_comb_defs[wire_it].size() == 1); + FlowGraph::Node *node = *flow.wire_comb_defs[wire_it].begin(); + if (node->type != FlowGraph::Node::Type::CONNECT) + break; // not an alias: def by cell + RTLIL::SigSpec rhs_sig = node->connect.second; + if (rhs_sig.is_wire()) { + RTLIL::Wire *rhs_wire = rhs_sig.as_wire(); + if (localized_wires[rhs_wire]) { + wire_it = rhs_wire; // maybe an alias + } else { + debug_alias_wires[wire] = rhs_wire; // is an alias + break; + } + } else if (rhs_sig.is_fully_const()) { + debug_const_wires[wire] = rhs_sig.as_const(); // is a const + break; + } else { + break; // not an alias: complex rhs + } + } + } + } } if (has_feedback_arcs || has_buffered_wires) { // Although both non-feedback buffered combinatorial wires and apparent feedback wires may be eliminated @@ -2120,6 +2295,7 @@ struct CxxrtlWorker { struct CxxrtlBackend : public Backend { static const int DEFAULT_OPT_LEVEL = 5; + static const int DEFAULT_DEBUG_LEVEL = 1; CxxrtlBackend() : Backend("cxxrtl", "convert design to C++ RTL simulation") { } void help() YS_OVERRIDE @@ -2313,10 +2489,23 @@ struct CxxrtlBackend : public Backend { log(" -O5\n"); log(" like -O4, and run `proc; flatten` first.\n"); log("\n"); + log(" -g <level>\n"); + log(" set the debug level. the default is -g%d. higher debug levels provide\n", DEFAULT_DEBUG_LEVEL); + log(" more visibility and generate more code, but do not pessimize evaluation.\n"); + log("\n"); + log(" -g0\n"); + log(" no debug information.\n"); + log("\n"); + log(" -g1\n"); + log(" debug information for non-optimized public wires. this also makes it\n"); + log(" possible to use the C API.\n"); + log("\n"); } + void execute(std::ostream *&f, std::string filename, std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE { int opt_level = DEFAULT_OPT_LEVEL; + int debug_level = DEFAULT_DEBUG_LEVEL; CxxrtlWorker worker; log_header(design, "Executing CXXRTL backend.\n"); @@ -2332,6 +2521,14 @@ struct CxxrtlBackend : public Backend { opt_level = std::stoi(args[argidx].substr(2)); continue; } + if (args[argidx] == "-g" && argidx+1 < args.size()) { + debug_level = std::stoi(args[++argidx]); + continue; + } + if (args[argidx].substr(0, 2) == "-g" && args[argidx].size() == 3 && isdigit(args[argidx][2])) { + debug_level = std::stoi(args[argidx].substr(2)); + continue; + } if (args[argidx] == "-header") { worker.split_intf = true; continue; @@ -2368,6 +2565,17 @@ struct CxxrtlBackend : public Backend { log_cmd_error("Invalid optimization level %d.\n", opt_level); } + switch (debug_level) { + // the highest level here must match DEFAULT_DEBUG_LEVEL + case 1: + worker.debug_info = true; + YS_FALLTHROUGH + case 0: + break; + default: + log_cmd_error("Invalid debug information level %d.\n", debug_level); + } + std::ofstream intf_f; if (worker.split_intf) { if (filename == "<stdout>") diff --git a/backends/cxxrtl/cxxrtl_capi.cc b/backends/cxxrtl/cxxrtl_capi.cc new file mode 100644 index 000000000..489d72da5 --- /dev/null +++ b/backends/cxxrtl/cxxrtl_capi.cc @@ -0,0 +1,60 @@ +/* + * yosys -- Yosys Open SYnthesis Suite + * + * Copyright (C) 2020 whitequark <whitequark@whitequark.org> + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + * + */ + +// This file is a part of the CXXRTL C API. It should be used together with `cxxrtl_capi.h`. + +#include <backends/cxxrtl/cxxrtl.h> +#include <backends/cxxrtl/cxxrtl_capi.h> + +struct _cxxrtl_handle { + std::unique_ptr<cxxrtl::module> module; + cxxrtl::debug_items objects; +}; + +// Private function for use by other units of the C API. +const cxxrtl::debug_items &cxxrtl_debug_items_from_handle(cxxrtl_handle handle) { + return handle->objects; +} + +cxxrtl_handle cxxrtl_create(cxxrtl_toplevel design) { + cxxrtl_handle handle = new _cxxrtl_handle; + handle->module = std::move(design->module); + handle->module->debug_info(handle->objects); + delete design; + return handle; +} + +void cxxrtl_destroy(cxxrtl_handle handle) { + delete handle; +} + +size_t cxxrtl_step(cxxrtl_handle handle) { + return handle->module->step(); +} + +cxxrtl_object *cxxrtl_get(cxxrtl_handle handle, const char *name) { + if (handle->objects.count(name) > 0) + return static_cast<cxxrtl_object*>(&handle->objects.at(name)); + return nullptr; +} + +void cxxrtl_enum(cxxrtl_handle handle, void *data, + void (*callback)(void *data, const char *name, cxxrtl_object *object)) { + for (auto &it : handle->objects) + callback(data, it.first.c_str(), static_cast<cxxrtl_object*>(&it.second)); +} diff --git a/backends/cxxrtl/cxxrtl_capi.h b/backends/cxxrtl/cxxrtl_capi.h new file mode 100644 index 000000000..46aa662b2 --- /dev/null +++ b/backends/cxxrtl/cxxrtl_capi.h @@ -0,0 +1,152 @@ +/* + * yosys -- Yosys Open SYnthesis Suite + * + * Copyright (C) 2020 whitequark <whitequark@whitequark.org> + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + * + */ + +#ifndef CXXRTL_CAPI_H +#define CXXRTL_CAPI_H + +// This file is a part of the CXXRTL C API. It should be used together with `cxxrtl_capi.cc`. +// +// The CXXRTL C API makes it possible to drive CXXRTL designs using C or any other language that +// supports the C ABI, for example, Python. It does not provide a way to implement black boxes. + +#include <stddef.h> +#include <stdint.h> + +#ifdef __cplusplus +extern "C" { +#endif + +// Opaque reference to a design toplevel. +// +// A design toplevel can only be used to create a design handle. +typedef struct _cxxrtl_toplevel *cxxrtl_toplevel; + +// The constructor for a design toplevel is provided as a part of generated code for that design. +// Its prototype matches: +// +// cxxrtl_toplevel <design-name>_create(); + +// Opaque reference to a design handle. +// +// A design handle is required by all operations in the C API. +typedef struct _cxxrtl_handle *cxxrtl_handle; + +// Create a design handle from a design toplevel. +// +// The `design` is consumed by this operation and cannot be used afterwards. +cxxrtl_handle cxxrtl_create(cxxrtl_toplevel design); + +// Release all resources used by a design and its handle. +void cxxrtl_destroy(cxxrtl_handle handle); + +// Simulate the design to a fixed point. +// +// Returns the number of delta cycles. +size_t cxxrtl_step(cxxrtl_handle handle); + +// Type of a simulated object. +enum cxxrtl_type { + // Values correspond to singly buffered netlist nodes, i.e. nodes driven exclusively by + // combinatorial cells, or toplevel input nodes. + // + // Values can be inspected via the `curr` pointer. If the `next` pointer is NULL, the value is + // driven by a constant and can never be modified. Otherwise, the value can be modified through + // the `next` pointer (which is equal to `curr` if not NULL). Note that changes to the bits + // driven by combinatorial cells will be ignored. + // + // Values always have depth 1. + CXXRTL_VALUE = 0, + + // Wires correspond to doubly buffered netlist nodes, i.e. nodes driven, at least in part, by + // storage cells, or by combinatorial cells that are a part of a feedback path. + // + // Wires can be inspected via the `curr` pointer and modified via the `next` pointer (which are + // distinct for wires). Note that changes to the bits driven by combinatorial cells will be + // ignored. + // + // Wires always have depth 1. + CXXRTL_WIRE = 1, + + // Memories correspond to memory cells. + // + // Memories can be inspected and modified via the `curr` pointer. Due to a limitation of this + // API, memories cannot yet be modified in a guaranteed race-free way, and the `next` pointer is + // always NULL. + CXXRTL_MEMORY = 2, + + // More object types will be added in the future, but the existing ones will never change. +}; + +// Description of a simulated object. +// +// The `data` array can be accessed directly to inspect and, if applicable, modify the bits +// stored in the object. +struct cxxrtl_object { + // Type of the object. + // + // All objects have the same memory layout determined by `width` and `depth`, but the type + // determines all other properties of the object. + uint32_t type; // actually `enum cxxrtl_type` + + // Width of the object in bits. + size_t width; + + // Depth of the object. Only meaningful for memories; for other objects, always 1. + size_t depth; + + // Bits stored in the object, as 32-bit chunks, least significant bits first. + // + // The width is rounded up to a multiple of 32; the padding bits are always set to 0 by + // the simulation code, and must be always written as 0 when modified by user code. + // In memories, every element is stored contiguously. Therefore, the total number of chunks + // in any object is `((width + 31) / 32) * depth`. + // + // To allow the simulation to be partitioned into multiple independent units communicating + // through wires, the bits are double buffered. To avoid race conditions, user code should + // always read from `curr` and write to `next`. The `curr` pointer is always valid; for objects + // that cannot be modified, or cannot be modified in a race-free way, `next` is NULL. + uint32_t *curr; + uint32_t *next; + + // More description fields will be added in the future, but the existing ones will never change. +}; + +// Retrieve description of a simulated object. +// +// The `name` is the full hierarchical name of the object in the Yosys notation, where public names +// have a `\` prefix and hierarchy levels are separated by single spaces. For example, if +// the top-level module instantiates a module `foo`, which in turn contains a wire `bar`, the full +// hierarchical name is `\foo \bar`. +// +// Returns the object if it was found, NULL otherwise. The returned value is valid until the design +// is destroyed. +struct cxxrtl_object *cxxrtl_get(cxxrtl_handle handle, const char *name); + +// Enumerate simulated objects. +// +// For every object in the simulation, `callback` is called with the provided `data`, the full +// hierarchical name of the object (see `cxxrtl_get` for details), and the object description. +// The provided `name` and `object` values are valid until the design is destroyed. +void cxxrtl_enum(cxxrtl_handle handle, void *data, + void (*callback)(void *data, const char *name, struct cxxrtl_object *object)); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/backends/cxxrtl/cxxrtl_vcd.h b/backends/cxxrtl/cxxrtl_vcd.h new file mode 100644 index 000000000..f6b78bbf7 --- /dev/null +++ b/backends/cxxrtl/cxxrtl_vcd.h @@ -0,0 +1,224 @@ +/* + * yosys -- Yosys Open SYnthesis Suite + * + * Copyright (C) 2020 whitequark <whitequark@whitequark.org> + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + * + */ + +#ifndef CXXRTL_VCD_H +#define CXXRTL_VCD_H + +#include <backends/cxxrtl/cxxrtl.h> + +namespace cxxrtl { + +class vcd_writer { + struct variable { + size_t ident; + size_t width; + chunk_t *curr; + size_t prev_off; + }; + + std::vector<std::string> current_scope; + std::vector<variable> variables; + std::vector<chunk_t> cache; + std::map<chunk_t*, size_t> aliases; + bool streaming = false; + + void emit_timescale(unsigned number, const std::string &unit) { + assert(!streaming); + assert(number == 1 || number == 10 || number == 100); + assert(unit == "s" || unit == "ms" || unit == "us" || + unit == "ns" || unit == "ps" || unit == "fs"); + buffer += "$timescale " + std::to_string(number) + " " + unit + " $end\n"; + } + + void emit_scope(const std::vector<std::string> &scope) { + assert(!streaming); + while (current_scope.size() > scope.size() || + (current_scope.size() > 0 && + current_scope[current_scope.size() - 1] != scope[current_scope.size() - 1])) { + buffer += "$upscope $end\n"; + current_scope.pop_back(); + } + while (current_scope.size() < scope.size()) { + buffer += "$scope module " + scope[current_scope.size()] + " $end\n"; + current_scope.push_back(scope[current_scope.size()]); + } + } + + void emit_ident(size_t ident) { + do { + buffer += '!' + ident % 94; // "base94" + ident /= 94; + } while (ident != 0); + } + + void emit_var(const variable &var, const std::string &type, const std::string &name) { + assert(!streaming); + buffer += "$var " + type + " " + std::to_string(var.width) + " "; + emit_ident(var.ident); + buffer += " " + name + " $end\n"; + } + + void emit_enddefinitions() { + assert(!streaming); + buffer += "$enddefinitions $end\n"; + streaming = true; + } + + void emit_time(uint64_t timestamp) { + assert(streaming); + buffer += "#" + std::to_string(timestamp) + "\n"; + } + + void emit_scalar(const variable &var) { + assert(streaming); + assert(var.width == 1); + buffer += (*var.curr ? '1' : '0'); + emit_ident(var.ident); + buffer += '\n'; + } + + void emit_vector(const variable &var) { + assert(streaming); + buffer += 'b'; + for (size_t bit = var.width - 1; bit != (size_t)-1; bit--) { + bool bit_curr = var.curr[bit / (8 * sizeof(chunk_t))] & (1 << (bit % (8 * sizeof(chunk_t)))); + buffer += (bit_curr ? '1' : '0'); + } + buffer += ' '; + emit_ident(var.ident); + buffer += '\n'; + } + + const variable ®ister_variable(size_t width, chunk_t *curr, bool immutable = false) { + if (aliases.count(curr)) { + return variables[aliases[curr]]; + } else { + const size_t chunks = (width + (sizeof(chunk_t) * 8 - 1)) / (sizeof(chunk_t) * 8); + aliases[curr] = variables.size(); + if (immutable) { + variables.emplace_back(variable { variables.size(), width, curr, (size_t)-1 }); + } else { + variables.emplace_back(variable { variables.size(), width, curr, cache.size() }); + cache.insert(cache.end(), &curr[0], &curr[chunks]); + } + return variables.back(); + } + } + + bool test_variable(const variable &var) { + if (var.prev_off == (size_t)-1) + return false; // immutable + const size_t chunks = (var.width + (sizeof(chunk_t) * 8 - 1)) / (sizeof(chunk_t) * 8); + if (std::equal(&var.curr[0], &var.curr[chunks], &cache[var.prev_off])) { + return false; + } else { + std::copy(&var.curr[0], &var.curr[chunks], &cache[var.prev_off]); + return true; + } + } + + static std::vector<std::string> split_hierarchy(const std::string &hier_name) { + std::vector<std::string> hierarchy; + size_t prev = 0; + while (true) { + size_t curr = hier_name.find_first_of(' ', prev); + if (curr == std::string::npos) { + hierarchy.push_back(hier_name.substr(prev)); + break; + } else { + hierarchy.push_back(hier_name.substr(prev, curr - prev)); + prev = curr + 1; + } + } + return hierarchy; + } + +public: + std::string buffer; + + void timescale(unsigned number, const std::string &unit) { + emit_timescale(number, unit); + } + + void add(const std::string &hier_name, const debug_item &item) { + std::vector<std::string> scope = split_hierarchy(hier_name); + std::string name = scope.back(); + scope.pop_back(); + + emit_scope(scope); + switch (item.type) { + // Not the best naming but oh well... + case debug_item::VALUE: + emit_var(register_variable(item.width, item.curr, /*immutable=*/item.next == nullptr), "wire", name); + break; + case debug_item::WIRE: + emit_var(register_variable(item.width, item.curr), "reg", name); + break; + case debug_item::MEMORY: { + const size_t stride = (item.width + (sizeof(chunk_t) * 8 - 1)) / (sizeof(chunk_t) * 8); + for (size_t index = 0; index < item.depth; index++) { + chunk_t *nth_curr = &item.curr[stride * index]; + std::string nth_name = name + '[' + std::to_string(index) + ']'; + emit_var(register_variable(item.width, nth_curr), "reg", nth_name); + } + break; + } + } + } + + template<class Filter> + void add(const debug_items &items, const Filter &filter) { + // `debug_items` is a map, so the items are already sorted in an order optimal for emitting + // VCD scope sections. + for (auto &it : items) + if (filter(it.first, it.second)) + add(it.first, it.second); + } + + void add(const debug_items &items) { + this->template add(items, [](const std::string &, const debug_item &) { + return true; + }); + } + + void add_without_memories(const debug_items &items) { + this->template add(items, [](const std::string &, const debug_item &item) { + return item.type == debug_item::VALUE || item.type == debug_item::WIRE; + }); + } + + void sample(uint64_t timestamp) { + bool first_sample = !streaming; + if (first_sample) { + emit_scope({}); + emit_enddefinitions(); + } + emit_time(timestamp); + for (auto var : variables) + if (test_variable(var) || first_sample) { + if (var.width == 1) + emit_scalar(var); + else + emit_vector(var); + } + } +}; + +} + +#endif diff --git a/backends/cxxrtl/cxxrtl_vcd_capi.cc b/backends/cxxrtl/cxxrtl_vcd_capi.cc new file mode 100644 index 000000000..52a9198b8 --- /dev/null +++ b/backends/cxxrtl/cxxrtl_vcd_capi.cc @@ -0,0 +1,83 @@ +/* + * yosys -- Yosys Open SYnthesis Suite + * + * Copyright (C) 2020 whitequark <whitequark@whitequark.org> + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + * + */ + +// This file is a part of the CXXRTL C API. It should be used together with `cxxrtl_vcd_capi.h`. + +#include <backends/cxxrtl/cxxrtl_vcd.h> +#include <backends/cxxrtl/cxxrtl_vcd_capi.h> + +extern const cxxrtl::debug_items &cxxrtl_debug_items_from_handle(cxxrtl_handle handle); + +struct _cxxrtl_vcd { + cxxrtl::vcd_writer writer; + bool flush = false; +}; + +cxxrtl_vcd cxxrtl_vcd_create() { + return new _cxxrtl_vcd; +} + +void cxxrtl_vcd_destroy(cxxrtl_vcd vcd) { + delete vcd; +} + +void cxxrtl_vcd_timescale(cxxrtl_vcd vcd, int number, const char *unit) { + vcd->writer.timescale(number, unit); +} + +void cxxrtl_vcd_add(cxxrtl_vcd vcd, const char *name, cxxrtl_object *object) { + // Note the copy. We don't know whether `object` came from a design (in which case it is + // an instance of `debug_item`), or from user code (in which case it is an instance of + // `cxxrtl_object`), so casting the pointer wouldn't be safe. + vcd->writer.add(name, cxxrtl::debug_item(*object)); +} + +void cxxrtl_vcd_add_from(cxxrtl_vcd vcd, cxxrtl_handle handle) { + vcd->writer.add(cxxrtl_debug_items_from_handle(handle)); +} + +void cxxrtl_vcd_add_from_if(cxxrtl_vcd vcd, cxxrtl_handle handle, void *data, + int (*filter)(void *data, const char *name, + const cxxrtl_object *object)) { + vcd->writer.add(cxxrtl_debug_items_from_handle(handle), + [=](const std::string &name, const cxxrtl::debug_item &item) { + return filter(data, name.c_str(), static_cast<const cxxrtl_object*>(&item)); + }); +} + +void cxxrtl_vcd_add_from_without_memories(cxxrtl_vcd vcd, cxxrtl_handle handle) { + vcd->writer.add_without_memories(cxxrtl_debug_items_from_handle(handle)); +} + +void cxxrtl_vcd_sample(cxxrtl_vcd vcd, uint64_t time) { + if (vcd->flush) { + vcd->writer.buffer.clear(); + vcd->flush = false; + } + vcd->writer.sample(time); +} + +void cxxrtl_vcd_read(cxxrtl_vcd vcd, const char **data, size_t *size) { + if (vcd->flush) { + vcd->writer.buffer.clear(); + vcd->flush = false; + } + *data = vcd->writer.buffer.c_str(); + *size = vcd->writer.buffer.size(); + vcd->flush = true; +} diff --git a/backends/cxxrtl/cxxrtl_vcd_capi.h b/backends/cxxrtl/cxxrtl_vcd_capi.h new file mode 100644 index 000000000..6a7fb9f47 --- /dev/null +++ b/backends/cxxrtl/cxxrtl_vcd_capi.h @@ -0,0 +1,107 @@ +/* + * yosys -- Yosys Open SYnthesis Suite + * + * Copyright (C) 2020 whitequark <whitequark@whitequark.org> + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + * + */ + +#ifndef CXXRTL_VCD_CAPI_H +#define CXXRTL_VCD_CAPI_H + +// This file is a part of the CXXRTL C API. It should be used together with `cxxrtl_vcd_capi.cc`. +// +// The CXXRTL C API for VCD writing makes it possible to insert virtual probes into designs and +// dump waveforms to Value Change Dump files. + +#include <stddef.h> +#include <stdint.h> + +#include <backends/cxxrtl/cxxrtl_capi.h> + +#ifdef __cplusplus +extern "C" { +#endif + +// Opaque reference to a VCD writer. +typedef struct _cxxrtl_vcd *cxxrtl_vcd; + +// Create a VCD writer. +cxxrtl_vcd cxxrtl_vcd_create(); + +// Release all resources used by a VCD writer. +void cxxrtl_vcd_destroy(cxxrtl_vcd vcd); + +// Set VCD timescale. +// +// The `number` must be 1, 10, or 100, and the `unit` must be one of `"s"`, `"ms"`, `"us"`, `"ns"`, +// `"ps"`, or `"fs"`. +// +// Timescale can only be set before the first call to `cxxrtl_vcd_sample`. +void cxxrtl_vcd_timescale(cxxrtl_vcd vcd, int number, const char *unit); + +// Schedule a specific CXXRTL object to be sampled. +// +// The `name` is a full hierarchical name as described for `cxxrtl_get`; it does not need to match +// the original name of `object`, if any. The `object` must outlive the VCD writer, but there are +// no other requirements; if desired, it can be provided by user code, rather than come from +// a design. +// +// Objects can only be scheduled before the first call to `cxxrtl_vcd_sample`. +void cxxrtl_vcd_add(cxxrtl_vcd vcd, const char *name, struct cxxrtl_object *object); + +// Schedule all CXXRTL objects in a simulation. +// +// The design `handle` must outlive the VCD writer. +// +// Objects can only be scheduled before the first call to `cxxrtl_vcd_sample`. +void cxxrtl_vcd_add_from(cxxrtl_vcd vcd, cxxrtl_handle handle); + +// Schedule CXXRTL objects in a simulation that match a given predicate. +// +// For every object in the simulation, `filter` is called with the provided `data`, the full +// hierarchical name of the object (see `cxxrtl_get` for details), and the object description. +// The object will be sampled if the predicate returns a non-zero value. +// +// Objects can only be scheduled before the first call to `cxxrtl_vcd_sample`. +void cxxrtl_vcd_add_from_if(cxxrtl_vcd vcd, cxxrtl_handle handle, void *data, + int (*filter)(void *data, const char *name, + const struct cxxrtl_object *object)); + +// Schedule all CXXRTL objects in a simulation except for memories. +// +// The design `handle` must outlive the VCD writer. +// +// Objects can only be scheduled before the first call to `cxxrtl_vcd_sample`. +void cxxrtl_vcd_add_from_without_memories(cxxrtl_vcd vcd, cxxrtl_handle handle); + +// Sample all scheduled objects. +// +// First, `time` is written to the internal buffer. Second, the values of every signal changed since +// the previous call to `cxxrtl_vcd_sample` (all values if this is the first call) are written to +// the internal buffer. The contents of the buffer can be retrieved with `cxxrtl_vcd_read`. +void cxxrtl_vcd_sample(cxxrtl_vcd vcd, uint64_t time); + +// Retrieve buffered VCD data. +// +// The pointer to the start of the next chunk of VCD data is assigned to `*data`, and the length +// of that chunk is assigned to `*size`. The pointer to the data is valid until the next call to +// `cxxrtl_vcd_sample` or `cxxrtl_vcd_read`. Once all of the buffered data has been retrieved, +// this function will always return zero sized chunks. +void cxxrtl_vcd_read(cxxrtl_vcd vcd, const char **data, size_t *size); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/backends/smt2/smtio.py b/backends/smt2/smtio.py index 9f7c8c6d9..72ab39d39 100644 --- a/backends/smt2/smtio.py +++ b/backends/smt2/smtio.py @@ -39,7 +39,7 @@ if os.name == "posix": smtio_stacksize = 128 * 1024 * 1024 if os.uname().sysname == "Darwin": # MacOS has rather conservative stack limits - smtio_stacksize = 16 * 1024 * 1024 + smtio_stacksize = 8 * 1024 * 1024 if current_rlimit_stack[1] != resource.RLIM_INFINITY: smtio_stacksize = min(smtio_stacksize, current_rlimit_stack[1]) if current_rlimit_stack[0] < smtio_stacksize: diff --git a/frontends/ast/simplify.cc b/frontends/ast/simplify.cc index 1d80a5dc4..5f026dfed 100644 --- a/frontends/ast/simplify.cc +++ b/frontends/ast/simplify.cc @@ -250,7 +250,37 @@ static AstNode *make_range(int left, int right, bool is_signed = false) return range; } -int size_packed_struct(AstNode *snode, int base_offset) +static int range_width(AstNode *node, AstNode *rnode) +{ + log_assert(rnode->type==AST_RANGE); + if (!rnode->range_valid) { + log_file_error(node->filename, node->location.first_line, "Size must be constant in packed struct/union member %s\n", node->str.c_str()); + + } + // note: range swapping has already been checked for + return rnode->range_left - rnode->range_right + 1; +} + +[[noreturn]] static void struct_array_packing_error(AstNode *node) +{ + log_file_error(node->filename, node->location.first_line, "Unpacked array in packed struct/union member %s\n", node->str.c_str()); +} + +static void save_struct_array_width(AstNode *node, int width) +{ + // stash the stride for the array + node->multirange_dimensions.push_back(width); + +} + +static int get_struct_array_width(AstNode *node) +{ + // the stride for the array, 1 if not an array + return (node->multirange_dimensions.empty() ? 1 : node->multirange_dimensions.back()); + +} + +static int size_packed_struct(AstNode *snode, int base_offset) { // Struct members will be laid out in the structure contiguously from left to right. // Union members all have zero offset from the start of the union. @@ -268,10 +298,40 @@ int size_packed_struct(AstNode *snode, int base_offset) } else { log_assert(node->type == AST_STRUCT_ITEM); - if (node->children.size() == 1 && node->children[0]->type == AST_RANGE) { + if (node->children.size() > 0 && node->children[0]->type == AST_RANGE) { + // member width e.g. bit [7:0] a + width = range_width(node, node->children[0]); + if (node->children.size() == 2) { + if (node->children[1]->type == AST_RANGE) { + // unpacked array e.g. bit [63:0] a [0:3] + auto rnode = node->children[1]; + int array_count = range_width(node, rnode); + if (array_count == 1) { + // C-type array size e.g. bit [63:0] a [4] + array_count = rnode->range_left; + } + save_struct_array_width(node, width); + width *= array_count; + } + else { + // array element must be single bit for a packed array + struct_array_packing_error(node); + } + } + // range nodes are now redundant + node->children.clear(); + } + else if (node->children.size() == 1 && node->children[0]->type == AST_MULTIRANGE) { + // packed 2D array, e.g. bit [3:0][63:0] a auto rnode = node->children[0]; - width = (rnode->range_swapped ? rnode->range_right - rnode->range_left : - rnode->range_left - rnode->range_right) + 1; + if (rnode->children.size() != 2) { + // packed arrays can only be 2D + struct_array_packing_error(node); + } + int array_count = range_width(node, rnode->children[0]); + width = range_width(node, rnode->children[1]); + save_struct_array_width(node, width); + width *= array_count; // range nodes are now redundant node->children.clear(); } @@ -313,6 +373,70 @@ int size_packed_struct(AstNode *snode, int base_offset) return (is_union ? packed_width : offset); } +[[noreturn]] static void struct_op_error(AstNode *node) +{ + log_file_error(node->filename, node->location.first_line, "Unsupported operation for struct/union member %s\n", node->str.c_str()+1); +} + +static AstNode *node_int(int ival) +{ + // maybe mkconst_int should have default values for the common integer case + return AstNode::mkconst_int(ival, true, 32); +} + +static AstNode *offset_indexed_range(int offset_right, int stride, AstNode *left_expr, AstNode *right_expr) +{ + // adjust the range expressions to add an offset into the struct + // and maybe index using an array stride + auto left = left_expr->clone(); + auto right = right_expr->clone(); + if (stride == 1) { + // just add the offset + left = new AstNode(AST_ADD, node_int(offset_right), left); + right = new AstNode(AST_ADD, node_int(offset_right), right); + } + else { + // newleft = offset_right - 1 + (left + 1) * stride + left = new AstNode(AST_ADD, new AstNode(AST_SUB, node_int(offset_right), node_int(1)), + new AstNode(AST_MUL, node_int(stride), new AstNode(AST_ADD, left, node_int(1)))); + // newright = offset_right + right * stride + right = new AstNode(AST_ADD, node_int(offset_right), new AstNode(AST_MUL, right, node_int(stride))); + } + return new AstNode(AST_RANGE, left, right); +} + +static AstNode *make_struct_member_range(AstNode *node, AstNode *member_node) +{ + // Work out the range in the packed array that corresponds to a struct member + // taking into account any range operations applicable to the current node + // such as array indexing or slicing + int range_left = member_node->range_left; + int range_right = member_node->range_right; + if (node->children.empty()) { + // no range operations apply, return the whole width + } + else if (node->children.size() == 1 && node->children[0]->type == AST_RANGE) { + auto rnode = node->children[0]; + int stride = get_struct_array_width(member_node); + if (rnode->children.size() == 1) { + // index e.g. s.a[i] + return offset_indexed_range(range_right, stride, rnode->children[0], rnode->children[0]); + } + else if (rnode->children.size() == 2) { + // slice e.g. s.a[i:j] + return offset_indexed_range(range_right, stride, rnode->children[0], rnode->children[1]); + } + else { + struct_op_error(node); + } + } + else { + // TODO multirange, i.e. bit slice after array index s.a[i][p:q] + struct_op_error(node); + } + return make_range(range_left, range_right); +} + static void add_members_to_scope(AstNode *snode, std::string name) { // add all the members in a struct or union to local scope @@ -1392,30 +1516,25 @@ bool AstNode::simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage, } } - // annotate identifiers using scope resolution and create auto-wires as needed if (type == AST_IDENTIFIER && !basic_prep) { // check if a plausible struct member sss.mmmm std::string sname; - if (name_has_dot(str, sname) && children.size() == 0) { - //dumpScope(); + if (name_has_dot(str, sname)) { if (current_scope.count(str) > 0) { auto item_node = current_scope[str]; if (item_node->type == AST_STRUCT_ITEM) { - //log("found struct item %s\n", item_node->str.c_str()); // structure member, rewrite this node to reference the packed struct wire - auto range = make_range(item_node->range_left, item_node->range_right); + auto range = make_struct_member_range(this, item_node); newNode = new AstNode(AST_IDENTIFIER, range); newNode->str = sname; - //newNode->dumpAst(NULL, "* "); newNode->basic_prep = true; goto apply_newNode; } } } } + // annotate identifiers using scope resolution and create auto-wires as needed if (type == AST_IDENTIFIER) { - //log("annotate ID %s, stage=%d cf=%d, ip=%d\n", str.c_str(), stage, const_fold, in_param); - //dumpScope(); if (current_scope.count(str) == 0) { AstNode *current_scope_ast = (current_ast_mod == nullptr) ? current_ast : current_ast_mod; for (auto node : current_scope_ast->children) { diff --git a/frontends/verilog/verilog_parser.y b/frontends/verilog/verilog_parser.y index c4867356c..b34a62248 100644 --- a/frontends/verilog/verilog_parser.y +++ b/frontends/verilog/verilog_parser.y @@ -1554,10 +1554,10 @@ member_name_list: member_name: TOK_ID { astbuf1->str = $1->substr(1); delete $1; - auto member_node = astbuf1->clone(); - SET_AST_NODE_LOC(member_node, @1, @1); - astbuf2->children.push_back(member_node); - } + astbuf3 = astbuf1->clone(); + SET_AST_NODE_LOC(astbuf3, @1, @1); + astbuf2->children.push_back(astbuf3); + } range { if ($3) astbuf3->children.push_back($3); } ; struct_member_type: { astbuf1 = new AstNode(AST_STRUCT_ITEM); } member_type_token @@ -1595,7 +1595,7 @@ member_type_token: ; member_type: type_atom type_signing - | type_vec type_signing range { if ($3) astbuf1->children.push_back($3); } + | type_vec type_signing range_or_multirange { if ($3) astbuf1->children.push_back($3); } ; struct_var_list: struct_var diff --git a/kernel/register.h b/kernel/register.h index 3d89386b7..7bbcd1727 100644 --- a/kernel/register.h +++ b/kernel/register.h @@ -125,7 +125,7 @@ struct Backend : Pass }; // implemented in passes/cmds/select.cc -extern void handle_extra_select_args(Pass *pass, std::vector<std::string> args, size_t argidx, size_t args_size, RTLIL::Design *design); +extern void handle_extra_select_args(Pass *pass, const std::vector<std::string> &args, size_t argidx, size_t args_size, RTLIL::Design *design); extern RTLIL::Selection eval_select_args(const vector<string> &args, RTLIL::Design *design); extern void eval_select_op(vector<RTLIL::Selection> &work, const string &op, RTLIL::Design *design); diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc index 397edc4e7..ef81cac01 100644 --- a/kernel/rtlil.cc +++ b/kernel/rtlil.cc @@ -319,7 +319,7 @@ void RTLIL::AttrObject::set_strpool_attribute(RTLIL::IdString id, const pool<str attrval += "|"; attrval += s; } - attributes[id] = RTLIL::Const(attrval); + set_string_attribute(id, attrval); } void RTLIL::AttrObject::add_strpool_attribute(RTLIL::IdString id, const pool<string> &data) @@ -334,11 +334,27 @@ pool<string> RTLIL::AttrObject::get_strpool_attribute(RTLIL::IdString id) const { pool<string> data; if (attributes.count(id) != 0) - for (auto s : split_tokens(attributes.at(id).decode_string(), "|")) + for (auto s : split_tokens(get_string_attribute(id), "|")) data.insert(s); return data; } +void RTLIL::AttrObject::set_hdlname_attribute(const vector<string> &hierarchy) +{ + string attrval; + for (const auto &ident : hierarchy) { + if (!attrval.empty()) + attrval += " "; + attrval += ident; + } + set_string_attribute(ID::hdlname, attrval); +} + +vector<string> RTLIL::AttrObject::get_hdlname_attribute() const +{ + return split_tokens(get_string_attribute(ID::hdlname), " "); +} + bool RTLIL::Selection::selected_module(RTLIL::IdString mod_name) const { if (full_selection) @@ -1520,13 +1536,13 @@ void RTLIL::Module::cloneInto(RTLIL::Module *new_mod) const new_mod->addWire(it.first, it.second); for (auto &it : memories) - new_mod->memories[it.first] = new RTLIL::Memory(*it.second); + new_mod->addMemory(it.first, it.second); for (auto &it : cells_) new_mod->addCell(it.first, it.second); for (auto &it : processes) - new_mod->processes[it.first] = it.second->clone(); + new_mod->addProcess(it.first, it.second); struct RewriteSigSpecWorker { @@ -1885,6 +1901,26 @@ RTLIL::Cell *RTLIL::Module::addCell(RTLIL::IdString name, const RTLIL::Cell *oth return cell; } +RTLIL::Memory *RTLIL::Module::addMemory(RTLIL::IdString name, const RTLIL::Memory *other) +{ + RTLIL::Memory *mem = new RTLIL::Memory; + mem->name = name; + mem->width = other->width; + mem->start_offset = other->start_offset; + mem->size = other->size; + mem->attributes = other->attributes; + memories[mem->name] = mem; + return mem; +} + +RTLIL::Process *RTLIL::Module::addProcess(RTLIL::IdString name, const RTLIL::Process *other) +{ + RTLIL::Process *proc = other->clone(); + proc->name = name; + processes[name] = proc; + return proc; +} + #define DEF_METHOD(_func, _y_size, _type) \ RTLIL::Cell* RTLIL::Module::add ## _func(RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_y, bool is_signed, const std::string &src) { \ RTLIL::Cell *cell = addCell(name, _type); \ diff --git a/kernel/rtlil.h b/kernel/rtlil.h index 51e573e76..f3dc3af68 100644 --- a/kernel/rtlil.h +++ b/kernel/rtlil.h @@ -682,6 +682,9 @@ struct RTLIL::AttrObject std::string get_src_attribute() const { return get_string_attribute(ID::src); } + + void set_hdlname_attribute(const vector<string> &hierarchy); + vector<string> get_hdlname_attribute() const; }; struct RTLIL::SigChunk @@ -1170,6 +1173,10 @@ public: RTLIL::Cell *addCell(RTLIL::IdString name, RTLIL::IdString type); RTLIL::Cell *addCell(RTLIL::IdString name, const RTLIL::Cell *other); + RTLIL::Memory *addMemory(RTLIL::IdString name, const RTLIL::Memory *other); + + RTLIL::Process *addProcess(RTLIL::IdString name, const RTLIL::Process *other); + // The add* methods create a cell and return the created cell. All signals must exist in advance. RTLIL::Cell* addNot (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = ""); diff --git a/manual/CHAPTER_Overview.tex b/manual/CHAPTER_Overview.tex index ac0f48e47..83cfa5cc4 100644 --- a/manual/CHAPTER_Overview.tex +++ b/manual/CHAPTER_Overview.tex @@ -193,6 +193,13 @@ Violating these rules results in a runtime error. All RTLIL identifiers are case sensitive. +Some transformations, such as flattening, may have to change identifiers provided by the user +to avoid name collisions. When that happens, attribute ``{\tt hdlname}`` is attached to the object +with the changed identifier. This attribute contains one name (if emitted directly by the frontend, +or is a result of disambiguation) or multiple names separated by spaces (if a result of flattening). +All names specified in the ``{\tt hdlname}`` attribute are public and do not include the leading +``\textbackslash``. + \subsection{RTLIL::Design and RTLIL::Module} The RTLIL::Design object is basically just a container for RTLIL::Module objects. In addition to diff --git a/passes/cmds/select.cc b/passes/cmds/select.cc index 6e728c16f..13ee030a5 100644 --- a/passes/cmds/select.cc +++ b/passes/cmds/select.cc @@ -30,26 +30,31 @@ using RTLIL::id2cstr; static std::vector<RTLIL::Selection> work_stack; -static bool match_ids(RTLIL::IdString id, std::string pattern) +static bool match_ids(RTLIL::IdString id, const std::string &pattern) { if (id == pattern) return true; - if (id.size() > 0 && id[0] == '\\' && id.compare(1, std::string::npos, pattern.c_str()) == 0) + + const char *id_c = id.c_str(); + const char *pat_c = pattern.c_str(); + size_t id_size = strlen(id_c); + size_t pat_size = pattern.size(); + + if (*id_c == '\\' && id_size == 1 + pat_size && memcmp(id_c + 1, pat_c, pat_size) == 0) return true; - if (patmatch(pattern.c_str(), id.c_str())) + if (patmatch(pat_c, id_c)) return true; - if (id.size() > 0 && id[0] == '\\' && patmatch(pattern.c_str(), id.substr(1).c_str())) + if (*id_c == '\\' && patmatch(pat_c, id_c + 1)) return true; - if (id.size() > 0 && id[0] == '$' && pattern.size() > 0 && pattern[0] == '$') { - const char *p = id.c_str(); - const char *q = strrchr(p, '$'); + if (*id_c == '$' && *pat_c == '$') { + const char *q = strrchr(id_c, '$'); if (pattern == q) return true; } return false; } -static bool match_attr_val(const RTLIL::Const &value, std::string pattern, char match_op) +static bool match_attr_val(const RTLIL::Const &value, const std::string &pattern, char match_op) { if (match_op == 0) return true; @@ -101,7 +106,7 @@ static bool match_attr_val(const RTLIL::Const &value, std::string pattern, char log_abort(); } -static bool match_attr(const dict<RTLIL::IdString, RTLIL::Const> &attributes, std::string name_pat, std::string value_pat, char match_op) +static bool match_attr(const dict<RTLIL::IdString, RTLIL::Const> &attributes, const std::string &name_pat, const std::string &value_pat, char match_op) { if (name_pat.find('*') != std::string::npos || name_pat.find('?') != std::string::npos || name_pat.find('[') != std::string::npos) { for (auto &it : attributes) { @@ -119,7 +124,7 @@ static bool match_attr(const dict<RTLIL::IdString, RTLIL::Const> &attributes, st return false; } -static bool match_attr(const dict<RTLIL::IdString, RTLIL::Const> &attributes, std::string match_expr) +static bool match_attr(const dict<RTLIL::IdString, RTLIL::Const> &attributes, const std::string &match_expr) { size_t pos = match_expr.find_first_of("<!=>"); @@ -410,7 +415,7 @@ namespace { }; } -static int parse_comma_list(std::set<RTLIL::IdString> &tokens, std::string str, size_t pos, std::string stopchar) +static int parse_comma_list(std::set<RTLIL::IdString> &tokens, const std::string &str, size_t pos, std::string stopchar) { stopchar += ','; while (1) { @@ -495,7 +500,7 @@ static int select_op_expand(RTLIL::Design *design, RTLIL::Selection &lhs, std::v return sel_objects; } -static void select_op_expand(RTLIL::Design *design, std::string arg, char mode, bool eval_only) +static void select_op_expand(RTLIL::Design *design, const std::string &arg, char mode, bool eval_only) { int pos = (mode == 'x' ? 2 : 3) + (eval_only ? 1 : 0); int levels = 1, rem_objects = -1; @@ -966,7 +971,7 @@ PRIVATE_NAMESPACE_END YOSYS_NAMESPACE_BEGIN // used in kernel/register.cc and maybe other locations, extern decl. in register.h -void handle_extra_select_args(Pass *pass, vector<string> args, size_t argidx, size_t args_size, RTLIL::Design *design) +void handle_extra_select_args(Pass *pass, const vector<string> &args, size_t argidx, size_t args_size, RTLIL::Design *design) { work_stack.clear(); for (; argidx < args_size; argidx++) { @@ -1670,7 +1675,7 @@ struct CdPass : public Pass { } CdPass; template<typename T> -static void log_matches(const char *title, Module *module, T list) +static void log_matches(const char *title, Module *module, const T &list) { std::vector<IdString> matches; diff --git a/passes/fsm/fsm_extract.cc b/passes/fsm/fsm_extract.cc index 3840aabc8..6f99886f0 100644 --- a/passes/fsm/fsm_extract.cc +++ b/passes/fsm/fsm_extract.cc @@ -394,7 +394,7 @@ static void extract_fsm(RTLIL::Wire *wire) RTLIL::Cell *cell = module->cells_.at(cellport.first); RTLIL::SigSpec port_sig = assign_map(cell->getPort(cellport.second)); RTLIL::SigSpec unconn_sig = port_sig.extract(ctrl_out); - RTLIL::Wire *unconn_wire = module->addWire(stringf("$fsm_unconnect$%s$%d", log_signal(unconn_sig), autoidx++), unconn_sig.size()); + RTLIL::Wire *unconn_wire = module->addWire(stringf("$fsm_unconnect$%d", autoidx++), unconn_sig.size()); port_sig.replace(unconn_sig, RTLIL::SigSpec(unconn_wire), &cell->connections_[cellport.second]); } } diff --git a/passes/hierarchy/hierarchy.cc b/passes/hierarchy/hierarchy.cc index f99d1509d..b4eb0f1dd 100644 --- a/passes/hierarchy/hierarchy.cc +++ b/passes/hierarchy/hierarchy.cc @@ -254,16 +254,6 @@ bool expand_module(RTLIL::Design *design, RTLIL::Module *module, bool flag_check // some lists, so that the ports for sub-modules can be replaced further down: for (auto &conn : cell->connections()) { if(mod->wire(conn.first) != nullptr && mod->wire(conn.first)->get_bool_attribute(ID::is_interface)) { // Check if the connection is present as an interface in the sub-module's port list - //const pool<string> &interface_type_pool = mod->wire(conn.first)->get_strpool_attribute(ID::interface_type); - //for (auto &d : interface_type_pool) { // TODO: Compare interface type to type in parent module (not crucially important, but good for robustness) - //} - - // Find if the sub-module has set a modport for the current interface connection: - const pool<string> &interface_modport_pool = mod->wire(conn.first)->get_strpool_attribute(ID::interface_modport); - std::string interface_modport = ""; - for (auto &d : interface_modport_pool) { - interface_modport = "\\" + d; - } if(conn.second.bits().size() == 1 && conn.second.bits()[0].wire->get_bool_attribute(ID::is_interface)) { // Check if the connected wire is a potential interface in the parent module std::string interface_name_str = conn.second.bits()[0].wire->name.str(); interface_name_str.replace(0,23,""); // Strip the prefix '$dummywireforinterface' from the dummy wire to get the name @@ -297,9 +287,12 @@ bool expand_module(RTLIL::Design *design, RTLIL::Module *module, bool flag_check connections_to_remove.push_back(conn.first); interfaces_to_add_to_submodule[conn.first] = interfaces_in_module.at(interface_name2); - // Add modports to a dict which will be passed to AstModule::derive - if (interface_modport != "") { - modports_used_in_submodule[conn.first] = interface_modport; + // Find if the sub-module has set a modport for the current + // interface connection. Add any modports to a dict which will + // be passed to AstModule::derive + string modport_name = mod->wire(conn.first)->get_string_attribute(ID::interface_modport); + if (!modport_name.empty()) { + modports_used_in_submodule[conn.first] = "\\" + modport_name; } } else not_found_interface = true; diff --git a/passes/techmap/Makefile.inc b/passes/techmap/Makefile.inc index 873286608..a54b4913d 100644 --- a/passes/techmap/Makefile.inc +++ b/passes/techmap/Makefile.inc @@ -1,4 +1,5 @@ +OBJS += passes/techmap/flatten.o OBJS += passes/techmap/techmap.o OBJS += passes/techmap/simplemap.o OBJS += passes/techmap/dfflibmap.o diff --git a/passes/techmap/flatten.cc b/passes/techmap/flatten.cc new file mode 100644 index 000000000..a03226f9f --- /dev/null +++ b/passes/techmap/flatten.cc @@ -0,0 +1,333 @@ +/* + * yosys -- Yosys Open SYnthesis Suite + * + * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at> + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + * + */ + +#include "kernel/yosys.h" +#include "kernel/utils.h" +#include "kernel/sigtools.h" + +#include <stdlib.h> +#include <stdio.h> +#include <string.h> + +USING_YOSYS_NAMESPACE +PRIVATE_NAMESPACE_BEGIN + +IdString concat_name(RTLIL::Cell *cell, IdString object_name) +{ + if (object_name[0] == '\\') + return stringf("%s.%s", cell->name.c_str(), object_name.c_str() + 1); + else { + std::string object_name_str = object_name.str(); + if (object_name_str.substr(0, 8) == "$flatten") + object_name_str.erase(0, 8); + return stringf("$flatten%s.%s", cell->name.c_str(), object_name_str.c_str()); + } +} + +template<class T> +IdString map_name(RTLIL::Cell *cell, T *object) +{ + return cell->module->uniquify(concat_name(cell, object->name)); +} + +template<class T> +void map_attributes(RTLIL::Cell *cell, T *object, IdString orig_object_name) +{ + if (object->has_attribute(ID::src)) + object->add_strpool_attribute(ID::src, cell->get_strpool_attribute(ID::src)); + + // Preserve original names via the hdlname attribute, but only for objects with a fully public name. + if (cell->name[0] == '\\' && (object->has_attribute(ID::hdlname) || orig_object_name[0] == '\\')) { + std::vector<std::string> hierarchy; + if (object->has_attribute(ID::hdlname)) + hierarchy = object->get_hdlname_attribute(); + else + hierarchy.push_back(orig_object_name.str().substr(1)); + hierarchy.insert(hierarchy.begin(), cell->name.str().substr(1)); + object->set_hdlname_attribute(hierarchy); + } +} + +void map_sigspec(const dict<RTLIL::Wire*, RTLIL::Wire*> &map, RTLIL::SigSpec &sig, RTLIL::Module *into = nullptr) +{ + vector<SigChunk> chunks = sig; + for (auto &chunk : chunks) + if (chunk.wire != nullptr && chunk.wire->module != into) + chunk.wire = map.at(chunk.wire); + sig = chunks; +} + +struct FlattenWorker +{ + bool ignore_wb = false; + + void flatten_cell(RTLIL::Design *design, RTLIL::Module *module, RTLIL::Cell *cell, RTLIL::Module *tpl, std::vector<RTLIL::Cell*> &new_cells) + { + // Copy the contents of the flattened cell + + dict<IdString, IdString> memory_map; + for (auto &tpl_memory_it : tpl->memories) { + RTLIL::Memory *new_memory = module->addMemory(map_name(cell, tpl_memory_it.second), tpl_memory_it.second); + map_attributes(cell, new_memory, tpl_memory_it.second->name); + memory_map[tpl_memory_it.first] = new_memory->name; + design->select(module, new_memory); + } + + dict<RTLIL::Wire*, RTLIL::Wire*> wire_map; + dict<IdString, IdString> positional_ports; + for (auto tpl_wire : tpl->wires()) { + if (tpl_wire->port_id > 0) + positional_ports.emplace(stringf("$%d", tpl_wire->port_id), tpl_wire->name); + + RTLIL::Wire *new_wire = nullptr; + if (tpl_wire->name[0] == '\\') { + RTLIL::Wire *hier_wire = module->wire(concat_name(cell, tpl_wire->name)); + if (hier_wire != nullptr && hier_wire->get_bool_attribute(ID::hierconn)) { + hier_wire->attributes.erase(ID::hierconn); + if (GetSize(hier_wire) < GetSize(tpl_wire)) { + log_warning("Widening signal %s.%s to match size of %s.%s (via %s.%s).\n", + log_id(module), log_id(hier_wire), log_id(tpl), log_id(tpl_wire), log_id(module), log_id(cell)); + hier_wire->width = GetSize(tpl_wire); + } + new_wire = hier_wire; + } + } + if (new_wire == nullptr) { + new_wire = module->addWire(map_name(cell, tpl_wire), tpl_wire); + new_wire->port_input = new_wire->port_output = false; + new_wire->port_id = false; + } + + map_attributes(cell, new_wire, tpl_wire->name); + wire_map[tpl_wire] = new_wire; + design->select(module, new_wire); + } + + for (auto &tpl_proc_it : tpl->processes) { + RTLIL::Process *new_proc = module->addProcess(map_name(cell, tpl_proc_it.second), tpl_proc_it.second); + map_attributes(cell, new_proc, tpl_proc_it.second->name); + auto rewriter = [&](RTLIL::SigSpec &sig) { map_sigspec(wire_map, sig); }; + new_proc->rewrite_sigspecs(rewriter); + design->select(module, new_proc); + } + + for (auto tpl_cell : tpl->cells()) { + RTLIL::Cell *new_cell = module->addCell(map_name(cell, tpl_cell), tpl_cell); + map_attributes(cell, new_cell, tpl_cell->name); + if (new_cell->type.in(ID($memrd), ID($memwr), ID($meminit))) { + IdString memid = new_cell->getParam(ID::MEMID).decode_string(); + new_cell->setParam(ID::MEMID, Const(memory_map.at(memid).str())); + } else if (new_cell->type == ID($mem)) { + IdString memid = new_cell->getParam(ID::MEMID).decode_string(); + new_cell->setParam(ID::MEMID, Const(concat_name(cell, memid).str())); + } + auto rewriter = [&](RTLIL::SigSpec &sig) { map_sigspec(wire_map, sig); }; + new_cell->rewrite_sigspecs(rewriter); + design->select(module, new_cell); + new_cells.push_back(new_cell); + } + + for (auto &tpl_conn_it : tpl->connections()) { + RTLIL::SigSig new_conn = tpl_conn_it; + map_sigspec(wire_map, new_conn.first); + map_sigspec(wire_map, new_conn.second); + module->connect(new_conn); + } + + // Attach port connections of the flattened cell + + SigMap tpl_sigmap(tpl); + pool<SigBit> tpl_driven; + for (auto tpl_cell : tpl->cells()) + for (auto &tpl_conn : tpl_cell->connections()) + if (tpl_cell->output(tpl_conn.first)) + for (auto bit : tpl_sigmap(tpl_conn.second)) + tpl_driven.insert(bit); + for (auto &tpl_conn : tpl->connections()) + for (auto bit : tpl_sigmap(tpl_conn.first)) + tpl_driven.insert(bit); + + SigMap sigmap(module); + for (auto &port_it : cell->connections()) + { + IdString port_name = port_it.first; + if (positional_ports.count(port_name) > 0) + port_name = positional_ports.at(port_name); + if (tpl->wire(port_name) == nullptr || tpl->wire(port_name)->port_id == 0) { + if (port_name.begins_with("$")) + log_error("Can't map port `%s' of cell `%s' to template `%s'!\n", + port_name.c_str(), cell->name.c_str(), tpl->name.c_str()); + continue; + } + + if (GetSize(port_it.second) == 0) + continue; + + RTLIL::Wire *tpl_wire = tpl->wire(port_name); + RTLIL::SigSig new_conn; + if (tpl_wire->port_output && !tpl_wire->port_input) { + new_conn.first = port_it.second; + new_conn.second = tpl_wire; + } else if (!tpl_wire->port_output && tpl_wire->port_input) { + new_conn.first = tpl_wire; + new_conn.second = port_it.second; + } else { + SigSpec sig_tpl = tpl_wire, sig_mod = port_it.second; + for (int i = 0; i < GetSize(sig_tpl) && i < GetSize(sig_mod); i++) { + if (tpl_driven.count(tpl_sigmap(sig_tpl[i]))) { + new_conn.first.append(sig_mod[i]); + new_conn.second.append(sig_tpl[i]); + } else { + new_conn.first.append(sig_tpl[i]); + new_conn.second.append(sig_mod[i]); + } + } + } + map_sigspec(wire_map, new_conn.first, module); + map_sigspec(wire_map, new_conn.second, module); + + if (new_conn.second.size() > new_conn.first.size()) + new_conn.second.remove(new_conn.first.size(), new_conn.second.size() - new_conn.first.size()); + if (new_conn.second.size() < new_conn.first.size()) + new_conn.second.append(RTLIL::SigSpec(RTLIL::State::S0, new_conn.first.size() - new_conn.second.size())); + log_assert(new_conn.first.size() == new_conn.second.size()); + + if (sigmap(new_conn.first).has_const()) + log_error("Mismatch in directionality for cell port %s.%s.%s: %s <= %s\n", + log_id(module), log_id(cell), log_id(port_it.first), log_signal(new_conn.first), log_signal(new_conn.second)); + + module->connect(new_conn); + } + + module->remove(cell); + } + + void flatten_module(RTLIL::Design *design, RTLIL::Module *module, pool<RTLIL::Module*> &used_modules) + { + if (!design->selected(module) || module->get_blackbox_attribute(ignore_wb)) + return; + + std::vector<RTLIL::Cell*> worklist = module->selected_cells(); + while (!worklist.empty()) + { + RTLIL::Cell *cell = worklist.back(); + worklist.pop_back(); + + if (!design->has(cell->type)) + continue; + + RTLIL::Module *tpl = design->module(cell->type); + if (tpl->get_blackbox_attribute(ignore_wb)) + continue; + + if (cell->get_bool_attribute(ID::keep_hierarchy) || tpl->get_bool_attribute(ID::keep_hierarchy)) { + log("Keeping %s.%s (found keep_hierarchy attribute).\n", log_id(module), log_id(cell)); + used_modules.insert(tpl); + continue; + } + + log_debug("Flattening %s.%s (%s).\n", log_id(module), log_id(cell), log_id(cell->type)); + // If a design is fully selected and has a top module defined, topological sorting ensures that all cells + // added during flattening are black boxes, and flattening is finished in one pass. However, when flattening + // individual modules, this isn't the case, and the newly added cells might have to be flattened further. + flatten_cell(design, module, cell, tpl, worklist); + } + } +}; + +struct FlattenPass : public Pass { + FlattenPass() : Pass("flatten", "flatten design") { } + void help() YS_OVERRIDE + { + // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| + log("\n"); + log(" flatten [options] [selection]\n"); + log("\n"); + log("This pass flattens the design by replacing cells by their implementation. This\n"); + log("pass is very similar to the 'techmap' pass. The only difference is that this\n"); + log("pass is using the current design as mapping library.\n"); + log("\n"); + log("Cells and/or modules with the 'keep_hierarchy' attribute set will not be\n"); + log("flattened by this command.\n"); + log("\n"); + log(" -wb\n"); + log(" Ignore the 'whitebox' attribute on cell implementations.\n"); + log("\n"); + } + void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE + { + log_header(design, "Executing FLATTEN pass (flatten design).\n"); + log_push(); + + FlattenWorker worker; + + size_t argidx; + for (argidx = 1; argidx < args.size(); argidx++) { + if (args[argidx] == "-wb") { + worker.ignore_wb = true; + continue; + } + break; + } + extra_args(args, argidx, design); + + RTLIL::Module *top = nullptr; + if (design->full_selection()) + for (auto module : design->modules()) + if (module->get_bool_attribute(ID::top)) + top = module; + + pool<RTLIL::Module*> used_modules; + if (top == nullptr) + used_modules = design->modules(); + else + used_modules.insert(top); + + TopoSort<RTLIL::Module*, IdString::compare_ptr_by_name<RTLIL::Module>> topo_modules; + pool<RTLIL::Module*> worklist = used_modules; + while (!worklist.empty()) { + RTLIL::Module *module = worklist.pop(); + for (auto cell : module->selected_cells()) { + RTLIL::Module *tpl = design->module(cell->type); + if (tpl != nullptr) { + if (topo_modules.database.count(tpl) == 0) + worklist.insert(tpl); + topo_modules.edge(tpl, module); + } + } + } + + if (!topo_modules.sort()) + log_error("Cannot flatten a design containing recursive instantiations.\n"); + + for (auto module : topo_modules.sorted) + worker.flatten_module(design, module, used_modules); + + if (top != nullptr) + for (auto module : design->modules().to_vector()) + if (!used_modules[module] && !module->get_blackbox_attribute(worker.ignore_wb)) { + log("Deleting now unused module %s.\n", log_id(module)); + design->remove(module); + } + + log_pop(); + } +} FlattenPass; + +PRIVATE_NAMESPACE_END diff --git a/passes/techmap/techmap.cc b/passes/techmap/techmap.cc index c88f7bd0a..535db9465 100644 --- a/passes/techmap/techmap.cc +++ b/passes/techmap/techmap.cc @@ -67,10 +67,6 @@ struct TechmapWorker pool<RTLIL::Module*> module_queue; dict<Module*, SigMap> sigmaps; - pool<IdString> flatten_do_list; - pool<IdString> flatten_done_list; - pool<Cell*> flatten_keep_list; - pool<string> log_msg_cache; struct TechmapWireData { @@ -82,7 +78,6 @@ struct TechmapWorker bool extern_mode = false; bool assert_mode = false; - bool flatten_mode = false; bool recursive_mode = false; bool autoproc_mode = false; bool ignore_wb = false; @@ -168,28 +163,20 @@ struct TechmapWorker pool<string> extra_src_attrs = cell->get_strpool_attribute(ID::src); orig_cell_name = cell->name.str(); - if (!flatten_mode) { - for (auto tpl_cell : tpl->cells()) - if (tpl_cell->name == ID::_TECHMAP_REPLACE_) { - module->rename(cell, stringf("$techmap%d", autoidx++) + cell->name.str()); - break; - } - } + for (auto tpl_cell : tpl->cells()) + if (tpl_cell->name == ID::_TECHMAP_REPLACE_) { + module->rename(cell, stringf("$techmap%d", autoidx++) + cell->name.str()); + break; + } dict<IdString, IdString> memory_renames; for (auto &it : tpl->memories) { IdString m_name = it.first; apply_prefix(cell->name, m_name); - RTLIL::Memory *m = new RTLIL::Memory; - m->name = m_name; - m->width = it.second->width; - m->start_offset = it.second->start_offset; - m->size = it.second->size; - m->attributes = it.second->attributes; + RTLIL::Memory *m = module->addMemory(m_name, it.second); if (m->attributes.count(ID::src)) m->add_strpool_attribute(ID::src, extra_src_attrs); - module->memories[m->name] = m; memory_renames[it.first] = m->name; design->select(module, m); } @@ -205,7 +192,7 @@ struct TechmapWorker IdString posportname = stringf("$%d", tpl_w->port_id); positional_ports.emplace(posportname, tpl_w->name); - if (!flatten_mode && tpl_w->get_bool_attribute(ID::techmap_autopurge) && + if (tpl_w->get_bool_attribute(ID::techmap_autopurge) && (!cell->hasPort(tpl_w->name) || !GetSize(cell->getPort(tpl_w->name))) && (!cell->hasPort(posportname) || !GetSize(cell->getPort(posportname)))) { @@ -221,26 +208,16 @@ struct TechmapWorker apply_prefix(cell->name, w_name); RTLIL::Wire *w = module->wire(w_name); if (w != nullptr) { - if (!flatten_mode || !w->get_bool_attribute(ID::hierconn)) { - temp_renamed_wires[w] = w->name; - module->rename(w, NEW_ID); - w = nullptr; - } else { - w->attributes.erase(ID::hierconn); - if (GetSize(w) < GetSize(tpl_w)) { - log_warning("Widening signal %s.%s to match size of %s.%s (via %s.%s).\n", log_id(module), log_id(w), - log_id(tpl), log_id(tpl_w), log_id(module), log_id(cell)); - w->width = GetSize(tpl_w); - } - } + temp_renamed_wires[w] = w->name; + module->rename(w, NEW_ID); + w = nullptr; } if (w == nullptr) { w = module->addWire(w_name, tpl_w); w->port_input = false; w->port_output = false; w->port_id = 0; - if (!flatten_mode) - w->attributes.erase(ID::techmap_autopurge); + w->attributes.erase(ID::techmap_autopurge); if (tpl_w->get_bool_attribute(ID::_techmap_special_)) w->attributes.clear(); if (w->attributes.count(ID::src)) @@ -322,56 +299,37 @@ struct TechmapWorker log_assert(c.first.size() == c.second.size()); - if (flatten_mode) - { - // more conservative approach: - // connect internal and external wires - - if (sigmaps.count(module) == 0) - sigmaps[module].set(module); - - if (sigmaps.at(module)(c.first).has_const()) - log_error("Mismatch in directionality for cell port %s.%s.%s: %s <= %s\n", - log_id(module), log_id(cell), log_id(it.first), log_signal(c.first), log_signal(c.second)); + // replace internal wires that are connected to external wires + if (w->port_output && !w->port_input) { + port_signal_map.add(c.second, c.first); + } else + if (!w->port_output && w->port_input) { + port_signal_map.add(c.first, c.second); + } else { module->connect(c); + extra_connect = SigSig(); } - else - { - // approach that yields nicer outputs: - // replace internal wires that are connected to external wires - - if (w->port_output && !w->port_input) { - port_signal_map.add(c.second, c.first); - } else - if (!w->port_output && w->port_input) { - port_signal_map.add(c.first, c.second); - } else { - module->connect(c); - extra_connect = SigSig(); - } - for (auto &attr : w->attributes) { - if (attr.first == ID::src) - continue; - auto lhs = GetSize(extra_connect.first); - auto rhs = GetSize(extra_connect.second); - if (lhs > rhs) - extra_connect.first.remove(rhs, lhs-rhs); - else if (rhs > lhs) - extra_connect.second.remove(lhs, rhs-lhs); - module->connect(extra_connect); - break; - } + for (auto &attr : w->attributes) { + if (attr.first == ID::src) + continue; + auto lhs = GetSize(extra_connect.first); + auto rhs = GetSize(extra_connect.second); + if (lhs > rhs) + extra_connect.first.remove(rhs, lhs-rhs); + else if (rhs > lhs) + extra_connect.second.remove(lhs, rhs-lhs); + module->connect(extra_connect); + break; } } for (auto tpl_cell : tpl->cells()) { IdString c_name = tpl_cell->name; - bool techmap_replace_cell = (!flatten_mode) && (c_name == ID::_TECHMAP_REPLACE_); - if (techmap_replace_cell) + if (c_name == ID::_TECHMAP_REPLACE_) c_name = orig_cell_name; else if (tpl_cell->name.begins_with("\\_TECHMAP_REPLACE_.")) c_name = stringf("%s%s", orig_cell_name.c_str(), c_name.c_str() + strlen("\\_TECHMAP_REPLACE_")); @@ -381,7 +339,7 @@ struct TechmapWorker RTLIL::Cell *c = module->addCell(c_name, tpl_cell); design->select(module, c); - if (!flatten_mode && c->type.begins_with("\\$")) + if (c->type.begins_with("\\$")) c->type = c->type.substr(1); vector<IdString> autopurge_ports; @@ -426,7 +384,7 @@ struct TechmapWorker if (c->attributes.count(ID::src)) c->add_strpool_attribute(ID::src, extra_src_attrs); - if (techmap_replace_cell) + if (c_name == ID::_TECHMAP_REPLACE_) for (auto attr : cell->attributes) if (!c->attributes.count(attr.first)) c->attributes[attr.first] = attr.second; @@ -499,22 +457,6 @@ struct TechmapWorker continue; } - if (flatten_mode) { - bool keepit = cell->get_bool_attribute(ID::keep_hierarchy); - for (auto &tpl_name : celltypeMap.at(cell_type)) - if (map->module(tpl_name)->get_bool_attribute(ID::keep_hierarchy)) - keepit = true; - if (keepit) { - if (!flatten_keep_list[cell]) { - log("Keeping %s.%s (found keep_hierarchy property).\n", log_id(module), log_id(cell)); - flatten_keep_list.insert(cell); - } - if (!flatten_done_list[cell->type]) - flatten_do_list.insert(cell->type); - continue; - } - } - for (auto &conn : cell->connections()) { RTLIL::SigSpec sig = sigmap(conn.second); @@ -564,172 +506,171 @@ struct TechmapWorker if (tpl->get_blackbox_attribute(ignore_wb)) continue; - if (!flatten_mode) - { - std::string extmapper_name; - - if (tpl->get_bool_attribute(ID::techmap_simplemap)) - extmapper_name = "simplemap"; + std::string extmapper_name; - if (tpl->get_bool_attribute(ID::techmap_maccmap)) - extmapper_name = "maccmap"; + if (tpl->get_bool_attribute(ID::techmap_simplemap)) + extmapper_name = "simplemap"; - if (tpl->attributes.count(ID::techmap_wrap)) - extmapper_name = "wrap"; + if (tpl->get_bool_attribute(ID::techmap_maccmap)) + extmapper_name = "maccmap"; - if (!extmapper_name.empty()) - { - cell->type = cell_type; + if (tpl->attributes.count(ID::techmap_wrap)) + extmapper_name = "wrap"; - if ((extern_mode && !in_recursion) || extmapper_name == "wrap") - { - std::string m_name = stringf("$extern:%s:%s", extmapper_name.c_str(), log_id(cell->type)); - - for (auto &c : cell->parameters) - m_name += stringf(":%s=%s", log_id(c.first), log_signal(c.second)); - - if (extmapper_name == "wrap") - m_name += ":" + sha1(tpl->attributes.at(ID::techmap_wrap).decode_string()); - - RTLIL::Design *extmapper_design = extern_mode && !in_recursion ? design : tpl->design; - RTLIL::Module *extmapper_module = extmapper_design->module(m_name); + if (!extmapper_name.empty()) + { + cell->type = cell_type; - if (extmapper_module == nullptr) - { - extmapper_module = extmapper_design->addModule(m_name); - RTLIL::Cell *extmapper_cell = extmapper_module->addCell(cell->type, cell); - - extmapper_cell->set_src_attribute(cell->get_src_attribute()); - - int port_counter = 1; - for (auto &c : extmapper_cell->connections_) { - RTLIL::Wire *w = extmapper_module->addWire(c.first, GetSize(c.second)); - if (w->name.in(ID::Y, ID::Q)) - w->port_output = true; - else - w->port_input = true; - w->port_id = port_counter++; - c.second = w; - } + if ((extern_mode && !in_recursion) || extmapper_name == "wrap") + { + std::string m_name = stringf("$extern:%s:%s", extmapper_name.c_str(), log_id(cell->type)); - extmapper_module->fixup_ports(); - extmapper_module->check(); + for (auto &c : cell->parameters) + m_name += stringf(":%s=%s", log_id(c.first), log_signal(c.second)); - if (extmapper_name == "simplemap") { - log("Creating %s with simplemap.\n", log_id(extmapper_module)); - if (simplemap_mappers.count(extmapper_cell->type) == 0) - log_error("No simplemap mapper for cell type %s found!\n", log_id(extmapper_cell->type)); - simplemap_mappers.at(extmapper_cell->type)(extmapper_module, extmapper_cell); - extmapper_module->remove(extmapper_cell); - } + if (extmapper_name == "wrap") + m_name += ":" + sha1(tpl->attributes.at(ID::techmap_wrap).decode_string()); - if (extmapper_name == "maccmap") { - log("Creating %s with maccmap.\n", log_id(extmapper_module)); - if (extmapper_cell->type != ID($macc)) - log_error("The maccmap mapper can only map $macc (not %s) cells!\n", log_id(extmapper_cell->type)); - maccmap(extmapper_module, extmapper_cell); - extmapper_module->remove(extmapper_cell); - } + RTLIL::Design *extmapper_design = extern_mode && !in_recursion ? design : tpl->design; + RTLIL::Module *extmapper_module = extmapper_design->module(m_name); - if (extmapper_name == "wrap") { - std::string cmd_string = tpl->attributes.at(ID::techmap_wrap).decode_string(); - log("Running \"%s\" on wrapper %s.\n", cmd_string.c_str(), log_id(extmapper_module)); - mkdebug.on(); - Pass::call_on_module(extmapper_design, extmapper_module, cmd_string); - log_continue = true; - } + if (extmapper_module == nullptr) + { + extmapper_module = extmapper_design->addModule(m_name); + RTLIL::Cell *extmapper_cell = extmapper_module->addCell(cell->type, cell); + + extmapper_cell->set_src_attribute(cell->get_src_attribute()); + + int port_counter = 1; + for (auto &c : extmapper_cell->connections_) { + RTLIL::Wire *w = extmapper_module->addWire(c.first, GetSize(c.second)); + if (w->name.in(ID::Y, ID::Q)) + w->port_output = true; + else + w->port_input = true; + w->port_id = port_counter++; + c.second = w; } - cell->type = extmapper_module->name; - cell->parameters.clear(); + extmapper_module->fixup_ports(); + extmapper_module->check(); - if (!extern_mode || in_recursion) { - tpl = extmapper_module; - goto use_wrapper_tpl; + if (extmapper_name == "simplemap") { + log("Creating %s with simplemap.\n", log_id(extmapper_module)); + if (simplemap_mappers.count(extmapper_cell->type) == 0) + log_error("No simplemap mapper for cell type %s found!\n", log_id(extmapper_cell->type)); + simplemap_mappers.at(extmapper_cell->type)(extmapper_module, extmapper_cell); + extmapper_module->remove(extmapper_cell); } - auto msg = stringf("Using extmapper %s for cells of type %s.", log_id(extmapper_module), log_id(cell->type)); - if (!log_msg_cache.count(msg)) { - log_msg_cache.insert(msg); - log("%s\n", msg.c_str()); - } - log_debug("%s %s.%s (%s) to %s.\n", mapmsg_prefix.c_str(), log_id(module), log_id(cell), log_id(cell->type), log_id(extmapper_module)); - } - else - { - auto msg = stringf("Using extmapper %s for cells of type %s.", extmapper_name.c_str(), log_id(cell->type)); - if (!log_msg_cache.count(msg)) { - log_msg_cache.insert(msg); - log("%s\n", msg.c_str()); + if (extmapper_name == "maccmap") { + log("Creating %s with maccmap.\n", log_id(extmapper_module)); + if (extmapper_cell->type != ID($macc)) + log_error("The maccmap mapper can only map $macc (not %s) cells!\n", log_id(extmapper_cell->type)); + maccmap(extmapper_module, extmapper_cell); + extmapper_module->remove(extmapper_cell); } - log_debug("%s %s.%s (%s) with %s.\n", mapmsg_prefix.c_str(), log_id(module), log_id(cell), log_id(cell->type), extmapper_name.c_str()); - if (extmapper_name == "simplemap") { - if (simplemap_mappers.count(cell->type) == 0) - log_error("No simplemap mapper for cell type %s found!\n", log_id(cell->type)); - simplemap_mappers.at(cell->type)(module, cell); + if (extmapper_name == "wrap") { + std::string cmd_string = tpl->attributes.at(ID::techmap_wrap).decode_string(); + log("Running \"%s\" on wrapper %s.\n", cmd_string.c_str(), log_id(extmapper_module)); + mkdebug.on(); + Pass::call_on_module(extmapper_design, extmapper_module, cmd_string); + log_continue = true; } + } - if (extmapper_name == "maccmap") { - if (cell->type != ID($macc)) - log_error("The maccmap mapper can only map $macc (not %s) cells!\n", log_id(cell->type)); - maccmap(module, cell); - } + cell->type = extmapper_module->name; + cell->parameters.clear(); - module->remove(cell); - cell = nullptr; + if (!extern_mode || in_recursion) { + tpl = extmapper_module; + goto use_wrapper_tpl; } - did_something = true; - mapped_cell = true; - break; + auto msg = stringf("Using extmapper %s for cells of type %s.", log_id(extmapper_module), log_id(cell->type)); + if (!log_msg_cache.count(msg)) { + log_msg_cache.insert(msg); + log("%s\n", msg.c_str()); + } + log_debug("%s %s.%s (%s) to %s.\n", mapmsg_prefix.c_str(), log_id(module), log_id(cell), log_id(cell->type), log_id(extmapper_module)); } + else + { + auto msg = stringf("Using extmapper %s for cells of type %s.", extmapper_name.c_str(), log_id(cell->type)); + if (!log_msg_cache.count(msg)) { + log_msg_cache.insert(msg); + log("%s\n", msg.c_str()); + } + log_debug("%s %s.%s (%s) with %s.\n", mapmsg_prefix.c_str(), log_id(module), log_id(cell), log_id(cell->type), extmapper_name.c_str()); - for (auto &conn : cell->connections()) { - if (conn.first.begins_with("$")) - continue; - if (tpl->wire(conn.first) != nullptr && tpl->wire(conn.first)->port_id > 0) - continue; - if (!conn.second.is_fully_const() || parameters.count(conn.first) > 0 || tpl->avail_parameters.count(conn.first) == 0) - goto next_tpl; - parameters[conn.first] = conn.second.as_const(); + if (extmapper_name == "simplemap") { + if (simplemap_mappers.count(cell->type) == 0) + log_error("No simplemap mapper for cell type %s found!\n", log_id(cell->type)); + simplemap_mappers.at(cell->type)(module, cell); + } + + if (extmapper_name == "maccmap") { + if (cell->type != ID($macc)) + log_error("The maccmap mapper can only map $macc (not %s) cells!\n", log_id(cell->type)); + maccmap(module, cell); + } + + module->remove(cell); + cell = nullptr; } - if (0) { - next_tpl: + did_something = true; + mapped_cell = true; + break; + } + + for (auto &conn : cell->connections()) { + if (conn.first.begins_with("$")) continue; - } + if (tpl->wire(conn.first) != nullptr && tpl->wire(conn.first)->port_id > 0) + continue; + if (!conn.second.is_fully_const() || parameters.count(conn.first) > 0 || tpl->avail_parameters.count(conn.first) == 0) + goto next_tpl; + parameters[conn.first] = conn.second.as_const(); + } - if (tpl->avail_parameters.count(ID::_TECHMAP_CELLTYPE_) != 0) - parameters.emplace(ID::_TECHMAP_CELLTYPE_, RTLIL::unescape_id(cell->type)); + if (0) { + next_tpl: + continue; + } - for (auto &conn : cell->connections()) { - if (tpl->avail_parameters.count(stringf("\\_TECHMAP_CONSTMSK_%s_", log_id(conn.first))) != 0) { - std::vector<RTLIL::SigBit> v = sigmap(conn.second).to_sigbit_vector(); - for (auto &bit : v) - bit = RTLIL::SigBit(bit.wire == nullptr ? RTLIL::State::S1 : RTLIL::State::S0); - parameters.emplace(stringf("\\_TECHMAP_CONSTMSK_%s_", log_id(conn.first)), RTLIL::SigSpec(v).as_const()); - } - if (tpl->avail_parameters.count(stringf("\\_TECHMAP_CONSTVAL_%s_", log_id(conn.first))) != 0) { - std::vector<RTLIL::SigBit> v = sigmap(conn.second).to_sigbit_vector(); - for (auto &bit : v) - if (bit.wire != nullptr) - bit = RTLIL::SigBit(RTLIL::State::Sx); - parameters.emplace(stringf("\\_TECHMAP_CONSTVAL_%s_", log_id(conn.first)), RTLIL::SigSpec(v).as_const()); - } - if (tpl->avail_parameters.count(stringf("\\_TECHMAP_WIREINIT_%s_", log_id(conn.first))) != 0) { - auto sig = sigmap(conn.second); - RTLIL::Const value(State::Sx, sig.size()); - for (int i = 0; i < sig.size(); i++) { - auto it = init_bits.find(sig[i]); - if (it != init_bits.end()) { - value[i] = it->second; - } + if (tpl->avail_parameters.count(ID::_TECHMAP_CELLTYPE_) != 0) + parameters.emplace(ID::_TECHMAP_CELLTYPE_, RTLIL::unescape_id(cell->type)); + + for (auto &conn : cell->connections()) { + if (tpl->avail_parameters.count(stringf("\\_TECHMAP_CONSTMSK_%s_", log_id(conn.first))) != 0) { + std::vector<RTLIL::SigBit> v = sigmap(conn.second).to_sigbit_vector(); + for (auto &bit : v) + bit = RTLIL::SigBit(bit.wire == nullptr ? RTLIL::State::S1 : RTLIL::State::S0); + parameters.emplace(stringf("\\_TECHMAP_CONSTMSK_%s_", log_id(conn.first)), RTLIL::SigSpec(v).as_const()); + } + if (tpl->avail_parameters.count(stringf("\\_TECHMAP_CONSTVAL_%s_", log_id(conn.first))) != 0) { + std::vector<RTLIL::SigBit> v = sigmap(conn.second).to_sigbit_vector(); + for (auto &bit : v) + if (bit.wire != nullptr) + bit = RTLIL::SigBit(RTLIL::State::Sx); + parameters.emplace(stringf("\\_TECHMAP_CONSTVAL_%s_", log_id(conn.first)), RTLIL::SigSpec(v).as_const()); + } + if (tpl->avail_parameters.count(stringf("\\_TECHMAP_WIREINIT_%s_", log_id(conn.first))) != 0) { + auto sig = sigmap(conn.second); + RTLIL::Const value(State::Sx, sig.size()); + for (int i = 0; i < sig.size(); i++) { + auto it = init_bits.find(sig[i]); + if (it != init_bits.end()) { + value[i] = it->second; } - parameters.emplace(stringf("\\_TECHMAP_WIREINIT_%s_", log_id(conn.first)), value); } + parameters.emplace(stringf("\\_TECHMAP_WIREINIT_%s_", log_id(conn.first)), value); } + } + { int unique_bit_id_counter = 0; dict<RTLIL::SigBit, int> unique_bit_id; unique_bit_id[RTLIL::State::S0] = unique_bit_id_counter++; @@ -787,13 +728,9 @@ struct TechmapWorker } } - if (flatten_mode) { - techmap_do_cache[tpl] = true; - } else { - RTLIL::Module *constmapped_tpl = map->module(constmap_tpl_name(sigmap, tpl, cell, false)); - if (constmapped_tpl != nullptr) - tpl = constmapped_tpl; - } + RTLIL::Module *constmapped_tpl = map->module(constmap_tpl_name(sigmap, tpl, cell, false)); + if (constmapped_tpl != nullptr) + tpl = constmapped_tpl; if (techmap_do_cache.count(tpl) == 0) { @@ -1333,97 +1270,4 @@ struct TechmapPass : public Pass { } } TechmapPass; -struct FlattenPass : public Pass { - FlattenPass() : Pass("flatten", "flatten design") { } - void help() YS_OVERRIDE - { - // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| - log("\n"); - log(" flatten [options] [selection]\n"); - log("\n"); - log("This pass flattens the design by replacing cells by their implementation. This\n"); - log("pass is very similar to the 'techmap' pass. The only difference is that this\n"); - log("pass is using the current design as mapping library.\n"); - log("\n"); - log("Cells and/or modules with the 'keep_hierarchy' attribute set will not be\n"); - log("flattened by this command.\n"); - log("\n"); - log(" -wb\n"); - log(" Ignore the 'whitebox' attribute on cell implementations.\n"); - log("\n"); - } - void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE - { - log_header(design, "Executing FLATTEN pass (flatten design).\n"); - log_push(); - - TechmapWorker worker; - worker.flatten_mode = true; - - size_t argidx; - for (argidx = 1; argidx < args.size(); argidx++) { - if (args[argidx] == "-wb") { - worker.ignore_wb = true; - continue; - } - break; - } - extra_args(args, argidx, design); - - - dict<IdString, pool<IdString>> celltypeMap; - for (auto module : design->modules()) - celltypeMap[module->name].insert(module->name); - for (auto &i : celltypeMap) - i.second.sort(RTLIL::sort_by_id_str()); - - RTLIL::Module *top_mod = nullptr; - if (design->full_selection()) - for (auto mod : design->modules()) - if (mod->get_bool_attribute(ID::top)) - top_mod = mod; - - pool<RTLIL::Cell*> handled_cells; - if (top_mod != nullptr) { - worker.flatten_do_list.insert(top_mod->name); - while (!worker.flatten_do_list.empty()) { - auto mod = design->module(*worker.flatten_do_list.begin()); - while (worker.techmap_module(design, mod, design, handled_cells, celltypeMap, false)) { } - worker.flatten_done_list.insert(mod->name); - worker.flatten_do_list.erase(mod->name); - } - } else { - for (auto mod : design->modules().to_vector()) - while (worker.techmap_module(design, mod, design, handled_cells, celltypeMap, false)) { } - } - - log_suppressed(); - log("No more expansions possible.\n"); - - if (top_mod != nullptr) - { - pool<IdString> used_modules, new_used_modules; - new_used_modules.insert(top_mod->name); - while (!new_used_modules.empty()) { - pool<IdString> queue; - queue.swap(new_used_modules); - for (auto modname : queue) - used_modules.insert(modname); - for (auto modname : queue) - for (auto cell : design->module(modname)->cells()) - if (design->module(cell->type) && !used_modules[cell->type]) - new_used_modules.insert(cell->type); - } - - for (auto mod : design->modules().to_vector()) - if (!used_modules[mod->name] && !mod->get_blackbox_attribute(worker.ignore_wb)) { - log("Deleting now unused module %s.\n", log_id(mod)); - design->remove(mod); - } - } - - log_pop(); - } -} FlattenPass; - PRIVATE_NAMESPACE_END diff --git a/tests/svtypes/struct_array.sv b/tests/svtypes/struct_array.sv new file mode 100644 index 000000000..022ad56c6 --- /dev/null +++ b/tests/svtypes/struct_array.sv @@ -0,0 +1,22 @@ +// test for array indexing in structures + +module top; + + struct packed { + bit [5:0] [7:0] a; // 6 element packed array of bytes + bit [15:0] b; // filler for non-zero offset + } s; + + initial begin + s = '0; + + s.a[2:1] = 16'h1234; + s.a[5] = 8'h42; + + s.b = '1; + s.b[1:0] = '0; + end + + always_comb assert(s==64'h4200_0012_3400_FFFC); + +endmodule |