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-rw-r--r--CHANGELOG1
-rw-r--r--backends/cxxrtl/cxxrtl.cc22
-rw-r--r--backends/cxxrtl/cxxrtl.h7
-rw-r--r--passes/cmds/select.cc25
-rw-r--r--tests/select/unset.ys10
-rw-r--r--tests/select/unset2.ys10
6 files changed, 62 insertions, 13 deletions
diff --git a/CHANGELOG b/CHANGELOG
index f9e420a09..df8e14b26 100644
--- a/CHANGELOG
+++ b/CHANGELOG
@@ -65,6 +65,7 @@ Yosys 0.9 .. Yosys 0.9-dev
- Added "logger" pass
- Removed "dffsr2dff" (use opt_rmdff instead)
- Added "design -delete"
+ - Added "select -unset"
Yosys 0.8 .. Yosys 0.9
----------------------
diff --git a/backends/cxxrtl/cxxrtl.cc b/backends/cxxrtl/cxxrtl.cc
index d1a855bf0..e4fa430f3 100644
--- a/backends/cxxrtl/cxxrtl.cc
+++ b/backends/cxxrtl/cxxrtl.cc
@@ -1166,8 +1166,7 @@ struct CxxrtlWorker {
});
dump_attrs(memory);
- f << indent << (writable_memories[memory] ? "" : "const ")
- << "memory<" << memory->width << "> " << mangle(memory)
+ f << indent << "memory<" << memory->width << "> " << mangle(memory)
<< " { " << memory->size << "u";
if (init_cells.empty()) {
f << " };\n";
@@ -1425,8 +1424,6 @@ struct CxxrtlWorker {
if (cell->getPort(ID(CLK)).is_wire())
register_edge_signal(sigmap, cell->getPort(ID(CLK)),
cell->parameters[ID(CLK_POLARITY)].as_bool() ? RTLIL::STp : RTLIL::STn);
- // The $adff and $dffsr cells are level-sensitive, not edge-sensitive (in spite of the fact that they
- // are inferred from an edge-sensitive Verilog process) and do not correspond to an edge-type sync rule.
}
// Similar for memory port cells.
if (cell->type.in(ID($memrd), ID($memwr))) {
@@ -1642,21 +1639,30 @@ struct CxxrtlBackend : public Backend {
log("\n");
log(" write_cxxrtl [options] [filename]\n");
log("\n");
- log("Write C++ code for simulating the design. The generated code requires a driver;\n");
- log("the following simple driver is provided as an example:\n");
+ log("Write C++ code for simulating the design. The generated code requires a driver\n");
+ log("that instantiates the design, toggles its clock, and interacts with its ports.\n");
+ log("\n");
+ log("The following driver may be used as an example for a design with a single clock\n");
+ log("driving rising edge triggered flip-flops:\n");
log("\n");
log(" #include \"top.cc\"\n");
log("\n");
log(" int main() {\n");
log(" cxxrtl_design::p_top top;\n");
+ log(" top.step();\n");
log(" while (1) {\n");
- log(" top.p_clk.next = value<1> {1u};\n");
- log(" top.step();\n");
+ log(" /* user logic */\n");
log(" top.p_clk.next = value<1> {0u};\n");
log(" top.step();\n");
+ log(" top.p_clk.next = value<1> {1u};\n");
+ log(" top.step();\n");
log(" }\n");
log(" }\n");
log("\n");
+ log("Note that CXXRTL simulations, just like the hardware they are simulating, are\n");
+ log("subject to race conditions. If, in then example above, the user logic would run\n");
+ log("simultaneously with the rising edge of the clock, the design would malfunction.\n");
+ log("\n");
log("The following options are supported by this backend:\n");
log("\n");
log(" -header\n");
diff --git a/backends/cxxrtl/cxxrtl.h b/backends/cxxrtl/cxxrtl.h
index 593c31c28..fd390db79 100644
--- a/backends/cxxrtl/cxxrtl.h
+++ b/backends/cxxrtl/cxxrtl.h
@@ -604,12 +604,15 @@ struct memory {
auto _ = {std::move(std::begin(init.data), std::end(init.data), data.begin() + init.offset)...};
}
- value<Width> &operator [](size_t index) {
+ // An operator for direct memory reads. May be used at any time during the simulation.
+ const value<Width> &operator [](size_t index) const {
assert(index < data.size());
return data[index];
}
- const value<Width> &operator [](size_t index) const {
+ // An operator for direct memory writes. May only be used before the simulation is started. If used
+ // after the simulation is started, the design may malfunction.
+ value<Width> &operator [](size_t index) {
assert(index < data.size());
return data[index];
}
diff --git a/passes/cmds/select.cc b/passes/cmds/select.cc
index b64b077e4..c04ff438a 100644
--- a/passes/cmds/select.cc
+++ b/passes/cmds/select.cc
@@ -1007,6 +1007,7 @@ struct SelectPass : public Pass {
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
log("\n");
log(" select [ -add | -del | -set <name> ] {-read <filename> | <selection>}\n");
+ log(" select [ -unset <name> ]\n");
log(" select [ <assert_option> ] {-read <filename> | <selection>}\n");
log(" select [ -list | -write <filename> | -count | -clear ]\n");
log(" select -module <modname>\n");
@@ -1029,6 +1030,10 @@ struct SelectPass : public Pass {
log(" under the given name (see @<name> below). to save the current selection,\n");
log(" use \"select -set <name> %%\"\n");
log("\n");
+ log(" -unset <name>\n");
+ log(" do not modify the current selection. instead remove a previously saved\n");
+ log(" selection under the given name (see @<name> below).");
+ log("\n");
log(" -assert-none\n");
log(" do not modify the current selection. instead assert that the given\n");
log(" selection is empty. i.e. produce an error if any object matching the\n");
@@ -1238,7 +1243,7 @@ struct SelectPass : public Pass {
int assert_max = -1;
int assert_min = -1;
std::string write_file, read_file;
- std::string set_name, sel_str;
+ std::string set_name, unset_name, sel_str;
work_stack.clear();
@@ -1310,6 +1315,10 @@ struct SelectPass : public Pass {
set_name = RTLIL::escape_id(args[++argidx]);
continue;
}
+ if (arg == "-unset" && argidx+1 < args.size()) {
+ unset_name = RTLIL::escape_id(args[++argidx]);
+ continue;
+ }
if (arg.size() > 0 && arg[0] == '-')
log_cmd_error("Unknown option %s.\n", arg.c_str());
bool disable_empty_warning = count_mode || assert_none || assert_any || (assert_count != -1) || (assert_max != -1) || (assert_min != -1);
@@ -1358,8 +1367,11 @@ struct SelectPass : public Pass {
if ((list_mode || !write_file.empty() || count_mode) && (add_mode || del_mode || assert_none || assert_any || assert_count >= 0 || assert_max >= 0 || assert_min >= 0))
log_cmd_error("Options -list, -write and -count can not be combined with -add, -del, -assert-none, -assert-any, assert-count, -assert-max, or -assert-min.\n");
- if (!set_name.empty() && (list_mode || !write_file.empty() || count_mode || add_mode || del_mode || assert_none || assert_any || assert_count >= 0 || assert_max >= 0 || assert_min >= 0))
- log_cmd_error("Option -set can not be combined with -list, -write, -count, -add, -del, -assert-none, -assert-any, -assert-count, -assert-max, or -assert-min.\n");
+ if (!set_name.empty() && (list_mode || !write_file.empty() || count_mode || add_mode || !unset_name.empty() || del_mode || assert_none || assert_any || assert_count >= 0 || assert_max >= 0 || assert_min >= 0))
+ log_cmd_error("Option -set can not be combined with -list, -write, -count, -add, -del, -unset, -assert-none, -assert-any, -assert-count, -assert-max, or -assert-min.\n");
+
+ if (!unset_name.empty() && (list_mode || !write_file.empty() || count_mode || add_mode || !set_name.empty() || del_mode || assert_none || assert_any || assert_count >= 0 || assert_max >= 0 || assert_min >= 0))
+ log_cmd_error("Option -unset can not be combined with -list, -write, -count, -add, -del, -set, -assert-none, -assert-any, -assert-count, -assert-max, or -assert-min.\n");
if (work_stack.size() == 0 && got_module) {
RTLIL::Selection sel;
@@ -1527,6 +1539,13 @@ struct SelectPass : public Pass {
return;
}
+ if (!unset_name.empty())
+ {
+ if (!design->selection_vars.erase(unset_name))
+ log_error("Selection '%s' does not exist!\n", unset_name.c_str());
+ return;
+ }
+
if (work_stack.size() == 0) {
RTLIL::Selection &sel = design->selection_stack.back();
if (sel.full_selection)
diff --git a/tests/select/unset.ys b/tests/select/unset.ys
new file mode 100644
index 000000000..4f60781c2
--- /dev/null
+++ b/tests/select/unset.ys
@@ -0,0 +1,10 @@
+read_verilog <<EOT
+module top(input i, output o);
+assign o = i;
+endmodule
+EOT
+select -set foo w:*
+select -assert-any @foo
+select -unset foo
+logger -expect error "Selection '\\foo' does not exist!" 1
+select -unset foo
diff --git a/tests/select/unset2.ys b/tests/select/unset2.ys
new file mode 100644
index 000000000..456b84c22
--- /dev/null
+++ b/tests/select/unset2.ys
@@ -0,0 +1,10 @@
+read_verilog <<EOT
+module top(input i, output o);
+assign o = i;
+endmodule
+EOT
+select -set foo w:*
+select -assert-any @foo
+select -unset foo
+logger -expect error "Selection @foo is not defined!" 1
+select -list @foo
generated by cgit v1.2.3 (git 2.25.1) at 2025-04-03 17:00:28 +0000