diff options
| -rw-r--r-- | examples/gowin/demo.cst | 51 | ||||
| -rw-r--r-- | examples/gowin/demo.v | 4 | ||||
| -rw-r--r-- | examples/gowin/device.cfg | 16 | ||||
| -rw-r--r-- | examples/gowin/pnr.cfg | 8 | ||||
| -rw-r--r-- | examples/gowin/run.sh | 3 | ||||
| -rw-r--r-- | examples/gowin/run.tcl | 9 | ||||
| -rw-r--r-- | techlibs/gowin/Makefile.inc | 10 | ||||
| -rw-r--r-- | techlibs/gowin/arith_map.v | 2 | ||||
| -rw-r--r-- | techlibs/gowin/bram.txt | 3 | ||||
| -rwxr-xr-x | techlibs/gowin/brams_init.py | 8 | ||||
| -rw-r--r-- | techlibs/gowin/brams_map.v | 43 | ||||
| -rw-r--r-- | techlibs/gowin/cells_map.v | 47 | ||||
| -rw-r--r-- | techlibs/gowin/cells_sim.v | 113 | ||||
| -rw-r--r-- | techlibs/gowin/synth_gowin.cc | 6 |
14 files changed, 252 insertions, 71 deletions
diff --git a/examples/gowin/demo.cst b/examples/gowin/demo.cst index 22d7eb668..c8f89dcf8 100644 --- a/examples/gowin/demo.cst +++ b/examples/gowin/demo.cst @@ -1,41 +1,10 @@ -// 50 MHz Clock -IO_LOC "clk" D11; - -// LEDs -IO_LOC "leds[0]" D22; -IO_LOC "leds[1]" E22; -IO_LOC "leds[2]" G22; -IO_LOC "leds[3]" J22; -IO_LOC "leds[4]" L22; -IO_LOC "leds[5]" L19; -IO_LOC "leds[6]" L20; -IO_LOC "leds[7]" M21; -IO_LOC "leds[8]" N19; -IO_LOC "leds[9]" R19; -IO_LOC "leds[10]" T18; -IO_LOC "leds[11]" AA22; -IO_LOC "leds[12]" U18; -IO_LOC "leds[13]" V20; -IO_LOC "leds[14]" AA21; -IO_LOC "leds[15]" AB21; - - -// 7-Segment Display -IO_LOC "seg7dig[0]" E20; -IO_LOC "seg7dig[1]" G18; -IO_LOC "seg7dig[2]" G20; -IO_LOC "seg7dig[3]" F21; -IO_LOC "seg7dig[4]" J20; -IO_LOC "seg7dig[5]" H21; -IO_LOC "seg7dig[6]" H18; -IO_LOC "seg7dig[7]" D20; -IO_LOC "seg7sel[0]" C19; -IO_LOC "seg7sel[1]" B22; -IO_LOC "seg7sel[2]" C20; -IO_LOC "seg7sel[3]" C21; - -// Switches -IO_LOC "sw[0]" AB20; -IO_LOC "sw[1]" AB19; -IO_LOC "sw[2]" AB18; -IO_LOC "sw[3]" AB17; +IO_LOC "clk" 35; +//IO_LOC "rst_n" 77; +IO_LOC "leds[0]" 79; +IO_LOC "leds[1]" 80; +IO_LOC "leds[2]" 81; +IO_LOC "leds[3]" 82; +IO_LOC "leds[4]" 83; +IO_LOC "leds[5]" 84; +IO_LOC "leds[6]" 85; +IO_LOC "leds[7]" 86;
\ No newline at end of file diff --git a/examples/gowin/demo.v b/examples/gowin/demo.v index 6ea108384..485fec97f 100644 --- a/examples/gowin/demo.v +++ b/examples/gowin/demo.v @@ -1,9 +1,7 @@ module demo ( input clk, - input [3:0] sw, output [15:0] leds, - output [7:0] seg7dig, - output [3:0] seg7sel + output unused ); localparam PRESCALE = 20; reg [PRESCALE+3:0] counter = 0; diff --git a/examples/gowin/device.cfg b/examples/gowin/device.cfg new file mode 100644 index 000000000..f6ab82159 --- /dev/null +++ b/examples/gowin/device.cfg @@ -0,0 +1,16 @@ +set JTAG regular_io = false +set SSPI regular_io = false +set MSPI regular_io = false +set READY regular_io = false +set DONE regular_io = false +set RECONFIG_N regular_io = false +set MODE regular_io = false +set CRC_check = true +set compress = false +set encryption = false +set security_bit_enable = true +set bsram_init_fuse_print = true +set download_speed = 250/100 +set spi_flash_address = 0x00FFF000 +set format = txt +set background_programming = false diff --git a/examples/gowin/pnr.cfg b/examples/gowin/pnr.cfg new file mode 100644 index 000000000..a1b43cc3b --- /dev/null +++ b/examples/gowin/pnr.cfg @@ -0,0 +1,8 @@ +-sdf +-oc +-ibs +-posp +-o +-warning_all +-tt +-timing diff --git a/examples/gowin/run.sh b/examples/gowin/run.sh index 33a7b5c37..cd260101e 100644 --- a/examples/gowin/run.sh +++ b/examples/gowin/run.sh @@ -1,8 +1,7 @@ #!/bin/bash set -ex yosys -p "synth_gowin -top demo -vout demo_syn.v" demo.v -$GOWIN_HOME/bin/gowin -d demo_syn.v -cst demo.cst -sdc demo.sdc -p GW2A55-PBGA484-6 \ - -warning_all -out demo_out.v -rpt demo.rpt -tr demo_tr.html -bit demo.bit +$GOWIN_HOME/bin/gowin -d demo_syn.v -cst demo.cst -sdc demo.sdc -p GW1NR-9-QFN88-6 -pn GW1NR-LV9QN88C6/I5 -cfg device.cfg -bit -tr -ph -timing -gpa -rpt -warning_all # post place&route simulation (icarus verilog) if false; then diff --git a/examples/gowin/run.tcl b/examples/gowin/run.tcl new file mode 100644 index 000000000..39da11cee --- /dev/null +++ b/examples/gowin/run.tcl @@ -0,0 +1,9 @@ +# gw_sh run.tcl +exec yosys -p "synth_gowin -top demo -vout demo_syn.v" demo.v +add_file -cst demo.cst +add_file -sdc demo.sdc +add_file -vm demo_syn.v +add_file -cfg device.cfg +set_option -device GW1NR-9-QFN88-6 +set_option -pn GW1NR-LV9QN88C6/I5 +run_pnr -opt pnr.cfg diff --git a/techlibs/gowin/Makefile.inc b/techlibs/gowin/Makefile.inc index 6f2159349..d2853704b 100644 --- a/techlibs/gowin/Makefile.inc +++ b/techlibs/gowin/Makefile.inc @@ -15,3 +15,13 @@ $(eval $(call add_share_file,share/gowin,techlibs/gowin/dram.txt)) $(eval $(call add_share_file,share/gowin,techlibs/gowin/brams_init3.vh)) +EXTRA_OBJS += techlibs/gowin/brams_init.mk +.SECONDARY: techlibs/gowin/brams_init.mk + +techlibs/gowin/brams_init.mk: techlibs/gowin/brams_init.py + $(Q) mkdir -p techlibs/gowin + $(P) python3 $< + $(Q) touch $@ + +techlibs/gowin/bram_init_16.vh: techlibs/gowin/brams_init.mk +$(eval $(call add_gen_share_file,share/gowin,techlibs/gowin/bram_init_16.vh)) diff --git a/techlibs/gowin/arith_map.v b/techlibs/gowin/arith_map.v index e15de6423..af805b254 100644 --- a/techlibs/gowin/arith_map.v +++ b/techlibs/gowin/arith_map.v @@ -45,7 +45,7 @@ module _80_gw1n_alu(A, B, CI, BI, X, Y, CO); genvar i; generate for (i = 0; i < Y_WIDTH; i = i + 1) begin:slice - ALU #(.ALU_MODE(32'b0)) + ALU #(.ALU_MODE(0)) alu(.I0(AA[i]), .I1(BB[i]), .I3(1'b0), diff --git a/techlibs/gowin/bram.txt b/techlibs/gowin/bram.txt index b5f9a981c..366a7106e 100644 --- a/techlibs/gowin/bram.txt +++ b/techlibs/gowin/bram.txt @@ -1,6 +1,5 @@ bram $__GW1NR_SDP -# uncomment when done -# init 1 + init 1 abits 10 @a10d18 dbits 16 @a10d18 abits 11 @a11d9 diff --git a/techlibs/gowin/brams_init.py b/techlibs/gowin/brams_init.py new file mode 100755 index 000000000..b78eb8da5 --- /dev/null +++ b/techlibs/gowin/brams_init.py @@ -0,0 +1,8 @@ +#!/usr/bin/env python3 + +with open("techlibs/gowin/bram_init_16.vh", "w") as f: + for i in range(0, 0x40): + low = i << 8 + hi = ((i+1) << 8)-1 + snippet = "INIT[%d:%d]" % (hi, low) + print(".INIT_RAM_%02X({%s})," % (i, snippet), file=f) diff --git a/techlibs/gowin/brams_map.v b/techlibs/gowin/brams_map.v index e963cfa88..6c5e4733a 100644 --- a/techlibs/gowin/brams_map.v +++ b/techlibs/gowin/brams_map.v @@ -8,26 +8,28 @@ module \$__GW1NR_SDP (CLK2, CLK3, A1ADDR, A1DATA, A1EN, B1ADDR, B1DATA, B1EN); parameter CFG_ABITS = 10; parameter CFG_DBITS = 16; - parameter CFG_ENABLE_A = 3; - - parameter [16383:0] INIT = 16384'hx; - parameter CLKPOL2 = 1; - parameter CLKPOL3 = 1; + parameter CFG_ENABLE_A = 1; + parameter [16383:0] INIT = 16384'hx; + parameter CLKPOL2 = 1; + parameter CLKPOL3 = 1; input CLK2; input CLK3; input [CFG_ABITS-1:0] A1ADDR; input [CFG_DBITS-1:0] A1DATA; - input [CFG_ENABLE_A-1:0] A1EN; + input [CFG_ENABLE_A-1:0] A1EN; input [CFG_ABITS-1:0] B1ADDR; output [CFG_DBITS-1:0] B1DATA; input B1EN; + wire [31-CFG_DBITS:0] open; + generate if (CFG_DBITS == 1) begin SDP #( + `include "bram_init_16.vh" .READ_MODE(0), .BIT_WIDTH_0(1), .BIT_WIDTH_1(1), @@ -38,10 +40,14 @@ module \$__GW1NR_SDP (CLK2, CLK3, A1ADDR, A1DATA, A1EN, B1ADDR, B1DATA, B1EN); .WREA(A1EN), .OCE(1'b0), .CEA(1'b1), .WREB(1'b0), .CEB(B1EN), .RESETA(1'b0), .RESETB(1'b0), .BLKSEL(3'b000), - .DI(A1DATA), .DO(B1DATA), .ADA(A1ADDR), .ADB(B1ADDR) + .DI({{(32-CFG_DBITS){1'b0}}, A1DATA}), + .DO({open, B1DATA}), + .ADA({A1ADDR, {(14-CFG_ABITS){1'b0}}}), + .ADB({B1ADDR, {(14-CFG_ABITS){1'b0}}}) ); end else if (CFG_DBITS == 2) begin SDP #( + `include "bram_init_16.vh" .READ_MODE(0), .BIT_WIDTH_0(2), .BIT_WIDTH_1(2), @@ -52,10 +58,14 @@ module \$__GW1NR_SDP (CLK2, CLK3, A1ADDR, A1DATA, A1EN, B1ADDR, B1DATA, B1EN); .WREA(A1EN), .OCE(1'b0), .CEA(1'b1), .WREB(1'b0), .CEB(B1EN), .RESETA(1'b0), .RESETB(1'b0), .BLKSEL(3'b000), - .DI(A1DATA), .DO(B1DATA), .ADA(A1ADDR), .ADB(B1ADDR) + .DI({{(32-CFG_DBITS){1'b0}}, A1DATA}), + .DO({open, B1DATA}), + .ADA({A1ADDR, {(14-CFG_ABITS){1'b0}}}), + .ADB({B1ADDR, {(14-CFG_ABITS){1'b0}}}) ); end else if (CFG_DBITS <= 4) begin SDP #( + `include "bram_init_16.vh" .READ_MODE(0), .BIT_WIDTH_0(4), .BIT_WIDTH_1(4), @@ -66,10 +76,14 @@ module \$__GW1NR_SDP (CLK2, CLK3, A1ADDR, A1DATA, A1EN, B1ADDR, B1DATA, B1EN); .WREA(A1EN), .OCE(1'b0), .WREB(1'b0), .CEB(B1EN), .CEA(1'b1), .RESETA(1'b0), .RESETB(1'b0), .BLKSEL(3'b000), - .DI(A1DATA), .DO(B1DATA), .ADA(A1ADDR), .ADB(B1ADDR) + .DI({{(32-CFG_DBITS){1'b0}}, A1DATA}), + .DO({open, B1DATA}), + .ADA({A1ADDR, {(14-CFG_ABITS){1'b0}}}), + .ADB({B1ADDR, {(14-CFG_ABITS){1'b0}}}) ); end else if (CFG_DBITS <= 8) begin SDP #( + `include "bram_init_16.vh" .READ_MODE(0), .BIT_WIDTH_0(8), .BIT_WIDTH_1(8), @@ -80,10 +94,14 @@ module \$__GW1NR_SDP (CLK2, CLK3, A1ADDR, A1DATA, A1EN, B1ADDR, B1DATA, B1EN); .WREA(A1EN), .OCE(1'b0), .CEA(1'b1), .WREB(1'b0), .CEB(B1EN), .RESETA(1'b0), .RESETB(1'b0), .BLKSEL(3'b000), - .DI(A1DATA), .DO(B1DATA), .ADA(A1ADDR), .ADB(B1ADDR) + .DI({{(32-CFG_DBITS){1'b0}}, A1DATA}), + .DO({open, B1DATA}), + .ADA({A1ADDR, {(14-CFG_ABITS){1'b0}}}), + .ADB({B1ADDR, {(14-CFG_ABITS){1'b0}}}) ); end else if (CFG_DBITS <= 16) begin SDP #( + `include "bram_init_16.vh" .READ_MODE(0), .BIT_WIDTH_0(16), .BIT_WIDTH_1(16), @@ -94,7 +112,10 @@ module \$__GW1NR_SDP (CLK2, CLK3, A1ADDR, A1DATA, A1EN, B1ADDR, B1DATA, B1EN); .WREA(A1EN), .OCE(1'b0), .WREB(1'b0), .CEB(B1EN), .CEA(1'b1), .RESETA(1'b0), .RESETB(1'b0), .BLKSEL(3'b000), - .DI(A1DATA), .DO(B1DATA), .ADA(A1ADDR), .ADB(B1ADDR) + .DI({{(32-CFG_DBITS){1'b0}}, A1DATA}), + .DO({open, B1DATA}), + .ADA({A1ADDR, {(12-CFG_ABITS){1'b0}}, 2'b11}), + .ADB({B1ADDR, {(14-CFG_ABITS){1'b0}}}) ); end else begin wire TECHMAP_FAIL = 1'b1; diff --git a/techlibs/gowin/cells_map.v b/techlibs/gowin/cells_map.v index ebdc88a0a..dc0e16db8 100644 --- a/techlibs/gowin/cells_map.v +++ b/techlibs/gowin/cells_map.v @@ -1,9 +1,54 @@ +// TODO add these DFF types +// Primitive Description +// DFFSE D Flip-Flop with Clock Enable and Synchronous Set +// DFFRE D Flip-Flop with Clock Enable and Synchronous Reset + +// DFFNS D Flip-Flop with Negative-Edge Clock and Synchronous Set +// DFFNSE D Flip-Flop with Negative-Edge Clock,Clock Enable,and Synchronous Set +// DFFNR D Flip-Flop with Negative-Edge Clock and Synchronous Reset +// DFFNRE D Flip-Flop with Negative-Edge Clock,Clock Enable, and Synchronous Reset +// DFFNP D Flip-Flop with Negative-Edge Clock and Asynchronous Preset +// DFFNPE D Flip-Flop with Negative-Edge Clock,Clock Enable, and Asynchronous Preset +// DFFNC D Flip-Flop with Negative-Edge Clock and Asynchronous Clear +// DFFNCE D Flip-Flop with Negative-Edge Clock,Clock Enable and Asynchronous Clear + +//TODO all DFF* have INIT + +// DFFN D Flip-Flop with Negative-Edge Clock module \$_DFF_N_ (input D, C, output Q); DFFN _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C)); endmodule +// DFF D Flip-Flop module \$_DFF_P_ #(parameter INIT = 1'b0) (input D, C, output Q); DFF #(.INIT(INIT)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C)); endmodule +// DFFE D Flip-Flop with Clock Enable +module \$_DFFE_PP_ (input D, C, E, output Q); DFFE _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .CE(E)); endmodule +module \$_DFFE_PN_ (input D, C, E, output Q); DFFE _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .CE(!E)); endmodule + +// DFFNE D Flip-Flop with Negative-Edge Clock and Clock Enable +module \$_DFFE_NP_ (input D, C, E, output Q); DFFNE _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .CE(E)); endmodule +module \$_DFFE_NN_ (input D, C, E, output Q); DFFNE _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .CE(!E)); endmodule + +// DFFR D Flip-Flop with Synchronous Reset module \$__DFFS_PN0_ (input D, C, R, output Q); DFFR _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .RESET(!R)); endmodule module \$__DFFS_PP0_ (input D, C, R, output Q); DFFR _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .RESET(R)); endmodule -module \$__DFFS_PP1_ (input D, C, R, output Q); DFFR _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .RESET(R)); endmodule + +// DFFS D Flip-Flop with Synchronous Set +module \$__DFFS_PN1_ (input D, C, R, output Q); DFFS _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .SET(!R)); endmodule +module \$__DFFS_PP1_ (input D, C, R, output Q); DFFS _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .SET(R)); endmodule + +// DFFP D Flip-Flop with Asynchronous Preset +module \$_DFF_PP1_ (input D, C, R, output Q); DFFP _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .PRESET(R)); endmodule +module \$_DFF_PN1_ (input D, C, R, output Q); DFFP _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .PRESET(!R)); endmodule +// DFFC D Flip-Flop with Asynchronous Clear +module \$_DFF_PP0_ (input D, C, R, output Q); DFFC _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .CLEAR(R)); endmodule +module \$_DFF_PN0_ (input D, C, R, output Q); DFFC _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .CLEAR(!R)); endmodule + +// DFFPE D Flip-Flop with Clock Enable and Asynchronous Preset +module \$__DFFE_PP1 (input D, C, R, E, output Q); DFFPE _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .PRESET(R), .CE(E)); endmodule +module \$__DFFE_PN1 (input D, C, R, E, output Q); DFFPE _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .PRESET(!R), .CE(E)); endmodule +// DFFCE D Flip-Flop with Clock Enable and Asynchronous Clear +module \$__DFFE_PP0 (input D, C, R, E, output Q); DFFCE _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .CLEAR(R), .CE(E)); endmodule +module \$__DFFE_PN0 (input D, C, R, E, output Q); DFFCE _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .CLEAR(!R), .CE(E)); endmodule + module \$lut (A, Y); parameter WIDTH = 0; diff --git a/techlibs/gowin/cells_sim.v b/techlibs/gowin/cells_sim.v index ebb238bad..de0cfa9f3 100644 --- a/techlibs/gowin/cells_sim.v +++ b/techlibs/gowin/cells_sim.v @@ -38,17 +38,114 @@ module DFFN (output reg Q, input CLK, D); Q <= D; endmodule + +module DFFE (output reg Q, input D, CLK, CE); + parameter [0:0] INIT = 1'b0; + initial Q = INIT; + always @(posedge CLK) begin + if (CE) + Q <= D; + end +endmodule // DFFE (positive clock edge; clock enable) + + +module DFFS (output reg Q, input D, CLK, SET); + parameter [0:0] INIT = 1'b0; + initial Q = INIT; + always @(posedge CLK) begin + if (SET) + Q <= 1'b1; + else + Q <= D; + end +endmodule // DFFS (positive clock edge; synchronous set) + + +module DFFSE (output reg Q, input D, CLK, CE, SET); + parameter [0:0] INIT = 1'b0; + initial Q = INIT; + always @(posedge CLK) begin + if (SET) + Q <= 1'b1; + else if (CE) + Q <= D; +end +endmodule // DFFSE (positive clock edge; synchronous set takes precedence over clock enable) + + module DFFR (output reg Q, input D, CLK, RESET); - parameter [0:0] INIT = 1'b0; - initial Q = INIT; - always @(posedge CLK) begin - if (RESET) - Q <= 1'b0; - else - Q <= D; - end + parameter [0:0] INIT = 1'b0; + initial Q = INIT; + always @(posedge CLK) begin + if (RESET) + Q <= 1'b0; + else + Q <= D; + end endmodule // DFFR (positive clock edge; synchronous reset) + +module DFFRE (output reg Q, input D, CLK, CE, RESET); + parameter [0:0] INIT = 1'b0; + initial Q = INIT; + always @(posedge CLK) begin + if (RESET) + Q <= 1'b0; + else if (CE) + Q <= D; + end +endmodule // DFFRE (positive clock edge; synchronous reset takes precedence over clock enable) + + +module DFFP (output reg Q, input D, CLK, PRESET); + parameter [0:0] INIT = 1'b0; + initial Q = INIT; + always @(posedge CLK or posedge PRESET) begin + if(PRESET) + Q <= 1'b1; + else + Q <= D; + end +endmodule // DFFP (positive clock edge; asynchronous preset) + + +module DFFPE (output reg Q, input D, CLK, CE, PRESET); + parameter [0:0] INIT = 1'b0; + initial Q = INIT; + always @(posedge CLK or posedge PRESET) begin + if(PRESET) + Q <= 1'b1; + else if (CE) + Q <= D; + end +endmodule // DFFPE (positive clock edge; asynchronous preset; clock enable) + + +module DFFC (output reg Q, input D, CLK, CLEAR); + parameter [0:0] INIT = 1'b0; + initial Q = INIT; + always @(posedge CLK or posedge CLEAR) begin + if(CLEAR) + Q <= 1'b0; + else + Q <= D; + end +endmodule // DFFC (positive clock edge; asynchronous clear) + + +module DFFCE (output reg Q, input D, CLK, CE, CLEAR); + parameter [0:0] INIT = 1'b0; + initial Q = INIT; + always @(posedge CLK or posedge CLEAR) begin + if(CLEAR) + Q <= 1'b0; + else if (CE) + Q <= D; + end +endmodule // DFFCE (positive clock edge; asynchronous clear; clock enable) + +// TODO add more DFF sim cells + module VCC(output V); assign V = 1; endmodule diff --git a/techlibs/gowin/synth_gowin.cc b/techlibs/gowin/synth_gowin.cc index ac3dbfb29..e93225fab 100644 --- a/techlibs/gowin/synth_gowin.cc +++ b/techlibs/gowin/synth_gowin.cc @@ -186,6 +186,7 @@ struct SynthGowinPass : public ScriptPass run("techmap -map +/techmap.v"); if (retime || help_mode) run("abc -dff", "(only if -retime)"); + run("splitnets"); } if (check_label("map_ffs")) @@ -209,7 +210,8 @@ struct SynthGowinPass : public ScriptPass if (check_label("map_cells")) { run("techmap -map +/gowin/cells_map.v"); - run("hilomap -hicell VCC V -locell GND G"); + run("setundef -undriven -params -zero"); + run("hilomap -singleton -hicell VCC V -locell GND G"); run("iopadmap -bits -inpad IBUF O:I -outpad OBUF I:O", "(unless -noiopads)"); run("dffinit -ff DFF Q INIT"); run("clean"); @@ -226,7 +228,7 @@ struct SynthGowinPass : public ScriptPass if (check_label("vout")) { if (!vout_file.empty() || help_mode) - run(stringf("write_verilog -nodec -attr2comment -defparam -renameprefix gen %s", + run(stringf("write_verilog -decimal -attr2comment -defparam -renameprefix gen %s", help_mode ? "<file-name>" : vout_file.c_str())); } } |