diff options
| -rw-r--r-- | frontends/json/jsonparse.cc | 1 | ||||
| -rw-r--r-- | techlibs/coolrunner2/cells_sim.v | 68 |
2 files changed, 67 insertions, 2 deletions
diff --git a/frontends/json/jsonparse.cc b/frontends/json/jsonparse.cc index 10d26c244..d34a27944 100644 --- a/frontends/json/jsonparse.cc +++ b/frontends/json/jsonparse.cc @@ -271,6 +271,7 @@ void json_import(Design *design, string &modname, JsonNode *node) port_wire->port_output = true; } else if (port_direction_node->data_string == "inout") { + port_wire->port_input = true; port_wire->port_output = true; } else log_error("JSON port node '%s' has invalid '%s' direction attribute.\n", log_id(port_name), port_direction_node->data_string.c_str()); diff --git a/techlibs/coolrunner2/cells_sim.v b/techlibs/coolrunner2/cells_sim.v index e08ee5f9b..562fb1efd 100644 --- a/techlibs/coolrunner2/cells_sim.v +++ b/techlibs/coolrunner2/cells_sim.v @@ -143,17 +143,21 @@ module BUFG(I, O); endmodule module BUFGSR(I, O); + parameter INVERT = 0; + input I; output O; - assign O = I; + assign O = INVERT ? ~I : I; endmodule module BUFGTS(I, O); + parameter INVERT = 0; + input I; output O; - assign O = I; + assign O = INVERT ? ~I : I; endmodule module FDDCP (C, PRE, CLR, D, Q); @@ -244,3 +248,63 @@ module FTDCP (C, PRE, CLR, T, Q); assign Q = Q_; endmodule + +module FDCPE (C, PRE, CLR, D, Q, CE); + parameter INIT = 0; + + input C, PRE, CLR, D, CE; + output reg Q; + + initial begin + Q <= INIT; + end + + always @(posedge C, posedge PRE, posedge CLR) begin + if (CLR == 1) + Q <= 0; + else if (PRE == 1) + Q <= 1; + else if (CE == 1) + Q <= D; + end +endmodule + +module FDCPE_N (C, PRE, CLR, D, Q, CE); + parameter INIT = 0; + + input C, PRE, CLR, D, CE; + output reg Q; + + initial begin + Q <= INIT; + end + + always @(negedge C, posedge PRE, posedge CLR) begin + if (CLR == 1) + Q <= 0; + else if (PRE == 1) + Q <= 1; + else if (CE == 1) + Q <= D; + end +endmodule + +module FDDCPE (C, PRE, CLR, D, Q, CE); + parameter INIT = 0; + + input C, PRE, CLR, D, CE; + output reg Q; + + initial begin + Q <= INIT; + end + + always @(posedge C, negedge C, posedge PRE, posedge CLR) begin + if (CLR == 1) + Q <= 0; + else if (PRE == 1) + Q <= 1; + else if (CE == 1) + Q <= D; + end +endmodule |