diff options
| -rw-r--r-- | backends/aiger/xaiger.cc | 2 | ||||
| -rw-r--r-- | frontends/aiger/aigerparse.cc | 2 | ||||
| -rw-r--r-- | passes/techmap/abc9.cc | 4 | ||||
| -rw-r--r-- | passes/techmap/techmap.cc | 8 | ||||
| -rw-r--r-- | techlibs/xilinx/abc9_map.v | 18 | ||||
| -rw-r--r-- | techlibs/xilinx/abc9_unmap.v | 1 |
6 files changed, 14 insertions, 21 deletions
diff --git a/backends/aiger/xaiger.cc b/backends/aiger/xaiger.cc index 09b5586fe..4547b9c09 100644 --- a/backends/aiger/xaiger.cc +++ b/backends/aiger/xaiger.cc @@ -254,7 +254,7 @@ struct XAigerWriter log_assert(!holes_mode); - if (cell->type == "$__ABC_FF_") + if (cell->type == "$__ABC9_FF_") { SigBit D = sigmap(cell->getPort("\\D").as_bit()); SigBit Q = sigmap(cell->getPort("\\Q").as_bit()); diff --git a/frontends/aiger/aigerparse.cc b/frontends/aiger/aigerparse.cc index 77a49c34f..4b66af3ad 100644 --- a/frontends/aiger/aigerparse.cc +++ b/frontends/aiger/aigerparse.cc @@ -833,7 +833,7 @@ void AigerReader::post_process() log_assert(q->port_input); q->port_input = false; - auto ff = module->addCell(NEW_ID, "$__ABC_FF_"); + auto ff = module->addCell(NEW_ID, "$__ABC9_FF_"); ff->setPort("\\D", d); ff->setPort("\\Q", q); flop_count++; diff --git a/passes/techmap/abc9.cc b/passes/techmap/abc9.cc index 87235f1a7..0dbe70a68 100644 --- a/passes/techmap/abc9.cc +++ b/passes/techmap/abc9.cc @@ -459,7 +459,7 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *module, std::string scrip dict<IdString, bool> abc9_box; vector<RTLIL::Cell*> boxes; for (auto cell : module->selected_cells()) { - if (cell->type.in(ID($_AND_), ID($_NOT_), ID($__ABC_FF_))) { + if (cell->type.in(ID($_AND_), ID($_NOT_), ID($__ABC9_FF_))) { module->remove(cell); continue; } @@ -533,7 +533,7 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *module, std::string scrip cell_stats[mapped_cell->type]++; RTLIL::Cell *existing_cell = nullptr; - if (mapped_cell->type.in(ID($lut), ID($__ABC_FF_))) { + if (mapped_cell->type.in(ID($lut), ID($__ABC9_FF_))) { if (mapped_cell->type == ID($lut) && GetSize(mapped_cell->getPort(ID::A)) == 1 && mapped_cell->getParam(ID(LUT)) == RTLIL::Const::from_string("01")) { diff --git a/passes/techmap/techmap.cc b/passes/techmap/techmap.cc index a07a2f280..0c57733d4 100644 --- a/passes/techmap/techmap.cc +++ b/passes/techmap/techmap.cc @@ -256,14 +256,6 @@ struct TechmapWorker if (w->attributes.count(ID(src))) w->add_strpool_attribute(ID(src), extra_src_attrs); } - - - if (it.second->name.begins_with("\\_TECHMAP_REPLACE_")) { - IdString replace_name = stringf("%s%s", orig_cell_name.c_str(), it.second->name.c_str() + strlen("\\_TECHMAP_REPLACE_")); - Wire *replace_w = module->addWire(replace_name, it.second); - module->connect(replace_w, w); - } - design->select(module, w); if (it.second->name.begins_with("\\_TECHMAP_REPLACE_.")) { diff --git a/techlibs/xilinx/abc9_map.v b/techlibs/xilinx/abc9_map.v index 0b81be15f..05063f86d 100644 --- a/techlibs/xilinx/abc9_map.v +++ b/techlibs/xilinx/abc9_map.v @@ -31,7 +31,7 @@ // The purpose of the following FD* rules are to wrap the flop (which, when // called with the `_ABC' macro set captures only its combinatorial // behaviour) with: -// (a) a special $__ABC_FF_ in front of the FD*'s output, indicating to abc9 +// (a) a special $__ABC9_FF_ in front of the FD*'s output, indicating to abc9 // the connectivity of its basic D-Q flop // (b) a special TECHMAP_REPLACE_.$currQ wire that will be used for feedback // into the (combinatorial) FD* cell to facilitate clock-enable behaviour @@ -50,7 +50,7 @@ module FDRE (output reg Q, input C, CE, D, R); .D(D), .Q($nextQ), .C(C), .CE(CE), .R(R) ); wire _TECHMAP_REPLACE_.$currQ = Q; - \$__ABC_FF_ abc_dff (.D($nextQ), .Q(Q)); + \$__ABC9_FF_ abc_dff (.D($nextQ), .Q(Q)); endmodule module FDRE_1 (output reg Q, input C, CE, D, R); parameter [0:0] INIT = 1'b0; @@ -61,7 +61,7 @@ module FDRE_1 (output reg Q, input C, CE, D, R); .D(D), .Q($nextQ), .C(C), .CE(CE), .R(R) ); wire _TECHMAP_REPLACE_.$currQ = Q; - \$__ABC_FF_ abc_dff (.D($nextQ), .Q(Q)); + \$__ABC9_FF_ abc_dff (.D($nextQ), .Q(Q)); endmodule module FDCE (output reg Q, input C, CE, D, CLR); @@ -79,7 +79,7 @@ module FDCE (output reg Q, input C, CE, D, CLR); .D(D), .Q($nextQ), .C(C), .CE(CE), .CLR(CLR) ); wire _TECHMAP_REPLACE_.$currQ = Q; - \$__ABC_FF_ abc_dff (.D($nextQ), .Q($currQ)); + \$__ABC9_FF_ abc_dff (.D($nextQ), .Q($currQ)); \$__ABC_ASYNC abc_async (.A($currQ), .S(CLR ^ IS_CLR_INVERTED), .Y(Q)); endmodule module FDCE_1 (output reg Q, input C, CE, D, CLR); @@ -91,7 +91,7 @@ module FDCE_1 (output reg Q, input C, CE, D, CLR); .D(D), .Q($nextQ), .C(C), .CE(CE), .CLR(CLR) ); wire _TECHMAP_REPLACE_.$currQ = Q; - \$__ABC_FF_ abc_dff (.D($nextQ), .Q($currQ)); + \$__ABC9_FF_ abc_dff (.D($nextQ), .Q($currQ)); \$__ABC_ASYNC abc_async (.A($currQ), .S(CLR), .Y(Q)); endmodule @@ -110,7 +110,7 @@ module FDPE (output reg Q, input C, CE, D, PRE); .D(D), .Q($nextQ), .C(C), .CE(CE), .PRE(PRE) ); wire _TECHMAP_REPLACE_.$currQ = Q; - \$__ABC_FF_ abc_dff (.D($nextQ), .Q($currQ)); + \$__ABC9_FF_ abc_dff (.D($nextQ), .Q($currQ)); \$__ABC_ASYNC abc_async (.A($currQ), .S(PRE ^ IS_PRE_INVERTED), .Y(Q)); endmodule module FDPE_1 (output reg Q, input C, CE, D, PRE); @@ -122,7 +122,7 @@ module FDPE_1 (output reg Q, input C, CE, D, PRE); .D(D), .Q($nextQ), .C(C), .CE(CE), .PRE(PRE) ); wire _TECHMAP_REPLACE_.$currQ = Q; - \$__ABC_FF_ abc_dff (.D($nextQ), .Q($currQ)); + \$__ABC9_FF_ abc_dff (.D($nextQ), .Q($currQ)); \$__ABC_ASYNC abc_async (.A($currQ), .S(PRE), .Y(Q)); endmodule @@ -141,7 +141,7 @@ module FDSE (output reg Q, input C, CE, D, S); .D(D), .Q($nextQ), .C(C), .CE(CE), .S(S) ); wire _TECHMAP_REPLACE_.$currQ = Q; - \$__ABC_FF_ abc_dff (.D($nextQ), .Q(Q)); + \$__ABC9_FF_ abc_dff (.D($nextQ), .Q(Q)); endmodule module FDSE_1 (output reg Q, input C, CE, D, S); parameter [0:0] INIT = 1'b0; @@ -152,7 +152,7 @@ module FDSE_1 (output reg Q, input C, CE, D, S); .D(D), .Q($nextQ), .C(C), .CE(CE), .S(S) ); wire _TECHMAP_REPLACE_.$currQ = Q; - \$__ABC_FF_ abc_dff (.D($nextQ), .Q(Q)); + \$__ABC9_FF_ abc_dff (.D($nextQ), .Q(Q)); endmodule module RAM32X1D ( diff --git a/techlibs/xilinx/abc9_unmap.v b/techlibs/xilinx/abc9_unmap.v index f97b0bc66..21fe78d08 100644 --- a/techlibs/xilinx/abc9_unmap.v +++ b/techlibs/xilinx/abc9_unmap.v @@ -26,6 +26,7 @@ endmodule module \$__ABC9_FF_ (input D, output Q); assign Q = D; +endmodule module \$__ABC9_LUT6 (input A, input [5:0] S, output Y); assign Y = A; |