diff options
| -rw-r--r-- | CHANGELOG | 18 | ||||
| -rw-r--r-- | Makefile | 4 | ||||
| -rw-r--r-- | frontends/verific/verific.cc | 21 | ||||
| -rw-r--r-- | kernel/driver.cc | 2 | ||||
| -rw-r--r-- | kernel/log.cc | 6 | ||||
| -rw-r--r-- | kernel/log.h | 1 | ||||
| -rw-r--r-- | kernel/yosys.cc | 96 | ||||
| -rw-r--r-- | manual/command-reference-manual.tex | 195 | ||||
| -rw-r--r-- | passes/cmds/stat.cc | 4 | ||||
| -rw-r--r-- | passes/cmds/tee.cc | 13 |
10 files changed, 340 insertions, 20 deletions
@@ -2,11 +2,27 @@ List of major changes and improvements between releases ======================================================= -Yosys 0.23 .. Yosys 0.23-dev +Yosys 0.24 .. Yosys 0.24-dev -------------------------- +Yosys 0.23 .. Yosys 0.24 +-------------------------- + * New commands and options + - Added option "-set-def-formal" to "sat" pass. + - Added option "-s" to "tee" command. + * Verilog - Support for module-scoped identifiers referring to tasks and functions. + - Support for arrays with swapped ranges within structs. + + * Verific support + - Support for importing verilog configurations per name. + - "verific -set-XXXXX" commands are now able to set severity to all messages + of certain type (errors, warnings, infos and comments) + + * Various + - TCL shell support (use "yosys -C") + - Added FABulous eFPGA frontend Yosys 0.22 .. Yosys 0.23 -------------------------- @@ -142,7 +142,7 @@ LDLIBS += -lrt endif endif -YOSYS_VER := 0.23+45 +YOSYS_VER := 0.24+1 # Note: We arrange for .gitcommit to contain the (short) commit hash in # tarballs generated with git-archive(1) using .gitattributes. The git repo @@ -158,7 +158,7 @@ endif OBJS = kernel/version_$(GIT_REV).o bumpversion: - sed -i "/^YOSYS_VER := / s/+[0-9][0-9]*$$/+`git log --oneline 7ce5011.. | wc -l`/;" Makefile + sed -i "/^YOSYS_VER := / s/+[0-9][0-9]*$$/+`git log --oneline 313b799.. | wc -l`/;" Makefile # set 'ABCREV = default' to use abc/ as it is # diff --git a/frontends/verific/verific.cc b/frontends/verific/verific.cc index 1e61b3a31..40f96e82c 100644 --- a/frontends/verific/verific.cc +++ b/frontends/verific/verific.cc @@ -2289,6 +2289,7 @@ std::string verific_import(Design *design, const std::map<std::string,std::strin #ifdef YOSYSHQ_VERIFIC_EXTENSIONS VerificExtensions::ElaborateAndRewrite("work", &verific_params); + verific_error_msg.clear(); #endif if (top.empty()) { @@ -2539,6 +2540,8 @@ struct VerificPass : public Pass { log("\n"); log("Set message severity. <msg_id> is the string in square brackets when a message\n"); log("is printed, such as VERI-1209.\n"); + log("Also errors, warnings, infos and comments could be used to set new severity for\n"); + log("all messages of certain type.\n"); log("\n"); log("\n"); log(" verific -import [options] <top>..\n"); @@ -2782,9 +2785,20 @@ struct VerificPass : public Pass { else log_abort(); - for (argidx++; argidx < GetSize(args); argidx++) - Message::SetMessageType(args[argidx].c_str(), new_type); - + for (argidx++; argidx < GetSize(args); argidx++) { + if (Strings::compare(args[argidx].c_str(), "errors")) { + Message::SetMessageType("VERI-1063", new_type); + Message::SetAllMessageType(VERIFIC_ERROR, new_type); + } else if (Strings::compare(args[argidx].c_str(), "warnings")) { + Message::SetAllMessageType(VERIFIC_WARNING, new_type); + } else if (Strings::compare(args[argidx].c_str(), "infos")) { + Message::SetAllMessageType(VERIFIC_INFO, new_type); + } else if (Strings::compare(args[argidx].c_str(), "comments")) { + Message::SetAllMessageType(VERIFIC_COMMENT, new_type); + } else { + Message::SetMessageType(args[argidx].c_str(), new_type); + } + } goto check_error; } @@ -3217,6 +3231,7 @@ struct VerificPass : public Pass { #ifdef YOSYSHQ_VERIFIC_EXTENSIONS VerificExtensions::ElaborateAndRewrite(work, ¶meters); + verific_error_msg.clear(); #endif if (!ppfile.empty()) veri_file::PrettyPrint(ppfile.c_str(), nullptr, work.c_str()); diff --git a/kernel/driver.cc b/kernel/driver.cc index aa90802c9..a89c790d9 100644 --- a/kernel/driver.cc +++ b/kernel/driver.cc @@ -205,6 +205,7 @@ extern char yosys_path[PATH_MAX]; #ifdef YOSYS_ENABLE_TCL namespace Yosys { extern int yosys_tcl_iterp_init(Tcl_Interp *interp); + extern void yosys_tcl_activate_repl(); }; #endif @@ -584,6 +585,7 @@ int main(int argc, char **argv) if (run_tcl_shell) { #ifdef YOSYS_ENABLE_TCL + yosys_tcl_activate_repl(); Tcl_Main(argc, argv, yosys_tcl_iterp_init); #else log_error("Can't exectue TCL shell: this version of yosys is not built with TCL support enabled.\n"); diff --git a/kernel/log.cc b/kernel/log.cc index af8c422b8..25d198744 100644 --- a/kernel/log.cc +++ b/kernel/log.cc @@ -40,6 +40,7 @@ YOSYS_NAMESPACE_BEGIN std::vector<FILE*> log_files; std::vector<std::ostream*> log_streams; +std::vector<std::string> log_scratchpads; std::map<std::string, std::set<std::string>> log_hdump; std::vector<YS_REGEX_TYPE> log_warn_regexes, log_nowarn_regexes, log_werror_regexes; dict<std::string, LogExpectedItem> log_expect_log, log_expect_warning, log_expect_error; @@ -158,6 +159,11 @@ void logv(const char *format, va_list ap) for (auto f : log_streams) *f << str; + RTLIL::Design *design = yosys_get_design(); + if (design != nullptr) + for (auto &scratchpad : log_scratchpads) + design->scratchpad[scratchpad].append(str); + static std::string linebuffer; static bool log_warn_regex_recusion_guard = false; diff --git a/kernel/log.h b/kernel/log.h index 822816cb4..35368a683 100644 --- a/kernel/log.h +++ b/kernel/log.h @@ -133,6 +133,7 @@ struct log_cmd_error_exception { }; extern std::vector<FILE*> log_files; extern std::vector<std::ostream*> log_streams; +extern std::vector<std::string> log_scratchpads; extern std::map<std::string, std::set<std::string>> log_hdump; extern std::vector<YS_REGEX_TYPE> log_warn_regexes, log_nowarn_regexes, log_werror_regexes; extern std::set<std::string> log_warnings, log_experimentals, log_experimentals_ignored; diff --git a/kernel/yosys.cc b/kernel/yosys.cc index 01085d29b..333faae6a 100644 --- a/kernel/yosys.cc +++ b/kernel/yosys.cc @@ -73,6 +73,8 @@ #include <limits.h> #include <errno.h> +#include "libs/json11/json11.hpp" + YOSYS_NAMESPACE_BEGIN int autoidx = 1; @@ -82,6 +84,7 @@ CellTypes yosys_celltypes; #ifdef YOSYS_ENABLE_TCL Tcl_Interp *yosys_tcl_interp = NULL; +bool yosys_tcl_repl_active = false; #endif std::set<std::string> yosys_input_files, yosys_output_files; @@ -709,6 +712,42 @@ void rewrite_filename(std::string &filename) } #ifdef YOSYS_ENABLE_TCL + +static Tcl_Obj *json_to_tcl(Tcl_Interp *interp, const json11::Json &json) +{ + if (json.is_null()) + return Tcl_NewStringObj("null", 4); + else if (json.is_string()) { + auto string = json.string_value(); + return Tcl_NewStringObj(string.data(), string.size()); + } else if (json.is_number()) { + double value = json.number_value(); + double round_val = std::nearbyint(value); + if (std::isfinite(round_val) && value == round_val && value >= LONG_MIN && value < -double(LONG_MIN)) + return Tcl_NewLongObj((long)round_val); + else + return Tcl_NewDoubleObj(value); + } else if (json.is_bool()) { + return Tcl_NewBooleanObj(json.bool_value()); + } else if (json.is_array()) { + auto list = json.array_items(); + Tcl_Obj *result = Tcl_NewListObj(list.size(), nullptr); + for (auto &item : list) + Tcl_ListObjAppendElement(interp, result, json_to_tcl(interp, item)); + return result; + } else if (json.is_object()) { + auto map = json.object_items(); + Tcl_Obj *result = Tcl_NewListObj(map.size() * 2, nullptr); + for (auto &item : map) { + Tcl_ListObjAppendElement(interp, result, Tcl_NewStringObj(item.first.data(), item.first.size())); + Tcl_ListObjAppendElement(interp, result, json_to_tcl(interp, item.second)); + } + return result; + } else { + log_abort(); + } +} + static int tcl_yosys_cmd(ClientData, Tcl_Interp *interp, int argc, const char *argv[]) { std::vector<std::string> args; @@ -733,12 +772,52 @@ static int tcl_yosys_cmd(ClientData, Tcl_Interp *interp, int argc, const char *a return TCL_OK; } - if (args.size() == 1) { - Pass::call(yosys_get_design(), args[0]); - return TCL_OK; + yosys_get_design()->scratchpad_unset("result.json"); + yosys_get_design()->scratchpad_unset("result.string"); + + bool in_repl = yosys_tcl_repl_active; + bool restore_log_cmd_error_throw = log_cmd_error_throw; + + log_cmd_error_throw = true; + + try { + if (args.size() == 1) { + Pass::call(yosys_get_design(), args[0]); + } else { + Pass::call(yosys_get_design(), args); + } + } catch (log_cmd_error_exception) { + if (in_repl) { + auto design = yosys_get_design(); + while (design->selection_stack.size() > 1) + design->selection_stack.pop_back(); + log_reset_stack(); + } + Tcl_SetResult(interp, (char *)"Yosys command produced an error", TCL_STATIC); + + yosys_tcl_repl_active = in_repl; + log_cmd_error_throw = restore_log_cmd_error_throw; + return TCL_ERROR; + } catch (...) { + log_error("uncaught exception during Yosys command invoked from TCL\n"); + } + + yosys_tcl_repl_active = in_repl; + log_cmd_error_throw = restore_log_cmd_error_throw; + + auto &scratchpad = yosys_get_design()->scratchpad; + auto result = scratchpad.find("result.json"); + if (result != scratchpad.end()) { + std::string err; + auto json = json11::Json::parse(result->second, err); + if (err.empty()) { + Tcl_SetObjResult(interp, json_to_tcl(interp, json)); + } else + log_warning("Ignoring result.json scratchpad value due to parse error: %s\n", err.c_str()); + } else if ((result = scratchpad.find("result.string")) != scratchpad.end()) { + Tcl_SetObjResult(interp, Tcl_NewStringObj(result->second.data(), result->second.size())); } - Pass::call(yosys_get_design(), args); return TCL_OK; } @@ -750,6 +829,11 @@ int yosys_tcl_iterp_init(Tcl_Interp *interp) return TCL_OK ; } +void yosys_tcl_activate_repl() +{ + yosys_tcl_repl_active = true; +} + extern Tcl_Interp *yosys_get_tcl_interp() { if (yosys_tcl_interp == NULL) { @@ -778,8 +862,8 @@ struct TclPass : public Pass { log("the standard $argc and $argv variables.\n"); log("\n"); log("Note, tcl will not recieve the output of any yosys command. If the output\n"); - log("of the tcl commands are needed, use the yosys command 'tee' to redirect yosys's\n"); - log("output to a temporary file.\n"); + log("of the tcl commands are needed, use the yosys command 'tee -s result.string'\n"); + log("to redirect yosys's output to the 'result.string' scratchpad value.\n"); log("\n"); } void execute(std::vector<std::string> args, RTLIL::Design *) override { diff --git a/manual/command-reference-manual.tex b/manual/command-reference-manual.tex index 17689c141..62183801d 100644 --- a/manual/command-reference-manual.tex +++ b/manual/command-reference-manual.tex @@ -764,12 +764,14 @@ When no module with the specified name is found, but there is a cell with the specified name in the current module, then this is equivalent to 'cd <celltype>'. + cd .. Remove trailing substrings that start with '.' in current module name until the name of a module in the current design is generated, then switch to that module. Otherwise clear the current selection. + cd This is just a shortcut for 'select -clear'. @@ -2166,6 +2168,13 @@ Options: -fm_set_fsm_file file -encfile file passed through to fsm_recode pass + +This pass uses a subset of FF types to detect FSMs. Run 'opt -nosdff -nodffe' +before this pass to prepare the design. + +The Verific frontend may merge multiplexers in a way that interferes with FSM +detection. Run 'verific -cfg db_infer_wide_muxes_post_elaboration 0' before +reading the source, and 'bmuxmap' after 'proc' for best results. \end{lstlisting} \section{fsm\_detect -- finding FSMs in design} @@ -2181,6 +2190,13 @@ Existing 'fsm_encoding' attributes are not changed by this pass. Signals can be protected from being detected by this pass by setting the 'fsm_encoding' attribute to "none". + +This pass uses a subset of FF types to detect FSMs. Run 'opt -nosdff -nodffe' +before this pass to prepare the design for fsm_detect. + +The Verific frontend may merge multiplexers in a way that interferes with FSM +detection. Run 'verific -cfg db_infer_wide_muxes_post_elaboration 0' before +reading the source, and 'bmuxmap' after 'proc' for best results. \end{lstlisting} \section{fsm\_expand -- expand FSM cells by merging logic into it} @@ -4435,6 +4451,9 @@ and additional constraints passed as parameters. -set-def-inputs add -set-def constraints for all module inputs + -set-def-formal + add -set-def constraints for formal $anyinit, $anyconst, $anyseq cells + -show <signal> show the model for the specified signal. if no -show option is passed then a set of signals to be shown is automatically selected. @@ -5233,7 +5252,7 @@ This command simulates the circuit using the given top-level module. -r read simulation results file File formats supported: FST, VCD, AIW and WIT - VCD support requires vcd2fst external tool to be present + VCD support requires vcd2fst external tool to be present -map <filename> read file with port and latch symbols, needed for AIGER witness input @@ -6099,6 +6118,165 @@ The following commands are executed by this synthesis command: write_json <file-name> \end{lstlisting} +\section{synth\_fabulous -- FABulous synthesis script} +\label{cmd:synth_fabulous} +\begin{lstlisting}[numbers=left,frame=single] + synth_fabulous [options] + +This command runs synthesis for FPGA fabrics generated with FABulous. This command does not operate +on partly selected designs. + + -top <module> + use the specified module as top module (default='top') + + -auto-top + automatically determine the top of the design hierarchy + + -blif <file> + write the design to the specified BLIF file. writing of an output file + is omitted if this parameter is not specified. + + -edif <file> + write the design to the specified EDIF file. writing of an output file + is omitted if this parameter is not specified. + + -json <file> + write the design to the specified JSON file. writing of an output file + is omitted if this parameter is not specified. + + -lut <k> + perform synthesis for a k-LUT architecture (default 4). + + -vpr + perform synthesis for the FABulous VPR flow (using slightly different techmapping). + + -plib <primitive_library.v> + use the specified Verilog file as a primitive library. + + -extra-plib <primitive_library.v> + use the specified Verilog file for extra primitives (can be specified multiple + times). + + -extra-map <techamp.v> + use the specified Verilog file for extra techmap rules (can be specified multiple + times). + + -encfile <file> + passed to 'fsm_recode' via 'fsm' + + -nofsm + do not run FSM optimization + + -noalumacc + do not run 'alumacc' pass. i.e. keep arithmetic operators in + their direct form ($add, $sub, etc.). + + -noregfile + do not map register files + + -iopad + enable automatic insertion of IO buffers (otherwise a wrapper + with manually inserted and constrained IO should be used.) + + -complex-dff + enable support for FFs with enable and synchronous SR (must also be + supported by the target fabric.) + + -noflatten + do not flatten design after elaboration + + -nordff + passed to 'memory'. prohibits merging of FFs into memory read ports + + -noshare + do not run SAT-based resource sharing + + -run <from_label>[:<to_label>] + only run the commands between the labels (see below). an empty + from label is synonymous to 'begin', and empty to label is + synonymous to the end of the command list. + + -no-rw-check + marks all recognized read ports as "return don't-care value on + read/write collision" (same result as setting the no_rw_check + attribute on all memories). + + +The following commands are executed by this synthesis command: + read_verilog -lib +/fabulous/prims.v + read_verilog -lib <extra_plib.v> (for each -extra-plib) + + begin: + hierarchy -check + proc + + flatten: (unless -noflatten) + flatten + tribuf -logic + deminout + + coarse: + tribuf -logic + deminout + opt_expr + opt_clean + check + opt -nodffe -nosdff + fsm (unless -nofsm) + opt + wreduce + peepopt + opt_clean + techmap -map +/cmp2lut.v -map +/cmp2lcu.v (if -lut) + alumacc (unless -noalumacc) + share (unless -noshare) + opt + memory -nomap + opt_clean + + map_ram: + memory_libmap -lib +/fabulous/ram_regfile.txt + techmap -map +/fabulous/regfile_map.v + + map_ffram: + opt -fast -mux_undef -undriven -fine + memory_map + opt -undriven -fine + + map_gates: + opt -full + techmap -map +/techmap.v + opt -fast + + map_iopad: (if -iopad) + + map_ffs: + dfflegalize -cell $_DFF_P_ 0 -cell $_DLATCH_?_ x without -complex-dff + techmap -map +/fabulous/latches_map.v + techmap -map +/fabulous/ff_map.v + techmap -map <extra_map.v>... (for each -extra-map) + clean + + map_luts: + abc -lut 4 -dress + clean + + map_cells: + techmap -D LUT_K=4 -map +/fabulous/cells_map.v + clean + + check: + hierarchy -check + stat + + blif: + opt_clean -purge + write_blif -attr -cname -conn -param <file-name> + + json: + write_json <file-name> +\end{lstlisting} + \section{synth\_gatemate -- synthesis for Cologne Chip GateMate FPGAs} \label{cmd:synth_gatemate} \begin{lstlisting}[numbers=left,frame=single] @@ -7550,8 +7728,8 @@ If any arguments are specified, these arguments are provided to the script via the standard $argc and $argv variables. Note, tcl will not recieve the output of any yosys command. If the output -of the tcl commands are needed, use the yosys command 'tee' to redirect yosys's -output to a temporary file. +of the tcl commands are needed, use the yosys command 'tee -s result.string' +to redirect yosys's output to the 'result.string' scratchpad value. \end{lstlisting} \section{techmap -- generic technology mapper} @@ -7736,6 +7914,9 @@ specified logfile(s). -a logfile Write output to this file, append if exists. + -s scratchpad + Write output to this scratchpad value, truncate if it exists. + +INT, -INT Add/subtract INT from the -v setting for this command. \end{lstlisting} @@ -8047,12 +8228,14 @@ Remove Verilog defines previously set with -vlog-define. Set message severity. <msg_id> is the string in square brackets when a message is printed, such as VERI-1209. +Also errors, warnings, infos and comments could be used to set new severity for +all messages of certain type. - verific -import [options] <top-module>.. + verific -import [options] <top>.. -Elaborate the design for the specified top modules, import to Yosys and -reset the internal state of Verific. +Elaborate the design for the specified top modules or configurations, import to +Yosys and reset the internal state of Verific. Import options: diff --git a/passes/cmds/stat.cc b/passes/cmds/stat.cc index a998ab8e7..10e98952e 100644 --- a/passes/cmds/stat.cc +++ b/passes/cmds/stat.cc @@ -452,7 +452,7 @@ struct StatPass : public Pass { if (json_mode) { log("\n"); - log(" },\n"); + log(top_mod == nullptr ? " }\n" : " },\n"); } if (top_mod != nullptr) @@ -466,7 +466,7 @@ struct StatPass : public Pass { statdata_t data = hierarchy_worker(mod_stat, top_mod->name, 0, /*quiet=*/json_mode); - if (json_mode) + if (json_mode) data.log_data_json("design", true); else if (GetSize(mod_stat) > 1) { log("\n"); diff --git a/passes/cmds/tee.cc b/passes/cmds/tee.cc index 7a1f4a36b..39ed4a7a8 100644 --- a/passes/cmds/tee.cc +++ b/passes/cmds/tee.cc @@ -45,6 +45,9 @@ struct TeePass : public Pass { log(" -a logfile\n"); log(" Write output to this file, append if exists.\n"); log("\n"); + log(" -s scratchpad\n"); + log(" Write output to this scratchpad value, truncate if it exists.\n"); + log("\n"); log(" +INT, -INT\n"); log(" Add/subtract INT from the -v setting for this command.\n"); log("\n"); @@ -53,9 +56,11 @@ struct TeePass : public Pass { { std::vector<FILE*> backup_log_files, files_to_close; std::vector<std::ostream*> backup_log_streams; + std::vector<std::string> backup_log_scratchpads; int backup_log_verbose_level = log_verbose_level; backup_log_streams = log_streams; backup_log_files = log_files; + backup_log_scratchpads = log_scratchpads; size_t argidx; for (argidx = 1; argidx < args.size(); argidx++) @@ -78,6 +83,12 @@ struct TeePass : public Pass { files_to_close.push_back(f); continue; } + if (args[argidx] == "-s" && argidx+1 < args.size()) { + auto name = args[++argidx]; + design->scratchpad[name] = ""; + log_scratchpads.push_back(name); + continue; + } if (GetSize(args[argidx]) >= 2 && (args[argidx][0] == '-' || args[argidx][0] == '+') && args[argidx][1] >= '0' && args[argidx][1] <= '9') { log_verbose_level += atoi(args[argidx].c_str()); continue; @@ -93,6 +104,7 @@ struct TeePass : public Pass { fclose(cf); log_files = backup_log_files; log_streams = backup_log_streams; + log_scratchpads = backup_log_scratchpads; throw; } @@ -102,6 +114,7 @@ struct TeePass : public Pass { log_verbose_level = backup_log_verbose_level; log_files = backup_log_files; log_streams = backup_log_streams; + log_scratchpads = backup_log_scratchpads; } } TeePass; |