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-rw-r--r--Brewfile1
-rw-r--r--backends/aiger/aiger.cc2
-rw-r--r--backends/aiger/xaiger.cc2
-rw-r--r--backends/btor/btor.cc5
-rw-r--r--backends/protobuf/protobuf.cc4
-rw-r--r--kernel/register.cc18
-rw-r--r--kernel/register.h2
-rw-r--r--passes/cmds/Makefile.inc1
-rw-r--r--passes/cmds/portlist.cc93
-rw-r--r--passes/cmds/show.cc8
-rw-r--r--passes/techmap/techmap.cc30
-rw-r--r--techlibs/xilinx/abc_xc7.box2
-rw-r--r--techlibs/xilinx/synth_xilinx.cc2
-rw-r--r--tests/ice40/adffs.v20
-rw-r--r--tests/ice40/adffs.ys13
-rwxr-xr-xtests/ice40/run-test.sh2
-rw-r--r--tests/techmap/wireinit.ys14
17 files changed, 171 insertions, 48 deletions
diff --git a/Brewfile b/Brewfile
index 4ffe50e86..8465d86f9 100644
--- a/Brewfile
+++ b/Brewfile
@@ -7,3 +7,4 @@ brew "graphviz"
brew "pkg-config"
brew "python3"
brew "tcl-tk"
+brew "xdot"
diff --git a/backends/aiger/aiger.cc b/backends/aiger/aiger.cc
index 0798fb35d..3e8b14dee 100644
--- a/backends/aiger/aiger.cc
+++ b/backends/aiger/aiger.cc
@@ -777,7 +777,7 @@ struct AigerBackend : public Backend {
}
break;
}
- extra_args(f, filename, args, argidx);
+ extra_args(f, filename, args, argidx, !ascii_mode);
Module *top_module = design->top_module();
diff --git a/backends/aiger/xaiger.cc b/backends/aiger/xaiger.cc
index 5e49f3c80..4018cc9de 100644
--- a/backends/aiger/xaiger.cc
+++ b/backends/aiger/xaiger.cc
@@ -856,7 +856,7 @@ struct XAigerBackend : public Backend {
}
break;
}
- extra_args(f, filename, args, argidx);
+ extra_args(f, filename, args, argidx, !ascii_mode);
Module *top_module = design->top_module();
diff --git a/backends/btor/btor.cc b/backends/btor/btor.cc
index 4472993d4..f617b7ec2 100644
--- a/backends/btor/btor.cc
+++ b/backends/btor/btor.cc
@@ -897,9 +897,12 @@ struct BtorWorker
int sid = get_bv_sid(GetSize(s));
int nid = next_nid++;
- btorf("%d input %d %s\n", nid, sid);
+ btorf("%d input %d\n", nid, sid);
nid_width[nid] = GetSize(s);
+ for (int j = 0; j < GetSize(s); j++)
+ nidbits.push_back(make_pair(nid, j));
+
i += GetSize(s)-1;
continue;
}
diff --git a/backends/protobuf/protobuf.cc b/backends/protobuf/protobuf.cc
index fff110bb0..671686173 100644
--- a/backends/protobuf/protobuf.cc
+++ b/backends/protobuf/protobuf.cc
@@ -266,7 +266,7 @@ struct ProtobufBackend : public Backend {
}
break;
}
- extra_args(f, filename, args, argidx);
+ extra_args(f, filename, args, argidx, !text_mode);
log_header(design, "Executing Protobuf backend.\n");
@@ -338,7 +338,7 @@ struct ProtobufPass : public Pass {
if (!filename.empty()) {
rewrite_filename(filename);
std::ofstream *ff = new std::ofstream;
- ff->open(filename.c_str(), std::ofstream::trunc);
+ ff->open(filename.c_str(), text_mode ? std::ofstream::trunc : (std::ofstream::trunc | std::ofstream::binary));
if (ff->fail()) {
delete ff;
log_error("Can't open file `%s' for writing: %s\n", filename.c_str(), strerror(errno));
diff --git a/kernel/register.cc b/kernel/register.cc
index 1fd1bad1d..3033ee710 100644
--- a/kernel/register.cc
+++ b/kernel/register.cc
@@ -48,7 +48,7 @@ using zlib to write gzip-compressed data every time the stream is flushed.
*/
class gzip_ostream : public std::ostream {
public:
- gzip_ostream()
+ gzip_ostream() : std::ostream(nullptr)
{
rdbuf(&outbuf);
}
@@ -71,7 +71,7 @@ private:
str("");
return 0;
}
- ~gzip_streambuf()
+ virtual ~gzip_streambuf()
{
sync();
gzclose(gzf);
@@ -498,7 +498,15 @@ void Frontend::extra_args(std::istream *&f, std::string &filename, std::vector<s
if (f != NULL) {
// Check for gzip magic
unsigned char magic[3];
- int n = readsome(*ff, reinterpret_cast<char*>(magic), 3);
+ int n = 0;
+ while (n < 3)
+ {
+ int c = ff->get();
+ if (c != EOF) {
+ magic[n] = (unsigned char) c;
+ }
+ n++;
+ }
if (n == 3 && magic[0] == 0x1f && magic[1] == 0x8b) {
#ifdef YOSYS_ENABLE_ZLIB
log("Found gzip magic in file `%s', decompressing using zlib.\n", filename.c_str());
@@ -604,7 +612,7 @@ void Backend::execute(std::vector<std::string> args, RTLIL::Design *design)
delete f;
}
-void Backend::extra_args(std::ostream *&f, std::string &filename, std::vector<std::string> args, size_t argidx)
+void Backend::extra_args(std::ostream *&f, std::string &filename, std::vector<std::string> args, size_t argidx, bool bin_output)
{
bool called_with_fp = f != NULL;
@@ -639,7 +647,7 @@ void Backend::extra_args(std::ostream *&f, std::string &filename, std::vector<st
#endif
} else {
std::ofstream *ff = new std::ofstream;
- ff->open(filename.c_str(), std::ofstream::trunc);
+ ff->open(filename.c_str(), bin_output ? (std::ofstream::trunc | std::ofstream::binary) : std::ofstream::trunc);
yosys_output_files.insert(filename);
if (ff->fail()) {
delete ff;
diff --git a/kernel/register.h b/kernel/register.h
index c74029823..be836013f 100644
--- a/kernel/register.h
+++ b/kernel/register.h
@@ -109,7 +109,7 @@ struct Backend : Pass
void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE YS_FINAL;
virtual void execute(std::ostream *&f, std::string filename, std::vector<std::string> args, RTLIL::Design *design) = 0;
- void extra_args(std::ostream *&f, std::string &filename, std::vector<std::string> args, size_t argidx);
+ void extra_args(std::ostream *&f, std::string &filename, std::vector<std::string> args, size_t argidx, bool bin_output = false);
static void backend_call(RTLIL::Design *design, std::ostream *f, std::string filename, std::string command);
static void backend_call(RTLIL::Design *design, std::ostream *f, std::string filename, std::vector<std::string> args);
diff --git a/passes/cmds/Makefile.inc b/passes/cmds/Makefile.inc
index c8067a8be..cf9663d1d 100644
--- a/passes/cmds/Makefile.inc
+++ b/passes/cmds/Makefile.inc
@@ -25,6 +25,7 @@ OBJS += passes/cmds/plugin.o
OBJS += passes/cmds/check.o
OBJS += passes/cmds/qwp.o
OBJS += passes/cmds/edgetypes.o
+OBJS += passes/cmds/portlist.o
OBJS += passes/cmds/chformal.o
OBJS += passes/cmds/chtype.o
OBJS += passes/cmds/blackbox.o
diff --git a/passes/cmds/portlist.cc b/passes/cmds/portlist.cc
new file mode 100644
index 000000000..38c4a8597
--- /dev/null
+++ b/passes/cmds/portlist.cc
@@ -0,0 +1,93 @@
+/*
+ * yosys -- Yosys Open SYnthesis Suite
+ *
+ * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ */
+
+#include "kernel/yosys.h"
+#include "kernel/sigtools.h"
+
+USING_YOSYS_NAMESPACE
+PRIVATE_NAMESPACE_BEGIN
+
+struct PortlistPass : public Pass {
+ PortlistPass() : Pass("portlist", "list (top-level) ports") { }
+ void help() YS_OVERRIDE
+ {
+ // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
+ log("\n");
+ log(" portlist [options] [selection]\n");
+ log("\n");
+ log("This command lists all module ports found in the selected modules.\n");
+ log("\n");
+ log("If no selection is provided then it lists the ports on the top module.\n");
+ log("\n");
+ log(" -m\n");
+ log(" print verilog blackbox module definitions instead of port lists\n");
+ log("\n");
+ }
+ void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
+ {
+ bool m_mode = false;
+
+ size_t argidx;
+ for (argidx = 1; argidx < args.size(); argidx++) {
+ if (args[argidx] == "-m") {
+ m_mode = true;
+ continue;
+ }
+ break;
+ }
+
+ bool first_module = true;
+
+ auto handle_module = [&](RTLIL::Module *module) {
+ vector<string> ports;
+ if (first_module)
+ first_module = false;
+ else
+ log("\n");
+ for (auto port : module->ports) {
+ auto *w = module->wire(port);
+ ports.push_back(stringf("%s [%d:%d] %s", w->port_input ? w->port_output ? "inout" : "input" : "output",
+ w->upto ? w->start_offset : w->start_offset + w->width - 1,
+ w->upto ? w->start_offset + w->width - 1 : w->start_offset,
+ log_id(w)));
+ }
+ log("module %s%s\n", log_id(module), m_mode ? " (" : "");
+ for (int i = 0; i < GetSize(ports); i++)
+ log("%s%s\n", ports[i].c_str(), m_mode && i+1 < GetSize(ports) ? "," : "");
+ if (m_mode)
+ log(");\nendmodule\n");
+ };
+
+ if (argidx == args.size())
+ {
+ auto *top = design->top_module();
+ if (top == nullptr)
+ log_cmd_error("Can't find top module in current design!\n");
+ handle_module(top);
+ }
+ else
+ {
+ extra_args(args, argidx, design);
+ for (auto module : design->selected_modules())
+ handle_module(module);
+ }
+ }
+} PortlistPass;
+
+PRIVATE_NAMESPACE_END
diff --git a/passes/cmds/show.cc b/passes/cmds/show.cc
index 2e9fc72af..a3e969ef1 100644
--- a/passes/cmds/show.cc
+++ b/passes/cmds/show.cc
@@ -26,6 +26,10 @@
# include <dirent.h>
#endif
+#ifdef __APPLE__
+# include <unistd.h>
+#endif
+
#ifdef YOSYS_ENABLE_READLINE
# include <readline/readline.h>
#endif
@@ -866,7 +870,11 @@ struct ShowPass : public Pass {
log_cmd_error("Shell command failed!\n");
} else
if (format.empty()) {
+ #ifdef __APPLE__
+ std::string cmd = stringf("ps -fu %d | grep -q '[ ]%s' || xdot '%s' &", getuid(), dot_file.c_str(), dot_file.c_str());
+ #else
std::string cmd = stringf("{ test -f '%s.pid' && fuser -s '%s.pid'; } || ( echo $$ >&3; exec xdot '%s'; ) 3> '%s.pid' &", dot_file.c_str(), dot_file.c_str(), dot_file.c_str(), dot_file.c_str());
+ #endif
log("Exec: %s\n", cmd.c_str());
if (run_command(cmd) != 0)
log_cmd_error("Shell command failed!\n");
diff --git a/passes/techmap/techmap.cc b/passes/techmap/techmap.cc
index 1d0362ad6..08a1af2d5 100644
--- a/passes/techmap/techmap.cc
+++ b/passes/techmap/techmap.cc
@@ -935,19 +935,6 @@ struct TechmapWorker
for (auto &it2 : it.second)
if (!it2.value.is_fully_const())
log_error("Techmap yielded config wire %s with non-const value %s.\n", RTLIL::id2cstr(it2.wire->name), log_signal(it2.value));
- if (it.first.substr(0, 20) == "_TECHMAP_REMOVEINIT_" && techmap_do_cache[tpl]) {
- for (auto &it2 : it.second) {
- auto val = it2.value.as_const();
- auto wirename = RTLIL::escape_id(it.first.substr(20, it.first.size() - 20 - 1));
- auto it = cell->connections().find(wirename);
- if (it != cell->connections().end()) {
- auto sig = sigmap(it->second);
- for (int i = 0; i < sig.size(); i++)
- if (val[i] == State::S1)
- remove_init_bits.insert(sig[i]);
- }
- }
- }
techmap_wire_names.erase(it.first);
}
@@ -973,6 +960,23 @@ struct TechmapWorker
mkdebug.off();
}
+ TechmapWires twd = techmap_find_special_wires(tpl);
+ for (auto &it : twd) {
+ if (it.first.substr(0, 20) == "_TECHMAP_REMOVEINIT_") {
+ for (auto &it2 : it.second) {
+ auto val = it2.value.as_const();
+ auto wirename = RTLIL::escape_id(it.first.substr(20, it.first.size() - 20 - 1));
+ auto it = cell->connections().find(wirename);
+ if (it != cell->connections().end()) {
+ auto sig = sigmap(it->second);
+ for (int i = 0; i < sig.size(); i++)
+ if (val[i] == State::S1)
+ remove_init_bits.insert(sig[i]);
+ }
+ }
+ }
+ }
+
if (extern_mode && !in_recursion)
{
std::string m_name = stringf("$extern:%s", log_id(tpl));
diff --git a/techlibs/xilinx/abc_xc7.box b/techlibs/xilinx/abc_xc7.box
index 9b64b4907..3da3d1b3f 100644
--- a/techlibs/xilinx/abc_xc7.box
+++ b/techlibs/xilinx/abc_xc7.box
@@ -7,7 +7,7 @@
# Average across F7[AB]MUX
# Inputs: I0 I1 S0
# Outputs: O
-F7MUX 1 1 3 1
+MUXF7 1 1 3 1
204 208 286
# Inputs: I0 I1 S0
diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc
index 6c58e0913..7085214de 100644
--- a/techlibs/xilinx/synth_xilinx.cc
+++ b/techlibs/xilinx/synth_xilinx.cc
@@ -252,7 +252,7 @@ struct SynthXilinxPass : public ScriptPass
}
extra_args(args, argidx, design);
- if (family != "xcup" && family != "xcu" && family != "xc7" && family != "xc6v" & family != "xc6s")
+ if (family != "xcup" && family != "xcu" && family != "xc7" && family != "xc6v" && family != "xc6s")
log_cmd_error("Invalid Xilinx -family setting: '%s'.\n", family.c_str());
if (widemux != 0 && widemux < 2)
diff --git a/tests/ice40/adffs.v b/tests/ice40/adffs.v
index 93c8bf52c..09dc36001 100644
--- a/tests/ice40/adffs.v
+++ b/tests/ice40/adffs.v
@@ -22,29 +22,25 @@ module adffn
q <= d;
endmodule
-module dffsr
+module dffs
( input d, clk, pre, clr, output reg q );
initial begin
q = 0;
end
- always @( posedge clk, posedge pre, posedge clr )
- if ( clr )
- q <= 1'b0;
- else if ( pre )
+ always @( posedge clk, posedge pre )
+ if ( pre )
q <= 1'b1;
else
q <= d;
endmodule
-module ndffnsnr
+module ndffnr
( input d, clk, pre, clr, output reg q );
initial begin
q = 0;
end
- always @( negedge clk, negedge pre, negedge clr )
- if ( !clr )
- q <= 1'b0;
- else if ( !pre )
+ always @( negedge clk, negedge pre )
+ if ( !pre )
q <= 1'b1;
else
q <= d;
@@ -58,7 +54,7 @@ input a,
output b,b1,b2,b3
);
-dffsr u_dffsr (
+dffs u_dffs (
.clk (clk ),
.clr (clr),
.pre (pre),
@@ -66,7 +62,7 @@ dffsr u_dffsr (
.q (b )
);
-ndffnsnr u_ndffnsnr (
+ndffnr u_ndffnr (
.clk (clk ),
.clr (clr),
.pre (pre),
diff --git a/tests/ice40/adffs.ys b/tests/ice40/adffs.ys
index 14b251c5c..548060b66 100644
--- a/tests/ice40/adffs.ys
+++ b/tests/ice40/adffs.ys
@@ -1,12 +1,11 @@
read_verilog adffs.v
proc
-async2sync # converts async flops to a 'sync' variant clocked by a 'super'-clock
flatten
-equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 # equivalency check
+equiv_opt -multiclock -assert -map +/ice40/cells_sim.v synth_ice40 # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd top # Constrain all select calls below inside the top module
-select -assert-count 1 t:SB_DFF
-select -assert-count 1 t:SB_DFFN
-select -assert-count 2 t:SB_DFFSR
-select -assert-count 7 t:SB_LUT4
-select -assert-none t:SB_DFF t:SB_DFFN t:SB_DFFSR t:SB_LUT4 %% t:* %D
+select -assert-count 1 t:SB_DFFNS
+select -assert-count 2 t:SB_DFFR
+select -assert-count 1 t:SB_DFFS
+select -assert-count 2 t:SB_LUT4
+select -assert-none t:SB_DFFNS t:SB_DFFR t:SB_DFFS t:SB_LUT4 %% t:* %D
diff --git a/tests/ice40/run-test.sh b/tests/ice40/run-test.sh
index 2c72ca3a9..46716f9a0 100755
--- a/tests/ice40/run-test.sh
+++ b/tests/ice40/run-test.sh
@@ -6,7 +6,7 @@ for x in *.ys; do
echo "all:: run-$x"
echo "run-$x:"
echo " @echo 'Running $x..'"
- echo " @../../yosys -ql ${x%.ys}.log $x -w 'Yosys has only limited support for tri-state logic at the moment.'"
+ echo " @../../yosys -ql ${x%.ys}.log -w 'Yosys has only limited support for tri-state logic at the moment.' $x"
done
for s in *.sh; do
if [ "$s" != "run-test.sh" ]; then
diff --git a/tests/techmap/wireinit.ys b/tests/techmap/wireinit.ys
index 1396839fe..89afaafb5 100644
--- a/tests/techmap/wireinit.ys
+++ b/tests/techmap/wireinit.ys
@@ -46,11 +46,13 @@ input clk;
input d;
output reg q0 = 0;
output reg q1 = 1;
+output reg qq0 = 0;
output reg qx;
always @(posedge clk) begin
q0 <= d;
q1 <= d;
+ qq0 <= q0;
qx <= d;
end
endmodule
@@ -64,16 +66,20 @@ simplemap
techmap -map %map
clean
# Make sure the parameter was used properly.
-select -assert-count 2 top/t:ffbb
+select -assert-count 3 top/t:ffbb
select -set ff0 top/w:q0 %ci t:ffbb %i
+select -set ffq0 top/w:qq0 %ci t:ffbb %i
select -set ffx top/w:qx %ci t:ffbb %i
select -assert-count 1 @ff0
+select -assert-count 1 @ffq0
select -assert-count 1 @ffx
select -assert-count 1 @ff0 r:INIT=1'b0 %i
+select -assert-count 1 @ffq0 r:INIT=1'b0 %i
select -assert-count 1 @ffx r:INIT=1'bx %i
select -assert-count 0 top/w:q1 %ci t:ffbb %i
# Make sure the init values are dropped from the wires iff mapping was performed.
select -assert-count 0 top/w:q0 a:init %i
+select -assert-count 0 top/w:qq0 a:init %i
select -assert-count 1 top/w:q1 a:init=1'b1 %i
select -assert-count 0 top/w:qx a:init %i
@@ -84,15 +90,19 @@ simplemap
techmap -map %map_noremove
clean
# Make sure the parameter was used properly.
-select -assert-count 2 top/t:ffbb
+select -assert-count 3 top/t:ffbb
select -set ff0 top/w:q0 %ci t:ffbb %i
+select -set ffq0 top/w:qq0 %ci t:ffbb %i
select -set ffx top/w:qx %ci t:ffbb %i
select -assert-count 1 @ff0
+select -assert-count 1 @ffq0
select -assert-count 1 @ffx
select -assert-count 1 @ff0 r:INIT=1'b0 %i
+select -assert-count 1 @ffq0 r:INIT=1'b0 %i
select -assert-count 1 @ffx r:INIT=1'bx %i
select -assert-count 0 top/w:q1 %ci t:ffbb %i
# Make sure the init values are not dropped from the wires.
select -assert-count 1 top/w:q0 a:init=1'b0 %i
+select -assert-count 1 top/w:qq0 a:init=1'b0 %i
select -assert-count 1 top/w:q1 a:init=1'b1 %i
select -assert-count 0 top/w:qx a:init %i
generated by cgit v1.2.3 (git 2.25.1) at 2025-04-03 12:50:24 +0000