diff options
| -rw-r--r-- | Makefile | 2 | ||||
| -rw-r--r-- | passes/sat/clk2fflogic.cc | 2 |
2 files changed, 3 insertions, 1 deletions
@@ -129,7 +129,7 @@ LDFLAGS += -rdynamic LDLIBS += -lrt endif -YOSYS_VER := 0.15+84 +YOSYS_VER := 0.15+89 GIT_REV := $(shell git -C $(YOSYS_SRC) rev-parse --short HEAD 2> /dev/null || echo UNKNOWN) OBJS = kernel/version_$(GIT_REV).o diff --git a/passes/sat/clk2fflogic.cc b/passes/sat/clk2fflogic.cc index f37e07a89..bc18bbbd6 100644 --- a/passes/sat/clk2fflogic.cc +++ b/passes/sat/clk2fflogic.cc @@ -44,6 +44,7 @@ struct Clk2fflogicPass : public Pass { } SigSpec wrap_async_control(Module *module, SigSpec sig, bool polarity, IdString past_sig_id) { Wire *past_sig = module->addWire(past_sig_id, GetSize(sig)); + past_sig->attributes[ID::init] = RTLIL::Const(polarity ? State::S0 : State::S1, GetSize(sig)); module->addFf(NEW_ID, sig, past_sig); if (polarity) sig = module->Or(NEW_ID, sig, past_sig); @@ -56,6 +57,7 @@ struct Clk2fflogicPass : public Pass { } SigSpec wrap_async_control_gate(Module *module, SigSpec sig, bool polarity) { Wire *past_sig = module->addWire(NEW_ID); + past_sig->attributes[ID::init] = RTLIL::Const(polarity ? State::S0 : State::S1, GetSize(sig)); module->addFfGate(NEW_ID, sig, past_sig); if (polarity) sig = module->OrGate(NEW_ID, sig, past_sig); |