diff options
| -rw-r--r-- | .gitattributes | 1 | ||||
| -rw-r--r-- | .gitcommit | 1 | ||||
| -rw-r--r-- | CHANGELOG | 5 | ||||
| -rw-r--r-- | Makefile | 11 | ||||
| -rw-r--r-- | frontends/ast/simplify.cc | 1 | ||||
| -rw-r--r-- | tests/verilog/unreachable_case_sign.ys | 33 |
6 files changed, 52 insertions, 0 deletions
diff --git a/.gitattributes b/.gitattributes index f85ae06c9..5e568606e 100644 --- a/.gitattributes +++ b/.gitattributes @@ -1 +1,2 @@ *.v linguist-language=Verilog +/.gitcommit export-subst diff --git a/.gitcommit b/.gitcommit new file mode 100644 index 000000000..46b7856fb --- /dev/null +++ b/.gitcommit @@ -0,0 +1 @@ +$Format:%h$ @@ -5,6 +5,11 @@ List of major changes and improvements between releases Yosys 0.17 .. Yosys 0.17-dev -------------------------- + * Verilog + - Fixed an issue where simplifying case statements by removing unreachable + cases could result in the wrong signedness being used for comparison with + the remaining cases + Yosys 0.16 .. Yosys 0.17 -------------------------- * New commands and options @@ -130,7 +130,18 @@ LDLIBS += -lrt endif YOSYS_VER := 0.17+41 + +# Note: We arrange for .gitcommit to contain the (short) commit hash in +# tarballs generated with git-archive(1) using .gitattributes. The git repo +# will have this file in its unexpanded form tough, in which case we fall +# back to calling git directly. +TARBALL_GIT_REV := $(shell cat $(YOSYS_SRC)/.gitcommit) +ifeq ($(TARBALL_GIT_REV),$$Format:%h$$) GIT_REV := $(shell git ls-remote $(YOSYS_SRC) HEAD -q | $(AWK) 'BEGIN {R = "UNKNOWN"}; ($$2 == "HEAD") {R = substr($$1, 1, 9); exit} END {print R}') +else +GIT_REV := $(TARBALL_GIT_REV) +endif + OBJS = kernel/version_$(GIT_REV).o bumpversion: diff --git a/frontends/ast/simplify.cc b/frontends/ast/simplify.cc index bd3e09c4b..4d7c4f522 100644 --- a/frontends/ast/simplify.cc +++ b/frontends/ast/simplify.cc @@ -1531,6 +1531,7 @@ bool AstNode::simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage, detectSignWidth(width_hint, sign_hint); while (children[0]->simplify(const_fold, at_zero, in_lvalue, stage, width_hint, sign_hint, in_param)) { } if (children[0]->type == AST_CONSTANT && children[0]->bits_only_01()) { + children[0]->is_signed = sign_hint; RTLIL::Const case_expr = children[0]->bitsAsConst(width_hint, sign_hint); std::vector<AstNode*> new_children; new_children.push_back(children[0]); diff --git a/tests/verilog/unreachable_case_sign.ys b/tests/verilog/unreachable_case_sign.ys new file mode 100644 index 000000000..25bc0c6f0 --- /dev/null +++ b/tests/verilog/unreachable_case_sign.ys @@ -0,0 +1,33 @@ +logger -expect-no-warnings + +read_verilog -formal <<EOT +module top(input clk); + reg good = 0; + + always @(posedge clk) begin + case (4'sb1111) 15: good = 1; 4'b0000: ; endcase + assert (good); + end +endmodule +EOT + +prep -top top +sim -n 3 -clock clk + +design -reset + +read_verilog -formal <<EOT +module top(input clk); + reg good = 1; + reg signed [1:0] case_value = -1; + + always @(posedge clk) begin + case (4'sb1111) 4'b0000: ; case_value: good = 0; endcase + assert (good); + end +endmodule +EOT + +prep -top top +sim -n 3 -clock clk + |