14 files changed, 191 insertions, 25 deletions
diff --git a/backends/cxxrtl/cxxrtl_backend.cc b/backends/cxxrtl/cxxrtl_backend.cc
index 39046bd78..d7402087f 100644
--- a/backends/cxxrtl/cxxrtl_backend.cc
+++ b/backends/cxxrtl/cxxrtl_backend.cc
@@ -614,6 +614,8 @@ struct CxxrtlWorker {
 	std::ostream *impl_f = nullptr;
 	std::ostream *intf_f = nullptr;
 
+	bool print_wire_types = false;
+	bool print_debug_wire_types = false;
 	bool run_hierarchy = false;
 	bool run_flatten = false;
 	bool run_proc = false;
@@ -1231,7 +1233,9 @@ struct CxxrtlWorker {
 			RTLIL::Memory *memory = cell->module->memories[cell->getParam(ID::MEMID).decode_string()];
 			std::string valid_index_temp = fresh_temporary();
 			f << indent << "auto " << valid_index_temp << " = memory_index(";
-			dump_sigspec_rhs(cell->getPort(ID::ADDR));
+			// Almost all non-elidable cells cannot appear in debug_eval(), but $memrd is an exception; asynchronous
+			// memory read ports can.
+			dump_sigspec_rhs(cell->getPort(ID::ADDR), for_debug);
 			f << ", " << memory->start_offset << ", " << memory->size << ");\n";
 			if (cell->type == ID($memrd)) {
 				bool has_enable = cell->getParam(ID::CLK_ENABLE).as_bool() && !cell->getPort(ID::EN).is_fully_ones();
@@ -2684,6 +2688,35 @@ struct CxxrtlWorker {
 					if (debug_live_nodes[node])
 						debug_schedule[module].push_back(*node);
 			}
+
+			auto show_wire_type = [&](const RTLIL::Wire* wire, const WireType &wire_type) {
+				const char *type_str;
+				switch (wire_type.type) {
+					case WireType::UNUSED:   type_str = "UNUSED";   break;
+					case WireType::BUFFERED: type_str = "BUFFERED"; break;
+					case WireType::MEMBER:   type_str = "MEMBER";   break;
+					case WireType::OUTLINE:  type_str = "OUTLINE";  break;
+					case WireType::LOCAL:    type_str = "LOCAL";    break;
+					case WireType::INLINE:   type_str = "INLINE";   break;
+					case WireType::ALIAS:    type_str = "ALIAS";    break;
+					case WireType::CONST:    type_str = "CONST";    break;
+					default:                 type_str = "(invalid)";
+				}
+				if (wire_type.sig_subst.empty())
+					log_debug("  %s: %s\n", log_signal((RTLIL::Wire*)wire), type_str);
+				else
+					log_debug("  %s: %s = %s\n", log_signal((RTLIL::Wire*)wire), type_str, log_signal(wire_type.sig_subst));
+			};
+			if (print_wire_types && !wire_types.empty()) {
+				log_debug("Wire types:\n");
+				for (auto wire_type : wire_types)
+					show_wire_type(wire_type.first, wire_type.second);
+			}
+			if (print_debug_wire_types && !debug_wire_types.empty()) {
+				log_debug("Debug wire types:\n");
+				for (auto debug_wire_type : debug_wire_types)
+					show_wire_type(debug_wire_type.first, debug_wire_type.second);
+			}
 		}
 		if (has_feedback_arcs || has_buffered_comb_wires) {
 			// Although both non-feedback buffered combinatorial wires and apparent feedback wires may be eliminated
@@ -2763,7 +2796,7 @@ struct CxxrtlWorker {
 		// Recheck the design if it was modified.
 		if (did_anything)
 			check_design(design, has_top, has_sync_init, has_packed_mem);
-		log_assert(has_top && !has_sync_init && !has_packed_mem);
+		log_assert(!has_sync_init && !has_packed_mem);
 		log_pop();
 		if (did_anything)
 			log_spacer();
@@ -2934,6 +2967,9 @@ struct CxxrtlBackend : public Backend {
 		log("\n");
 		log("The following options are supported by this backend:\n");
 		log("\n");
+		log("    -print-wire-types, -print-debug-wire-types\n");
+		log("        enable additional debug logging, for pass developers.\n");
+		log("\n");
 		log("    -header\n");
 		log("        generate separate interface (.h) and implementation (.cc) files.\n");
 		log("        if specified, the backend must be called with a filename, and filename\n");
@@ -3013,6 +3049,8 @@ struct CxxrtlBackend : public Backend {
 
 	void execute(std::ostream *&f, std::string filename, std::vector<std::string> args, RTLIL::Design *design) override
 	{
+		bool print_wire_types = false;
+		bool print_debug_wire_types = false;
 		bool nohierarchy = false;
 		bool noflatten = false;
 		bool noproc = false;
@@ -3025,6 +3063,14 @@ struct CxxrtlBackend : public Backend {
 		size_t argidx;
 		for (argidx = 1; argidx < args.size(); argidx++)
 		{
+			if (args[argidx] == "-print-wire-types") {
+				print_wire_types = true;
+				continue;
+			}
+			if (args[argidx] == "-print-debug-wire-types") {
+				print_debug_wire_types = true;
+				continue;
+			}
 			if (args[argidx] == "-nohierarchy") {
 				nohierarchy = true;
 				continue;
@@ -3076,6 +3122,8 @@ struct CxxrtlBackend : public Backend {
 		}
 		extra_args(f, filename, args, argidx);
 
+		worker.print_wire_types = print_wire_types;
+		worker.print_debug_wire_types = print_debug_wire_types;
 		worker.run_hierarchy = !nohierarchy;
 		worker.run_flatten = !noflatten;
 		worker.run_proc = !noproc;
diff --git a/frontends/ast/ast.cc b/frontends/ast/ast.cc
index 7fb61bb34..af5e326ad 100644
--- a/frontends/ast/ast.cc
+++ b/frontends/ast/ast.cc
@@ -317,6 +317,8 @@ void AstNode::dumpAst(FILE *f, std::string indent) const
 		fprintf(f, " reg");
 	if (is_signed)
 		fprintf(f, " signed");
+	if (is_unsized)
+		fprintf(f, " unsized");
 	if (basic_prep)
 		fprintf(f, " basic_prep");
 	if (lookahead)
diff --git a/frontends/ast/genrtlil.cc b/frontends/ast/genrtlil.cc
index d4299bf69..e0a522430 100644
--- a/frontends/ast/genrtlil.cc
+++ b/frontends/ast/genrtlil.cc
@@ -1000,6 +1000,12 @@ void AstNode::detectSignWidth(int &width_hint, bool &sign_hint, bool *found_real
 	if (found_real)
 		*found_real = false;
 	detectSignWidthWorker(width_hint, sign_hint, found_real);
+
+	constexpr int kWidthLimit = 1 << 24;
+	if (width_hint >= kWidthLimit)
+		log_file_error(filename, location.first_line,
+			"Expression width %d exceeds implementation limit of %d!\n",
+			width_hint, kWidthLimit);
 }
 
 static void check_unique_id(RTLIL::Module *module, RTLIL::IdString id,
diff --git a/frontends/ast/simplify.cc b/frontends/ast/simplify.cc
index 5c4dd290f..e7f897b3c 100644
--- a/frontends/ast/simplify.cc
+++ b/frontends/ast/simplify.cc
@@ -915,6 +915,22 @@ bool AstNode::simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage,
 			}
 	}
 
+	if (type == AST_ARGUMENT)
+	{
+		if (children.size() == 1 && children[0]->type == AST_CONSTANT)
+		{
+			// HACK: For port bindings using unbased unsized literals, mark them
+			// signed so they sign-extend. The hierarchy will still incorrectly
+			// generate a warning complaining about resizing the expression.
+			// This also doesn't handle the complex of something like a ternary
+			// expression bound to a port, where the actual size of the port is
+			// needed to resolve the expression correctly.
+			AstNode *arg = children[0];
+			if (arg->is_unsized)
+				arg->is_signed = true;
+		}
+	}
+
 	int backup_width_hint = width_hint;
 	bool backup_sign_hint = sign_hint;
 
@@ -3773,7 +3789,11 @@ replace_fcall_later:;
 		case AST_CAST_SIZE:
 			if (children.at(0)->type == AST_CONSTANT && children.at(1)->type == AST_CONSTANT) {
 				int width = children[0]->bitsAsConst().as_int();
-				RTLIL::Const val = children[1]->bitsAsConst(width);
+				RTLIL::Const val;
+				if (children[1]->is_unsized)
+					val = children[1]->bitsAsUnsizedConst(width);
+				else
+					val = children[1]->bitsAsConst(width);
 				newNode = mkconst_bits(val.bits, children[1]->is_signed);
 			}
 			break;
diff --git a/frontends/verific/README b/frontends/verific/README
index c37d76343..952fb1e0c 100644
--- a/frontends/verific/README
+++ b/frontends/verific/README
@@ -1,11 +1,11 @@
 
 This directory contains Verific bindings for Yosys.
 
-Use Symbiotic EDA Suite if you need Yosys+Verifc.
-https://www.symbioticeda.com/seda-suite
+Use Tabby CAD Suite from YosysHQ if you need Yosys+Verifc.
+https://www.yosyshq.com/
 
-Contact office@symbioticeda.com for free evaluation
-binaries of Symbiotic EDA Suite.
+Contact YosysHQ at contact@yosyshq.com for free evaluation
+binaries of Tabby CAD Suite.
 
 
 Verific Features that should be enabled in your Verific library
diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc
index 1faf376e7..40079ffc5 100644
--- a/kernel/rtlil.cc
+++ b/kernel/rtlil.cc
@@ -613,7 +613,8 @@ void RTLIL::Design::add(RTLIL::Module *module)
 
 RTLIL::Module *RTLIL::Design::addModule(RTLIL::IdString name)
 {
-	log_assert(modules_.count(name) == 0);
+	if (modules_.count(name) != 0)
+		log_error("Attempted to add new module named '%s', but a module by that name already exists\n", name.c_str());
 	log_assert(refcount_modules_ == 0);
 
 	RTLIL::Module *module = new RTLIL::Module;
diff --git a/kernel/rtlil.h b/kernel/rtlil.h
index 6170ea55e..f03f27617 100644
--- a/kernel/rtlil.h
+++ b/kernel/rtlil.h
@@ -1339,7 +1339,6 @@ public:
 
 	RTLIL::SigSpec Not (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, bool is_signed = false, const std::string &src = "");
 	RTLIL::SigSpec Pos (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, bool is_signed = false, const std::string &src = "");
-	RTLIL::SigSpec Bu0 (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, bool is_signed = false, const std::string &src = "");
 	RTLIL::SigSpec Neg (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, bool is_signed = false, const std::string &src = "");
 
 	RTLIL::SigSpec And  (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, const std::string &src = "");
@@ -1520,7 +1519,6 @@ struct RTLIL::CaseRule : public RTLIL::AttrObject
 	std::vector<RTLIL::SwitchRule*> switches;
 
 	~CaseRule();
-	void optimize();
 
 	bool empty() const;
 
diff --git a/manual/command-reference-manual.tex b/manual/command-reference-manual.tex
index 988f034b4..e2d54cb03 100644
--- a/manual/command-reference-manual.tex
+++ b/manual/command-reference-manual.tex
@@ -6652,11 +6652,11 @@ bindings (for Yosys and/or Verific developers):
     Dump the Verific netlist as a verilog file.
 
 
-Use Symbiotic EDA Suite if you need Yosys+Verifc.
-https://www.symbioticeda.com/seda-suite
+Use YosysHQ Tabby CAD Suite if you need Yosys+Verific.
+https://www.yosyshq.com/\n");
 
-Contact office@symbioticeda.com for free evaluation
-binaries of Symbiotic EDA Suite.
+Contact office@yosyshq.com for free evaluation
+binaries of YosysHQ Tabby CAD Suite.
 \end{lstlisting}
 
 \section{verilog\_defaults -- set default options for read\_verilog}
diff --git a/misc/py_wrap_generator.py b/misc/py_wrap_generator.py
index 38bd6129e..2de3c1f99 100644
--- a/misc/py_wrap_generator.py
+++ b/misc/py_wrap_generator.py
@@ -997,7 +997,7 @@ sources = [
 	Source("kernel/cost",[])
 	]
 
-blacklist_methods = ["YOSYS_NAMESPACE::Pass::run_register", "YOSYS_NAMESPACE::Module::Pow", "YOSYS_NAMESPACE::Module::Bu0", "YOSYS_NAMESPACE::CaseRule::optimize"]
+blacklist_methods = ["YOSYS_NAMESPACE::Pass::run_register", "YOSYS_NAMESPACE::Module::Pow"]
 
 enum_names = ["State","SyncType","ConstFlags"]
 
diff --git a/passes/proc/proc_clean.cc b/passes/proc/proc_clean.cc
index 5e78b7316..54d5a81ff 100644
--- a/passes/proc/proc_clean.cc
+++ b/passes/proc/proc_clean.cc
@@ -76,22 +76,33 @@ void proc_clean_switch(RTLIL::SwitchRule *sw, RTLIL::CaseRule *parent, bool &did
 	}
 	else
 	{
-		bool all_fully_def = true;
 		for (auto cs : sw->cases)
-		{
 			if (max_depth != 0)
 				proc_clean_case(cs, did_something, count, max_depth-1);
-			int size = 0;
-			for (auto cmp : cs->compare)
+
+		bool is_parallel_case = sw->get_bool_attribute(ID::parallel_case);
+		bool is_full_case = sw->get_bool_attribute(ID::full_case);
+
+		// Empty case removal.  The rules are:
+		//
+		// - for full_case: only remove cases if *all* cases are empty
+		// - for parallel_case but not full_case: remove any empty case
+		// - for non-parallel and non-full case: remove the final case if it's empty
+
+		if (is_full_case)
+		{
+			bool all_empty = true;
+			for (auto cs : sw->cases)
+				if (!cs->empty())
+					all_empty = false;
+			if (all_empty)
 			{
-				size += cmp.size();
-				if (!cmp.is_fully_def())
-					all_fully_def = false;
+				for (auto cs : sw->cases)
+					delete cs;
+				sw->cases.clear();
 			}
-			if (sw->signal.size() != size)
-				all_fully_def = false;
 		}
-		if (all_fully_def)
+		else if (is_parallel_case)
 		{
 			for (auto cs = sw->cases.begin(); cs != sw->cases.end();)
 			{
diff --git a/tests/verilog/absurd_width.ys b/tests/verilog/absurd_width.ys
new file mode 100644
index 000000000..c0d2af4c2
--- /dev/null
+++ b/tests/verilog/absurd_width.ys
@@ -0,0 +1,17 @@
+logger -expect error "Expression width 1073741824 exceeds implementation limit of 16777216!" 1
+read_verilog <<EOF
+module top(
+    input inp,
+    output out
+);
+    assign out =
+        {1024 {
+        {1024 {
+        {1024 {
+        inp
+        }}
+        }}
+        }}
+        ;
+endmodule
+EOF
diff --git a/tests/verilog/absurd_width_const.ys b/tests/verilog/absurd_width_const.ys
new file mode 100644
index 000000000..b7191fd0d
--- /dev/null
+++ b/tests/verilog/absurd_width_const.ys
@@ -0,0 +1,16 @@
+logger -expect error "Expression width 1073741824 exceeds implementation limit of 16777216!" 1
+read_verilog <<EOF
+module top(
+    output out
+);
+    assign out =
+        {1024 {
+        {1024 {
+        {1024 {
+        1'b1
+        }}
+        }}
+        }}
+        ;
+endmodule
+EOF
diff --git a/tests/verilog/unbased_unsized.sv b/tests/verilog/unbased_unsized.sv
new file mode 100644
index 000000000..1d0c5a72c
--- /dev/null
+++ b/tests/verilog/unbased_unsized.sv
@@ -0,0 +1,40 @@
+module pass_through(
+    input [63:0] inp,
+    output [63:0] out
+);
+    assign out = inp;
+endmodule
+
+module top;
+    logic [63:0]
+        o01, o02, o03, o04,
+        o05, o06, o07, o08,
+        o09, o10, o11, o12,
+        o13, o14, o15, o16;
+    assign o01 = '0;
+    assign o02 = '1;
+    assign o03 = 'x;
+    assign o04 = 'z;
+    assign o05 = 3'('0);
+    assign o06 = 3'('1);
+    assign o07 = 3'('x);
+    assign o08 = 3'('z);
+    pass_through pt09('0, o09);
+    pass_through pt10('1, o10);
+    pass_through pt11('x, o11);
+    pass_through pt12('z, o12);
+    always @* begin
+        assert (o01 === {64 {1'b0}});
+        assert (o02 === {64 {1'b1}});
+        assert (o03 === {64 {1'bx}});
+        assert (o04 === {64 {1'bz}});
+        assert (o05 === {61'b0, 3'b000});
+        assert (o06 === {61'b0, 3'b111});
+        assert (o07 === {61'b0, 3'bxxx});
+        assert (o08 === {61'b0, 3'bzzz});
+        assert (o09 === {64 {1'b0}});
+        assert (o10 === {64 {1'b1}});
+        assert (o11 === {64 {1'bx}});
+        assert (o12 === {64 {1'bz}});
+    end
+endmodule
diff --git a/tests/verilog/unbased_unsized.ys b/tests/verilog/unbased_unsized.ys
new file mode 100644
index 000000000..e1bc99c64
--- /dev/null
+++ b/tests/verilog/unbased_unsized.ys
@@ -0,0 +1,7 @@
+read_verilog -sv unbased_unsized.sv
+hierarchy
+proc
+flatten
+opt -full
+select -module top
+sat -verify -seq 1 -tempinduct -prove-asserts -show-all