diff options
| -rw-r--r-- | frontends/verific/verific.cc | 2 | ||||
| -rw-r--r-- | passes/sat/sim.cc | 5 | ||||
| -rw-r--r-- | passes/techmap/techmap.cc | 5 | ||||
| -rw-r--r-- | passes/tests/test_cell.cc | 4 | ||||
| -rw-r--r-- | techlibs/common/gen_fine_ffs.py | 2 | ||||
| -rw-r--r-- | techlibs/common/simcells.v | 8 |
6 files changed, 15 insertions, 11 deletions
diff --git a/frontends/verific/verific.cc b/frontends/verific/verific.cc index ccd13e92f..9785b8eff 100644 --- a/frontends/verific/verific.cc +++ b/frontends/verific/verific.cc @@ -53,7 +53,7 @@ USING_YOSYS_NAMESPACE # error "Only Symbiotic EDA flavored Verific is supported. Please contact office@symbioticeda.com for commercial support for Yosys+Verific." #endif -#if SYMBIOTIC_VERIFIC_API_VERSION < 1 +#if SYMBIOTIC_VERIFIC_API_VERSION < 202006 # error "Please update your version of Symbiotic EDA flavored Verific." #endif diff --git a/passes/sat/sim.cc b/passes/sat/sim.cc index 1ab082b09..fb496ff87 100644 --- a/passes/sat/sim.cc +++ b/passes/sat/sim.cc @@ -163,7 +163,10 @@ struct SimInstance mem_database[cell] = mem; } - + if (cell->type.in(ID($memwr),ID($memrd))) + { + log_error("$memrd and $memwr cells have to be merged to stand-alone $mem cells (execute memory_collect pass)\n"); + } if (cell->type.in(ID($assert), ID($cover), ID($assume))) { formal_database.insert(cell); } diff --git a/passes/techmap/techmap.cc b/passes/techmap/techmap.cc index 1cee51d06..f98d1564a 100644 --- a/passes/techmap/techmap.cc +++ b/passes/techmap/techmap.cc @@ -328,8 +328,9 @@ struct TechmapWorker for (auto tpl_cell : tpl->cells()) { IdString c_name = tpl_cell->name; + bool techmap_replace_cell = (c_name == ID::_TECHMAP_REPLACE_); - if (c_name == ID::_TECHMAP_REPLACE_) + if (techmap_replace_cell) c_name = orig_cell_name; else if (tpl_cell->name.begins_with("\\_TECHMAP_REPLACE_.")) c_name = stringf("%s%s", orig_cell_name.c_str(), c_name.c_str() + strlen("\\_TECHMAP_REPLACE_")); @@ -384,7 +385,7 @@ struct TechmapWorker if (c->attributes.count(ID::src)) c->add_strpool_attribute(ID::src, extra_src_attrs); - if (c_name == ID::_TECHMAP_REPLACE_) + if (techmap_replace_cell) for (auto attr : cell->attributes) if (!c->attributes.count(attr.first)) c->attributes[attr.first] = attr.second; diff --git a/passes/tests/test_cell.cc b/passes/tests/test_cell.cc index 125efbaa3..bdb475d3b 100644 --- a/passes/tests/test_cell.cc +++ b/passes/tests/test_cell.cc @@ -909,7 +909,7 @@ struct TestCellPass : public Pass { if (!ilang_file.empty()) { if (!selected_cell_types.empty()) log_cmd_error("Do not specify any cell types when using -f.\n"); - selected_cell_types.push_back("ilang"); + selected_cell_types.push_back(ID(ilang)); } if (selected_cell_types.empty()) @@ -921,7 +921,7 @@ struct TestCellPass : public Pass { for (int i = 0; i < num_iter; i++) { RTLIL::Design *design = new RTLIL::Design; - if (cell_type == "ilang") + if (cell_type == ID(ilang)) Frontend::frontend_call(design, NULL, std::string(), "ilang " + ilang_file); else create_gold_module(design, cell_type, cell_types.at(cell_type), constmode, muxdiv); diff --git a/techlibs/common/gen_fine_ffs.py b/techlibs/common/gen_fine_ffs.py index e92d58f40..5d331e767 100644 --- a/techlibs/common/gen_fine_ffs.py +++ b/techlibs/common/gen_fine_ffs.py @@ -300,7 +300,7 @@ module \$_DLATCH_{E:N|P}{R:N|P}{V:0|1}_ (E, R, D, Q); input E, R, D; output reg Q; always @* begin - if (R == {E:0|1}) + if (R == {R:0|1}) Q <= {V:0|1}; else if (E == {E:0|1}) Q <= D; diff --git a/techlibs/common/simcells.v b/techlibs/common/simcells.v index 01b5bdfa6..27ef44232 100644 --- a/techlibs/common/simcells.v +++ b/techlibs/common/simcells.v @@ -2986,7 +2986,7 @@ module \$_DLATCH_NP0_ (E, R, D, Q); input E, R, D; output reg Q; always @* begin - if (R == 0) + if (R == 1) Q <= 0; else if (E == 0) Q <= D; @@ -3009,7 +3009,7 @@ module \$_DLATCH_NP1_ (E, R, D, Q); input E, R, D; output reg Q; always @* begin - if (R == 0) + if (R == 1) Q <= 1; else if (E == 0) Q <= D; @@ -3032,7 +3032,7 @@ module \$_DLATCH_PN0_ (E, R, D, Q); input E, R, D; output reg Q; always @* begin - if (R == 1) + if (R == 0) Q <= 0; else if (E == 1) Q <= D; @@ -3055,7 +3055,7 @@ module \$_DLATCH_PN1_ (E, R, D, Q); input E, R, D; output reg Q; always @* begin - if (R == 1) + if (R == 0) Q <= 1; else if (E == 1) Q <= D; |