diff options
98 files changed, 9896 insertions, 1826 deletions
diff --git a/CODEOWNERS b/CODEOWNERS index 350a62120..0419e6e44 100644 --- a/CODEOWNERS +++ b/CODEOWNERS @@ -25,6 +25,9 @@ passes/opt/opt_lut.cc @whitequark # These still override previous lines, so be careful not to # accidentally disable any of the above rules. +frontends/verilog/ @zachjs +frontends/ast/ @zachjs + techlibs/intel_alm/ @ZirconiumX # pyosys @@ -6,7 +6,7 @@ CONFIG := clang # CONFIG := emcc # CONFIG := wasi # CONFIG := mxe -# CONFIG := msys2 +# CONFIG := msys2-32 # CONFIG := msys2-64 # features (the more the better) @@ -16,6 +16,7 @@ ENABLE_GLOB := 1 ENABLE_PLUGINS := 1 ENABLE_READLINE := 1 ENABLE_EDITLINE := 0 +ENABLE_GHDL := 0 ENABLE_VERIFIC := 0 ENABLE_COVER := 1 ENABLE_LIBYOSYS := 0 @@ -125,7 +126,7 @@ LDFLAGS += -rdynamic LDLIBS += -lrt endif -YOSYS_VER := 0.9+3710 +YOSYS_VER := 0.9+3901 GIT_REV := $(shell cd $(YOSYS_SRC) && git rev-parse --short HEAD 2> /dev/null || echo UNKNOWN) OBJS = kernel/version_$(GIT_REV).o @@ -322,7 +323,7 @@ ABCMKARGS += ARCHFLAGS="-DWIN32_NO_DLL -DHAVE_STRUCT_TIMESPEC -fpermissive -w" ABCMKARGS += LIBS="lib/x86/pthreadVC2.lib -s" LDFLAGS="-Wl,--allow-multiple-definition" ABC_USE_NO_READLINE=1 CC="/usr/local/src/mxe/usr/bin/i686-w64-mingw32.static-gcc" EXE = .exe -else ifeq ($(CONFIG),msys2) +else ifeq ($(CONFIG),msys2-32) CXX = i686-w64-mingw32-g++ LD = i686-w64-mingw32-g++ CXXFLAGS += -std=c++11 -Os -D_POSIX_SOURCE -DYOSYS_WIN32_UNIX_DIR @@ -345,7 +346,7 @@ ABCMKARGS += LIBS="-lpthread -s" ABC_USE_NO_READLINE=0 CC="x86_64-w64-mingw32-gc EXE = .exe else ifneq ($(CONFIG),none) -$(error Invalid CONFIG setting '$(CONFIG)'. Valid values: clang, gcc, gcc-4.8, emcc, mxe, msys2, msys2-64) +$(error Invalid CONFIG setting '$(CONFIG)'. Valid values: clang, gcc, gcc-4.8, emcc, mxe, msys2-32, msys2-64) endif ifeq ($(ENABLE_LIBYOSYS),1) @@ -511,6 +512,14 @@ endif endif endif +ifeq ($(ENABLE_GHDL),1) +GHDL_PREFIX ?= $(PREFIX) +GHDL_INCLUDE_DIR ?= $(GHDL_PREFIX)/include +GHDL_LIB_DIR ?= $(GHDL_PREFIX)/lib +CXXFLAGS += -I$(GHDL_INCLUDE_DIR) -DYOSYS_ENABLE_GHDL +LDLIBS += $(GHDL_LIB_DIR)/libghdl.a $(file <$(GHDL_LIB_DIR)/libghdl.link) +endif + ifeq ($(ENABLE_VERIFIC),1) VERIFIC_DIR ?= /usr/local/src/verific_lib VERIFIC_COMPONENTS ?= verilog vhdl database util containers hier_tree @@ -608,6 +617,11 @@ $(eval $(call add_include_file,backends/cxxrtl/cxxrtl_vcd_capi.cc)) $(eval $(call add_include_file,backends/cxxrtl/cxxrtl_vcd_capi.h)) OBJS += kernel/driver.o kernel/register.o kernel/rtlil.o kernel/log.o kernel/calc.o kernel/yosys.o +ifeq ($(ENABLE_ABC),1) +ifneq ($(ABCEXTERNAL),) +kernel/yosys.o: CXXFLAGS += -DABCEXTERNAL='"$(ABCEXTERNAL)"' +endif +endif OBJS += kernel/cellaigs.o kernel/celledges.o kernel/satgen.o kernel/mem.o kernel/log.o: CXXFLAGS += -DYOSYS_SRC='"$(YOSYS_SRC)"' @@ -984,13 +998,15 @@ config-mxe: clean echo 'CONFIG := mxe' > Makefile.conf echo 'ENABLE_PLUGINS := 0' >> Makefile.conf -config-msys2: clean - echo 'CONFIG := msys2' > Makefile.conf +config-msys2-32: clean + echo 'CONFIG := msys2-32' > Makefile.conf echo 'ENABLE_PLUGINS := 0' >> Makefile.conf + echo "PREFIX := $(MINGW_PREFIX)" >> Makefile.conf config-msys2-64: clean echo 'CONFIG := msys2-64' > Makefile.conf echo 'ENABLE_PLUGINS := 0' >> Makefile.conf + echo "PREFIX := $(MINGW_PREFIX)" >> Makefile.conf config-cygwin: clean echo 'CONFIG := cygwin' > Makefile.conf diff --git a/backends/cxxrtl/cxxrtl.h b/backends/cxxrtl/cxxrtl.h index 41089a153..0e55c46c2 100644 --- a/backends/cxxrtl/cxxrtl.h +++ b/backends/cxxrtl/cxxrtl.h @@ -36,22 +36,48 @@ #include <map> #include <algorithm> #include <memory> +#include <functional> #include <sstream> #include <backends/cxxrtl/cxxrtl_capi.h> +#ifndef __has_attribute +# define __has_attribute(x) 0 +#endif + // CXXRTL essentially uses the C++ compiler as a hygienic macro engine that feeds an instruction selector. // It generates a lot of specialized template functions with relatively large bodies that, when inlined // into the caller and (for those with loops) unrolled, often expose many new optimization opportunities. // Because of this, most of the CXXRTL runtime must be always inlined for best performance. -#ifndef __has_attribute -# define __has_attribute(x) 0 -#endif #if __has_attribute(always_inline) #define CXXRTL_ALWAYS_INLINE inline __attribute__((__always_inline__)) #else #define CXXRTL_ALWAYS_INLINE inline #endif +// Conversely, some functions in the generated code are extremely large yet very cold, with both of these +// properties being extreme enough to confuse C++ compilers into spending pathological amounts of time +// on a futile (the code becomes worse) attempt to optimize the least important parts of code. +#if __has_attribute(optnone) +#define CXXRTL_EXTREMELY_COLD __attribute__((__optnone__)) +#elif __has_attribute(optimize) +#define CXXRTL_EXTREMELY_COLD __attribute__((__optimize__(0))) +#else +#define CXXRTL_EXTREMELY_COLD +#endif + +// CXXRTL uses assert() to check for C++ contract violations (which may result in e.g. undefined behavior +// of the simulation code itself), and CXXRTL_ASSERT to check for RTL contract violations (which may at +// most result in undefined simulation results). +// +// Though by default, CXXRTL_ASSERT() expands to assert(), it may be overridden e.g. when integrating +// the simulation into another process that should survive violating RTL contracts. +#ifndef CXXRTL_ASSERT +#ifndef CXXRTL_NDEBUG +#define CXXRTL_ASSERT(x) assert(x) +#else +#define CXXRTL_ASSERT(x) +#endif +#endif namespace cxxrtl { @@ -96,9 +122,11 @@ struct value : public expr_base<value<Bits>> { explicit constexpr value(Init ...init) : data{init...} {} value(const value<Bits> &) = default; - value(value<Bits> &&) = default; value<Bits> &operator=(const value<Bits> &) = default; + value(value<Bits> &&) = default; + value<Bits> &operator=(value<Bits> &&) = default; + // A (no-op) helper that forces the cast to value<>. CXXRTL_ALWAYS_INLINE const value<Bits> &val() const { @@ -289,6 +317,14 @@ struct value : public expr_base<value<Bits>> { return sext_cast<NewBits>()(*this); } + // Bit replication is far more efficient than the equivalent concatenation. + template<size_t Count> + CXXRTL_ALWAYS_INLINE + value<Bits * Count> repeat() const { + static_assert(Bits == 1, "repeat() is implemented only for 1-bit values"); + return *this ? value<Bits * Count>().bit_not() : value<Bits * Count>(); + } + // Operations with run-time parameters (offsets, amounts, etc). // // These operations are used for computations. @@ -643,14 +679,20 @@ struct wire { value<Bits> next; wire() = default; - constexpr wire(const value<Bits> &init) : curr(init), next(init) {} + explicit constexpr wire(const value<Bits> &init) : curr(init), next(init) {} template<typename... Init> explicit constexpr wire(Init ...init) : curr{init...}, next{init...} {} + // Copying and copy-assigning values is natural. If, however, a value is replaced with a wire, + // e.g. because a module is built with a different optimization level, then existing code could + // unintentionally copy a wire instead, which would create a subtle but serious bug. To make sure + // this doesn't happen, prohibit copying and copy-assigning wires. wire(const wire<Bits> &) = delete; - wire(wire<Bits> &&) = default; wire<Bits> &operator=(const wire<Bits> &) = delete; + wire(wire<Bits> &&) = default; + wire<Bits> &operator=(wire<Bits> &&) = default; + template<class IntegerT> CXXRTL_ALWAYS_INLINE IntegerT get() const { @@ -692,6 +734,9 @@ struct memory { memory(const memory<Width> &) = delete; memory<Width> &operator=(const memory<Width> &) = delete; + memory(memory<Width> &&) = default; + memory<Width> &operator=(memory<Width> &&) = default; + // The only way to get the compiler to put the initializer in .rodata and do not copy it on stack is to stuff it // into a plain array. You'd think an std::initializer_list would work here, but it doesn't, because you can't // construct an initializer_list in a constexpr (or something) and so if you try to do that the whole thing is @@ -815,9 +860,12 @@ struct metadata { typedef std::map<std::string, metadata> metadata_map; -// Helper class to disambiguate values/wires and their aliases. +// Tag class to disambiguate values/wires and their aliases. struct debug_alias {}; +// Tag declaration to disambiguate values and debug outlines. +using debug_outline = ::_cxxrtl_outline; + // This structure is intended for consumption via foreign function interfaces, like Python's ctypes. // Because of this it uses a C-style layout that is easy to parse rather than more idiomatic C++. // @@ -826,10 +874,11 @@ struct debug_alias {}; struct debug_item : ::cxxrtl_object { // Object types. enum : uint32_t { - VALUE = CXXRTL_VALUE, - WIRE = CXXRTL_WIRE, - MEMORY = CXXRTL_MEMORY, - ALIAS = CXXRTL_ALIAS, + VALUE = CXXRTL_VALUE, + WIRE = CXXRTL_WIRE, + MEMORY = CXXRTL_MEMORY, + ALIAS = CXXRTL_ALIAS, + OUTLINE = CXXRTL_OUTLINE, }; // Object flags. @@ -856,6 +905,7 @@ struct debug_item : ::cxxrtl_object { zero_at = 0; curr = item.data; next = item.data; + outline = nullptr; } template<size_t Bits> @@ -870,6 +920,7 @@ struct debug_item : ::cxxrtl_object { zero_at = 0; curr = const_cast<chunk_t*>(item.data); next = nullptr; + outline = nullptr; } template<size_t Bits> @@ -885,6 +936,7 @@ struct debug_item : ::cxxrtl_object { zero_at = 0; curr = item.curr.data; next = item.next.data; + outline = nullptr; } template<size_t Width> @@ -899,6 +951,7 @@ struct debug_item : ::cxxrtl_object { zero_at = zero_offset; curr = item.data.empty() ? nullptr : item.data[0].data; next = nullptr; + outline = nullptr; } template<size_t Bits> @@ -913,6 +966,7 @@ struct debug_item : ::cxxrtl_object { zero_at = 0; curr = const_cast<chunk_t*>(item.data); next = nullptr; + outline = nullptr; } template<size_t Bits> @@ -928,6 +982,22 @@ struct debug_item : ::cxxrtl_object { zero_at = 0; curr = const_cast<chunk_t*>(item.curr.data); next = nullptr; + outline = nullptr; + } + + template<size_t Bits> + debug_item(debug_outline &group, const value<Bits> &item, size_t lsb_offset = 0) { + static_assert(sizeof(item) == value<Bits>::chunks * sizeof(chunk_t), + "value<Bits> is not compatible with C layout"); + type = OUTLINE; + flags = DRIVEN_COMB; + width = Bits; + lsb_at = lsb_offset; + depth = 1; + zero_at = 0; + curr = const_cast<chunk_t*>(item.data); + next = nullptr; + outline = &group; } }; static_assert(std::is_standard_layout<debug_item>::value, "debug_item is not compatible with C layout"); @@ -965,13 +1035,25 @@ struct debug_items { } }; +// Tag class to disambiguate module move constructor and module constructor that takes black boxes +// out of another instance of the module. +struct adopt {}; + struct module { module() {} virtual ~module() {} + // Modules with black boxes cannot be copied. Although not all designs include black boxes, + // delete the copy constructor and copy assignment operator to make sure that any downstream + // code that manipulates modules doesn't accidentally depend on their availability. module(const module &) = delete; module &operator=(const module &) = delete; + module(module &&) = default; + module &operator=(module &&) = default; + + virtual void reset() = 0; + virtual bool eval() = 0; virtual bool commit() = 0; @@ -992,11 +1074,16 @@ struct module { } // namespace cxxrtl -// Internal structure used to communicate with the implementation of the C interface. +// Internal structures used to communicate with the implementation of the C interface. + typedef struct _cxxrtl_toplevel { std::unique_ptr<cxxrtl::module> module; } *cxxrtl_toplevel; +typedef struct _cxxrtl_outline { + std::function<void()> eval; +} *cxxrtl_outline; + // Definitions of internal Yosys cells. Other than the functions in this namespace, CXXRTL is fully generic // and indepenent of Yosys implementation details. // @@ -1130,49 +1217,49 @@ value<BitsY> xnor_ss(const value<BitsA> &a, const value<BitsB> &b) { template<size_t BitsY, size_t BitsA, size_t BitsB> CXXRTL_ALWAYS_INLINE value<BitsY> shl_uu(const value<BitsA> &a, const value<BitsB> &b) { - return a.template zcast<BitsY>().template shl(b); + return a.template zcast<BitsY>().shl(b); } template<size_t BitsY, size_t BitsA, size_t BitsB> CXXRTL_ALWAYS_INLINE value<BitsY> shl_su(const value<BitsA> &a, const value<BitsB> &b) { - return a.template scast<BitsY>().template shl(b); + return a.template scast<BitsY>().shl(b); } template<size_t BitsY, size_t BitsA, size_t BitsB> CXXRTL_ALWAYS_INLINE value<BitsY> sshl_uu(const value<BitsA> &a, const value<BitsB> &b) { - return a.template zcast<BitsY>().template shl(b); + return a.template zcast<BitsY>().shl(b); } template<size_t BitsY, size_t BitsA, size_t BitsB> CXXRTL_ALWAYS_INLINE value<BitsY> sshl_su(const value<BitsA> &a, const value<BitsB> &b) { - return a.template scast<BitsY>().template shl(b); + return a.template scast<BitsY>().shl(b); } template<size_t BitsY, size_t BitsA, size_t BitsB> CXXRTL_ALWAYS_INLINE value<BitsY> shr_uu(const value<BitsA> &a, const value<BitsB> &b) { - return a.template shr(b).template zcast<BitsY>(); + return a.shr(b).template zcast<BitsY>(); } template<size_t BitsY, size_t BitsA, size_t BitsB> CXXRTL_ALWAYS_INLINE value<BitsY> shr_su(const value<BitsA> &a, const value<BitsB> &b) { - return a.template shr(b).template scast<BitsY>(); + return a.shr(b).template scast<BitsY>(); } template<size_t BitsY, size_t BitsA, size_t BitsB> CXXRTL_ALWAYS_INLINE value<BitsY> sshr_uu(const value<BitsA> &a, const value<BitsB> &b) { - return a.template shr(b).template zcast<BitsY>(); + return a.shr(b).template zcast<BitsY>(); } template<size_t BitsY, size_t BitsA, size_t BitsB> CXXRTL_ALWAYS_INLINE value<BitsY> sshr_su(const value<BitsA> &a, const value<BitsB> &b) { - return a.template sshr(b).template scast<BitsY>(); + return a.sshr(b).template scast<BitsY>(); } template<size_t BitsY, size_t BitsA, size_t BitsB> diff --git a/backends/cxxrtl/cxxrtl_backend.cc b/backends/cxxrtl/cxxrtl_backend.cc index a48ea5b23..39046bd78 100644 --- a/backends/cxxrtl/cxxrtl_backend.cc +++ b/backends/cxxrtl/cxxrtl_backend.cc @@ -195,7 +195,7 @@ bool is_extending_cell(RTLIL::IdString type) ID($reduce_and), ID($reduce_or), ID($reduce_xor), ID($reduce_xnor), ID($reduce_bool)); } -bool is_elidable_cell(RTLIL::IdString type) +bool is_inlinable_cell(RTLIL::IdString type) { return is_unary_cell(type) || is_binary_cell(type) || type.in( ID($mux), ID($concat), ID($slice), ID($pmux)); @@ -211,7 +211,12 @@ bool is_ff_cell(RTLIL::IdString type) bool is_internal_cell(RTLIL::IdString type) { - return type[0] == '$' && !type.begins_with("$paramod"); + return !type.isPublic() && !type.begins_with("$paramod"); +} + +bool is_effectful_cell(RTLIL::IdString type) +{ + return type == ID($memwr) || type.isPublic(); } bool is_cxxrtl_blackbox_cell(const RTLIL::Cell *cell) @@ -227,18 +232,15 @@ enum class CxxrtlPortType { SYNC = 2, }; -CxxrtlPortType cxxrtl_port_type(const RTLIL::Cell *cell, RTLIL::IdString port) +CxxrtlPortType cxxrtl_port_type(RTLIL::Module *module, RTLIL::IdString port) { - RTLIL::Module *cell_module = cell->module->design->module(cell->type); - if (cell_module == nullptr || !cell_module->get_bool_attribute(ID(cxxrtl_blackbox))) - return CxxrtlPortType::UNKNOWN; - RTLIL::Wire *cell_output_wire = cell_module->wire(port); - log_assert(cell_output_wire != nullptr); - bool is_comb = cell_output_wire->get_bool_attribute(ID(cxxrtl_comb)); - bool is_sync = cell_output_wire->get_bool_attribute(ID(cxxrtl_sync)); + RTLIL::Wire *output_wire = module->wire(port); + log_assert(output_wire != nullptr); + bool is_comb = output_wire->get_bool_attribute(ID(cxxrtl_comb)); + bool is_sync = output_wire->get_bool_attribute(ID(cxxrtl_sync)); if (is_comb && is_sync) log_cmd_error("Port `%s.%s' is marked as both `cxxrtl_comb` and `cxxrtl_sync`.\n", - log_id(cell_module), log_signal(cell_output_wire)); + log_id(module), log_signal(output_wire)); else if (is_comb) return CxxrtlPortType::COMB; else if (is_sync) @@ -246,6 +248,14 @@ CxxrtlPortType cxxrtl_port_type(const RTLIL::Cell *cell, RTLIL::IdString port) return CxxrtlPortType::UNKNOWN; } +CxxrtlPortType cxxrtl_port_type(const RTLIL::Cell *cell, RTLIL::IdString port) +{ + RTLIL::Module *cell_module = cell->module->design->module(cell->type); + if (cell_module == nullptr || !cell_module->get_bool_attribute(ID(cxxrtl_blackbox))) + return CxxrtlPortType::UNKNOWN; + return cxxrtl_port_type(cell_module, port); +} + bool is_cxxrtl_comb_port(const RTLIL::Cell *cell, RTLIL::IdString port) { return cxxrtl_port_type(cell, port) == CxxrtlPortType::COMB; @@ -262,7 +272,8 @@ struct FlowGraph { CONNECT, CELL_SYNC, CELL_EVAL, - PROCESS + PROCESS_SYNC, + PROCESS_CASE, }; Type type; @@ -273,7 +284,9 @@ struct FlowGraph { std::vector<Node*> nodes; dict<const RTLIL::Wire*, pool<Node*, hash_ptr_ops>> wire_comb_defs, wire_sync_defs, wire_uses; - dict<const RTLIL::Wire*, bool> wire_def_elidable, wire_use_elidable; + dict<Node*, pool<const RTLIL::Wire*>, hash_ptr_ops> node_comb_defs, node_sync_defs, node_uses; + dict<const RTLIL::Wire*, bool> wire_def_inlinable; + dict<const RTLIL::Wire*, dict<Node*, bool, hash_ptr_ops>> wire_use_inlinable; dict<RTLIL::SigBit, bool> bit_has_state; ~FlowGraph() @@ -282,7 +295,7 @@ struct FlowGraph { delete node; } - void add_defs(Node *node, const RTLIL::SigSpec &sig, bool is_ff, bool elidable) + void add_defs(Node *node, const RTLIL::SigSpec &sig, bool is_ff, bool inlinable) { for (auto chunk : sig.chunks()) if (chunk.wire) { @@ -290,17 +303,19 @@ struct FlowGraph { // A sync def means that a wire holds design state because it is driven directly by // a flip-flop output. Such a wire can never be unbuffered. wire_sync_defs[chunk.wire].insert(node); + node_sync_defs[node].insert(chunk.wire); } else { // A comb def means that a wire doesn't hold design state. It might still be connected, // indirectly, to a flip-flop output. wire_comb_defs[chunk.wire].insert(node); + node_comb_defs[node].insert(chunk.wire); } } for (auto bit : sig.bits()) bit_has_state[bit] |= is_ff; - // Only comb defs of an entire wire in the right order can be elided. + // Only comb defs of an entire wire in the right order can be inlined. if (!is_ff && sig.is_wire()) - wire_def_elidable[sig.as_wire()] = elidable; + wire_def_inlinable[sig.as_wire()] = inlinable; } void add_uses(Node *node, const RTLIL::SigSpec &sig) @@ -308,26 +323,41 @@ struct FlowGraph { for (auto chunk : sig.chunks()) if (chunk.wire) { wire_uses[chunk.wire].insert(node); - // Only a single use of an entire wire in the right order can be elided. - // (But the use can include other chunks.) - if (!wire_use_elidable.count(chunk.wire)) - wire_use_elidable[chunk.wire] = true; + node_uses[node].insert(chunk.wire); + // Only a single use of an entire wire in the right order can be inlined. (But the use can include + // other chunks.) This is tracked per-node because a wire used by multiple nodes can still be inlined + // if all but one of those nodes is dead. + if (!wire_use_inlinable[chunk.wire].count(node)) + wire_use_inlinable[chunk.wire][node] = true; else - wire_use_elidable[chunk.wire] = false; + wire_use_inlinable[chunk.wire][node] = false; } } - bool is_elidable(const RTLIL::Wire *wire) const + bool is_inlinable(const RTLIL::Wire *wire) const { - if (wire_def_elidable.count(wire) && wire_use_elidable.count(wire)) - return wire_def_elidable.at(wire) && wire_use_elidable.at(wire); + // Can the wire be inlined at all? + if (wire_def_inlinable.count(wire)) + return wire_def_inlinable.at(wire); + return false; + } + + bool is_inlinable(const RTLIL::Wire *wire, const pool<Node*, hash_ptr_ops> &nodes) const + { + // Can the wire be inlined, knowing that the given nodes are reachable? + if (nodes.size() != 1) + return false; + Node *node = *nodes.begin(); + log_assert(node_uses.at(node).count(wire)); + if (is_inlinable(wire) && wire_use_inlinable.count(wire) && wire_use_inlinable.at(wire).count(node)) + return wire_use_inlinable.at(wire).at(node); return false; } // Connections void add_connect_defs_uses(Node *node, const RTLIL::SigSig &conn) { - add_defs(node, conn.first, /*is_ff=*/false, /*elidable=*/true); + add_defs(node, conn.first, /*is_ff=*/false, /*inlinable=*/true); add_uses(node, conn.second); } @@ -373,8 +403,8 @@ struct FlowGraph { for (auto conn : cell->connections()) if (cell->output(conn.first)) if (is_cxxrtl_sync_port(cell, conn.first)) { - // See note regarding elidability below. - add_defs(node, conn.second, /*is_ff=*/false, /*elidable=*/false); + // See note regarding inlinability below. + add_defs(node, conn.second, /*is_ff=*/false, /*inlinable=*/false); } } @@ -382,19 +412,19 @@ struct FlowGraph { { for (auto conn : cell->connections()) { if (cell->output(conn.first)) { - if (is_elidable_cell(cell->type)) - add_defs(node, conn.second, /*is_ff=*/false, /*elidable=*/true); + if (is_inlinable_cell(cell->type)) + add_defs(node, conn.second, /*is_ff=*/false, /*inlinable=*/true); else if (is_ff_cell(cell->type) || (cell->type == ID($memrd) && cell->getParam(ID::CLK_ENABLE).as_bool())) - add_defs(node, conn.second, /*is_ff=*/true, /*elidable=*/false); + add_defs(node, conn.second, /*is_ff=*/true, /*inlinable=*/false); else if (is_internal_cell(cell->type)) - add_defs(node, conn.second, /*is_ff=*/false, /*elidable=*/false); + add_defs(node, conn.second, /*is_ff=*/false, /*inlinable=*/false); else if (!is_cxxrtl_sync_port(cell, conn.first)) { - // Although at first it looks like outputs of user-defined cells may always be elided, the reality is - // more complex. Fully sync outputs produce no defs and so don't participate in elision. Fully comb + // Although at first it looks like outputs of user-defined cells may always be inlined, the reality is + // more complex. Fully sync outputs produce no defs and so don't participate in inlining. Fully comb // outputs are assigned in a different way depending on whether the cell's eval() immediately converged. - // Unknown/mixed outputs could be elided, but should be rare in practical designs and don't justify - // the infrastructure required to elide outputs of cells with many of them. - add_defs(node, conn.second, /*is_ff=*/false, /*elidable=*/false); + // Unknown/mixed outputs could be inlined, but should be rare in practical designs and don't justify + // the infrastructure required to inline outputs of cells with many of them. + add_defs(node, conn.second, /*is_ff=*/false, /*inlinable=*/false); } } if (cell->input(conn.first)) @@ -429,10 +459,10 @@ struct FlowGraph { } // Processes - void add_case_defs_uses(Node *node, const RTLIL::CaseRule *case_) + void add_case_rule_defs_uses(Node *node, const RTLIL::CaseRule *case_) { for (auto &action : case_->actions) { - add_defs(node, action.first, /*is_ff=*/false, /*elidable=*/false); + add_defs(node, action.first, /*is_ff=*/false, /*inlinable=*/false); add_uses(node, action.second); } for (auto sub_switch : case_->switches) { @@ -440,20 +470,19 @@ struct FlowGraph { for (auto sub_case : sub_switch->cases) { for (auto &compare : sub_case->compare) add_uses(node, compare); - add_case_defs_uses(node, sub_case); + add_case_rule_defs_uses(node, sub_case); } } } - void add_process_defs_uses(Node *node, const RTLIL::Process *process) + void add_sync_rules_defs_uses(Node *node, const RTLIL::Process *process) { - add_case_defs_uses(node, &process->root_case); for (auto sync : process->syncs) for (auto action : sync->actions) { if (sync->type == RTLIL::STp || sync->type == RTLIL::STn || sync->type == RTLIL::STe) - add_defs(node, action.first, /*is_ff=*/true, /*elidable=*/false); + add_defs(node, action.first, /*is_ff=*/true, /*inlinable=*/false); else - add_defs(node, action.first, /*is_ff=*/false, /*elidable=*/false); + add_defs(node, action.first, /*is_ff=*/false, /*inlinable=*/false); add_uses(node, action.second); } } @@ -461,10 +490,16 @@ struct FlowGraph { Node *add_node(const RTLIL::Process *process) { Node *node = new Node; - node->type = Node::Type::PROCESS; + node->type = Node::Type::PROCESS_SYNC; node->process = process; nodes.push_back(node); - add_process_defs_uses(node, process); + add_sync_rules_defs_uses(node, process); + + node = new Node; + node->type = Node::Type::PROCESS_CASE; + node->process = process; + nodes.push_back(node); + add_case_rule_defs_uses(node, &process->root_case); return node; } }; @@ -520,6 +555,58 @@ std::string get_hdl_name(T *object) return object->name.str().substr(1); } +struct WireType { + enum Type { + // Non-referenced wire; is not a part of the design. + UNUSED, + // Double-buffered wire; is a class member, and holds design state. + BUFFERED, + // Single-buffered wire; is a class member, but holds no state. + MEMBER, + // Single-buffered wire; is a class member, and is computed on demand. + OUTLINE, + // Local wire; is a local variable in eval method. + LOCAL, + // Inline wire; is an unnamed temporary in eval method. + INLINE, + // Alias wire; is replaced with aliasee, except in debug info. + ALIAS, + // Const wire; is replaced with constant, except in debug info. + CONST, + }; + + Type type = UNUSED; + const RTLIL::Cell *cell_subst = nullptr; // for INLINE + RTLIL::SigSpec sig_subst = {}; // for INLINE, ALIAS, and CONST + + WireType() = default; + + WireType(Type type) : type(type) { + log_assert(type == UNUSED || type == BUFFERED || type == MEMBER || type == OUTLINE || type == LOCAL); + } + + WireType(Type type, const RTLIL::Cell *cell) : type(type), cell_subst(cell) { + log_assert(type == INLINE && is_inlinable_cell(cell->type)); + } + + WireType(Type type, RTLIL::SigSpec sig) : type(type), sig_subst(sig) { + log_assert(type == INLINE || (type == ALIAS && sig.is_wire()) || (type == CONST && sig.is_fully_const())); + } + + bool is_buffered() const { return type == BUFFERED; } + bool is_member() const { return type == BUFFERED || type == MEMBER || type == OUTLINE; } + bool is_outline() const { return type == OUTLINE; } + bool is_named() const { return is_member() || type == LOCAL; } + bool is_local() const { return type == LOCAL || type == INLINE; } + bool is_exact() const { return type == ALIAS || type == CONST; } +}; + +// Tests for a SigSpec that is a valid clock input, clocks have to have a backing wire and be a single bit +// using this instead of sig.is_wire() solves issues when the clock is a slice instead of a full wire +bool is_valid_clock(const RTLIL::SigSpec& sig) { + return sig.is_chunk() && sig.is_bit() && sig[0].wire; +} + struct CxxrtlWorker { bool split_intf = false; std::string intf_filename; @@ -535,10 +622,13 @@ struct CxxrtlWorker { bool unbuffer_public = false; bool localize_internal = false; bool localize_public = false; - bool elide_internal = false; - bool elide_public = false; + bool inline_internal = false; + bool inline_public = false; bool debug_info = false; + bool debug_member = false; + bool debug_alias = false; + bool debug_eval = false; std::ostringstream f; std::string indent; @@ -549,12 +639,8 @@ struct CxxrtlWorker { dict<RTLIL::SigBit, RTLIL::SyncType> edge_types; pool<const RTLIL::Memory*> writable_memories; dict<const RTLIL::Cell*, pool<const RTLIL::Cell*>> transparent_for; - dict<const RTLIL::Wire*, FlowGraph::Node> elided_wires; - dict<const RTLIL::Module*, std::vector<FlowGraph::Node>> schedule; - pool<const RTLIL::Wire*> unbuffered_wires; - pool<const RTLIL::Wire*> localized_wires; - dict<const RTLIL::Wire*, const RTLIL::Wire*> debug_alias_wires; - dict<const RTLIL::Wire*, RTLIL::Const> debug_const_wires; + dict<const RTLIL::Module*, std::vector<FlowGraph::Node>> schedule, debug_schedule; + dict<const RTLIL::Wire*, WireType> wire_types, debug_wire_types; dict<RTLIL::SigBit, bool> bit_has_state; dict<const RTLIL::Module*, pool<std::string>> blackbox_specializations; dict<const RTLIL::Module*, bool> eval_converges; @@ -786,30 +872,37 @@ struct CxxrtlWorker { dump_const(data, data.size()); } - bool dump_sigchunk(const RTLIL::SigChunk &chunk, bool is_lhs) + bool dump_sigchunk(const RTLIL::SigChunk &chunk, bool is_lhs, bool for_debug = false) { if (chunk.wire == NULL) { dump_const(chunk.data, chunk.width, chunk.offset); return false; } else { - if (elided_wires.count(chunk.wire)) { - log_assert(!is_lhs); - const FlowGraph::Node &node = elided_wires[chunk.wire]; - switch (node.type) { - case FlowGraph::Node::Type::CONNECT: - dump_connect_elided(node.connect); - break; - case FlowGraph::Node::Type::CELL_EVAL: - log_assert(is_elidable_cell(node.cell->type)); - dump_cell_elided(node.cell); + const auto &wire_type = (for_debug ? debug_wire_types : wire_types)[chunk.wire]; + switch (wire_type.type) { + case WireType::BUFFERED: + f << mangle(chunk.wire) << (is_lhs ? ".next" : ".curr"); + break; + case WireType::MEMBER: + case WireType::LOCAL: + case WireType::OUTLINE: + f << mangle(chunk.wire); + break; + case WireType::INLINE: + log_assert(!is_lhs); + if (wire_type.cell_subst != nullptr) { + dump_cell_expr(wire_type.cell_subst, for_debug); break; - default: - log_assert(false); - } - } else if (unbuffered_wires[chunk.wire]) { - f << mangle(chunk.wire); - } else { - f << mangle(chunk.wire) << (is_lhs ? ".next" : ".curr"); + } + YS_FALLTHROUGH + case WireType::ALIAS: + case WireType::CONST: + log_assert(!is_lhs); + return dump_sigspec(wire_type.sig_subst.extract(chunk.offset, chunk.width), is_lhs, for_debug); + case WireType::UNUSED: + log_assert(is_lhs); + f << "value<" << chunk.width << ">()"; + return false; } if (chunk.width == chunk.wire->width && chunk.offset == 0) return false; @@ -821,92 +914,116 @@ struct CxxrtlWorker { } } - bool dump_sigspec(const RTLIL::SigSpec &sig, bool is_lhs) + bool dump_sigspec(const RTLIL::SigSpec &sig, bool is_lhs, bool for_debug = false) { if (sig.empty()) { f << "value<0>()"; return false; } else if (sig.is_chunk()) { - return dump_sigchunk(sig.as_chunk(), is_lhs); + return dump_sigchunk(sig.as_chunk(), is_lhs, for_debug); } else { - dump_sigchunk(*sig.chunks().rbegin(), is_lhs); - for (auto it = sig.chunks().rbegin() + 1; it != sig.chunks().rend(); ++it) { - f << ".concat("; - dump_sigchunk(*it, is_lhs); - f << ")"; + bool first = true; + auto chunks = sig.chunks(); + for (auto it = chunks.rbegin(); it != chunks.rend(); it++) { + if (!first) + f << ".concat("; + bool is_complex = dump_sigchunk(*it, is_lhs, for_debug); + if (!is_lhs && it->width == 1) { + size_t repeat = 1; + while ((it + repeat) != chunks.rend() && *(it + repeat) == *it) + repeat++; + if (repeat > 1) { + if (is_complex) + f << ".val()"; + f << ".repeat<" << repeat << ">()"; + } + it += repeat - 1; + } + if (!first) + f << ")"; + first = false; } return true; } } - void dump_sigspec_lhs(const RTLIL::SigSpec &sig) + void dump_sigspec_lhs(const RTLIL::SigSpec &sig, bool for_debug = false) { - dump_sigspec(sig, /*is_lhs=*/true); + dump_sigspec(sig, /*is_lhs=*/true, for_debug); } - void dump_sigspec_rhs(const RTLIL::SigSpec &sig) + void dump_sigspec_rhs(const RTLIL::SigSpec &sig, bool for_debug = false) { // In the contexts where we want template argument deduction to occur for `template<size_t Bits> ... value<Bits>`, // it is necessary to have the argument to already be a `value<N>`, since template argument deduction and implicit // type conversion are mutually exclusive. In these contexts, we use dump_sigspec_rhs() to emit an explicit // type conversion, but only if the expression needs it. - bool is_complex = dump_sigspec(sig, /*is_lhs=*/false); + bool is_complex = dump_sigspec(sig, /*is_lhs=*/false, for_debug); if (is_complex) f << ".val()"; } - void collect_sigspec_rhs(const RTLIL::SigSpec &sig, std::vector<RTLIL::IdString> &cells) + void dump_inlined_cells(const std::vector<const RTLIL::Cell*> &cells) + { + if (cells.empty()) { + f << indent << "// connection\n"; + } else if (cells.size() == 1) { + dump_attrs(cells.front()); + f << indent << "// cell " << cells.front()->name.str() << "\n"; + } else { + f << indent << "// cells"; + for (auto cell : cells) + f << " " << cell->name.str(); + f << "\n"; + } + } + + void collect_sigspec_rhs(const RTLIL::SigSpec &sig, bool for_debug, std::vector<const RTLIL::Cell*> &cells) { for (auto chunk : sig.chunks()) { - if (!chunk.wire || !elided_wires.count(chunk.wire)) + if (!chunk.wire) continue; - - const FlowGraph::Node &node = elided_wires[chunk.wire]; - switch (node.type) { - case FlowGraph::Node::Type::CONNECT: - collect_connect(node.connect, cells); - break; - case FlowGraph::Node::Type::CELL_EVAL: - collect_cell_eval(node.cell, cells); + const auto &wire_type = wire_types[chunk.wire]; + switch (wire_type.type) { + case WireType::INLINE: + if (wire_type.cell_subst != nullptr) { + collect_cell_eval(wire_type.cell_subst, for_debug, cells); + break; + } + YS_FALLTHROUGH + case WireType::ALIAS: + collect_sigspec_rhs(wire_type.sig_subst, for_debug, cells); break; default: - log_assert(false); + break; } } } - void dump_connect_elided(const RTLIL::SigSig &conn) - { - dump_sigspec_rhs(conn.second); - } - - bool is_connect_elided(const RTLIL::SigSig &conn) + void dump_connect_expr(const RTLIL::SigSig &conn, bool for_debug = false) { - return conn.first.is_wire() && elided_wires.count(conn.first.as_wire()); + dump_sigspec_rhs(conn.second, for_debug); } - void collect_connect(const RTLIL::SigSig &conn, std::vector<RTLIL::IdString> &cells) + void dump_connect(const RTLIL::SigSig &conn, bool for_debug = false) { - if (!is_connect_elided(conn)) - return; + std::vector<const RTLIL::Cell*> inlined_cells; + collect_sigspec_rhs(conn.second, for_debug, inlined_cells); + dump_inlined_cells(inlined_cells); - collect_sigspec_rhs(conn.second, cells); - } - - void dump_connect(const RTLIL::SigSig &conn) - { - if (is_connect_elided(conn)) - return; - - f << indent << "// connection\n"; f << indent; - dump_sigspec_lhs(conn.first); + dump_sigspec_lhs(conn.first, for_debug); f << " = "; - dump_connect_elided(conn); + dump_connect_expr(conn, for_debug); f << ";\n"; } - void dump_cell_sync(const RTLIL::Cell *cell) + void collect_connect(const RTLIL::SigSig &conn, bool for_debug, std::vector<const RTLIL::Cell*> &cells) + { + collect_sigspec_rhs(conn.second, for_debug, cells); + } + + void dump_cell_sync(const RTLIL::Cell *cell, bool for_debug = false) { const char *access = is_cxxrtl_blackbox_cell(cell) ? "->" : "."; f << indent << "// cell " << cell->name.str() << " syncs\n"; @@ -914,12 +1031,12 @@ struct CxxrtlWorker { if (cell->output(conn.first)) if (is_cxxrtl_sync_port(cell, conn.first)) { f << indent; - dump_sigspec_lhs(conn.second); + dump_sigspec_lhs(conn.second, for_debug); f << " = " << mangle(cell) << access << mangle_wire_name(conn.first) << ".curr;\n"; } } - void dump_cell_elided(const RTLIL::Cell *cell) + void dump_cell_expr(const RTLIL::Cell *cell, bool for_debug = false) { // Unary cells if (is_unary_cell(cell->type)) { @@ -927,7 +1044,7 @@ struct CxxrtlWorker { if (is_extending_cell(cell->type)) f << '_' << (cell->getParam(ID::A_SIGNED).as_bool() ? 's' : 'u'); f << "<" << cell->getParam(ID::Y_WIDTH).as_int() << ">("; - dump_sigspec_rhs(cell->getPort(ID::A)); + dump_sigspec_rhs(cell->getPort(ID::A), for_debug); f << ")"; // Binary cells } else if (is_binary_cell(cell->type)) { @@ -936,18 +1053,18 @@ struct CxxrtlWorker { f << '_' << (cell->getParam(ID::A_SIGNED).as_bool() ? 's' : 'u') << (cell->getParam(ID::B_SIGNED).as_bool() ? 's' : 'u'); f << "<" << cell->getParam(ID::Y_WIDTH).as_int() << ">("; - dump_sigspec_rhs(cell->getPort(ID::A)); + dump_sigspec_rhs(cell->getPort(ID::A), for_debug); f << ", "; - dump_sigspec_rhs(cell->getPort(ID::B)); + dump_sigspec_rhs(cell->getPort(ID::B), for_debug); f << ")"; // Muxes } else if (cell->type == ID($mux)) { f << "("; - dump_sigspec_rhs(cell->getPort(ID::S)); + dump_sigspec_rhs(cell->getPort(ID::S), for_debug); f << " ? "; - dump_sigspec_rhs(cell->getPort(ID::B)); + dump_sigspec_rhs(cell->getPort(ID::B), for_debug); f << " : "; - dump_sigspec_rhs(cell->getPort(ID::A)); + dump_sigspec_rhs(cell->getPort(ID::A), for_debug); f << ")"; // Parallel (one-hot) muxes } else if (cell->type == ID($pmux)) { @@ -955,24 +1072,24 @@ struct CxxrtlWorker { int s_width = cell->getParam(ID::S_WIDTH).as_int(); for (int part = 0; part < s_width; part++) { f << "("; - dump_sigspec_rhs(cell->getPort(ID::S).extract(part)); + dump_sigspec_rhs(cell->getPort(ID::S).extract(part), for_debug); f << " ? "; - dump_sigspec_rhs(cell->getPort(ID::B).extract(part * width, width)); + dump_sigspec_rhs(cell->getPort(ID::B).extract(part * width, width), for_debug); f << " : "; } - dump_sigspec_rhs(cell->getPort(ID::A)); + dump_sigspec_rhs(cell->getPort(ID::A), for_debug); for (int part = 0; part < s_width; part++) { f << ")"; } // Concats } else if (cell->type == ID($concat)) { - dump_sigspec_rhs(cell->getPort(ID::B)); + dump_sigspec_rhs(cell->getPort(ID::B), for_debug); f << ".concat("; - dump_sigspec_rhs(cell->getPort(ID::A)); + dump_sigspec_rhs(cell->getPort(ID::A), for_debug); f << ").val()"; // Slices } else if (cell->type == ID($slice)) { - dump_sigspec_rhs(cell->getPort(ID::A)); + dump_sigspec_rhs(cell->getPort(ID::A), for_debug); f << ".slice<"; f << cell->getParam(ID::OFFSET).as_int() + cell->getParam(ID::Y_WIDTH).as_int() - 1; f << ","; @@ -983,61 +1100,33 @@ struct CxxrtlWorker { } } - bool is_cell_elided(const RTLIL::Cell *cell) + void dump_cell_eval(const RTLIL::Cell *cell, bool for_debug = false) { - return is_elidable_cell(cell->type) && cell->hasPort(ID::Y) && cell->getPort(ID::Y).is_wire() && - elided_wires.count(cell->getPort(ID::Y).as_wire()); - } - - void collect_cell_eval(const RTLIL::Cell *cell, std::vector<RTLIL::IdString> &cells) - { - if (!is_cell_elided(cell)) - return; - - cells.push_back(cell->name); - for (auto port : cell->connections()) - if (port.first != ID::Y) - collect_sigspec_rhs(port.second, cells); - } - - void dump_cell_eval(const RTLIL::Cell *cell) - { - if (is_cell_elided(cell)) - return; - if (cell->type == ID($meminit)) - return; // Handled elsewhere. - - std::vector<RTLIL::IdString> elided_cells; - if (is_elidable_cell(cell->type)) { - for (auto port : cell->connections()) - if (port.first != ID::Y) - collect_sigspec_rhs(port.second, elided_cells); - } - if (elided_cells.empty()) { - dump_attrs(cell); - f << indent << "// cell " << cell->name.str() << "\n"; - } else { - f << indent << "// cells"; - for (auto elided_cell : elided_cells) - f << " " << elided_cell.str(); - f << "\n"; - } + std::vector<const RTLIL::Cell*> inlined_cells; + collect_cell_eval(cell, for_debug, inlined_cells); + dump_inlined_cells(inlined_cells); // Elidable cells - if (is_elidable_cell(cell->type)) { + if (is_inlinable_cell(cell->type)) { f << indent; - dump_sigspec_lhs(cell->getPort(ID::Y)); + dump_sigspec_lhs(cell->getPort(ID::Y), for_debug); f << " = "; - dump_cell_elided(cell); + dump_cell_expr(cell, for_debug); f << ";\n"; // Flip-flops } else if (is_ff_cell(cell->type)) { - if (cell->hasPort(ID::CLK) && cell->getPort(ID::CLK).is_wire()) { + log_assert(!for_debug); + // Clocks might be slices of larger signals but should only ever be single bit + if (cell->hasPort(ID::CLK) && is_valid_clock(cell->getPort(ID::CLK))) { // Edge-sensitive logic RTLIL::SigBit clk_bit = cell->getPort(ID::CLK)[0]; clk_bit = sigmaps[clk_bit.wire->module](clk_bit); - f << indent << "if (" << (cell->getParam(ID::CLK_POLARITY).as_bool() ? "posedge_" : "negedge_") - << mangle(clk_bit) << ") {\n"; + if (clk_bit.wire) { + f << indent << "if (" << (cell->getParam(ID::CLK_POLARITY).as_bool() ? "posedge_" : "negedge_") + << mangle(clk_bit) << ") {\n"; + } else { + f << indent << "if (false) {\n"; + } inc_indent(); if (cell->hasPort(ID::EN)) { f << indent << "if ("; @@ -1128,10 +1217,15 @@ struct CxxrtlWorker { // Memory ports } else if (cell->type.in(ID($memrd), ID($memwr))) { if (cell->getParam(ID::CLK_ENABLE).as_bool()) { + log_assert(!for_debug); RTLIL::SigBit clk_bit = cell->getPort(ID::CLK)[0]; clk_bit = sigmaps[clk_bit.wire->module](clk_bit); - f << indent << "if (" << (cell->getParam(ID::CLK_POLARITY).as_bool() ? "posedge_" : "negedge_") - << mangle(clk_bit) << ") {\n"; + if (clk_bit.wire) { + f << indent << "if (" << (cell->getParam(ID::CLK_POLARITY).as_bool() ? "posedge_" : "negedge_") + << mangle(clk_bit) << ") {\n"; + } else { + f << indent << "if (false) {\n"; + } inc_indent(); } RTLIL::Memory *memory = cell->module->memories[cell->getParam(ID::MEMID).decode_string()]; @@ -1149,12 +1243,12 @@ struct CxxrtlWorker { } // The generated code has two bounds checks; one in an assertion, and another that guards the read. // This is done so that the code does not invoke undefined behavior under any conditions, but nevertheless - // loudly crashes if an illegal condition is encountered. The assert may be turned off with -DNDEBUG not - // just for release builds, but also to make sure the simulator (which is presumably embedded in some + // loudly crashes if an illegal condition is encountered. The assert may be turned off with -DCXXRTL_NDEBUG + // not only for release builds, but also to make sure the simulator (which is presumably embedded in some // larger program) will never crash the code that calls into it. // // If assertions are disabled, out of bounds reads are defined to return zero. - f << indent << "assert(" << valid_index_temp << ".valid && \"out of bounds read\");\n"; + f << indent << "CXXRTL_ASSERT(" << valid_index_temp << ".valid && \"out of bounds read\");\n"; f << indent << "if(" << valid_index_temp << ".valid) {\n"; inc_indent(); if (writable_memories[memory]) { @@ -1211,7 +1305,7 @@ struct CxxrtlWorker { // See above for rationale of having both the assert and the condition. // // If assertions are disabled, out of bounds writes are defined to do nothing. - f << indent << "assert(" << valid_index_temp << ".valid && \"out of bounds write\");\n"; + f << indent << "CXXRTL_ASSERT(" << valid_index_temp << ".valid && \"out of bounds write\");\n"; f << indent << "if (" << valid_index_temp << ".valid) {\n"; inc_indent(); f << indent << mangle(memory) << ".update(" << valid_index_temp << ".index, "; @@ -1231,11 +1325,21 @@ struct CxxrtlWorker { log_cmd_error("Unsupported internal cell `%s'.\n", cell->type.c_str()); // User cells } else { + log_assert(!for_debug); log_assert(cell->known()); + bool buffered_inputs = false; const char *access = is_cxxrtl_blackbox_cell(cell) ? "->" : "."; for (auto conn : cell->connections()) - if (cell->input(conn.first) && !cell->output(conn.first)) { - f << indent << mangle(cell) << access << mangle_wire_name(conn.first) << " = "; + if (cell->input(conn.first)) { + RTLIL::Module *cell_module = cell->module->design->module(cell->type); + log_assert(cell_module != nullptr && cell_module->wire(conn.first) && conn.second.is_wire()); + RTLIL::Wire *cell_module_wire = cell_module->wire(conn.first); + f << indent << mangle(cell) << access << mangle_wire_name(conn.first); + if (!is_cxxrtl_blackbox_cell(cell) && wire_types[cell_module_wire].is_buffered()) { + buffered_inputs = true; + f << ".next"; + } + f << " = "; dump_sigspec_rhs(conn.second); f << ";\n"; if (getenv("CXXRTL_VOID_MY_WARRANTY")) { @@ -1247,19 +1351,11 @@ struct CxxrtlWorker { // with: // top.prev_p_clk = value<1>{0u}; top.p_clk = value<1>{1u}; top.step(); // Don't rely on this; it will be removed without warning. - RTLIL::Module *cell_module = cell->module->design->module(cell->type); - if (cell_module != nullptr && cell_module->wire(conn.first) && conn.second.is_wire()) { - RTLIL::Wire *cell_module_wire = cell_module->wire(conn.first); - if (edge_wires[conn.second.as_wire()] && edge_wires[cell_module_wire]) { - f << indent << mangle(cell) << access << "prev_" << mangle(cell_module_wire) << " = "; - f << "prev_" << mangle(conn.second.as_wire()) << ";\n"; - } + if (edge_wires[conn.second.as_wire()] && edge_wires[cell_module_wire]) { + f << indent << mangle(cell) << access << "prev_" << mangle(cell_module_wire) << " = "; + f << "prev_" << mangle(conn.second.as_wire()) << ";\n"; } } - } else if (cell->input(conn.first)) { - f << indent << mangle(cell) << access << mangle_wire_name(conn.first) << ".next = "; - dump_sigspec_rhs(conn.second); - f << ";\n"; } auto assign_from_outputs = [&](bool cell_converged) { for (auto conn : cell->connections()) { @@ -1277,9 +1373,9 @@ struct CxxrtlWorker { // have any buffered wires if they were not output ports. Imagine inlining the cell's eval() function, // and consider the fate of the localized wires that used to be output ports.) // - // Unlike cell inputs (which are never buffered), it is not possible to know apriori whether the cell - // (which may be late bound) will converge immediately. Because of this, the choice between using .curr - // (appropriate for buffered outputs) and .next (appropriate for unbuffered outputs) is made at runtime. + // It is not possible to know apriori whether the cell (which may be late bound) will converge immediately. + // Because of this, the choice between using .curr (appropriate for buffered outputs) and .next (appropriate + // for unbuffered outputs) is made at runtime. if (cell_converged && is_cxxrtl_comb_port(cell, conn.first)) f << ".next;\n"; else @@ -1287,19 +1383,34 @@ struct CxxrtlWorker { } } }; - f << indent << "if (" << mangle(cell) << access << "eval()) {\n"; - inc_indent(); - assign_from_outputs(/*cell_converged=*/true); - dec_indent(); - f << indent << "} else {\n"; - inc_indent(); + if (buffered_inputs) { + // If we have any buffered inputs, there's no chance of converging immediately. + f << indent << mangle(cell) << access << "eval();\n"; f << indent << "converged = false;\n"; assign_from_outputs(/*cell_converged=*/false); - dec_indent(); - f << indent << "}\n"; + } else { + f << indent << "if (" << mangle(cell) << access << "eval()) {\n"; + inc_indent(); + assign_from_outputs(/*cell_converged=*/true); + dec_indent(); + f << indent << "} else {\n"; + inc_indent(); + f << indent << "converged = false;\n"; + assign_from_outputs(/*cell_converged=*/false); + dec_indent(); + f << indent << "}\n"; + } } } + void collect_cell_eval(const RTLIL::Cell *cell, bool for_debug, std::vector<const RTLIL::Cell*> &cells) + { + cells.push_back(cell); + for (auto port : cell->connections()) + if (cell->input(port.first)) + collect_sigspec_rhs(port.second, for_debug, cells); + } + void dump_assign(const RTLIL::SigSig &sigsig) { f << indent; @@ -1383,13 +1494,19 @@ struct CxxrtlWorker { f << indent << "}\n"; } - void dump_process(const RTLIL::Process *proc) + void dump_process_case(const RTLIL::Process *proc) { dump_attrs(proc); - f << indent << "// process " << proc->name.str() << "\n"; + f << indent << "// process " << proc->name.str() << " case\n"; // The case attributes (for root case) are always empty. log_assert(proc->root_case.attributes.empty()); dump_case_rule(&proc->root_case); + } + + void dump_process_syncs(const RTLIL::Process *proc) + { + dump_attrs(proc); + f << indent << "// process " << proc->name.str() << " syncs\n"; for (auto sync : proc->syncs) { RTLIL::SigBit sync_bit; if (!sync->signal.empty()) { @@ -1442,78 +1559,89 @@ struct CxxrtlWorker { } } - void dump_wire(const RTLIL::Wire *wire, bool is_local_context) + void dump_wire(const RTLIL::Wire *wire, bool is_local) { - if (elided_wires.count(wire)) + const auto &wire_type = wire_types[wire]; + if (!wire_type.is_named() || wire_type.is_local() != is_local) return; - if (localized_wires[wire] && is_local_context) { - dump_attrs(wire); - f << indent << "value<" << wire->width << "> " << mangle(wire) << ";\n"; + dump_attrs(wire); + f << indent; + if (wire->port_input && wire->port_output) + f << "/*inout*/ "; + else if (wire->port_input) + f << "/*input*/ "; + else if (wire->port_output) + f << "/*output*/ "; + f << (wire_type.is_buffered() ? "wire" : "value"); + if (wire->module->has_attribute(ID(cxxrtl_blackbox)) && wire->has_attribute(ID(cxxrtl_width))) { + f << "<" << wire->get_string_attribute(ID(cxxrtl_width)) << ">"; + } else { + f << "<" << wire->width << ">"; } - if (!localized_wires[wire] && !is_local_context) { - std::string width; - if (wire->module->has_attribute(ID(cxxrtl_blackbox)) && wire->has_attribute(ID(cxxrtl_width))) { - width = wire->get_string_attribute(ID(cxxrtl_width)); - } else { - width = std::to_string(wire->width); - } - - dump_attrs(wire); - f << indent; - if (wire->port_input && wire->port_output) - f << "/*inout*/ "; - else if (wire->port_input) - f << "/*input*/ "; - else if (wire->port_output) - f << "/*output*/ "; - f << (unbuffered_wires[wire] ? "value" : "wire") << "<" << width << "> " << mangle(wire); - if (wire->has_attribute(ID::init)) { - f << " "; - dump_const_init(wire->attributes.at(ID::init)); + f << " " << mangle(wire); + if (wire->has_attribute(ID::init)) { + f << " "; + dump_const_init(wire->attributes.at(ID::init)); + } + f << ";\n"; + if (edge_wires[wire]) { + if (!wire_type.is_buffered()) { + f << indent << "value<" << wire->width << "> prev_" << mangle(wire); + if (wire->has_attribute(ID::init)) { + f << " "; + dump_const_init(wire->attributes.at(ID::init)); + } + f << ";\n"; } - f << ";\n"; - if (edge_wires[wire]) { - if (unbuffered_wires[wire]) { - f << indent << "value<" << width << "> prev_" << mangle(wire); - if (wire->has_attribute(ID::init)) { - f << " "; - dump_const_init(wire->attributes.at(ID::init)); + for (auto edge_type : edge_types) { + if (edge_type.first.wire == wire) { + std::string prev, next; + if (!wire_type.is_buffered()) { + prev = "prev_" + mangle(edge_type.first.wire); + next = mangle(edge_type.first.wire); + } else { + prev = mangle(edge_type.first.wire) + ".curr"; + next = mangle(edge_type.first.wire) + ".next"; } - f << ";\n"; - } - for (auto edge_type : edge_types) { - if (edge_type.first.wire == wire) { - std::string prev, next; - if (unbuffered_wires[wire]) { - prev = "prev_" + mangle(edge_type.first.wire); - next = mangle(edge_type.first.wire); - } else { - prev = mangle(edge_type.first.wire) + ".curr"; - next = mangle(edge_type.first.wire) + ".next"; - } - prev += ".slice<" + std::to_string(edge_type.first.offset) + ">().val()"; - next += ".slice<" + std::to_string(edge_type.first.offset) + ">().val()"; - if (edge_type.second != RTLIL::STn) { - f << indent << "bool posedge_" << mangle(edge_type.first) << "() const {\n"; - inc_indent(); - f << indent << "return !" << prev << " && " << next << ";\n"; - dec_indent(); - f << indent << "}\n"; - } - if (edge_type.second != RTLIL::STp) { - f << indent << "bool negedge_" << mangle(edge_type.first) << "() const {\n"; - inc_indent(); - f << indent << "return " << prev << " && !" << next << ";\n"; - dec_indent(); - f << indent << "}\n"; - } + prev += ".slice<" + std::to_string(edge_type.first.offset) + ">().val()"; + next += ".slice<" + std::to_string(edge_type.first.offset) + ">().val()"; + if (edge_type.second != RTLIL::STn) { + f << indent << "bool posedge_" << mangle(edge_type.first) << "() const {\n"; + inc_indent(); + f << indent << "return !" << prev << " && " << next << ";\n"; + dec_indent(); + f << indent << "}\n"; + } + if (edge_type.second != RTLIL::STp) { + f << indent << "bool negedge_" << mangle(edge_type.first) << "() const {\n"; + inc_indent(); + f << indent << "return " << prev << " && !" << next << ";\n"; + dec_indent(); + f << indent << "}\n"; } } } } } + void dump_debug_wire(const RTLIL::Wire *wire, bool is_local) + { + const auto &wire_type = wire_types[wire]; + if (wire_type.is_member()) + return; + + const auto &debug_wire_type = debug_wire_types[wire]; + if (!debug_wire_type.is_named() || debug_wire_type.is_local() != is_local) + return; + + dump_attrs(wire); + f << indent; + if (debug_wire_type.is_outline()) + f << "/*outline*/ "; + f << "value<" << wire->width << "> " << mangle(wire) << ";\n"; + } + void dump_memory(RTLIL::Module *module, const RTLIL::Memory *memory) { vector<const RTLIL::Cell*> init_cells; @@ -1581,7 +1709,7 @@ struct CxxrtlWorker { } } for (auto wire : module->wires()) - dump_wire(wire, /*is_local_context=*/true); + dump_wire(wire, /*is_local=*/true); for (auto node : schedule[module]) { switch (node.type) { case FlowGraph::Node::Type::CONNECT: @@ -1593,8 +1721,11 @@ struct CxxrtlWorker { case FlowGraph::Node::Type::CELL_EVAL: dump_cell_eval(node.cell); break; - case FlowGraph::Node::Type::PROCESS: - dump_process(node.process); + case FlowGraph::Node::Type::PROCESS_SYNC: + dump_process_syncs(node.process); + break; + case FlowGraph::Node::Type::PROCESS_CASE: + dump_process_case(node.process); break; } } @@ -1603,32 +1734,51 @@ struct CxxrtlWorker { dec_indent(); } + void dump_debug_eval_method(RTLIL::Module *module) + { + inc_indent(); + for (auto wire : module->wires()) + dump_debug_wire(wire, /*is_local=*/true); + for (auto node : debug_schedule[module]) { + switch (node.type) { + case FlowGraph::Node::Type::CONNECT: + dump_connect(node.connect, /*for_debug=*/true); + break; + case FlowGraph::Node::Type::CELL_SYNC: + dump_cell_sync(node.cell, /*for_debug=*/true); + break; + case FlowGraph::Node::Type::CELL_EVAL: + dump_cell_eval(node.cell, /*for_debug=*/true); + break; + default: + log_abort(); + } + } + dec_indent(); + } + void dump_commit_method(RTLIL::Module *module) { inc_indent(); f << indent << "bool changed = false;\n"; for (auto wire : module->wires()) { - if (elided_wires.count(wire)) - continue; - if (unbuffered_wires[wire]) { - if (edge_wires[wire]) - f << indent << "prev_" << mangle(wire) << " = " << mangle(wire) << ";\n"; - continue; - } - if (!module->get_bool_attribute(ID(cxxrtl_blackbox)) || wire->port_id != 0) - f << indent << "changed |= " << mangle(wire) << ".commit();\n"; + const auto &wire_type = wire_types[wire]; + if (wire_type.type == WireType::MEMBER && edge_wires[wire]) + f << indent << "prev_" << mangle(wire) << " = " << mangle(wire) << ";\n"; + if (wire_type.is_buffered()) + f << indent << "if (" << mangle(wire) << ".commit()) changed = true;\n"; } if (!module->get_bool_attribute(ID(cxxrtl_blackbox))) { for (auto memory : module->memories) { if (!writable_memories[memory.second]) continue; - f << indent << "changed |= " << mangle(memory.second) << ".commit();\n"; + f << indent << "if (" << mangle(memory.second) << ".commit()) changed = true;\n"; } for (auto cell : module->cells()) { if (is_internal_cell(cell->type)) continue; const char *access = is_cxxrtl_blackbox_cell(cell) ? "->" : "."; - f << indent << "changed |= " << mangle(cell) << access << "commit();\n"; + f << indent << "if (" << mangle(cell) << access << "commit()) changed = true;\n"; } } f << indent << "return changed;\n"; @@ -1638,96 +1788,134 @@ struct CxxrtlWorker { void dump_debug_info_method(RTLIL::Module *module) { size_t count_public_wires = 0; - size_t count_const_wires = 0; - size_t count_alias_wires = 0; size_t count_member_wires = 0; - size_t count_skipped_wires = 0; + size_t count_undriven = 0; size_t count_driven_sync = 0; size_t count_driven_comb = 0; - size_t count_undriven = 0; size_t count_mixed_driver = 0; + size_t count_alias_wires = 0; + size_t count_const_wires = 0; + size_t count_inline_wires = 0; + size_t count_skipped_wires = 0; inc_indent(); f << indent << "assert(path.empty() || path[path.size() - 1] == ' ');\n"; for (auto wire : module->wires()) { - if (wire->name[0] != '\\') - continue; - if (module->get_bool_attribute(ID(cxxrtl_blackbox)) && (wire->port_id == 0)) + const auto &debug_wire_type = debug_wire_types[wire]; + if (!wire->name.isPublic()) continue; count_public_wires++; - if (debug_const_wires.count(wire)) { - // Wire tied to a constant - f << indent << "static const value<" << wire->width << "> const_" << mangle(wire) << " = "; - dump_const(debug_const_wires[wire]); - f << ";\n"; - f << indent << "items.add(path + " << escape_cxx_string(get_hdl_name(wire)); - f << ", debug_item(const_" << mangle(wire) << ", "; - f << wire->start_offset << "));\n"; - count_const_wires++; - } else if (debug_alias_wires.count(wire)) { - // Alias of a member wire - f << indent << "items.add(path + " << escape_cxx_string(get_hdl_name(wire)); - f << ", debug_item(debug_alias(), " << mangle(debug_alias_wires[wire]) << ", "; - f << wire->start_offset << "));\n"; - count_alias_wires++; - } else if (!localized_wires.count(wire)) { - // Member wire - std::vector<std::string> flags; - - if (wire->port_input && wire->port_output) - flags.push_back("INOUT"); - else if (wire->port_input) - flags.push_back("INPUT"); - else if (wire->port_output) - flags.push_back("OUTPUT"); - - bool has_driven_sync = false; - bool has_driven_comb = false; - bool has_undriven = false; - SigSpec sig(wire); - for (auto bit : sig.bits()) - if (!bit_has_state.count(bit)) - has_undriven = true; - else if (bit_has_state[bit]) - has_driven_sync = true; - else - has_driven_comb = true; - if (has_driven_sync) - flags.push_back("DRIVEN_SYNC"); - if (has_driven_sync && !has_driven_comb && !has_undriven) - count_driven_sync++; - if (has_driven_comb) - flags.push_back("DRIVEN_COMB"); - if (!has_driven_sync && has_driven_comb && !has_undriven) - count_driven_comb++; - if (has_undriven) - flags.push_back("UNDRIVEN"); - if (!has_driven_sync && !has_driven_comb && has_undriven) - count_undriven++; - if (has_driven_sync + has_driven_comb + has_undriven > 1) - count_mixed_driver++; - - f << indent << "items.add(path + " << escape_cxx_string(get_hdl_name(wire)); - f << ", debug_item(" << mangle(wire) << ", "; - f << wire->start_offset; - bool first = true; - for (auto flag : flags) { - if (first) { - first = false; - f << ", "; + switch (debug_wire_type.type) { + case WireType::BUFFERED: + case WireType::MEMBER: { + // Member wire + std::vector<std::string> flags; + + if (wire->port_input && wire->port_output) + flags.push_back("INOUT"); + else if (wire->port_output) + flags.push_back("OUTPUT"); + else if (wire->port_input) + flags.push_back("INPUT"); + + bool has_driven_sync = false; + bool has_driven_comb = false; + bool has_undriven = false; + if (!module->get_bool_attribute(ID(cxxrtl_blackbox))) { + for (auto bit : SigSpec(wire)) + if (!bit_has_state.count(bit)) + has_undriven = true; + else if (bit_has_state[bit]) + has_driven_sync = true; + else + has_driven_comb = true; + } else if (wire->port_output) { + switch (cxxrtl_port_type(module, wire->name)) { + case CxxrtlPortType::SYNC: + has_driven_sync = true; + break; + case CxxrtlPortType::COMB: + has_driven_comb = true; + break; + case CxxrtlPortType::UNKNOWN: + has_driven_sync = has_driven_comb = true; + break; + } } else { - f << "|"; + has_undriven = true; } - f << "debug_item::" << flag; + if (has_undriven) + flags.push_back("UNDRIVEN"); + if (!has_driven_sync && !has_driven_comb && has_undriven) + count_undriven++; + if (has_driven_sync) + flags.push_back("DRIVEN_SYNC"); + if (has_driven_sync && !has_driven_comb && !has_undriven) + count_driven_sync++; + if (has_driven_comb) + flags.push_back("DRIVEN_COMB"); + if (!has_driven_sync && has_driven_comb && !has_undriven) + count_driven_comb++; + if (has_driven_sync + has_driven_comb + has_undriven > 1) + count_mixed_driver++; + + f << indent << "items.add(path + " << escape_cxx_string(get_hdl_name(wire)); + f << ", debug_item(" << mangle(wire) << ", " << wire->start_offset; + bool first = true; + for (auto flag : flags) { + if (first) { + first = false; + f << ", "; + } else { + f << "|"; + } + f << "debug_item::" << flag; + } + f << "));\n"; + count_member_wires++; + break; + } + case WireType::ALIAS: { + // Alias of a member wire + const RTLIL::Wire *aliasee = debug_wire_type.sig_subst.as_wire(); + f << indent << "items.add(path + " << escape_cxx_string(get_hdl_name(wire)); + f << ", debug_item("; + // If the aliasee is an outline, then the alias must be an outline, too; otherwise downstream + // tooling has no way to find out about the outline. + if (debug_wire_types[aliasee].is_outline()) + f << "debug_eval_outline"; + else + f << "debug_alias()"; + f << ", " << mangle(aliasee) << ", " << wire->start_offset << "));\n"; + count_alias_wires++; + break; + } + case WireType::CONST: { + // Wire tied to a constant + f << indent << "static const value<" << wire->width << "> const_" << mangle(wire) << " = "; + dump_const(debug_wire_type.sig_subst.as_const()); + f << ";\n"; + f << indent << "items.add(path + " << escape_cxx_string(get_hdl_name(wire)); + f << ", debug_item(const_" << mangle(wire) << ", " << wire->start_offset << "));\n"; + count_const_wires++; + break; + } + case WireType::OUTLINE: { + // Localized or inlined, but rematerializable wire + f << indent << "items.add(path + " << escape_cxx_string(get_hdl_name(wire)); + f << ", debug_item(debug_eval_outline, " << mangle(wire) << ", " << wire->start_offset << "));\n"; + count_inline_wires++; + break; + } + default: { + // Localized or inlined wire with no debug information + count_skipped_wires++; + break; } - f << "));\n"; - count_member_wires++; - } else { - count_skipped_wires++; } } if (!module->get_bool_attribute(ID(cxxrtl_blackbox))) { for (auto &memory_it : module->memories) { - if (memory_it.first[0] != '\\') + if (!memory_it.first.isPublic()) continue; f << indent << "items.add(path + " << escape_cxx_string(get_hdl_name(memory_it.second)); f << ", debug_item(" << mangle(memory_it.second) << ", "; @@ -1745,14 +1933,18 @@ struct CxxrtlWorker { log_debug("Debug information statistics for module `%s':\n", log_id(module)); log_debug(" Public wires: %zu, of which:\n", count_public_wires); - log_debug(" Const wires: %zu\n", count_const_wires); - log_debug(" Alias wires: %zu\n", count_alias_wires); log_debug(" Member wires: %zu, of which:\n", count_member_wires); + log_debug(" Undriven: %zu (incl. inputs)\n", count_undriven); log_debug(" Driven sync: %zu\n", count_driven_sync); log_debug(" Driven comb: %zu\n", count_driven_comb); - log_debug(" Undriven: %zu\n", count_undriven); log_debug(" Mixed driver: %zu\n", count_mixed_driver); - log_debug(" Other wires: %zu (no debug information)\n", count_skipped_wires); + if (!module->get_bool_attribute(ID(cxxrtl_blackbox))) { + log_debug(" Inline wires: %zu\n", count_inline_wires); + log_debug(" Alias wires: %zu\n", count_alias_wires); + log_debug(" Const wires: %zu\n", count_const_wires); + log_debug(" Other wires: %zu%s\n", count_skipped_wires, + count_skipped_wires > 0 ? " (debug unavailable)" : ""); + } } void dump_metadata_map(const dict<RTLIL::IdString, RTLIL::Const> &metadata_map) @@ -1792,7 +1984,7 @@ struct CxxrtlWorker { inc_indent(); for (auto wire : module->wires()) { if (wire->port_id != 0) - dump_wire(wire, /*is_local_context=*/false); + dump_wire(wire, /*is_local=*/false); } f << "\n"; f << indent << "bool eval() override {\n"; @@ -1838,8 +2030,9 @@ struct CxxrtlWorker { f << indent << "struct " << mangle(module) << " : public module {\n"; inc_indent(); for (auto wire : module->wires()) - dump_wire(wire, /*is_local_context=*/false); - f << "\n"; + dump_wire(wire, /*is_local=*/false); + for (auto wire : module->wires()) + dump_debug_wire(wire, /*is_local=*/false); bool has_memories = false; for (auto memory : module->memories) { dump_memory(module, memory.second); @@ -1869,10 +2062,62 @@ struct CxxrtlWorker { } if (has_cells) f << "\n"; + f << indent << mangle(module) << "() {}\n"; + if (has_cells) { + f << indent << mangle(module) << "(adopt, " << mangle(module) << " other) :\n"; + bool first = true; + for (auto cell : module->cells()) { + if (is_internal_cell(cell->type)) + continue; + if (first) { + first = false; + } else { + f << ",\n"; + } + RTLIL::Module *cell_module = module->design->module(cell->type); + if (cell_module->get_bool_attribute(ID(cxxrtl_blackbox))) { + f << indent << " " << mangle(cell) << "(std::move(other." << mangle(cell) << "))"; + } else { + f << indent << " " << mangle(cell) << "(adopt {}, std::move(other." << mangle(cell) << "))"; + } + } + f << " {\n"; + inc_indent(); + for (auto cell : module->cells()) { + if (is_internal_cell(cell->type)) + continue; + RTLIL::Module *cell_module = module->design->module(cell->type); + if (cell_module->get_bool_attribute(ID(cxxrtl_blackbox))) + f << indent << mangle(cell) << "->reset();\n"; + } + dec_indent(); + f << indent << "}\n"; + } else { + f << indent << mangle(module) << "(adopt, " << mangle(module) << " other) {}\n"; + } + f << "\n"; + f << indent << "void reset() override {\n"; + inc_indent(); + f << indent << "*this = " << mangle(module) << "(adopt {}, std::move(*this));\n"; + dec_indent(); + f << indent << "}\n"; + f << "\n"; f << indent << "bool eval() override;\n"; f << indent << "bool commit() override;\n"; - if (debug_info) + if (debug_info) { + if (debug_eval) { + f << "\n"; + f << indent << "void debug_eval();\n"; + for (auto wire : module->wires()) + if (debug_wire_types[wire].is_outline()) { + f << indent << "debug_outline debug_eval_outline { std::bind(&" + << mangle(module) << "::debug_eval, this) };\n"; + break; + } + } + f << "\n"; f << indent << "void debug_info(debug_items &items, std::string path = \"\") override;\n"; + } dec_indent(); f << indent << "}; // struct " << mangle(module) << "\n"; f << "\n"; @@ -1892,6 +2137,13 @@ struct CxxrtlWorker { f << indent << "}\n"; f << "\n"; if (debug_info) { + if (debug_eval) { + f << indent << "void " << mangle(module) << "::debug_eval() {\n"; + dump_debug_eval_method(module); + f << indent << "}\n"; + f << "\n"; + } + f << indent << "CXXRTL_EXTREMELY_COLD\n"; f << indent << "void " << mangle(module) << "::debug_info(debug_items &items, std::string path) {\n"; dump_debug_info_method(module); f << indent << "}\n"; @@ -2021,7 +2273,7 @@ struct CxxrtlWorker { void register_edge_signal(SigMap &sigmap, RTLIL::SigSpec signal, RTLIL::SyncType type) { signal = sigmap(signal); - log_assert(signal.is_wire() && signal.is_bit()); + log_assert(is_valid_clock(signal)); log_assert(type == RTLIL::STp || type == RTLIL::STn || type == RTLIL::STe); RTLIL::SigBit sigbit = signal[0]; @@ -2029,7 +2281,8 @@ struct CxxrtlWorker { edge_types[sigbit] = type; else if (edge_types[sigbit] != type) edge_types[sigbit] = RTLIL::STe; - edge_wires.insert(signal.as_wire()); + // Cannot use as_wire because signal might not be a full wire, instead extract the wire from the sigbit + edge_wires.insert(sigbit.wire); } void analyze_design(RTLIL::Design *design) @@ -2047,8 +2300,11 @@ struct CxxrtlWorker { if (module->get_bool_attribute(ID(cxxrtl_blackbox))) { for (auto port : module->ports) { RTLIL::Wire *wire = module->wire(port); - if (wire->port_input && !wire->port_output) - unbuffered_wires.insert(wire); + if (wire->port_input && !wire->port_output) { + wire_types[wire] = debug_wire_types[wire] = {WireType::MEMBER}; + } else if (wire->port_input || wire->port_output) { + wire_types[wire] = debug_wire_types[wire] = {WireType::BUFFERED}; + } if (wire->has_attribute(ID(cxxrtl_edge))) { RTLIL::Const edge_attr = wire->attributes[ID(cxxrtl_edge)]; if (!(edge_attr.flags & RTLIL::CONST_FLAG_STRING) || (int)edge_attr.decode_string().size() != GetSize(wire)) @@ -2078,6 +2334,8 @@ struct CxxrtlWorker { continue; } + // Construct a flow graph where each node is a basic computational operation generally corresponding + // to a fragment of the RTLIL netlist. FlowGraph flow; for (auto conn : module->connections()) @@ -2105,14 +2363,14 @@ struct CxxrtlWorker { // Various DFF cells are treated like posedge/negedge processes, see above for details. if (cell->type.in(ID($dff), ID($dffe), ID($adff), ID($adffe), ID($dffsr), ID($dffsre), ID($sdff), ID($sdffe), ID($sdffce))) { - if (cell->getPort(ID::CLK).is_wire()) + if (is_valid_clock(cell->getPort(ID::CLK))) register_edge_signal(sigmap, cell->getPort(ID::CLK), cell->parameters[ID::CLK_POLARITY].as_bool() ? RTLIL::STp : RTLIL::STn); } // Similar for memory port cells. if (cell->type.in(ID($memrd), ID($memwr))) { if (cell->getParam(ID::CLK_ENABLE).as_bool()) { - if (cell->getPort(ID::CLK).is_wire()) + if (is_valid_clock(cell->getPort(ID::CLK))) register_edge_signal(sigmap, cell->getPort(ID::CLK), cell->parameters[ID::CLK_POLARITY].as_bool() ? RTLIL::STp : RTLIL::STn); } @@ -2122,7 +2380,7 @@ struct CxxrtlWorker { if (cell->type == ID($memwr)) writable_memories.insert(module->memories[cell->getParam(ID::MEMID).decode_string()]); // Collect groups of memory write ports in the same domain. - if (cell->type == ID($memwr) && cell->getParam(ID::CLK_ENABLE).as_bool() && cell->getPort(ID::CLK).is_wire()) { + if (cell->type == ID($memwr) && cell->getParam(ID::CLK_ENABLE).as_bool() && is_valid_clock(cell->getPort(ID::CLK))) { RTLIL::SigBit clk_bit = sigmap(cell->getPort(ID::CLK))[0]; const RTLIL::Memory *memory = module->memories[cell->getParam(ID::MEMID).decode_string()]; memwr_per_domain[{clk_bit, memory}].insert(cell); @@ -2134,7 +2392,7 @@ struct CxxrtlWorker { } for (auto cell : module->cells()) { // Collect groups of memory write ports read by every transparent read port. - if (cell->type == ID($memrd) && cell->getParam(ID::CLK_ENABLE).as_bool() && cell->getPort(ID::CLK).is_wire() && + if (cell->type == ID($memrd) && cell->getParam(ID::CLK_ENABLE).as_bool() && is_valid_clock(cell->getPort(ID::CLK)) && cell->getParam(ID::TRANSPARENT).as_bool()) { RTLIL::SigBit clk_bit = sigmap(cell->getPort(ID::CLK))[0]; const RTLIL::Memory *memory = module->memories[cell->getParam(ID::MEMID).decode_string()]; @@ -2177,59 +2435,40 @@ struct CxxrtlWorker { } } - for (auto wire : module->wires()) { - if (!flow.is_elidable(wire)) continue; - if (wire->port_id != 0) continue; - if (wire->get_bool_attribute(ID::keep)) continue; - if (wire->name.begins_with("$") && !elide_internal) continue; - if (wire->name.begins_with("\\") && !elide_public) continue; - if (edge_wires[wire]) continue; - if (flow.wire_comb_defs[wire].size() > 1) - log_cmd_error("Wire %s.%s has multiple drivers.\n", log_id(module), log_id(wire)); - log_assert(flow.wire_comb_defs[wire].size() == 1); - elided_wires[wire] = **flow.wire_comb_defs[wire].begin(); - } - - dict<FlowGraph::Node*, pool<const RTLIL::Wire*>, hash_ptr_ops> node_defs; - for (auto wire_comb_def : flow.wire_comb_defs) - for (auto node : wire_comb_def.second) - node_defs[node].insert(wire_comb_def.first); - + // Construct a linear order of the flow graph that minimizes the amount of feedback arcs. A flow graph + // without feedback arcs can generally be evaluated in a single pass, i.e. it always requires only + // a single delta cycle. Scheduler<FlowGraph::Node> scheduler; - dict<FlowGraph::Node*, Scheduler<FlowGraph::Node>::Vertex*, hash_ptr_ops> node_map; + dict<FlowGraph::Node*, Scheduler<FlowGraph::Node>::Vertex*, hash_ptr_ops> node_vertex_map; for (auto node : flow.nodes) - node_map[node] = scheduler.add(node); - for (auto node_def : node_defs) { - auto vertex = node_map[node_def.first]; - for (auto wire : node_def.second) + node_vertex_map[node] = scheduler.add(node); + for (auto node_comb_def : flow.node_comb_defs) { + auto vertex = node_vertex_map[node_comb_def.first]; + for (auto wire : node_comb_def.second) for (auto succ_node : flow.wire_uses[wire]) { - auto succ_vertex = node_map[succ_node]; + auto succ_vertex = node_vertex_map[succ_node]; vertex->succs.insert(succ_vertex); succ_vertex->preds.insert(vertex); } } - auto eval_order = scheduler.schedule(); - pool<FlowGraph::Node*, hash_ptr_ops> evaluated; + // Find out whether the order includes any feedback arcs. + std::vector<FlowGraph::Node*> node_order; + pool<FlowGraph::Node*, hash_ptr_ops> evaluated_nodes; pool<const RTLIL::Wire*> feedback_wires; - for (auto vertex : eval_order) { + for (auto vertex : scheduler.schedule()) { auto node = vertex->data; - schedule[module].push_back(*node); + node_order.push_back(node); // Any wire that is an output of node vo and input of node vi where vo is scheduled later than vi // is a feedback wire. Feedback wires indicate apparent logic loops in the design, which may be // caused by a true logic loop, but usually are a benign result of dependency tracking that works - // on wire, not bit, level. Nevertheless, feedback wires cannot be localized. - evaluated.insert(node); - for (auto wire : node_defs[node]) + // on wire, not bit, level. Nevertheless, feedback wires cannot be unbuffered. + evaluated_nodes.insert(node); + for (auto wire : flow.node_comb_defs[node]) for (auto succ_node : flow.wire_uses[wire]) - if (evaluated[succ_node]) { + if (evaluated_nodes[succ_node]) feedback_wires.insert(wire); - // Feedback wires may never be elided because feedback requires state, but the point of elision - // (and localization) is to eliminate state. - elided_wires.erase(wire); - } } - if (!feedback_wires.empty()) { has_feedback_arcs = true; log("Module `%s' contains feedback arcs through wires:\n", log_id(module)); @@ -2237,21 +2476,86 @@ struct CxxrtlWorker { log(" %s\n", log_id(wire)); } + // Conservatively assign wire types. Assignment of types BUFFERED and MEMBER is final, but assignment + // of type LOCAL may be further refined to UNUSED or INLINE. for (auto wire : module->wires()) { + auto &wire_type = wire_types[wire]; + wire_type = {WireType::BUFFERED}; + if (feedback_wires[wire]) continue; if (wire->port_output && !module->get_bool_attribute(ID::top)) continue; - if (wire->name.begins_with("$") && !unbuffer_internal) continue; - if (wire->name.begins_with("\\") && !unbuffer_public) continue; + if (!wire->name.isPublic() && !unbuffer_internal) continue; + if (wire->name.isPublic() && !unbuffer_public) continue; if (flow.wire_sync_defs.count(wire) > 0) continue; - unbuffered_wires.insert(wire); + wire_type = {WireType::MEMBER}; + if (edge_wires[wire]) continue; if (wire->get_bool_attribute(ID::keep)) continue; if (wire->port_input || wire->port_output) continue; - if (wire->name.begins_with("$") && !localize_internal) continue; - if (wire->name.begins_with("\\") && !localize_public) continue; - localized_wires.insert(wire); + if (!wire->name.isPublic() && !localize_internal) continue; + if (wire->name.isPublic() && !localize_public) continue; + wire_type = {WireType::LOCAL}; + } + + // Discover nodes reachable from primary outputs (i.e. members) and collect reachable wire users. + pool<FlowGraph::Node*, hash_ptr_ops> worklist; + for (auto node : flow.nodes) { + if (node->type == FlowGraph::Node::Type::CELL_EVAL && is_effectful_cell(node->cell->type)) + worklist.insert(node); // node has effects + else if (flow.node_sync_defs.count(node)) + worklist.insert(node); // node is a flip-flop + else if (flow.node_comb_defs.count(node)) { + for (auto wire : flow.node_comb_defs[node]) + if (wire_types[wire].is_member()) + worklist.insert(node); // node drives public wires + } + } + dict<const RTLIL::Wire*, pool<FlowGraph::Node*, hash_ptr_ops>> live_wires; + pool<FlowGraph::Node*, hash_ptr_ops> live_nodes; + while (!worklist.empty()) { + auto node = worklist.pop(); + live_nodes.insert(node); + for (auto wire : flow.node_uses[node]) { + live_wires[wire].insert(node); + for (auto pred_node : flow.wire_comb_defs[wire]) + if (!live_nodes[pred_node]) + worklist.insert(pred_node); + } + } + + // Refine wire types taking into account the amount of uses from reachable nodes only. + for (auto wire : module->wires()) { + auto &wire_type = wire_types[wire]; + if (!wire_type.is_local()) continue; + if (!wire->name.isPublic() && !inline_internal) continue; + if (wire->name.isPublic() && !inline_public) continue; + + if (live_wires[wire].empty()) { + wire_type = {WireType::UNUSED}; // wire never used + } else if (flow.is_inlinable(wire, live_wires[wire])) { + if (flow.wire_comb_defs[wire].size() > 1) + log_cmd_error("Wire %s.%s has multiple drivers!\n", log_id(module), log_id(wire)); + log_assert(flow.wire_comb_defs[wire].size() == 1); + FlowGraph::Node *node = *flow.wire_comb_defs[wire].begin(); + switch (node->type) { + case FlowGraph::Node::Type::CELL_EVAL: + if (!is_inlinable_cell(node->cell->type)) continue; + wire_type = {WireType::INLINE, node->cell}; // wire replaced with cell + break; + case FlowGraph::Node::Type::CONNECT: + wire_type = {WireType::INLINE, node->connect.second}; // wire replaced with sig + break; + default: continue; + } + live_nodes.erase(node); + } } + // Emit reachable nodes in eval(). + for (auto node : node_order) + if (live_nodes[node]) + schedule[module].push_back(*node); + // For maximum performance, the state of the simulation (which is the same as the set of its double buffered // wires, since using a singly buffered wire for any kind of state introduces a race condition) should contain // no wires attached to combinatorial outputs. Feedback wires, by definition, make that impossible. However, @@ -2259,10 +2563,9 @@ struct CxxrtlWorker { // as a wire with multiple drivers where one of them is combinatorial and the other is synchronous. Such designs // also require more than one delta cycle to converge. pool<const RTLIL::Wire*> buffered_comb_wires; - for (auto wire : module->wires()) { - if (flow.wire_comb_defs[wire].size() > 0 && !unbuffered_wires[wire] && !feedback_wires[wire]) + for (auto wire : module->wires()) + if (wire_types[wire].is_buffered() && !feedback_wires[wire] && flow.wire_comb_defs[wire].size() > 0) buffered_comb_wires.insert(wire); - } if (!buffered_comb_wires.empty()) { has_buffered_comb_wires = true; log("Module `%s' contains buffered combinatorial wires:\n", log_id(module)); @@ -2270,47 +2573,116 @@ struct CxxrtlWorker { log(" %s\n", log_id(wire)); } + // Record whether eval() requires only one delta cycle in this module. eval_converges[module] = feedback_wires.empty() && buffered_comb_wires.empty(); - for (auto item : flow.bit_has_state) - bit_has_state.insert(item); - if (debug_info) { - // Find wires that alias other wires or are tied to a constant; debug information can be enriched with these - // at essentially zero additional cost. - // - // Note that the information collected here can't be used for optimizing the netlist: debug information queries - // are pure and run on a design in a stable state, which allows assumptions that do not otherwise hold. + // Annotate wire bits with the type of their driver; this is exposed in the debug metadata. + for (auto item : flow.bit_has_state) + bit_has_state.insert(item); + + // Assign debug information wire types to public wires according to the chosen debug level. + // Unlike with optimized wire types, all assignments here are final. for (auto wire : module->wires()) { - if (wire->name[0] != '\\') - continue; - if (!unbuffered_wires[wire]) - continue; - const RTLIL::Wire *wire_it = wire; - while (1) { - if (!(flow.wire_def_elidable.count(wire_it) && flow.wire_def_elidable[wire_it])) - break; // not an alias: complex def - log_assert(flow.wire_comb_defs[wire_it].size() == 1); - FlowGraph::Node *node = *flow.wire_comb_defs[wire_it].begin(); - if (node->type != FlowGraph::Node::Type::CONNECT) - break; // not an alias: def by cell - RTLIL::SigSpec rhs_sig = node->connect.second; - if (rhs_sig.is_wire()) { - RTLIL::Wire *rhs_wire = rhs_sig.as_wire(); - if (unbuffered_wires[rhs_wire]) { - wire_it = rhs_wire; // maybe an alias - } else { - debug_alias_wires[wire] = rhs_wire; // is an alias + const auto &wire_type = wire_types[wire]; + auto &debug_wire_type = debug_wire_types[wire]; + if (wire_type.type == WireType::UNUSED) continue; + if (!wire->name.isPublic()) continue; + + if (!debug_info) continue; + if (wire->port_input || wire_type.is_buffered()) + debug_wire_type = wire_type; // wire contains state + + if (!debug_member) continue; + if (wire_type.is_member()) + debug_wire_type = wire_type; // wire is a member + + if (!debug_alias) continue; + const RTLIL::Wire *it = wire; + while (flow.is_inlinable(it)) { + log_assert(flow.wire_comb_defs[it].size() == 1); + FlowGraph::Node *node = *flow.wire_comb_defs[it].begin(); + if (node->type != FlowGraph::Node::Type::CONNECT) break; // not an alias + RTLIL::SigSpec rhs = node->connect.second; + if (rhs.is_fully_const()) { + debug_wire_type = {WireType::CONST, rhs}; // wire replaced with const + } else if (rhs.is_wire()) { + if (wire_types[rhs.as_wire()].is_member()) + debug_wire_type = {WireType::ALIAS, rhs}; // wire replaced with wire + else if (debug_eval && rhs.as_wire()->name.isPublic()) + debug_wire_type = {WireType::ALIAS, rhs}; // wire replaced with outline + it = rhs.as_wire(); // and keep looking + continue; + } + break; + } + + if (!debug_eval) continue; + if (!debug_wire_type.is_exact() && !wire_type.is_member()) + debug_wire_type = {WireType::OUTLINE}; // wire is local or inlined + } + + // Discover nodes reachable from primary outputs (i.e. outlines) up until primary inputs (i.e. members) + // and collect reachable wire users. + pool<FlowGraph::Node*, hash_ptr_ops> worklist; + for (auto node : flow.nodes) { + if (flow.node_comb_defs.count(node)) + for (auto wire : flow.node_comb_defs[node]) + if (debug_wire_types[wire].is_outline()) + worklist.insert(node); // node drives outline + } + dict<const RTLIL::Wire*, pool<FlowGraph::Node*, hash_ptr_ops>> debug_live_wires; + pool<FlowGraph::Node*, hash_ptr_ops> debug_live_nodes; + while (!worklist.empty()) { + auto node = worklist.pop(); + debug_live_nodes.insert(node); + for (auto wire : flow.node_uses[node]) { + if (debug_wire_types[wire].is_member()) + continue; // node uses member + if (debug_wire_types[wire].is_exact()) + continue; // node uses alias or const + debug_live_wires[wire].insert(node); + for (auto pred_node : flow.wire_comb_defs[wire]) + if (!debug_live_nodes[pred_node]) + worklist.insert(pred_node); + } + } + + // Assign debug information wire types to internal wires used by reachable nodes. This is similar + // to refining optimized wire types with the exception that the assignments here are first and final. + for (auto wire : module->wires()) { + const auto &wire_type = wire_types[wire]; + auto &debug_wire_type = debug_wire_types[wire]; + if (wire->name.isPublic()) continue; + + if (live_wires[wire].empty() || debug_live_wires[wire].empty()) { + continue; // wire never used + } else if (flow.is_inlinable(wire, debug_live_wires[wire])) { + log_assert(flow.wire_comb_defs[wire].size() == 1); + FlowGraph::Node *node = *flow.wire_comb_defs[wire].begin(); + switch (node->type) { + case FlowGraph::Node::Type::CELL_EVAL: + if (!is_inlinable_cell(node->cell->type)) continue; + debug_wire_type = {WireType::INLINE, node->cell}; // wire replaced with cell break; - } - } else if (rhs_sig.is_fully_const()) { - debug_const_wires[wire] = rhs_sig.as_const(); // is a const - break; - } else { - break; // not an alias: complex rhs + case FlowGraph::Node::Type::CONNECT: + debug_wire_type = {WireType::INLINE, node->connect.second}; // wire replaced with sig + break; + default: continue; } + debug_live_nodes.erase(node); + } else if (wire_type.is_local()) { + debug_wire_type = {WireType::LOCAL}; // wire not inlinable + } else { + log_assert(wire_type.is_member()); + debug_wire_type = wire_type; // wire is a member } } + + // Emit reachable nodes in debug_eval(). + for (auto node : node_order) + if (debug_live_nodes[node]) + debug_schedule[module].push_back(*node); } } if (has_feedback_arcs || has_buffered_comb_wires) { @@ -2401,8 +2773,7 @@ struct CxxrtlWorker { struct CxxrtlBackend : public Backend { static const int DEFAULT_OPT_LEVEL = 6; - static const int OPT_LEVEL_DEBUG = 4; - static const int DEFAULT_DEBUG_LEVEL = 1; + static const int DEFAULT_DEBUG_LEVEL = 4; CxxrtlBackend() : Backend("cxxrtl", "convert design to C++ RTL simulation") { } void help() override @@ -2598,13 +2969,13 @@ struct CxxrtlBackend : public Backend { log(" no optimization.\n"); log("\n"); log(" -O1\n"); - log(" localize internal wires if possible.\n"); + log(" unbuffer internal wires if possible.\n"); log("\n"); log(" -O2\n"); - log(" like -O1, and unbuffer internal wires if possible.\n"); + log(" like -O1, and localize internal wires if possible.\n"); log("\n"); log(" -O3\n"); - log(" like -O2, and elide internal wires if possible.\n"); + log(" like -O2, and inline internal wires if possible.\n"); log("\n"); log(" -O4\n"); log(" like -O3, and unbuffer public wires not marked (*keep*) if possible.\n"); @@ -2613,22 +2984,30 @@ struct CxxrtlBackend : public Backend { log(" like -O4, and localize public wires not marked (*keep*) if possible.\n"); log("\n"); log(" -O6\n"); - log(" like -O5, and elide public wires not marked (*keep*) if possible.\n"); - log("\n"); - log(" -Og\n"); - log(" highest optimization level that provides debug information for all\n"); - log(" public wires. currently, alias for -O%d.\n", OPT_LEVEL_DEBUG); + log(" like -O5, and inline public wires not marked (*keep*) if possible.\n"); log("\n"); log(" -g <level>\n"); log(" set the debug level. the default is -g%d. higher debug levels provide\n", DEFAULT_DEBUG_LEVEL); log(" more visibility and generate more code, but do not pessimize evaluation.\n"); log("\n"); log(" -g0\n"); - log(" no debug information.\n"); + log(" no debug information. the C API is disabled.\n"); log("\n"); log(" -g1\n"); - log(" debug information for non-optimized public wires. this also makes it\n"); - log(" possible to use the C API.\n"); + log(" include bare minimum of debug information necessary to access all design\n"); + log(" state. the C API is enabled.\n"); + log("\n"); + log(" -g2\n"); + log(" like -g1, but include debug information for all public wires that are\n"); + log(" directly accessible through the C++ interface.\n"); + log("\n"); + log(" -g3\n"); + log(" like -g2, and include debug information for public wires that are tied\n"); + log(" to a constant or another public wire.\n"); + log("\n"); + log(" -g4\n"); + log(" like -g3, and compute debug information on demand for all public wires\n"); + log(" that were optimized out.\n"); log("\n"); } @@ -2659,12 +3038,14 @@ struct CxxrtlBackend : public Backend { continue; } if (args[argidx] == "-Og") { - opt_level = OPT_LEVEL_DEBUG; + log_warning("The `-Og` option has been removed. Use `-g3` instead for complete " + "design coverage regardless of optimization level.\n"); continue; } if (args[argidx] == "-O" && argidx+1 < args.size() && args[argidx+1] == "g") { argidx++; - opt_level = OPT_LEVEL_DEBUG; + log_warning("The `-Og` option has been removed. Use `-g3` instead for complete " + "design coverage regardless of optimization level.\n"); continue; } if (args[argidx] == "-O" && argidx+1 < args.size()) { @@ -2701,7 +3082,7 @@ struct CxxrtlBackend : public Backend { switch (opt_level) { // the highest level here must match DEFAULT_OPT_LEVEL case 6: - worker.elide_public = true; + worker.inline_public = true; YS_FALLTHROUGH case 5: worker.localize_public = true; @@ -2710,7 +3091,7 @@ struct CxxrtlBackend : public Backend { worker.unbuffer_public = true; YS_FALLTHROUGH case 3: - worker.elide_internal = true; + worker.inline_internal = true; YS_FALLTHROUGH case 2: worker.localize_internal = true; @@ -2725,6 +3106,15 @@ struct CxxrtlBackend : public Backend { } switch (debug_level) { // the highest level here must match DEFAULT_DEBUG_LEVEL + case 4: + worker.debug_eval = true; + YS_FALLTHROUGH + case 3: + worker.debug_alias = true; + YS_FALLTHROUGH + case 2: + worker.debug_member = true; + YS_FALLTHROUGH case 1: worker.debug_info = true; YS_FALLTHROUGH diff --git a/backends/cxxrtl/cxxrtl_capi.cc b/backends/cxxrtl/cxxrtl_capi.cc index b77e4c491..227173ba8 100644 --- a/backends/cxxrtl/cxxrtl_capi.cc +++ b/backends/cxxrtl/cxxrtl_capi.cc @@ -32,9 +32,22 @@ const cxxrtl::debug_items &cxxrtl_debug_items_from_handle(cxxrtl_handle handle) } cxxrtl_handle cxxrtl_create(cxxrtl_toplevel design) { + return cxxrtl_create_at(design, ""); +} + +cxxrtl_handle cxxrtl_create_at(cxxrtl_toplevel design, const char *root) { + std::string path = root; + if (!path.empty()) { + // module::debug_info() accepts either an empty path, or a path ending in space to simplify + // the logic in generated code. While this is sketchy at best to expose in the C++ API, this + // would be a lot worse in the C API, so don't expose it here. + assert(path.back() != ' '); + path += ' '; + } + cxxrtl_handle handle = new _cxxrtl_handle; handle->module = std::move(design->module); - handle->module->debug_info(handle->objects); + handle->module->debug_info(handle->objects, path); delete design; return handle; } @@ -43,6 +56,10 @@ void cxxrtl_destroy(cxxrtl_handle handle) { delete handle; } +void cxxrtl_reset(cxxrtl_handle handle) { + handle->module->reset(); +} + int cxxrtl_eval(cxxrtl_handle handle) { return handle->module->eval(); } @@ -69,3 +86,7 @@ void cxxrtl_enum(cxxrtl_handle handle, void *data, for (auto &it : handle->objects.table) callback(data, it.first.c_str(), static_cast<cxxrtl_object*>(&it.second[0]), it.second.size()); } + +void cxxrtl_outline_eval(cxxrtl_outline outline) { + outline->eval(); +} diff --git a/backends/cxxrtl/cxxrtl_capi.h b/backends/cxxrtl/cxxrtl_capi.h index 385d6dcf3..2df2b7287 100644 --- a/backends/cxxrtl/cxxrtl_capi.h +++ b/backends/cxxrtl/cxxrtl_capi.h @@ -52,9 +52,23 @@ typedef struct _cxxrtl_handle *cxxrtl_handle; // The `design` is consumed by this operation and cannot be used afterwards. cxxrtl_handle cxxrtl_create(cxxrtl_toplevel design); +// Create a design handle at a given hierarchy position from a design toplevel. +// +// This operation is similar to `cxxrtl_create`, except the full hierarchical name of every object +// is prepended with `root`. +cxxrtl_handle cxxrtl_create_at(cxxrtl_toplevel design, const char *root); + // Release all resources used by a design and its handle. void cxxrtl_destroy(cxxrtl_handle handle); +// Reinitialize the design, replacing the internal state with the reset values while preserving +// black boxes. +// +// This operation is essentially equivalent to a power-on reset. Values, wires, and memories are +// returned to their reset state while preserving the state of black boxes and keeping all of +// the interior pointers obtained with e.g. `cxxrtl_get` valid. +void cxxrtl_reset(cxxrtl_handle handle); + // Evaluate the design, propagating changes on inputs to the `next` value of internal state and // output wires. // @@ -114,6 +128,18 @@ enum cxxrtl_type { // pointer is always NULL. CXXRTL_ALIAS = 3, + // Outlines correspond to netlist nodes that were optimized in a way that makes them inaccessible + // outside of a module's `eval()` function. At the highest debug information level, every inlined + // node has a corresponding outline object. + // + // Outlines can be inspected via the `curr` pointer and can never be modified; the `next` pointer + // is always NULL. Unlike all other objects, the bits of an outline object are meaningful only + // after a call to `cxxrtl_outline_eval` and until any subsequent modification to the netlist. + // Observing this requirement is the responsibility of the caller; it is not enforced. + // + // Outlines always correspond to combinatorial netlist nodes that are not ports. + CXXRTL_OUTLINE = 4, + // More object types may be added in the future, but the existing ones will never change. }; @@ -157,8 +183,8 @@ enum cxxrtl_flag { // Node has bits that are driven by a combinatorial cell or another node. // - // This flag can be set on objects of type `CXXRTL_VALUE` and `CXXRTL_WIRE`. It may be combined - // with `CXXRTL_DRIVEN_SYNC` and `CXXRTL_UNDRIVEN`, as well as other flags. + // This flag can be set on objects of type `CXXRTL_VALUE`, `CXXRTL_WIRE`, and `CXXRTL_OUTLINE`. + // It may be combined with `CXXRTL_DRIVEN_SYNC` and `CXXRTL_UNDRIVEN`, as well as other flags. // // This flag is set on objects that have bits connected to the output of a combinatorial cell, // or directly to another node. For designs without combinatorial loops, writing to such bits @@ -179,8 +205,8 @@ enum cxxrtl_flag { // Description of a simulated object. // -// The `data` array can be accessed directly to inspect and, if applicable, modify the bits -// stored in the object. +// The `curr` and `next` arrays can be accessed directly to inspect and, if applicable, modify +// the bits stored in the object. struct cxxrtl_object { // Type of the object. // @@ -217,6 +243,12 @@ struct cxxrtl_object { uint32_t *curr; uint32_t *next; + // Opaque reference to an outline. Only meaningful for outline objects. + // + // See the documentation of `cxxrtl_outline` for details. When creating a `cxxrtl_object`, set + // this field to NULL. + struct _cxxrtl_outline *outline; + // More description fields may be added in the future, but the existing ones will never change. }; @@ -240,7 +272,7 @@ struct cxxrtl_object *cxxrtl_get_parts(cxxrtl_handle handle, const char *name, s // This function is a shortcut for the most common use of `cxxrtl_get_parts`. It asserts that, // if the object exists, it consists of a single part. If assertions are disabled, it returns NULL // for multi-part objects. -inline struct cxxrtl_object *cxxrtl_get(cxxrtl_handle handle, const char *name) { +static inline struct cxxrtl_object *cxxrtl_get(cxxrtl_handle handle, const char *name) { size_t parts = 0; struct cxxrtl_object *object = cxxrtl_get_parts(handle, name, &parts); assert(object == NULL || parts == 1); @@ -258,6 +290,20 @@ void cxxrtl_enum(cxxrtl_handle handle, void *data, void (*callback)(void *data, const char *name, struct cxxrtl_object *object, size_t parts)); +// Opaque reference to an outline. +// +// An outline is a group of outline objects that are evaluated simultaneously. The identity of +// an outline can be compared to determine whether any two objects belong to the same outline. +typedef struct _cxxrtl_outline *cxxrtl_outline; + +// Evaluate an outline. +// +// After evaluating an outline, the bits of every outline object contained in it are consistent +// with the current state of the netlist. In general, any further modification to the netlist +// causes every outline object to become stale, after which the corresponding outline must be +// re-evaluated, otherwise the bits read from that object are meaningless. +void cxxrtl_outline_eval(cxxrtl_outline outline); + #ifdef __cplusplus } #endif diff --git a/backends/cxxrtl/cxxrtl_vcd.h b/backends/cxxrtl/cxxrtl_vcd.h index dbeabbaf2..3f40a8d12 100644 --- a/backends/cxxrtl/cxxrtl_vcd.h +++ b/backends/cxxrtl/cxxrtl_vcd.h @@ -28,10 +28,13 @@ class vcd_writer { size_t ident; size_t width; chunk_t *curr; - size_t prev_off; + size_t cache_offset; + debug_outline *outline; + bool *outline_warm; }; std::vector<std::string> current_scope; + std::map<debug_outline*, bool> outlines; std::vector<variable> variables; std::vector<chunk_t> cache; std::map<chunk_t*, size_t> aliases; @@ -112,16 +115,22 @@ class vcd_writer { buffer += '\n'; } - const variable ®ister_variable(size_t width, chunk_t *curr, bool constant = false) { + void reset_outlines() { + for (auto &outline_it : outlines) + outline_it.second = /*warm=*/(outline_it.first == nullptr); + } + + variable ®ister_variable(size_t width, chunk_t *curr, bool constant = false, debug_outline *outline = nullptr) { if (aliases.count(curr)) { return variables[aliases[curr]]; } else { + auto outline_it = outlines.emplace(outline, /*warm=*/(outline == nullptr)).first; const size_t chunks = (width + (sizeof(chunk_t) * 8 - 1)) / (sizeof(chunk_t) * 8); aliases[curr] = variables.size(); if (constant) { - variables.emplace_back(variable { variables.size(), width, curr, (size_t)-1 }); + variables.emplace_back(variable { variables.size(), width, curr, (size_t)-1, outline_it->first, &outline_it->second }); } else { - variables.emplace_back(variable { variables.size(), width, curr, cache.size() }); + variables.emplace_back(variable { variables.size(), width, curr, cache.size(), outline_it->first, &outline_it->second }); cache.insert(cache.end(), &curr[0], &curr[chunks]); } return variables.back(); @@ -129,13 +138,17 @@ class vcd_writer { } bool test_variable(const variable &var) { - if (var.prev_off == (size_t)-1) + if (var.cache_offset == (size_t)-1) return false; // constant + if (!*var.outline_warm) { + var.outline->eval(); + *var.outline_warm = true; + } const size_t chunks = (var.width + (sizeof(chunk_t) * 8 - 1)) / (sizeof(chunk_t) * 8); - if (std::equal(&var.curr[0], &var.curr[chunks], &cache[var.prev_off])) { + if (std::equal(&var.curr[0], &var.curr[chunks], &cache[var.cache_offset])) { return false; } else { - std::copy(&var.curr[0], &var.curr[chunks], &cache[var.prev_off]); + std::copy(&var.curr[0], &var.curr[chunks], &cache[var.cache_offset]); return true; } } @@ -197,6 +210,10 @@ public: emit_var(register_variable(item.width, item.curr), "wire", name, item.lsb_at, multipart); break; + case debug_item::OUTLINE: + emit_var(register_variable(item.width, item.curr, /*constant=*/false, item.outline), + "wire", name, item.lsb_at, multipart); + break; } } @@ -211,13 +228,13 @@ public: } void add(const debug_items &items) { - this->template add(items, [](const std::string &, const debug_item &) { + this->add(items, [](const std::string &, const debug_item &) { return true; }); } void add_without_memories(const debug_items &items) { - this->template add(items, [](const std::string &, const debug_item &item) { + this->add(items, [](const std::string &, const debug_item &item) { return item.type != debug_item::MEMORY; }); } @@ -228,6 +245,7 @@ public: emit_scope({}); emit_enddefinitions(); } + reset_outlines(); emit_time(timestamp); for (auto var : variables) if (test_variable(var) || first_sample) { diff --git a/backends/spice/spice.cc b/backends/spice/spice.cc index aa20f106a..ca5c680c9 100644 --- a/backends/spice/spice.cc +++ b/backends/spice/spice.cc @@ -64,7 +64,7 @@ static void print_spice_net(std::ostream &f, RTLIL::SigBit s, std::string &neg, } } -static void print_spice_module(std::ostream &f, RTLIL::Module *module, RTLIL::Design *design, std::string &neg, std::string &pos, std::string &ncpf, bool big_endian, bool use_inames) +static void print_spice_module(std::ostream &f, RTLIL::Module *module, RTLIL::Design *design, std::string &neg, std::string &pos, std::string &buf, std::string &ncpf, bool big_endian, bool use_inames) { SigMap sigmap(module); idict<IdString, 1> inums; @@ -121,10 +121,10 @@ static void print_spice_module(std::ostream &f, RTLIL::Module *module, RTLIL::De for (auto &conn : module->connections()) for (int i = 0; i < conn.first.size(); i++) { - f << stringf("V%d", conn_counter++); - print_spice_net(f, conn.first.extract(i, 1), neg, pos, ncpf, nc_counter, use_inames, inums); + f << (buf == "DC" ? stringf("V%d", conn_counter++) : stringf("X%d", cell_counter++)); print_spice_net(f, conn.second.extract(i, 1), neg, pos, ncpf, nc_counter, use_inames, inums); - f << stringf(" DC 0\n"); + print_spice_net(f, conn.first.extract(i, 1), neg, pos, ncpf, nc_counter, use_inames, inums); + f << (buf == "DC" ? " DC 0\n" : stringf(" %s\n", buf.c_str())); } } @@ -148,6 +148,10 @@ struct SpiceBackend : public Backend { log(" -pos net_name\n"); log(" set the net name for constant 1 (default: Vdd)\n"); log("\n"); + log(" -buf DC|subckt_name\n"); + log(" set the name for jumper element (default: DC)\n"); + log(" (used to connect different nets)\n"); + log("\n"); log(" -nc_prefix\n"); log(" prefix for not-connected nets (default: _NC)\n"); log("\n"); @@ -164,7 +168,7 @@ struct SpiceBackend : public Backend { std::string top_module_name; RTLIL::Module *top_module = NULL; bool big_endian = false, use_inames = false; - std::string neg = "Vss", pos = "Vdd", ncpf = "_NC"; + std::string neg = "Vss", pos = "Vdd", ncpf = "_NC", buf = "DC"; log_header(design, "Executing SPICE backend.\n"); @@ -187,6 +191,10 @@ struct SpiceBackend : public Backend { pos = args[++argidx]; continue; } + if (args[argidx] == "-buf" && argidx+1 < args.size()) { + buf = args[++argidx]; + continue; + } if (args[argidx] == "-nc_prefix" && argidx+1 < args.size()) { ncpf = args[++argidx]; continue; @@ -241,14 +249,14 @@ struct SpiceBackend : public Backend { *f << stringf(" %s", spice_id2str(wire->name).c_str()); } *f << stringf("\n"); - print_spice_module(*f, module, design, neg, pos, ncpf, big_endian, use_inames); + print_spice_module(*f, module, design, neg, pos, buf, ncpf, big_endian, use_inames); *f << stringf(".ENDS %s\n\n", spice_id2str(module->name).c_str()); } if (!top_module_name.empty()) { if (top_module == NULL) log_error("Can't find top module `%s'!\n", top_module_name.c_str()); - print_spice_module(*f, top_module, design, neg, pos, ncpf, big_endian, use_inames); + print_spice_module(*f, top_module, design, neg, pos, buf, ncpf, big_endian, use_inames); *f << stringf("\n"); } diff --git a/frontends/ast/ast.cc b/frontends/ast/ast.cc index c8183580b..dc47420af 100644 --- a/frontends/ast/ast.cc +++ b/frontends/ast/ast.cc @@ -548,9 +548,9 @@ void AstNode::dumpVlog(FILE *f, std::string indent) const break; case AST_CASE: - if (!children.empty() && children[0]->type == AST_CONDX) + if (children.size() > 1 && children[1]->type == AST_CONDX) fprintf(f, "%s" "casex (", indent.c_str()); - else if (!children.empty() && children[0]->type == AST_CONDZ) + else if (children.size() > 1 && children[1]->type == AST_CONDZ) fprintf(f, "%s" "casez (", indent.c_str()); else fprintf(f, "%s" "case (", indent.c_str()); @@ -1511,6 +1511,7 @@ RTLIL::IdString AstModule::derive(RTLIL::Design *design, const dict<RTLIL::IdStr } } else { + modname = new_modname; log("Found cached RTLIL representation for module `%s'.\n", modname.c_str()); } diff --git a/frontends/ast/ast.h b/frontends/ast/ast.h index 1b8ed22ca..d8818df31 100644 --- a/frontends/ast/ast.h +++ b/frontends/ast/ast.h @@ -250,9 +250,10 @@ namespace AST // simplify() creates a simpler AST by unrolling for-loops, expanding generate blocks, etc. // it also sets the id2ast pointers so that identifier lookups are fast in genRTLIL() bool simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage, int width_hint, bool sign_hint, bool in_param); + void replace_result_wire_name_in_function(const std::string &from, const std::string &to); AstNode *readmem(bool is_readmemh, std::string mem_filename, AstNode *memory, int start_addr, int finish_addr, bool unconditional_init); - void expand_genblock(std::string index_var, std::string prefix, std::map<std::string, std::string> &name_map, bool original_scope = true); - void replace_ids(const std::string &prefix, const std::map<std::string, std::string> &rules); + void expand_genblock(const std::string &prefix); + void label_genblks(std::set<std::string>& existing, int &counter); void mem2reg_as_needed_pass1(dict<AstNode*, pool<std::string>> &mem2reg_places, dict<AstNode*, uint32_t> &mem2reg_flags, dict<AstNode*, uint32_t> &proc_flags, uint32_t &status_flags); bool mem2reg_as_needed_pass2(pool<AstNode*> &mem2reg_set, AstNode *mod, AstNode *block, AstNode *&async_block); @@ -263,9 +264,9 @@ namespace AST // additional functionality for evaluating constant functions struct varinfo_t { RTLIL::Const val; int offset; bool is_signed; }; - bool has_const_only_constructs(bool &recommend_const_eval); - void replace_variables(std::map<std::string, varinfo_t> &variables, AstNode *fcall); - AstNode *eval_const_function(AstNode *fcall); + bool has_const_only_constructs(); + bool replace_variables(std::map<std::string, varinfo_t> &variables, AstNode *fcall, bool must_succeed); + AstNode *eval_const_function(AstNode *fcall, bool must_succeed); bool is_simple_const_expr(); std::string process_format_str(const std::string &sformat, int next_arg, int stage, int width_hint, bool sign_hint); diff --git a/frontends/ast/dpicall.cc b/frontends/ast/dpicall.cc index e241142d3..948c9083c 100644 --- a/frontends/ast/dpicall.cc +++ b/frontends/ast/dpicall.cc @@ -67,7 +67,7 @@ static ffi_fptr resolve_fn (std::string symbol_name) AST::AstNode *AST::dpi_call(const std::string &rtype, const std::string &fname, const std::vector<std::string> &argtypes, const std::vector<AstNode*> &args) { AST::AstNode *newNode = nullptr; - union { double f64; float f32; int32_t i32; } value_store [args.size() + 1]; + union { double f64; float f32; int32_t i32; void *ptr; } value_store [args.size() + 1]; ffi_type *types [args.size() + 1]; void *values [args.size() + 1]; ffi_cif cif; @@ -92,6 +92,11 @@ AST::AstNode *AST::dpi_call(const std::string &rtype, const std::string &fname, value_store[i].i32 = args[i]->asInt(args[i]->is_signed); values[i] = &value_store[i].i32; types[i] = &ffi_type_sint32; + } else if (argtypes[i] == "chandle") { + log(" arg %d (%s): %llx\n", i, argtypes[i].c_str(), (unsigned long long)args[i]->asInt(false)); + value_store[i].ptr = (void *)args[i]->asInt(args[i]->is_signed); + values[i] = &value_store[i].ptr; + types[i] = &ffi_type_pointer; } else { log_error("invalid argtype '%s' for argument %d.\n", argtypes[i].c_str(), i); } @@ -106,6 +111,9 @@ AST::AstNode *AST::dpi_call(const std::string &rtype, const std::string &fname, } else if (rtype == "real") { types[args.size()] = &ffi_type_double; values[args.size()] = &value_store[args.size()].f64; + } else if (rtype == "chandle") { + types[args.size()] = &ffi_type_pointer; + values[args.size()] = &value_store[args.size()].ptr; } else { log_error("invalid rtype '%s'.\n", rtype.c_str()); } @@ -123,6 +131,13 @@ AST::AstNode *AST::dpi_call(const std::string &rtype, const std::string &fname, newNode = new AstNode(AST_REALVALUE); newNode->realvalue = value_store[args.size()].f32; log(" return realvalue: %g\n", newNode->asReal(true)); + } else if (rtype == "chandle") { + uint64_t rawval = (uint64_t)value_store[args.size()].ptr; + std::vector<RTLIL::State> bits(64); + for (int i = 0; i < 64; i++) + bits.at(i) = (rawval & (1ULL << i)) ? RTLIL::State::S1 : RTLIL::State::S0; + newNode = AstNode::mkconst_bits(bits, false); + log(" return chandle: %llx\n", (unsigned long long)newNode->asInt(false)); } else { newNode = AstNode::mkconst_int(value_store[args.size()].i32, false); log(" return integer: %lld\n", (long long)newNode->asInt(true)); diff --git a/frontends/ast/genrtlil.cc b/frontends/ast/genrtlil.cc index e878d0dd2..24f5e1bef 100644 --- a/frontends/ast/genrtlil.cc +++ b/frontends/ast/genrtlil.cc @@ -49,6 +49,7 @@ static RTLIL::SigSpec uniop2rtlil(AstNode *that, IdString type, int result_width RTLIL::Wire *wire = current_module->addWire(cell->name.str() + "_Y", result_width); wire->attributes[ID::src] = stringf("%s:%d.%d-%d.%d", that->filename.c_str(), that->location.first_line, that->location.first_column, that->location.last_line, that->location.last_column); + wire->is_signed = that->is_signed; if (gen_attributes) for (auto &attr : that->attributes) { @@ -80,6 +81,7 @@ static void widthExtend(AstNode *that, RTLIL::SigSpec &sig, int width, bool is_s RTLIL::Wire *wire = current_module->addWire(cell->name.str() + "_Y", width); wire->attributes[ID::src] = stringf("%s:%d.%d-%d.%d", that->filename.c_str(), that->location.first_line, that->location.first_column, that->location.last_line, that->location.last_column); + wire->is_signed = that->is_signed; if (that != NULL) for (auto &attr : that->attributes) { @@ -106,6 +108,7 @@ static RTLIL::SigSpec binop2rtlil(AstNode *that, IdString type, int result_width RTLIL::Wire *wire = current_module->addWire(cell->name.str() + "_Y", result_width); wire->attributes[ID::src] = stringf("%s:%d.%d-%d.%d", that->filename.c_str(), that->location.first_line, that->location.first_column, that->location.last_line, that->location.last_column); + wire->is_signed = that->is_signed; for (auto &attr : that->attributes) { if (attr.second->type != AST_CONSTANT) @@ -140,6 +143,7 @@ static RTLIL::SigSpec mux2rtlil(AstNode *that, const RTLIL::SigSpec &cond, const RTLIL::Wire *wire = current_module->addWire(cell->name.str() + "_Y", left.size()); wire->attributes[ID::src] = stringf("%s:%d.%d-%d.%d", that->filename.c_str(), that->location.first_line, that->location.first_column, that->location.last_line, that->location.last_column); + wire->is_signed = that->is_signed; for (auto &attr : that->attributes) { if (attr.second->type != AST_CONSTANT) @@ -1048,6 +1052,7 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint) RTLIL::Const val = children[0]->bitsAsConst(); RTLIL::Wire *wire = current_module->addWire(str, GetSize(val)); current_module->connect(wire, val); + wire->is_signed = children[0]->is_signed; wire->attributes[ID::src] = stringf("%s:%d.%d-%d.%d", filename.c_str(), location.first_line, location.first_column, location.last_line, location.last_column); wire->attributes[type == AST_PARAMETER ? ID::parameter : ID::localparam] = 1; @@ -1549,6 +1554,7 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint) int mem_width, mem_size, addr_bits; is_signed = id2ast->is_signed; + wire->is_signed = is_signed; id2ast->meminfo(mem_width, mem_size, addr_bits); RTLIL::SigSpec addr_sig = children[0]->genRTLIL(); @@ -1721,8 +1727,29 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint) } if (child->type == AST_ARGUMENT) { RTLIL::SigSpec sig; - if (child->children.size() > 0) - sig = child->children[0]->genRTLIL(); + if (child->children.size() > 0) { + AstNode *arg = child->children[0]; + int local_width_hint = -1; + bool local_sign_hint = false; + // don't inadvertently attempt to detect the width of interfaces + if (arg->type != AST_IDENTIFIER || !arg->id2ast || arg->id2ast->type != AST_CELL) + arg->detectSignWidth(local_width_hint, local_sign_hint); + sig = arg->genRTLIL(local_width_hint, local_sign_hint); + log_assert(local_sign_hint == arg->is_signed); + if (sig.is_wire()) { + // if the resulting SigSpec is a wire, its + // signedness should match that of the AstNode + log_assert(arg->is_signed == sig.as_wire()->is_signed); + } else if (arg->is_signed) { + // non-trivial signed nodes are indirected through + // signed wires to enable sign extension + RTLIL::IdString wire_name = NEW_ID; + RTLIL::Wire *wire = current_module->addWire(wire_name, GetSize(sig)); + wire->is_signed = true; + current_module->connect(wire, sig); + sig = wire; + } + } if (child->str.size() == 0) { char buf[100]; snprintf(buf, 100, "$%d", ++port_counter); diff --git a/frontends/ast/simplify.cc b/frontends/ast/simplify.cc index fb6623f02..402b7257b 100644 --- a/frontends/ast/simplify.cc +++ b/frontends/ast/simplify.cc @@ -549,6 +549,16 @@ static bool node_contains_assignment_to(const AstNode* node, const AstNode* var) return true; } +static std::string prefix_id(const std::string &prefix, const std::string &str) +{ + log_assert(!prefix.empty() && (prefix.front() == '$' || prefix.front() == '\\')); + log_assert(!str.empty() && (str.front() == '$' || str.front() == '\\')); + log_assert(prefix.back() == '.'); + if (str.front() == '\\') + return prefix + str.substr(1); + return prefix + str; +} + // convert the AST into a simpler AST that has all parameters substituted by their // values, unrolled for-loops, expanded generate blocks, etc. when this function // is done with an AST it can be converted into RTLIL using genRTLIL(). @@ -748,6 +758,9 @@ bool AstNode::simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage, // also merge multiple declarations for the same wire (e.g. "output foobar; reg foobar;") if (type == AST_MODULE) { current_scope.clear(); + std::set<std::string> existing; + int counter = 0; + label_genblks(existing, counter); std::map<std::string, AstNode*> this_wire_scope; for (size_t i = 0; i < children.size(); i++) { AstNode *node = children[i]; @@ -1325,6 +1338,9 @@ bool AstNode::simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage, if (template_node->type == AST_STRUCT || template_node->type == AST_UNION) { // replace with wire representing the packed structure newNode = make_packed_struct(template_node, str); + // add original input/output attribute to resolved wire + newNode->is_input = this->is_input; + newNode->is_output = this->is_output; current_scope[str] = this; goto apply_newNode; } @@ -1847,19 +1863,24 @@ bool AstNode::simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage, // expand body int index = varbuf->children[0]->integer; - if (body_ast->type == AST_GENBLOCK) - buf = body_ast->clone(); - else - buf = new AstNode(AST_GENBLOCK, body_ast->clone()); - if (buf->str.empty()) { - std::stringstream sstr; - sstr << "$genblock$" << filename << ":" << location.first_line << "$" << (autoidx++); - buf->str = sstr.str(); - } - std::map<std::string, std::string> name_map; + log_assert(body_ast->type == AST_GENBLOCK || body_ast->type == AST_BLOCK); + log_assert(!body_ast->str.empty()); + buf = body_ast->clone(); + std::stringstream sstr; sstr << buf->str << "[" << index << "]."; - buf->expand_genblock(varbuf->str, sstr.str(), name_map); + std::string prefix = sstr.str(); + + // create a scoped localparam for the current value of the loop variable + AstNode *local_index = varbuf->clone(); + size_t pos = local_index->str.rfind('.'); + if (pos != std::string::npos) // remove outer prefix + local_index->str = "\\" + local_index->str.substr(pos + 1); + local_index->str = prefix_id(prefix, local_index->str); + current_scope[local_index->str] = local_index; + current_ast_mod->children.push_back(local_index); + + buf->expand_genblock(prefix); if (type == AST_GENFOR) { for (size_t i = 0; i < buf->children.size(); i++) { @@ -1907,14 +1928,16 @@ bool AstNode::simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage, { for (size_t i = 0; i < children.size(); i++) if (children[i]->type == AST_WIRE || children[i]->type == AST_MEMORY || children[i]->type == AST_PARAMETER || children[i]->type == AST_LOCALPARAM || children[i]->type == AST_TYPEDEF) - log_file_error(children[i]->filename, children[i]->location.first_line, "Local declaration in unnamed block is an unsupported SystemVerilog feature!\n"); + { + log_assert(!VERILOG_FRONTEND::sv_mode); + log_file_error(children[i]->filename, children[i]->location.first_line, "Local declaration in unnamed block is only supported in SystemVerilog mode!\n"); + } } // transform block with name if (type == AST_BLOCK && !str.empty()) { - std::map<std::string, std::string> name_map; - expand_genblock(std::string(), str + ".", name_map); + expand_genblock(str + "."); std::vector<AstNode*> new_children; for (size_t i = 0; i < children.size(); i++) @@ -1934,8 +1957,7 @@ bool AstNode::simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage, if (type == AST_GENBLOCK && children.size() != 0) { if (!str.empty()) { - std::map<std::string, std::string> name_map; - expand_genblock(std::string(), str + ".", name_map); + expand_genblock(str + "."); } for (size_t i = 0; i < children.size(); i++) { @@ -1971,8 +1993,7 @@ bool AstNode::simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage, buf = new AstNode(AST_GENBLOCK, buf); if (!buf->str.empty()) { - std::map<std::string, std::string> name_map; - buf->expand_genblock(std::string(), buf->str + ".", name_map); + buf->expand_genblock(buf->str + "."); } for (size_t i = 0; i < buf->children.size(); i++) { @@ -2050,8 +2071,7 @@ bool AstNode::simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage, buf = selected_case->clone(); if (!buf->str.empty()) { - std::map<std::string, std::string> name_map; - buf->expand_genblock(std::string(), buf->str + ".", name_map); + buf->expand_genblock(buf->str + "."); } for (size_t i = 0; i < buf->children.size(); i++) { @@ -3151,16 +3171,19 @@ skip_dynamic_range_lvalue_expansion:; log_file_error(filename, location.first_line, "Can't resolve task name `%s'.\n", str.c_str()); } - AstNode *decl = current_scope[str]; std::stringstream sstr; - sstr << "$func$" << str << "$" << filename << ":" << location.first_line << "$" << (autoidx++) << "$"; + sstr << str << "$func$" << filename << ":" << location.first_line << "$" << (autoidx++) << '.'; std::string prefix = sstr.str(); - bool recommend_const_eval = false; - bool require_const_eval = in_param ? false : has_const_only_constructs(recommend_const_eval); - if ((in_param || recommend_const_eval || require_const_eval) && !decl->attributes.count(ID::via_celltype)) + AstNode *decl = current_scope[str]; + decl = decl->clone(); + decl->replace_result_wire_name_in_function(str, "$result"); // enables recursion + decl->expand_genblock(prefix); + + if (decl->type == AST_FUNCTION && !decl->attributes.count(ID::via_celltype)) { + bool require_const_eval = decl->has_const_only_constructs(); bool all_args_const = true; for (auto child : children) { while (child->simplify(true, false, false, 1, -1, false, true)) { } @@ -3169,10 +3192,14 @@ skip_dynamic_range_lvalue_expansion:; } if (all_args_const) { - AstNode *func_workspace = current_scope[str]->clone(); - newNode = func_workspace->eval_const_function(this); + AstNode *func_workspace = decl->clone(); + func_workspace->str = prefix_id(prefix, "$result"); + newNode = func_workspace->eval_const_function(this, in_param || require_const_eval); delete func_workspace; - goto apply_newNode; + if (newNode) { + delete decl; + goto apply_newNode; + } } if (in_param) @@ -3182,8 +3209,6 @@ skip_dynamic_range_lvalue_expansion:; } size_t arg_count = 0; - std::map<std::string, std::string> replace_rules; - vector<AstNode*> added_mod_children; dict<std::string, AstNode*> wire_cache; vector<AstNode*> new_stmts; vector<AstNode*> output_assignments; @@ -3193,16 +3218,17 @@ skip_dynamic_range_lvalue_expansion:; log_assert(type == AST_FCALL); AstNode *wire = NULL; + std::string res_name = prefix_id(prefix, "$result"); for (auto child : decl->children) - if (child->type == AST_WIRE && child->str == str) + if (child->type == AST_WIRE && child->str == res_name) wire = child->clone(); log_assert(wire != NULL); - wire->str = prefix + str; wire->port_id = 0; wire->is_input = false; wire->is_output = false; + current_scope[wire->str] = wire; current_ast_mod->children.push_back(wire); while (wire->simplify(true, false, false, 1, -1, false, false)) { } @@ -3246,7 +3272,6 @@ skip_dynamic_range_lvalue_expansion:; if (child->type == AST_WIRE && (child->is_input || child->is_output || (type == AST_FCALL && child->str == str))) { AstNode *wire = child->clone(); - wire->str = prefix + wire->str; wire->port_id = 0; wire->is_input = false; wire->is_output = false; @@ -3308,7 +3333,6 @@ skip_dynamic_range_lvalue_expansion:; else { wire = child->clone(); - wire->str = prefix + wire->str; wire->port_id = 0; wire->is_input = false; wire->is_output = false; @@ -3319,15 +3343,11 @@ skip_dynamic_range_lvalue_expansion:; wire_cache[child->str] = wire; + current_scope[wire->str] = wire; current_ast_mod->children.push_back(wire); - added_mod_children.push_back(wire); } - if (child->type == AST_WIRE) - while (wire->simplify(true, false, false, 1, -1, false, false)) { } - - replace_rules[child->str] = wire->str; - current_scope[wire->str] = wire; + while (wire->simplify(true, false, false, 1, -1, false, false)) { } if ((child->is_input || child->is_output) && arg_count < children.size()) { @@ -3337,6 +3357,25 @@ skip_dynamic_range_lvalue_expansion:; wire->type = AST_LOCALPARAM; wire->attributes.erase(ID::nosync); wire->children.insert(wire->children.begin(), arg->clone()); + // args without a range implicitly have width 1 + if (wire->children.back()->type != AST_RANGE) { + // check if this wire is redeclared with an explicit size + bool uses_explicit_size = false; + for (const AstNode *other_child : decl->children) + if (other_child->type == AST_WIRE && child->str == other_child->str + && !other_child->children.empty() + && other_child->children.back()->type == AST_RANGE) { + uses_explicit_size = true; + break; + } + if (!uses_explicit_size) { + AstNode* range = new AstNode(); + range->type = AST_RANGE; + wire->children.push_back(range); + range->children.push_back(mkconst_int(0, true)); + range->children.push_back(mkconst_int(0, true)); + } + } continue; } AstNode *wire_id = new AstNode(AST_IDENTIFIER); @@ -3352,18 +3391,9 @@ skip_dynamic_range_lvalue_expansion:; } } - for (auto child : added_mod_children) { - child->replace_ids(prefix, replace_rules); - while (child->simplify(true, false, false, 1, -1, false, false)) { } - } - for (auto child : decl->children) if (child->type != AST_WIRE && child->type != AST_MEMORY && child->type != AST_PARAMETER && child->type != AST_LOCALPARAM) - { - AstNode *stmt = child->clone(); - stmt->replace_ids(prefix, replace_rules); - new_stmts.push_back(stmt); - } + new_stmts.push_back(child->clone()); new_stmts.insert(new_stmts.end(), output_assignments.begin(), output_assignments.end()); @@ -3376,10 +3406,11 @@ skip_dynamic_range_lvalue_expansion:; } replace_fcall_with_id: + delete decl; if (type == AST_FCALL) { delete_children(); type = AST_IDENTIFIER; - str = prefix + str; + str = prefix_id(prefix, "$result"); } if (type == AST_TCALL) str = ""; @@ -3427,7 +3458,14 @@ replace_fcall_later:; if (current_scope[str]->children[0]->isConst()) newNode = current_scope[str]->children[0]->clone(); } - else if (at_zero && current_scope.count(str) > 0 && (current_scope[str]->type == AST_WIRE || current_scope[str]->type == AST_AUTOWIRE)) { + else if (at_zero && current_scope.count(str) > 0) { + AstNode *node = current_scope[str]; + if (node->type == AST_WIRE || node->type == AST_AUTOWIRE || node->type == AST_MEMORY) + newNode = mkconst_int(0, sign_hint, width_hint); + } + break; + case AST_MEMRD: + if (at_zero) { newNode = mkconst_int(0, sign_hint, width_hint); } break; @@ -3683,12 +3721,12 @@ apply_newNode: return did_something; } -static void replace_result_wire_name_in_function(AstNode *node, std::string &from, std::string &to) +void AstNode::replace_result_wire_name_in_function(const std::string &from, const std::string &to) { - for (auto &it : node->children) - replace_result_wire_name_in_function(it, from, to); - if (node->str == from) - node->str = to; + for (AstNode *child : children) + child->replace_result_wire_name_in_function(from, to); + if (str == from && type != AST_FCALL && type != AST_TCALL) + str = to; } // replace a readmem[bh] TCALL ast node with a block of memory assignments @@ -3823,65 +3861,54 @@ AstNode *AstNode::readmem(bool is_readmemh, std::string mem_filename, AstNode *m return block; } -// annotate the names of all wires and other named objects in a generate block -void AstNode::expand_genblock(std::string index_var, std::string prefix, std::map<std::string, std::string> &name_map, bool original_scope) +// annotate the names of all wires and other named objects in a named generate +// or procedural block; nested blocks are themselves annotated such that the +// prefix is carried forward, but resolution of their children is deferred +void AstNode::expand_genblock(const std::string &prefix) { - // `original_scope` defaults to false, and is used to prevent the premature - // prefixing of items in named sub-blocks - - if (!index_var.empty() && type == AST_IDENTIFIER && str == index_var) { - if (children.empty()) { - current_scope[index_var]->children[0]->cloneInto(this); - } else { - AstNode *p = new AstNode(AST_LOCALPARAM, current_scope[index_var]->children[0]->clone()); - p->str = stringf("$genval$%d", autoidx++); - current_ast_mod->children.push_back(p); - str = p->str; - id2ast = p; - } - } - if (type == AST_IDENTIFIER || type == AST_FCALL || type == AST_TCALL || type == AST_WIRETYPE) { - if (name_map.count(str) > 0) { - str = name_map[str]; - } else { - // remap the prefix of this ident if it is a local generate scope - size_t pos = str.rfind('.'); - if (pos != std::string::npos) { - std::string existing_prefix = str.substr(0, pos); - if (name_map.count(existing_prefix) > 0) { - str = name_map[existing_prefix] + str.substr(pos); - } + log_assert(!str.empty()); + + // search starting in the innermost scope and then stepping outward + for (size_t ppos = prefix.size() - 1; ppos; --ppos) { + if (prefix.at(ppos) != '.') continue; + + std::string new_prefix = prefix.substr(0, ppos + 1); + auto attempt_resolve = [&new_prefix](const std::string &ident) -> std::string { + std::string new_name = prefix_id(new_prefix, ident); + if (current_scope.count(new_name)) + return new_name; + return {}; + }; + + // attempt to resolve the full identifier + std::string resolved = attempt_resolve(str); + if (!resolved.empty()) { + str = resolved; + break; } - } - } - - std::map<std::string, std::string> backup_name_map; - auto prefix_node = [&](AstNode* child) { - if (backup_name_map.size() == 0) - backup_name_map = name_map; + // attempt to resolve hierarchical prefixes within the identifier, + // as the prefix could refer to a local scope which exists but + // hasn't yet been elaborated + for (size_t spos = str.size() - 1; spos; --spos) { + if (str.at(spos) != '.') continue; + resolved = attempt_resolve(str.substr(0, spos)); + if (!resolved.empty()) { + str = resolved + str.substr(spos); + ppos = 1; // break outer loop + break; + } + } - // if within a nested scope - if (!original_scope) { - // this declaration shadows anything in the parent scope(s) - name_map[child->str] = child->str; - return; } + } - std::string new_name = prefix[0] == '\\' ? prefix.substr(1) : prefix; - size_t pos = child->str.rfind('.'); - if (pos == std::string::npos) - pos = child->str[0] == '\\' && prefix[0] == '\\' ? 1 : 0; - else - pos = pos + 1; - new_name = child->str.substr(0, pos) + new_name + child->str.substr(pos); - if (new_name[0] != '$' && new_name[0] != '\\') - new_name = prefix[0] + new_name; - - name_map[child->str] = new_name; + auto prefix_node = [&prefix](AstNode* child) { + if (child->str.empty()) return; + std::string new_name = prefix_id(prefix, child->str); if (child->type == AST_FUNCTION) - replace_result_wire_name_in_function(child, child->str, new_name); + child->replace_result_wire_name_in_function(child->str, new_name); else child->str = new_name; current_scope[new_name] = child; @@ -3931,43 +3958,55 @@ void AstNode::expand_genblock(std::string index_var, std::string prefix, std::ma continue; // functions/tasks may reference wires, constants, etc. in this scope if (child->type == AST_FUNCTION || child->type == AST_TASK) - child->expand_genblock(index_var, prefix, name_map, false); - // continue prefixing if this child block is anonymous - else if (child->type == AST_GENBLOCK || child->type == AST_BLOCK) - child->expand_genblock(index_var, prefix, name_map, original_scope && child->str.empty()); - else - child->expand_genblock(index_var, prefix, name_map, original_scope); - } - + continue; + // named blocks pick up the current prefix and will expanded later + if ((child->type == AST_GENBLOCK || child->type == AST_BLOCK) && !child->str.empty()) + continue; - if (backup_name_map.size() > 0) - name_map.swap(backup_name_map); + child->expand_genblock(prefix); + } } -// rename stuff (used when tasks of functions are instantiated) -void AstNode::replace_ids(const std::string &prefix, const std::map<std::string, std::string> &rules) +// add implicit AST_GENBLOCK names according to IEEE 1364-2005 Section 12.4.3 or +// IEEE 1800-2017 Section 27.6 +void AstNode::label_genblks(std::set<std::string>& existing, int &counter) { - if (type == AST_BLOCK) - { - std::map<std::string, std::string> new_rules = rules; - std::string new_prefix = prefix + str; - - for (auto child : children) - if (child->type == AST_WIRE) { - new_rules[child->str] = new_prefix + child->str; - child->str = new_prefix + child->str; - } + switch (type) { + case AST_GENIF: + case AST_GENFOR: + case AST_GENCASE: + // seeing a proper generate control flow construct increments the + // counter once + ++counter; + for (AstNode *child : children) + child->label_genblks(existing, counter); + break; - for (auto child : children) - if (child->type != AST_WIRE) - child->replace_ids(new_prefix, new_rules); + case AST_GENBLOCK: { + // if this block is unlabeled, generate its corresponding unique name + for (int padding = 0; str.empty(); ++padding) { + std::string candidate = "\\genblk"; + for (int i = 0; i < padding; ++i) + candidate += '0'; + candidate += std::to_string(counter); + if (!existing.count(candidate)) + str = candidate; + } + // within a genblk, the counter starts fresh + std::set<std::string> existing_local = existing; + int counter_local = 0; + for (AstNode *child : children) + child->label_genblks(existing_local, counter_local); + break; } - else - { - if (type == AST_IDENTIFIER && rules.count(str) > 0) - str = rules.at(str); - for (auto child : children) - child->replace_ids(prefix, rules); + + default: + // track names which could conflict with implicit genblk names + if (str.rfind("\\genblk", 0) == 0) + existing.insert(str); + for (AstNode *child : children) + child->label_genblks(existing, counter); + break; } } @@ -4459,17 +4498,12 @@ bool AstNode::detect_latch(const std::string &var) } } -bool AstNode::has_const_only_constructs(bool &recommend_const_eval) +bool AstNode::has_const_only_constructs() { - if (type == AST_FOR) - recommend_const_eval = true; if (type == AST_WHILE || type == AST_REPEAT) return true; - if (type == AST_FCALL && current_scope.count(str)) - if (current_scope[str]->has_const_only_constructs(recommend_const_eval)) - return true; for (auto child : children) - if (child->AstNode::has_const_only_constructs(recommend_const_eval)) + if (child->has_const_only_constructs()) return true; return false; } @@ -4485,19 +4519,26 @@ bool AstNode::is_simple_const_expr() } // helper function for AstNode::eval_const_function() -void AstNode::replace_variables(std::map<std::string, AstNode::varinfo_t> &variables, AstNode *fcall) +bool AstNode::replace_variables(std::map<std::string, AstNode::varinfo_t> &variables, AstNode *fcall, bool must_succeed) { if (type == AST_IDENTIFIER && variables.count(str)) { int offset = variables.at(str).offset, width = variables.at(str).val.bits.size(); if (!children.empty()) { - if (children.size() != 1 || children.at(0)->type != AST_RANGE) + if (children.size() != 1 || children.at(0)->type != AST_RANGE) { + if (!must_succeed) + return false; log_file_error(filename, location.first_line, "Memory access in constant function is not supported\n%s:%d.%d-%d.%d: ...called from here.\n", fcall->filename.c_str(), fcall->location.first_line, fcall->location.first_column, fcall->location.last_line, fcall->location.last_column); - children.at(0)->replace_variables(variables, fcall); + } + if (!children.at(0)->replace_variables(variables, fcall, must_succeed)) + return false; while (simplify(true, false, false, 1, -1, false, true)) { } - if (!children.at(0)->range_valid) + if (!children.at(0)->range_valid) { + if (!must_succeed) + return false; log_file_error(filename, location.first_line, "Non-constant range\n%s:%d.%d-%d.%d: ... called from here.\n", fcall->filename.c_str(), fcall->location.first_line, fcall->location.first_column, fcall->location.last_line, fcall->location.last_column); + } offset = min(children.at(0)->range_left, children.at(0)->range_right); width = min(std::abs(children.at(0)->range_left - children.at(0)->range_right) + 1, width); } @@ -4507,19 +4548,22 @@ void AstNode::replace_variables(std::map<std::string, AstNode::varinfo_t> &varia AstNode *newNode = mkconst_bits(new_bits, variables.at(str).is_signed); newNode->cloneInto(this); delete newNode; - return; + return true; } for (auto &child : children) - child->replace_variables(variables, fcall); + if (!child->replace_variables(variables, fcall, must_succeed)) + return false; + return true; } -// evaluate functions with all-const arguments -AstNode *AstNode::eval_const_function(AstNode *fcall) +// attempt to statically evaluate a functions with all-const arguments +AstNode *AstNode::eval_const_function(AstNode *fcall, bool must_succeed) { - std::map<std::string, AstNode*> backup_scope; + std::map<std::string, AstNode*> backup_scope = current_scope; std::map<std::string, AstNode::varinfo_t> variables; AstNode *block = new AstNode(AST_BLOCK); + AstNode *result = nullptr; size_t argidx = 0; for (auto child : children) @@ -4541,9 +4585,12 @@ AstNode *AstNode::eval_const_function(AstNode *fcall) if (stmt->type == AST_WIRE) { while (stmt->simplify(true, false, false, 1, -1, false, true)) { } - if (!stmt->range_valid) + if (!stmt->range_valid) { + if (!must_succeed) + goto finished; log_file_error(stmt->filename, stmt->location.first_line, "Can't determine size of variable %s\n%s:%d.%d-%d.%d: ... called from here.\n", stmt->str.c_str(), fcall->filename.c_str(), fcall->location.first_line, fcall->location.first_column, fcall->location.last_line, fcall->location.last_column); + } variables[stmt->str].val = RTLIL::Const(RTLIL::State::Sx, abs(stmt->range_left - stmt->range_right)+1); variables[stmt->str].offset = min(stmt->range_left, stmt->range_right); variables[stmt->str].is_signed = stmt->is_signed; @@ -4557,8 +4604,6 @@ AstNode *AstNode::eval_const_function(AstNode *fcall) variables[stmt->str].val = arg_node->realAsConst(width); } } - if (!backup_scope.count(stmt->str)) - backup_scope[stmt->str] = current_scope[stmt->str]; current_scope[stmt->str] = stmt; block->children.erase(block->children.begin()); @@ -4571,8 +4616,6 @@ AstNode *AstNode::eval_const_function(AstNode *fcall) { while (stmt->simplify(true, false, false, 1, -1, false, true)) { } - if (!backup_scope.count(stmt->str)) - backup_scope[stmt->str] = current_scope[stmt->str]; current_scope[stmt->str] = stmt; block->children.erase(block->children.begin()); @@ -4583,32 +4626,46 @@ AstNode *AstNode::eval_const_function(AstNode *fcall) { if (stmt->children.at(0)->type == AST_IDENTIFIER && stmt->children.at(0)->children.size() != 0 && stmt->children.at(0)->children.at(0)->type == AST_RANGE) - stmt->children.at(0)->children.at(0)->replace_variables(variables, fcall); - stmt->children.at(1)->replace_variables(variables, fcall); + if (!stmt->children.at(0)->children.at(0)->replace_variables(variables, fcall, must_succeed)) + goto finished; + if (!stmt->children.at(1)->replace_variables(variables, fcall, must_succeed)) + goto finished; while (stmt->simplify(true, false, false, 1, -1, false, true)) { } if (stmt->type != AST_ASSIGN_EQ) continue; - if (stmt->children.at(1)->type != AST_CONSTANT) + if (stmt->children.at(1)->type != AST_CONSTANT) { + if (!must_succeed) + goto finished; log_file_error(stmt->filename, stmt->location.first_line, "Non-constant expression in constant function\n%s:%d.%d-%d.%d: ... called from here. X\n", fcall->filename.c_str(), fcall->location.first_line, fcall->location.first_column, fcall->location.last_line, fcall->location.last_column); + } - if (stmt->children.at(0)->type != AST_IDENTIFIER) + if (stmt->children.at(0)->type != AST_IDENTIFIER) { + if (!must_succeed) + goto finished; log_file_error(stmt->filename, stmt->location.first_line, "Unsupported composite left hand side in constant function\n%s:%d.%d-%d.%d: ... called from here.\n", fcall->filename.c_str(), fcall->location.first_line, fcall->location.first_column, fcall->location.last_line, fcall->location.last_column); + } - if (!variables.count(stmt->children.at(0)->str)) + if (!variables.count(stmt->children.at(0)->str)) { + if (!must_succeed) + goto finished; log_file_error(stmt->filename, stmt->location.first_line, "Assignment to non-local variable in constant function\n%s:%d.%d-%d.%d: ... called from here.\n", fcall->filename.c_str(), fcall->location.first_line, fcall->location.first_column, fcall->location.last_line, fcall->location.last_column); + } if (stmt->children.at(0)->children.empty()) { variables[stmt->children.at(0)->str].val = stmt->children.at(1)->bitsAsConst(variables[stmt->children.at(0)->str].val.bits.size()); } else { AstNode *range = stmt->children.at(0)->children.at(0); - if (!range->range_valid) + if (!range->range_valid) { + if (!must_succeed) + goto finished; log_file_error(range->filename, range->location.first_line, "Non-constant range\n%s:%d.%d-%d.%d: ... called from here.\n", fcall->filename.c_str(), fcall->location.first_line, fcall->location.first_column, fcall->location.last_line, fcall->location.last_column); + } int offset = min(range->range_left, range->range_right); int width = std::abs(range->range_left - range->range_right) + 1; varinfo_t &v = variables[stmt->children.at(0)->str]; @@ -4635,12 +4692,16 @@ AstNode *AstNode::eval_const_function(AstNode *fcall) if (stmt->type == AST_WHILE) { AstNode *cond = stmt->children.at(0)->clone(); - cond->replace_variables(variables, fcall); + if (!cond->replace_variables(variables, fcall, must_succeed)) + goto finished; while (cond->simplify(true, false, false, 1, -1, false, true)) { } - if (cond->type != AST_CONSTANT) + if (cond->type != AST_CONSTANT) { + if (!must_succeed) + goto finished; log_file_error(stmt->filename, stmt->location.first_line, "Non-constant expression in constant function\n%s:%d.%d-%d.%d: ... called from here.\n", fcall->filename.c_str(), fcall->location.first_line, fcall->location.first_column, fcall->location.last_line, fcall->location.last_column); + } if (cond->asBool()) { block->children.insert(block->children.begin(), stmt->children.at(1)->clone()); @@ -4656,12 +4717,16 @@ AstNode *AstNode::eval_const_function(AstNode *fcall) if (stmt->type == AST_REPEAT) { AstNode *num = stmt->children.at(0)->clone(); - num->replace_variables(variables, fcall); + if (!num->replace_variables(variables, fcall, must_succeed)) + goto finished; while (num->simplify(true, false, false, 1, -1, false, true)) { } - if (num->type != AST_CONSTANT) + if (num->type != AST_CONSTANT) { + if (!must_succeed) + goto finished; log_file_error(stmt->filename, stmt->location.first_line, "Non-constant expression in constant function\n%s:%d.%d-%d.%d: ... called from here.\n", fcall->filename.c_str(), fcall->location.first_line, fcall->location.first_column, fcall->location.last_line, fcall->location.last_column); + } block->children.erase(block->children.begin()); for (int i = 0; i < num->bitsAsConst().as_int(); i++) @@ -4675,7 +4740,8 @@ AstNode *AstNode::eval_const_function(AstNode *fcall) if (stmt->type == AST_CASE) { AstNode *expr = stmt->children.at(0)->clone(); - expr->replace_variables(variables, fcall); + if (!expr->replace_variables(variables, fcall, must_succeed)) + goto finished; while (expr->simplify(true, false, false, 1, -1, false, true)) { } AstNode *sel_case = NULL; @@ -4692,14 +4758,18 @@ AstNode *AstNode::eval_const_function(AstNode *fcall) for (size_t j = 0; j+1 < stmt->children.at(i)->children.size() && !found_match; j++) { AstNode *cond = stmt->children.at(i)->children.at(j)->clone(); - cond->replace_variables(variables, fcall); + if (!cond->replace_variables(variables, fcall, must_succeed)) + goto finished; cond = new AstNode(AST_EQ, expr->clone(), cond); while (cond->simplify(true, false, false, 1, -1, false, true)) { } - if (cond->type != AST_CONSTANT) + if (cond->type != AST_CONSTANT) { + if (!must_succeed) + goto finished; log_file_error(stmt->filename, stmt->location.first_line, "Non-constant expression in constant function\n%s:%d.%d-%d.%d: ... called from here.\n", fcall->filename.c_str(), fcall->location.first_line, fcall->location.first_column, fcall->location.last_line, fcall->location.last_column); + } found_match = cond->asBool(); delete cond; @@ -4721,6 +4791,9 @@ AstNode *AstNode::eval_const_function(AstNode *fcall) if (stmt->type == AST_BLOCK) { + if (!stmt->str.empty()) + stmt->expand_genblock(stmt->str + "."); + block->children.erase(block->children.begin()); block->children.insert(block->children.begin(), stmt->children.begin(), stmt->children.end()); stmt->children.clear(); @@ -4728,20 +4801,20 @@ AstNode *AstNode::eval_const_function(AstNode *fcall) continue; } + if (!must_succeed) + goto finished; log_file_error(stmt->filename, stmt->location.first_line, "Unsupported language construct in constant function\n%s:%d.%d-%d.%d: ... called from here.\n", fcall->filename.c_str(), fcall->location.first_line, fcall->location.first_column, fcall->location.last_line, fcall->location.last_column); log_abort(); } - delete block; + result = AstNode::mkconst_bits(variables.at(str).val.bits, variables.at(str).is_signed); - for (auto &it : backup_scope) - if (it.second == NULL) - current_scope.erase(it.first); - else - current_scope[it.first] = it.second; +finished: + delete block; + current_scope = backup_scope; - return AstNode::mkconst_bits(variables.at(str).val.bits, variables.at(str).is_signed); + return result; } void AstNode::allocateDefaultEnumValues() diff --git a/frontends/verific/verific.cc b/frontends/verific/verific.cc index 31c77d39c..7aa3ebcbb 100644 --- a/frontends/verific/verific.cc +++ b/frontends/verific/verific.cc @@ -49,14 +49,17 @@ USING_YOSYS_NAMESPACE #include "VeriWrite.h" #include "VhdlUnits.h" #include "VeriLibrary.h" + +#if defined(YOSYSHQ_VERIFIC_INITSTATE) || defined(YOSYSHQ_VERIFIC_TEMPLATES) || defined(YOSYSHQ_VERIFIC_FORMALAPPS) #include "VeriExtensions.h" +#endif -#ifndef SYMBIOTIC_VERIFIC_API_VERSION -# error "Only Symbiotic EDA flavored Verific is supported. Please contact office@symbioticeda.com for commercial support for Yosys+Verific." +#ifndef YOSYSHQ_VERIFIC_API_VERSION +# error "Only YosysHQ flavored Verific is supported. Please contact office@yosyshq.com for commercial support for Yosys+Verific." #endif -#if SYMBIOTIC_VERIFIC_API_VERSION < 20201001 -# error "Please update your version of Symbiotic EDA flavored Verific." +#if YOSYSHQ_VERIFIC_API_VERSION < 20210103 +# error "Please update your version of YosysHQ flavored Verific." #endif #ifdef __clang__ @@ -1471,7 +1474,8 @@ void VerificImporter::import_netlist(RTLIL::Design *design, Netlist *nl, std::se continue; } - if (inst->Type() == PRIM_SEDA_INITSTATE) +#ifdef YOSYSHQ_VERIFIC_INITSTATE + if (inst->Type() == PRIM_YOSYSHQ_INITSTATE) { SigBit initstate = module->Initstate(new_verific_id(inst)); SigBit sig_o = net_map_at(inst->GetOutput()); @@ -1480,7 +1484,7 @@ void VerificImporter::import_netlist(RTLIL::Design *design, Netlist *nl, std::se if (!mode_keep) continue; } - +#endif if (!mode_keep && verific_sva_prims.count(inst->Type())) { if (verific_verbose) log(" skipping SVA cell in non k-mode\n"); @@ -1958,9 +1962,10 @@ void verific_import(Design *design, const std::map<std::string,std::string> &par for (const auto &i : parameters) verific_params.Insert(i.first.c_str(), i.second.c_str()); +#ifdef YOSYSHQ_VERIFIC_INITSTATE InitialAssertionRewriter rw; rw.RegisterCallBack(); - +#endif if (top.empty()) { netlists = hier_tree::ElaborateAll(&veri_libs, &vhdl_libs, &verific_params); } @@ -2199,7 +2204,7 @@ struct VerificPass : public Pass { log("\n"); log(" verific -app <application>..\n"); log("\n"); - log("Execute SEDA formal application on loaded Verilog files.\n"); + log("Execute YosysHQ formal application on loaded Verilog files.\n"); log("\n"); log("Application options:\n"); log("\n"); @@ -2217,7 +2222,7 @@ struct VerificPass : public Pass { log("\n"); log("Applications:\n"); log("\n"); -#ifdef YOSYS_ENABLE_VERIFIC +#if defined(YOSYS_ENABLE_VERIFIC) && defined(YOSYSHQ_VERIFIC_FORMALAPPS) VerificFormalApplications vfa; log("%s\n",vfa.GetHelp().c_str()); #else @@ -2243,18 +2248,18 @@ struct VerificPass : public Pass { log("\n"); log("Templates:\n"); log("\n"); -#ifdef YOSYS_ENABLE_VERIFIC +#if defined(YOSYS_ENABLE_VERIFIC) && defined(YOSYSHQ_VERIFIC_TEMPLATES) VerificTemplateGenerator vfg; log("%s\n",vfg.GetHelp().c_str()); #else log(" WARNING: Templates only available in commercial build.\n"); log("\n"); #endif - log("Use Symbiotic EDA Suite if you need Yosys+Verifc.\n"); - log("https://www.symbioticeda.com/seda-suite\n"); + log("Use YosysHQ Tabby CAD Suite if you need Yosys+Verific.\n"); + log("https://www.yosyshq.com/\n"); log("\n"); - log("Contact office@symbioticeda.com for free evaluation\n"); - log("binaries of Symbiotic EDA Suite.\n"); + log("Contact office@yosyshq.com for free evaluation\n"); + log("binaries of YosysHQ Tabby CAD Suite.\n"); log("\n"); } #ifdef YOSYS_ENABLE_VERIFIC @@ -2265,11 +2270,11 @@ struct VerificPass : public Pass { if (check_noverific_env()) log_cmd_error("This version of Yosys is built without Verific support.\n" "\n" - "Use Symbiotic EDA Suite if you need Yosys+Verifc.\n" - "https://www.symbioticeda.com/seda-suite\n" + "Use YosysHQ Tabby CAD Suite if you need Yosys+Verific.\n" + "https://www.yosyshq.com/\n" "\n" - "Contact office@symbioticeda.com for free evaluation\n" - "binaries of Symbiotic EDA Suite.\n"); + "Contact office@yosyshq.com for free evaluation\n" + "binaries of YosysHQ Tabby CAD Suite.\n"); log_header(design, "Executing VERIFIC (loading SystemVerilog and VHDL designs using Verific).\n"); @@ -2494,6 +2499,7 @@ struct VerificPass : public Pass { goto check_error; } +#ifdef YOSYSHQ_VERIFIC_FORMALAPPS if (argidx < GetSize(args) && args[argidx] == "-app") { if (!(argidx+1 < GetSize(args))) @@ -2587,7 +2593,7 @@ struct VerificPass : public Pass { } goto check_error; } - +#endif if (argidx < GetSize(args) && args[argidx] == "-pp") { const char* filename = nullptr; @@ -2630,6 +2636,7 @@ struct VerificPass : public Pass { goto check_error; } +#ifdef YOSYSHQ_VERIFIC_TEMPLATES if (argidx < GetSize(args) && args[argidx] == "-template") { if (!(argidx+1 < GetSize(args))) @@ -2713,7 +2720,7 @@ struct VerificPass : public Pass { fclose(of); goto check_error; } - +#endif if (GetSize(args) > argidx && args[argidx] == "-import") { std::set<Netlist*> nl_todo, nl_done; @@ -2798,9 +2805,10 @@ struct VerificPass : public Pass { std::set<std::string> top_mod_names; +#ifdef YOSYSHQ_VERIFIC_INITSTATE InitialAssertionRewriter rw; rw.RegisterCallBack(); - +#endif if (mode_all) { log("Running hier_tree::ElaborateAll().\n"); @@ -2926,11 +2934,11 @@ struct VerificPass : public Pass { void execute(std::vector<std::string>, RTLIL::Design *) override { log_cmd_error("This version of Yosys is built without Verific support.\n" "\n" - "Use Symbiotic EDA Suite if you need Yosys+Verifc.\n" - "https://www.symbioticeda.com/seda-suite\n" + "Use YosysHQ Tabby CAD Suite if you need Yosys+Verific.\n" + "https://www.yosyshq.com/\n" "\n" - "Contact office@symbioticeda.com for free evaluation\n" - "binaries of Symbiotic EDA Suite.\n"); + "Contact office@yosyshq.com for free evaluation\n" + "binaries of YosysHQ Tabby CAD Suite.\n"); } #endif } VerificPass; diff --git a/frontends/verilog/preproc.cc b/frontends/verilog/preproc.cc index ea23139e2..c451c4c20 100644 --- a/frontends/verilog/preproc.cc +++ b/frontends/verilog/preproc.cc @@ -321,7 +321,6 @@ struct define_body_t define_map_t::define_map_t() { add("YOSYS", "1"); - add(formal_mode ? "FORMAL" : "SYNTHESIS", "1"); } // We must define this destructor here (rather than relying on the default), because we need to @@ -391,13 +390,16 @@ static void input_file(std::istream &f, std::string filename) // the argument list); false if we finished with ','. static bool read_argument(std::string &dest) { + skip_spaces(); std::vector<char> openers; for (;;) { - skip_spaces(); std::string tok = next_token(true); if (tok == ")") { - if (openers.empty()) + if (openers.empty()) { + while (dest.size() && (dest.back() == ' ' || dest.back() == '\t')) + dest = dest.substr(0, dest.size() - 1); return true; + } if (openers.back() != '(') log_error("Mismatched brackets in macro argument: %c and %c.\n", openers.back(), tok[0]); diff --git a/frontends/verilog/verilog_frontend.cc b/frontends/verilog/verilog_frontend.cc index 2e9c9b2e2..5319a45ad 100644 --- a/frontends/verilog/verilog_frontend.cc +++ b/frontends/verilog/verilog_frontend.cc @@ -446,6 +446,9 @@ struct VerilogFrontend : public Frontend { } break; } + + defines_map.add(formal_mode ? "FORMAL" : "SYNTHESIS", "1"); + extra_args(f, filename, args, argidx); log_header(design, "Executing Verilog-2005 frontend: %s\n", filename.c_str()); diff --git a/frontends/verilog/verilog_parser.y b/frontends/verilog/verilog_parser.y index 678ce6c87..7fbd2aa27 100644 --- a/frontends/verilog/verilog_parser.y +++ b/frontends/verilog/verilog_parser.y @@ -282,7 +282,7 @@ static void rewriteAsMemoryNode(AstNode *node, AstNode *rangeNode) %token TOK_OR_ASSIGN TOK_XOR_ASSIGN TOK_AND_ASSIGN TOK_SUB_ASSIGN %type <ast> range range_or_multirange non_opt_range non_opt_multirange range_or_signed_int -%type <ast> wire_type expr basic_expr concat_list rvalue lvalue lvalue_concat_list +%type <ast> wire_type expr basic_expr concat_list rvalue lvalue lvalue_concat_list non_io_wire_type io_wire_type %type <string> opt_label opt_sva_label tok_prim_wrapper hierarchical_id hierarchical_type_id integral_number %type <string> type_name %type <ast> opt_enum_init enum_type struct_type non_wire_data_type @@ -619,26 +619,19 @@ non_opt_delay: delay: non_opt_delay | %empty; -wire_type: - { - astbuf3 = new AstNode(AST_WIRE); - current_wire_rand = false; - current_wire_const = false; - } wire_type_token_list { - $$ = astbuf3; - SET_RULE_LOC(@$, @2, @$); - }; +io_wire_type: + { astbuf3 = new AstNode(AST_WIRE); current_wire_rand = false; current_wire_const = false; } + wire_type_token_io wire_type_const_rand opt_wire_type_token wire_type_signedness + { $$ = astbuf3; SET_RULE_LOC(@$, @2, @$); }; -wire_type_token_list: - wire_type_token | - wire_type_token_list wire_type_token | - wire_type_token_io | - hierarchical_type_id { - astbuf3->is_custom_type = true; - astbuf3->children.push_back(new AstNode(AST_WIRETYPE)); - astbuf3->children.back()->str = *$1; - delete $1; - }; +non_io_wire_type: + { astbuf3 = new AstNode(AST_WIRE); current_wire_rand = false; current_wire_const = false; } + wire_type_const_rand wire_type_token wire_type_signedness + { $$ = astbuf3; SET_RULE_LOC(@$, @2, @$); }; + +wire_type: + io_wire_type | + non_io_wire_type; wire_type_token_io: TOK_INPUT { @@ -652,8 +645,32 @@ wire_type_token_io: astbuf3->is_output = true; }; +wire_type_signedness: + TOK_SIGNED { astbuf3->is_signed = true; } | + TOK_UNSIGNED { astbuf3->is_signed = false; } | + %empty; + +wire_type_const_rand: + TOK_RAND TOK_CONST { + current_wire_rand = true; + current_wire_const = true; + } | + TOK_CONST { + current_wire_const = true; + } | + TOK_RAND { + current_wire_rand = true; + } | + %empty; + +opt_wire_type_token: + wire_type_token | %empty; + wire_type_token: - TOK_WIRE { + hierarchical_type_id { + astbuf3->is_custom_type = true; + astbuf3->children.push_back(new AstNode(AST_WIRETYPE)); + astbuf3->children.back()->str = *$1; } | TOK_WOR { astbuf3->is_wor = true; @@ -661,20 +678,27 @@ wire_type_token: TOK_WAND { astbuf3->is_wand = true; } | + // wires + TOK_WIRE { + } | + TOK_WIRE logic_type { + } | + // regs TOK_REG { astbuf3->is_reg = true; } | - TOK_LOGIC { - astbuf3->is_logic = true; + TOK_VAR TOK_REG { + astbuf3->is_reg = true; } | + // logics TOK_VAR { astbuf3->is_logic = true; } | - TOK_INTEGER { - astbuf3->is_reg = true; - astbuf3->range_left = 31; - astbuf3->range_right = 0; - astbuf3->is_signed = true; + TOK_VAR logic_type { + astbuf3->is_logic = true; + } | + logic_type { + astbuf3->is_logic = true; } | TOK_GENVAR { astbuf3->type = AST_GENVAR; @@ -682,15 +706,15 @@ wire_type_token: astbuf3->is_signed = true; astbuf3->range_left = 31; astbuf3->range_right = 0; + }; + +logic_type: + TOK_LOGIC { } | - TOK_SIGNED { + TOK_INTEGER { + astbuf3->range_left = 31; + astbuf3->range_right = 0; astbuf3->is_signed = true; - } | - TOK_RAND { - current_wire_rand = true; - } | - TOK_CONST { - current_wire_const = true; }; non_opt_range: @@ -746,6 +770,7 @@ module_body: module_body module_body_stmt | /* the following line makes the generate..endgenrate keywords optional */ module_body gen_stmt | + module_body gen_block | module_body ';' | %empty; @@ -884,7 +909,11 @@ task_func_args: task_func_port: attr wire_type range { + bool prev_was_input = true; + bool prev_was_output = false; if (albuf) { + prev_was_input = astbuf1->is_input; + prev_was_output = astbuf1->is_output; delete astbuf1; if (astbuf2 != NULL) delete astbuf2; @@ -893,6 +922,12 @@ task_func_port: albuf = $1; astbuf1 = $2; astbuf2 = checkRange(astbuf1, $3); + if (!astbuf1->is_input && !astbuf1->is_output) { + if (!sv_mode) + frontend_verilog_yyerror("task/function argument direction missing"); + astbuf1->is_input = prev_was_input; + astbuf1->is_output = prev_was_output; + } } wire_name | { if (!astbuf1) { @@ -1456,10 +1491,10 @@ enum_base_type: type_atom type_signing | %empty { astbuf1->is_reg = true; addRange(astbuf1); } ; -type_atom: TOK_INTEGER { astbuf1->is_reg = true; addRange(astbuf1); } // 4-state signed - | TOK_INT { astbuf1->is_reg = true; addRange(astbuf1); } // 2-state signed - | TOK_SHORTINT { astbuf1->is_reg = true; addRange(astbuf1, 15, 0); } // 2-state signed - | TOK_BYTE { astbuf1->is_reg = true; addRange(astbuf1, 7, 0); } // 2-state signed +type_atom: TOK_INTEGER { astbuf1->is_reg = true; astbuf1->is_signed = true; addRange(astbuf1); } // 4-state signed + | TOK_INT { astbuf1->is_reg = true; astbuf1->is_signed = true; addRange(astbuf1); } // 2-state signed + | TOK_SHORTINT { astbuf1->is_reg = true; astbuf1->is_signed = true; addRange(astbuf1, 15, 0); } // 2-state signed + | TOK_BYTE { astbuf1->is_reg = true; astbuf1->is_signed = true; addRange(astbuf1, 7, 0); } // 2-state signed ; type_vec: TOK_REG { astbuf1->is_reg = true; } // unsigned @@ -1749,7 +1784,13 @@ wire_name: } rewriteAsMemoryNode(node, $2); } - if (current_function_or_task == NULL) { + if (current_function_or_task) { + if (node->is_input || node->is_output) + node->port_id = current_function_or_task_port_id++; + } else if (ast_stack.back()->type == AST_GENBLOCK) { + if (node->is_input || node->is_output) + frontend_verilog_yyerror("Cannot declare module port `%s' within a generate block.", $1->c_str()); + } else { if (do_not_require_port_stubs && (node->is_input || node->is_output) && port_stubs.count(*$1) == 0) { port_stubs[*$1] = ++port_counter; } @@ -1764,9 +1805,6 @@ wire_name: if (node->is_input || node->is_output) frontend_verilog_yyerror("Module port `%s' is not declared in module header.", $1->c_str()); } - } else { - if (node->is_input || node->is_output) - node->port_id = current_function_or_task_port_id++; } //FIXME: for some reason, TOK_ID has a location which always points to one column *after* the real last column... SET_AST_NODE_LOC(node, @1, @1); @@ -1793,7 +1831,7 @@ type_name: TOK_ID // first time seen ; typedef_decl: - TOK_TYPEDEF wire_type range type_name range_or_multirange ';' { + TOK_TYPEDEF non_io_wire_type range type_name range_or_multirange ';' { astbuf1 = $2; astbuf2 = checkRange(astbuf1, $3); if (astbuf2) @@ -2425,6 +2463,16 @@ behavioral_stmt: exitTypeScope(); if ($4 != NULL && $8 != NULL && *$4 != *$8) frontend_verilog_yyerror("Begin label (%s) and end label (%s) don't match.", $4->c_str()+1, $8->c_str()+1); + AstNode *node = ast_stack.back(); + // In SystemVerilog, unnamed blocks with block item declarations + // create an implicit hierarchy scope + if (sv_mode && node->str.empty()) + for (const AstNode* child : node->children) + if (child->type == AST_WIRE || child->type == AST_MEMORY || child->type == AST_PARAMETER + || child->type == AST_LOCALPARAM || child->type == AST_TYPEDEF) { + node->str = "$unnamed_block$" + std::to_string(autoidx++); + break; + } SET_AST_NODE_LOC(ast_stack.back(), @2, @8); delete $4; delete $8; @@ -2439,6 +2487,7 @@ behavioral_stmt: ast_stack.back()->children.push_back($7); } ';' simple_behavioral_stmt ')' { AstNode *block = new AstNode(AST_BLOCK); + block->str = "$for_loop$" + std::to_string(autoidx++); ast_stack.back()->children.push_back(block); ast_stack.push_back(block); } behavioral_stmt { @@ -2688,6 +2737,7 @@ single_arg: module_gen_body: module_gen_body gen_stmt_or_module_body_stmt | + module_gen_body gen_block | %empty; gen_stmt_or_module_body_stmt: @@ -2713,12 +2763,7 @@ gen_stmt: ast_stack.back()->children.push_back(node); ast_stack.push_back(node); ast_stack.back()->children.push_back($3); - AstNode *block = new AstNode(AST_GENBLOCK); - ast_stack.back()->children.push_back(block); - ast_stack.push_back(block); - } gen_stmt_block { - ast_stack.pop_back(); - } opt_gen_else { + } gen_stmt_block opt_gen_else { SET_AST_NODE_LOC(ast_stack.back(), @1, @7); ast_stack.pop_back(); } | @@ -2731,6 +2776,18 @@ gen_stmt: SET_AST_NODE_LOC(ast_stack.back(), @1, @7); ast_stack.pop_back(); } | + TOK_MSG_TASKS { + AstNode *node = new AstNode(AST_TECALL); + node->str = *$1; + delete $1; + ast_stack.back()->children.push_back(node); + ast_stack.push_back(node); + } opt_arg_list ';'{ + SET_AST_NODE_LOC(ast_stack.back(), @1, @3); + ast_stack.pop_back(); + }; + +gen_block: TOK_BEGIN { enterTypeScope(); } opt_label { @@ -2740,22 +2797,15 @@ gen_stmt: ast_stack.push_back(node); } module_gen_body TOK_END opt_label { exitTypeScope(); + if ($3 != NULL && $7 != NULL && *$3 != *$7) + frontend_verilog_yyerror("Begin label (%s) and end label (%s) don't match.", $3->c_str()+1, $7->c_str()+1); delete $3; delete $7; SET_AST_NODE_LOC(ast_stack.back(), @1, @7); ast_stack.pop_back(); - } | - TOK_MSG_TASKS { - AstNode *node = new AstNode(AST_TECALL); - node->str = *$1; - delete $1; - ast_stack.back()->children.push_back(node); - ast_stack.push_back(node); - } opt_arg_list ';'{ - SET_AST_NODE_LOC(ast_stack.back(), @1, @3); - ast_stack.pop_back(); }; +// result is wrapped in a genblock only if necessary gen_stmt_block: { AstNode *node = new AstNode(AST_GENBLOCK); @@ -2764,7 +2814,7 @@ gen_stmt_block: } gen_stmt_or_module_body_stmt { SET_AST_NODE_LOC(ast_stack.back(), @2, @2); ast_stack.pop_back(); - }; + } | gen_block; opt_gen_else: TOK_ELSE gen_stmt_block | %empty %prec FAKE_THEN; diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc index a9f585616..1faf376e7 100644 --- a/kernel/rtlil.cc +++ b/kernel/rtlil.cc @@ -1826,7 +1826,7 @@ void RTLIL::Module::remove(const pool<RTLIL::Wire*> &wires) sig.pack(); for (auto &c : sig.chunks_) if (c.wire != NULL && wires_p->count(c.wire)) { - c.wire = module->addWire(NEW_ID, c.width); + c.wire = module->addWire(stringf("$delete_wire$%d", autoidx++), c.width); c.offset = 0; } } diff --git a/kernel/rtlil.h b/kernel/rtlil.h index a03e8933c..4dad3c428 100644 --- a/kernel/rtlil.h +++ b/kernel/rtlil.h @@ -334,6 +334,10 @@ namespace RTLIL return compare(size()-len, len, suffix) == 0; } + bool contains(const char* str) const { + return strstr(c_str(), str); + } + size_t size() const { return strlen(c_str()); } @@ -376,7 +380,7 @@ namespace RTLIL bool in(const std::string &rhs) const { return *this == rhs; } bool in(const pool<IdString> &rhs) const { return rhs.count(*this) != 0; } - bool isPublic() { return begins_with("\\"); } + bool isPublic() const { return begins_with("\\"); } }; namespace ID { diff --git a/kernel/timinginfo.h b/kernel/timinginfo.h index d818e580b..eba3386d6 100644 --- a/kernel/timinginfo.h +++ b/kernel/timinginfo.h @@ -88,10 +88,10 @@ struct TimingInfo auto src = cell->getPort(ID::SRC); auto dst = cell->getPort(ID::DST); for (const auto &c : src.chunks()) - if (!c.wire->port_input) + if (!c.wire || !c.wire->port_input) log_error("Module '%s' contains specify cell '%s' where SRC '%s' is not a module input.\n", log_id(module), log_id(cell), log_signal(src)); for (const auto &c : dst.chunks()) - if (!c.wire->port_output) + if (!c.wire || !c.wire->port_output) log_error("Module '%s' contains specify cell '%s' where DST '%s' is not a module output.\n", log_id(module), log_id(cell), log_signal(dst)); int rise_max = cell->getParam(ID::T_RISE_MAX).as_int(); int fall_max = cell->getParam(ID::T_FALL_MAX).as_int(); diff --git a/kernel/yosys.h b/kernel/yosys.h index ab6eb5f8c..43aecdbc8 100644 --- a/kernel/yosys.h +++ b/kernel/yosys.h @@ -93,6 +93,8 @@ extern Tcl_Obj *Tcl_NewIntObj(int intValue); extern Tcl_Obj *Tcl_NewListObj(int objc, Tcl_Obj *const objv[]); extern Tcl_Obj *Tcl_ObjSetVar2(Tcl_Interp *interp, Tcl_Obj *part1Ptr, Tcl_Obj *part2Ptr, Tcl_Obj *newValuePtr, int flags); # endif +# undef CONST +# undef INLINE #endif #ifdef _WIN32 @@ -119,8 +121,9 @@ extern Tcl_Obj *Tcl_ObjSetVar2(Tcl_Interp *interp, Tcl_Obj *part1Ptr, Tcl_Obj *p # define fileno _fileno # endif -// mingw and msvc include `wingdi.h` which defines a TRANSPARENT macro -// that conflicts with X(TRANSPARENT) entry in kernel/constids.inc +// The following defines conflict with our identifiers: +# undef CONST +// `wingdi.h` defines a TRANSPARENT macro that conflicts with X(TRANSPARENT) entry in kernel/constids.inc # undef TRANSPARENT #endif diff --git a/manual/CHAPTER_Overview.tex b/manual/CHAPTER_Overview.tex index ed8b4cd49..83db5aac7 100644 --- a/manual/CHAPTER_Overview.tex +++ b/manual/CHAPTER_Overview.tex @@ -230,6 +230,7 @@ generated twice. For modules with only a few parameters, a name directly contain is generated instead of a hash string.) \subsection{RTLIL::Cell and RTLIL::Wire} +\label{sec:rtlil_cell_wire} A module contains zero to many RTLIL::Cell and RTLIL::Wire objects. Objects of these types are used to model netlists. Usually the goal of all synthesis efforts is to convert @@ -275,6 +276,7 @@ The connections of ports to wires are coded by assigning an RTLIL::SigSpec to each cell port. The RTLIL::SigSpec data type is described in the next section. \subsection{RTLIL::SigSpec} +\label{sec:rtlil_sigspec} A ``signal'' is everything that can be applied to a cell port. I.e. @@ -295,6 +297,7 @@ RTLIL::SigSpec objects. Such pairs are needed in different locations. Therefore the type name RTLIL::SigSig was defined for such a pair. \subsection{RTLIL::Process} +\label{sec:rtlil_process} When a high-level HDL frontend processes behavioural code it splits it up into data path logic (e.g.~the expression {\tt a + b} is replaced by the output of an @@ -444,6 +447,7 @@ pass calls a series of other passes that together perform this conversion in a w for most synthesis tasks. \subsection{RTLIL::Memory} +\label{sec:rtlil_memory} For every array (memory) in the HDL code an RTLIL::Memory object is created. A memory object has the following properties: diff --git a/manual/CHAPTER_TextRtlil.tex b/manual/CHAPTER_TextRtlil.tex new file mode 100644 index 000000000..243b56a87 --- /dev/null +++ b/manual/CHAPTER_TextRtlil.tex @@ -0,0 +1,299 @@ +\chapter{RTLIL Text Representation} +\label{chapter:textrtlil} + +% Stolen from stackexchange: calculate indent based on given keyword, +% with some nice hrules added in. +\newlength{\myl} + +\newenvironment{indentgrammar}[1] + {\vspace{0.5cm}\hrule + \setlength{\myl}{\widthof{#1}+2em} + \grammarindent\the\myl + \begin{grammar}} + {\end{grammar} + \hrule} + +This appendix documents the text representation of RTLIL in extended Backus-Naur form (EBNF). + +The grammar is not meant to represent semantic limitations. That is, the grammar is ``permissive'', and later stages of processing perform more rigorous checks. + +The grammar is also not meant to represent the exact grammar used in the RTLIL frontend, since that grammar is specific to processing by lex and yacc, is even more permissive, and is somewhat less understandable than simple EBNF notation. + +Finally, note that all statements (rules ending in \texttt{-stmt}) terminate in an end-of-line. Because of this, a statement cannot be broken into multiple lines. + +\section{Lexical elements} + +\subsection{Characters} + +An RTLIL file is a stream of bytes. Strictly speaking, a ``character'' in an RTLIL file is a single byte. The lexer treats multi-byte encoded characters as consecutive single-byte characters. While other encodings \textit{may} work, UTF-8 is known to be safe to use. Byte order marks at the beginning of the file will cause an error. + +ASCII spaces (32) and tabs (9) separate lexer tokens. + +A \texttt{nonws} character, used in identifiers, is any character whose encoding consists solely of bytes above ASCII space (32). + +An \texttt{eol} is one or more consecutive ASCII newlines (10) and carriage returns (13). + +\subsection{Identifiers} + +There are two types of identifiers in RTLIL: + +\begin{itemize} + \item Publically visible identifiers + \item Auto-generated identifiers +\end{itemize} + +\begin{indentgrammar}{<autogen-id>} +<id> ::= <public-id> | <autogen-id> + +<public-id> ::= "\textbackslash" <nonws>$+$ + +<autogen-id> ::= "\textdollar" <nonws>$+$ +\end{indentgrammar} + +\subsection{Values} + +A \textit{value} consists of a width in bits and a bit representation, most significant bit first. Bits may be any of: +\begin{itemize} + \item \texttt{0}: A logic zero value + \item \texttt{1}: A logic one value + \item \texttt{x}: An unknown logic value (or don't care in case patterns) + \item \texttt{z}: A high-impedance value (or don't care in case patterns) + \item \texttt{m}: A marked bit (internal use only) + \item \texttt{-}: A don't care value +\end{itemize} + +An \textit{integer} is simply a signed integer value in decimal format. \textbf{Warning:} Integer constants are limited to 32 bits. That is, they may only be in the range $[-2147483648, 2147483648)$. Integers outside this range will result in an error. + +\begin{indentgrammar}{<binary-digit>} +<value> ::= <decimal-digit>$+$ \texttt{\textbf{'}} <binary-digit>$*$ + +<decimal-digit> ::= "0" | "1" | "2" | "3" | "4" | "5" | "6" | "7" | "8" | "9" + +<binary-digit> ::= "0" | "1" | "x" | "z" | "m" | "-" + +<integer> ::= "-"$?$ <decimal-digit>$+$ +\end{indentgrammar} + +\subsection{Strings} + +A string is a series of characters delimited by double-quote characters. Within a string, any character except ASCII NUL (0) may be used. In addition, certain escapes can be used: + +\begin{itemize} + \item \texttt{\textbackslash n}: A newline + \item \texttt{\textbackslash t}: A tab + \item \texttt{\textbackslash \textit{ooo}}: A character specified as a one, two, or three digit octal value +\end{itemize} + +All other characters may be escaped by a backslash, and become the following character. Thus: + +\begin{itemize} + \item \texttt{\textbackslash \textbackslash}: A backslash + \item \texttt{\textbackslash ''}: A double-quote + \item \texttt{\textbackslash r}: An 'r' character +\end{itemize} + +\subsection{Comments} + +A comment starts with a \texttt{\textbf{\#}} character and proceeds to the end of the line. All comments are ignored. + +\section{File} + +A file consists of an optional autoindex statement followed by zero or more modules. + +\begin{indentgrammar}{<design>} +<file> ::= <autoidx-stmt>$?$ <module>* +\end{indentgrammar} + +\subsection{Autoindex statements} + +The autoindex statement sets the global autoindex value used by Yosys when it needs to generate a unique name, e.g. \texttt{\textdollar{}flatten\textdollar{}N}. The N part is filled with the value of the global autoindex value, which is subsequently incremented. This global has to be dumped into RTLIL, otherwise e.g. dumping and running a pass would have different properties than just running a pass on a warm design. + +\begin{indentgrammar}{<autoidx-stmt>} +<autoidx-stmt> ::= "autoidx" <integer> <eol> +\end{indentgrammar} + +\subsection{Modules} + +Declares a module, with zero or more attributes, consisting of zero or more wires, memories, cells, processes, and connections. + +\begin{indentgrammar}{<module-body-stmt>} +<module> ::= <attr-stmt>$*$ <module-stmt> <module-body> <module-end-stmt> + +<module-stmt> ::= "module" <id> <eol> + +<module-body> ::= +(<param-stmt> + \alt <wire> + \alt <memory> + \alt <cell> + \alt <process> + \alt <conn-stmt>)$*$ + +<param-stmt> ::= "parameter" <id> <constant>$?$ <eol> + +<constant> ::= <value> | <integer> | <string> + +<module-end-stmt> ::= "end" <eol> +\end{indentgrammar} + +\subsection{Attribute statements} + +Declares an attribute with the given identifier and value. + +\begin{indentgrammar}{<attr-stmt>} +<attr-stmt> ::= "attribute" <id> <constant> <eol> +\end{indentgrammar} + +\subsection{Signal specifications} + +A signal is anything that can be applied to a cell port, i.e. a constant value, all bits or a selection of bits from a wire, or concatenations of those. + +\textbf{Warning:} When an integer constant is a sigspec, it is always 32 bits wide, 2's complement. For example, a constant of $-1$ is the same as \texttt{32'11111111111111111111111111111111}, while a constant of $1$ is the same as \texttt{32'1}. + +See Sec.~\ref{sec:rtlil_sigspec} for an overview of signal specifications. + +\begin{indentgrammar}{<sigspec>} +<sigspec> ::= +<constant> + \alt <wire-id> + \alt <sigspec> "[" <integer> (":" <integer>)$?$ "]" + \alt "\{" <sigspec>$*$ "\}" +\end{indentgrammar} + +\subsection{Connections} + +Declares a connection between the given signals. + +\begin{indentgrammar}{<conn-stmt>} +<conn-stmt> ::= "connect" <sigspec> <sigspec> <eol> +\end{indentgrammar} + +\subsection{Wires} + +Declares a wire, with zero or more attributes, with the given identifier and options in the enclosing module. + +See Sec.~\ref{sec:rtlil_cell_wire} for an overview of wires. + +\begin{indentgrammar}{<wire-option>} +<wire> ::= <attr-stmt>$*$ <wire-stmt> + +<wire-stmt> ::= "wire" <wire-option>$*$ <wire-id> <eol> + +<wire-id> ::= <id> + +<wire-option> ::= +"width" <integer> + \alt "offset" <integer> + \alt "input" <integer> + \alt "output" <integer> + \alt "inout" <integer> + \alt "upto" + \alt "signed" +\end{indentgrammar} + +\subsection{Memories} + +Declares a memory, with zero or more attributes, with the given identifier and options in the enclosing module. + +See Sec.~\ref{sec:rtlil_memory} for an overview of memory cells, and Sec.~\ref{sec:memcells} for details about memory cell types. + +\begin{indentgrammar}{<memory-option>} +<memory> ::= <attr-stmt>$*$ <memory-stmt> + +<memory-stmt> ::= "memory" <memory-option>$*$ <id> <eol> + +<memory-option> ::= +"width" <integer> + \alt "size" <integer> + \alt "offset" <integer> +\end{indentgrammar} + +\subsection{Cells} + +Declares a cell, with zero or more attributes, with the given identifier and type in the enclosing module. + +Cells perform functions on input signals. See Chap.~\ref{chapter:celllib} for a detailed list of cell types. + +\begin{indentgrammar}{<cell-body-stmt>} +<cell> ::= <attr-stmt>$*$ <cell-stmt> <cell-body-stmt>$*$ <cell-end-stmt> + +<cell-stmt> ::= "cell" <cell-id> <cell-type> <eol> + +<cell-id> ::= <id> + +<cell-type> ::= <id> + +<cell-body-stmt> ::= +"parameter" ("signed" | "real")$?$ <id> <constant> <eol> + \alt "connect" <id> <sigspec> <eol> + +<cell-end-stmt> ::= "end" <eol> +\end{indentgrammar} + +\subsection{Processes} + +Declares a process, with zero or more attributes, with the given identifier in the enclosing module. The body of a process consists of zero or more assignments, exactly one switch, and zero or more syncs. + +See Sec.~\ref{sec:rtlil_process} for an overview of processes. + +\begin{indentgrammar}{<switch-end-stmt>} +<process> ::= <attr-stmt>$*$ <proc-stmt> <process-body> <proc-end-stmt> + +<proc-stmt> ::= "process" <id> <eol> + +<process-body> ::= <assign-stmt>$*$ <switch> <assign-stmt>$*$ <sync>$*$ + +<assign-stmt> ::= "assign" <dest-sigspec> <src-sigspec> <eol> + +<dest-sigspec> ::= <sigspec> + +<src-sigspec> ::= <sigspec> + +<proc-end-stmt> ::= "end" <eol> + +\end{indentgrammar} + +\subsection{Switches} + +Switches test a signal for equality against a list of cases. Each case specifies a comma-separated list of signals to check against. If there are no signals in the list, then the case is the default case. The body of a case consists of zero or more switches and assignments. Both switches and cases may have zero or more attributes. + +\begin{indentgrammar}{<switch-end-stmt>} +<switch> ::= <switch-stmt> <case>$*$ <switch-end-stmt> + +<switch-stmt> := <attr-stmt>$*$ "switch" <sigspec> <eol> + +<case> ::= <attr-stmt>$*$ <case-stmt> <case-body> + +<case-stmt> ::= "case" <compare>$?$ <eol> + +<compare> ::= <sigspec> ("," <sigspec>)$*$ + +<case-body> ::= (<switch> | <assign-stmt>)$*$ + +<switch-end-stmt> ::= "end" <eol> +\end{indentgrammar} + +\subsection{Syncs} + +Syncs update signals with other signals when an event happens. Such an event may be: + +\begin{itemize} + \item An edge or level on a signal + \item Global clock ticks + \item Initialization + \item Always +\end{itemize} + +\begin{indentgrammar}{<dest-sigspec>} +<sync> ::= <sync-stmt> <update-stmt>$*$ + +<sync-stmt> ::= +"sync" <sync-type> <sigspec> <eol> + \alt "sync" "global" <eol> + \alt "sync" "init" <eol> + \alt "sync" "always" <eol> + +<sync-type> ::= "low" | "high" | "posedge" | "negedge" | "edge" + +<update-stmt> ::= "update" <dest-sigspec> <src-sigspec> <eol> +\end{indentgrammar} diff --git a/manual/manual.tex b/manual/manual.tex index 75f087eca..dac8b1000 100644 --- a/manual/manual.tex +++ b/manual/manual.tex @@ -75,6 +75,9 @@ bookmarksopen=false% \usetikzlibrary{through} \usetikzlibrary{shapes.geometric} +\usepackage{calc} +\usepackage[nounderscore]{syntax} + \lstset{basicstyle=\ttfamily} \def\B#1{{\tt\textbackslash{}#1}} @@ -214,6 +217,7 @@ YOSYS & Yosys Open SYnthesis Suite \\ \label{commandref} \input{command-reference-manual} +\include{CHAPTER_TextRtlil} \include{CHAPTER_Appnotes} % \include{CHAPTER_StateOfTheArt} diff --git a/passes/cmds/bugpoint.cc b/passes/cmds/bugpoint.cc index 81d7a34bb..da81e7f09 100644 --- a/passes/cmds/bugpoint.cc +++ b/passes/cmds/bugpoint.cc @@ -30,7 +30,7 @@ struct BugpointPass : public Pass { { // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| log("\n"); - log(" bugpoint [options] -script <filename>\n"); + log(" bugpoint [options] [-script <filename> | -command \"<command>\"]\n"); log("\n"); log("This command minimizes the current design that is known to crash Yosys with the\n"); log("given script into a smaller testcase. It does this by removing an arbitrary part\n"); @@ -39,13 +39,13 @@ struct BugpointPass : public Pass { log("still causes a crash. Once this command finishes, it replaces the current design\n"); log("with the smallest testcase it was able to produce.\n"); log("\n"); - log(" -script <filename>\n"); - log(" use this script to crash Yosys. required.\n"); + log(" -script <filename> | -command \"<command>\"\n"); + log(" use this script file or command to crash Yosys. required.\n"); log("\n"); log(" -yosys <filename>\n"); log(" use this Yosys binary. if not specified, `yosys` is used.\n"); log("\n"); - log(" -grep <string>\n"); + log(" -grep \"<string>\"\n"); log(" only consider crashes that place this string in the log file.\n"); log("\n"); log(" -fast\n"); @@ -77,6 +77,10 @@ struct BugpointPass : public Pass { log(" -connections\n"); log(" try to reconnect ports to 'x.\n"); log("\n"); + log(" -processes\n"); + log(" try to remove processes. processes with a (* bugpoint_keep *) attribute\n"); + log(" will be skipped.\n"); + log("\n"); log(" -assigns\n"); log(" try to remove process assigns from cases.\n"); log("\n"); @@ -85,7 +89,7 @@ struct BugpointPass : public Pass { log("\n"); } - bool run_yosys(RTLIL::Design *design, string yosys_cmd, string script) + bool run_yosys(RTLIL::Design *design, string yosys_cmd, string yosys_arg) { design->sort(); @@ -93,7 +97,7 @@ struct BugpointPass : public Pass { RTLIL_BACKEND::dump_design(f, design, /*only_selected=*/false, /*flag_m=*/true, /*flag_n=*/false); f.close(); - string yosys_cmdline = stringf("%s -qq -L bugpoint-case.log -s %s bugpoint-case.il", yosys_cmd.c_str(), script.c_str()); + string yosys_cmdline = stringf("%s -qq -L bugpoint-case.log %s bugpoint-case.il", yosys_cmd.c_str(), yosys_arg.c_str()); return run_command(yosys_cmdline) == 0; } @@ -102,6 +106,9 @@ struct BugpointPass : public Pass { if (grep.empty()) return true; + if (grep.size() > 2 && grep.front() == '"' && grep.back() == '"') + grep = grep.substr(1, grep.size() - 2); + std::ifstream f("bugpoint-case.log"); while (!f.eof()) { @@ -129,7 +136,7 @@ struct BugpointPass : public Pass { return design_copy; } - RTLIL::Design *simplify_something(RTLIL::Design *design, int &seed, bool stage2, bool modules, bool ports, bool cells, bool connections, bool assigns, bool updates) + RTLIL::Design *simplify_something(RTLIL::Design *design, int &seed, bool stage2, bool modules, bool ports, bool cells, bool connections, bool processes, bool assigns, bool updates, bool wires) { RTLIL::Design *design_copy = new RTLIL::Design; for (auto module : design->modules()) @@ -194,7 +201,6 @@ struct BugpointPass : public Pass { if (mod->get_blackbox_attribute()) continue; - Cell *removed_cell = nullptr; for (auto cell : mod->cells()) { @@ -257,6 +263,33 @@ struct BugpointPass : public Pass { } } } + if (processes) + { + for (auto mod : design_copy->modules()) + { + if (mod->get_blackbox_attribute()) + continue; + + RTLIL::IdString removed_process; + for (auto process : mod->processes) + { + if (process.second->get_bool_attribute(ID::bugpoint_keep)) + continue; + + if (index++ == seed) + { + log_header(design, "Trying to remove process %s.%s.\n", log_id(mod), log_id(process.first)); + removed_process = process.first; + break; + } + } + if (!removed_process.empty()) { + delete mod->processes[removed_process]; + mod->processes.erase(removed_process); + return design_copy; + } + } + } if (assigns) { for (auto mod : design_copy->modules()) @@ -310,14 +343,43 @@ struct BugpointPass : public Pass { } } } + if (wires) + { + for (auto mod : design_copy->modules()) + { + if (mod->get_blackbox_attribute()) + continue; + + Wire *removed_wire = nullptr; + for (auto wire : mod->wires()) + { + if (wire->get_bool_attribute(ID::bugpoint_keep)) + continue; + + if (wire->name.begins_with("$delete_wire")) + continue; + + if (index++ == seed) + { + log_header(design, "Trying to remove wire %s.%s.\n", log_id(mod), log_id(wire)); + removed_wire = wire; + break; + } + } + if (removed_wire) { + mod->remove({removed_wire}); + return design_copy; + } + } + } return nullptr; } void execute(std::vector<std::string> args, RTLIL::Design *design) override { - string yosys_cmd = "yosys", script, grep; + string yosys_cmd = "yosys", yosys_arg, grep; bool fast = false, clean = false; - bool modules = false, ports = false, cells = false, connections = false, assigns = false, updates = false, has_part = false; + bool modules = false, ports = false, cells = false, connections = false, processes = false, assigns = false, updates = false, wires = false, has_part = false; log_header(design, "Executing BUGPOINT pass (minimize testcases).\n"); log_push(); @@ -330,7 +392,15 @@ struct BugpointPass : public Pass { continue; } if (args[argidx] == "-script" && argidx + 1 < args.size()) { - script = args[++argidx]; + if (!yosys_arg.empty()) + log_cmd_error("A -script or -command option can be only provided once!\n"); + yosys_arg = stringf("-s %s", args[++argidx].c_str()); + continue; + } + if (args[argidx] == "-command" && argidx + 1 < args.size()) { + if (!yosys_arg.empty()) + log_cmd_error("A -script or -command option can be only provided once!\n"); + yosys_arg = stringf("-p %s", args[++argidx].c_str()); continue; } if (args[argidx] == "-grep" && argidx + 1 < args.size()) { @@ -365,6 +435,11 @@ struct BugpointPass : public Pass { has_part = true; continue; } + if (args[argidx] == "-processes") { + processes = true; + has_part = true; + continue; + } if (args[argidx] == "-assigns") { assigns = true; has_part = true; @@ -375,12 +450,17 @@ struct BugpointPass : public Pass { has_part = true; continue; } + if (args[argidx] == "-wires") { + wires = true; + has_part = true; + continue; + } break; } extra_args(args, argidx, design); - if (script.empty()) - log_cmd_error("Missing -script option.\n"); + if (yosys_arg.empty()) + log_cmd_error("Missing -script or -command option.\n"); if (!has_part) { @@ -388,16 +468,18 @@ struct BugpointPass : public Pass { ports = true; cells = true; connections = true; + processes = true; assigns = true; updates = true; + wires = true; } if (!design->full_selection()) log_cmd_error("This command only operates on fully selected designs!\n"); RTLIL::Design *crashing_design = clean_design(design, clean); - if (run_yosys(crashing_design, yosys_cmd, script)) - log_cmd_error("The provided script file and Yosys binary do not crash on this design!\n"); + if (run_yosys(crashing_design, yosys_cmd, yosys_arg)) + log_cmd_error("The provided script file or command and Yosys binary do not crash on this design!\n"); if (!check_logfile(grep)) log_cmd_error("The provided grep string is not found in the log file!\n"); @@ -405,7 +487,7 @@ struct BugpointPass : public Pass { bool found_something = false, stage2 = false; while (true) { - if (RTLIL::Design *simplified = simplify_something(crashing_design, seed, stage2, modules, ports, cells, connections, assigns, updates)) + if (RTLIL::Design *simplified = simplify_something(crashing_design, seed, stage2, modules, ports, cells, connections, processes, assigns, updates, wires)) { simplified = clean_design(simplified, fast, /*do_delete=*/true); @@ -413,12 +495,12 @@ struct BugpointPass : public Pass { if (clean) { RTLIL::Design *testcase = clean_design(simplified); - crashes = !run_yosys(testcase, yosys_cmd, script); + crashes = !run_yosys(testcase, yosys_cmd, yosys_arg); delete testcase; } else { - crashes = !run_yosys(simplified, yosys_cmd, script); + crashes = !run_yosys(simplified, yosys_cmd, yosys_arg); } if (crashes && check_logfile(grep)) diff --git a/passes/cmds/plugin.cc b/passes/cmds/plugin.cc index 3ed19497d..a94769bcd 100644 --- a/passes/cmds/plugin.cc +++ b/passes/cmds/plugin.cc @@ -93,7 +93,11 @@ void load_plugin(std::string filename, std::vector<std::string> aliases) #else void load_plugin(std::string, std::vector<std::string>) { - log_error("This version of yosys is built without plugin support.\n"); + log_error( + "\n This version of Yosys cannot load plugins at runtime.\n" + " Some plugins may have been included at build time.\n" + " Use option `-H' to see the available built-in and plugin commands.\n" + ); } #endif diff --git a/passes/cmds/scc.cc b/passes/cmds/scc.cc index 8e7f3f990..7aa9a484f 100644 --- a/passes/cmds/scc.cc +++ b/passes/cmds/scc.cc @@ -37,7 +37,7 @@ struct SccWorker RTLIL::Design *design; RTLIL::Module *module; SigMap sigmap; - CellTypes ct; + CellTypes ct, specifyCells; std::set<RTLIL::Cell*> workQueue; std::map<RTLIL::Cell*, std::set<RTLIL::Cell*>> cellToNextCell; @@ -100,7 +100,7 @@ struct SccWorker } } - SccWorker(RTLIL::Design *design, RTLIL::Module *module, bool nofeedbackMode, bool allCellTypes, int maxDepth) : + SccWorker(RTLIL::Design *design, RTLIL::Module *module, bool nofeedbackMode, bool allCellTypes, bool specifyMode, int maxDepth) : design(design), module(module), sigmap(module) { if (module->processes.size() > 0) { @@ -115,6 +115,18 @@ struct SccWorker ct.setup_stdcells(); } + // Discover boxes with specify rules in them, for special handling. + if (specifyMode) { + for (auto mod : design->modules()) + if (mod->get_blackbox_attribute(false)) + for (auto cell : mod->cells()) + if (cell->type == ID($specify2)) + { + specifyCells.setup_module(mod); + break; + } + } + SigPool selectedSignals; SigSet<RTLIL::Cell*> sigToNextCells; @@ -129,29 +141,52 @@ struct SccWorker if (!design->selected(module, cell)) continue; - if (!allCellTypes && !ct.cell_known(cell->type)) + if (!allCellTypes && !ct.cell_known(cell->type) && !specifyCells.cell_known(cell->type)) continue; workQueue.insert(cell); RTLIL::SigSpec inputSignals, outputSignals; - for (auto &conn : cell->connections()) - { - bool isInput = true, isOutput = true; + if (specifyCells.cell_known(cell->type)) { + // Use specify rules of the type `(X => Y) = NN` to look for asynchronous paths in boxes. + for (auto subcell : design->module(cell->type)->cells()) + { + if (subcell->type != ID($specify2)) + continue; - if (ct.cell_known(cell->type)) { - isInput = ct.cell_input(cell->type, conn.first); - isOutput = ct.cell_output(cell->type, conn.first); + for (auto bit : subcell->getPort(ID::SRC)) + { + if (!bit.wire || !cell->hasPort(bit.wire->name)) + continue; + inputSignals.append(sigmap(cell->getPort(bit.wire->name))); + } + + for (auto bit : subcell->getPort(ID::DST)) + { + if (!bit.wire || !cell->hasPort(bit.wire->name)) + continue; + outputSignals.append(sigmap(cell->getPort(bit.wire->name))); + } } + } else { + for (auto &conn : cell->connections()) + { + bool isInput = true, isOutput = true; + + if (ct.cell_known(cell->type)) { + isInput = ct.cell_input(cell->type, conn.first); + isOutput = ct.cell_output(cell->type, conn.first); + } - RTLIL::SigSpec sig = selectedSignals.extract(sigmap(conn.second)); - sig.sort_and_unify(); + RTLIL::SigSpec sig = selectedSignals.extract(sigmap(conn.second)); + sig.sort_and_unify(); - if (isInput) - inputSignals.append(sig); - if (isOutput) - outputSignals.append(sig); + if (isInput) + inputSignals.append(sig); + if (isOutput) + outputSignals.append(sig); + } } inputSignals.sort_and_unify(); @@ -228,7 +263,7 @@ struct SccPass : public Pass { log("design.\n"); log("\n"); log(" -expect <num>\n"); - log(" expect to find exactly <num> SSCs. A different number of SSCs will\n"); + log(" expect to find exactly <num> SCCs. A different number of SCCs will\n"); log(" produce an error.\n"); log("\n"); log(" -max_depth <num>\n"); @@ -254,6 +289,9 @@ struct SccPass : public Pass { log(" replace the current selection with a selection of all cells and wires\n"); log(" that are part of a found logic loop\n"); log("\n"); + log(" -specify\n"); + log(" examine specify rules to detect logic loops in whitebox/blackbox cells\n"); + log("\n"); } void execute(std::vector<std::string> args, RTLIL::Design *design) override { @@ -261,6 +299,7 @@ struct SccPass : public Pass { bool allCellTypes = false; bool selectMode = false; bool nofeedbackMode = false; + bool specifyMode = false; int maxDepth = -1; int expect = -1; @@ -293,6 +332,10 @@ struct SccPass : public Pass { selectMode = true; continue; } + if (args[argidx] == "-specify") { + specifyMode = true; + continue; + } break; } int origSelectPos = design->selection_stack.size() - 1; @@ -303,7 +346,7 @@ struct SccPass : public Pass { for (auto mod : design->selected_modules()) { - SccWorker worker(design, mod, nofeedbackMode, allCellTypes, maxDepth); + SccWorker worker(design, mod, nofeedbackMode, allCellTypes, specifyMode, maxDepth); if (!setAttr.empty()) { diff --git a/passes/hierarchy/hierarchy.cc b/passes/hierarchy/hierarchy.cc index 225e1feae..3372687e1 100644 --- a/passes/hierarchy/hierarchy.cc +++ b/passes/hierarchy/hierarchy.cc @@ -1233,14 +1233,18 @@ struct HierarchyPass : public Pass { { int n = GetSize(conn.second) - GetSize(w); if (!w->port_input && w->port_output) - module->connect(sig.extract(GetSize(w), n), Const(0, n)); + { + RTLIL::SigSpec out = sig.extract(0, GetSize(w)); + out.extend_u0(GetSize(sig), w->is_signed); + module->connect(sig.extract(GetSize(w), n), out.extract(GetSize(w), n)); + } sig.remove(GetSize(w), n); } else { int n = GetSize(w) - GetSize(conn.second); if (w->port_input && !w->port_output) - sig.append(Const(0, n)); + sig.extend_u0(GetSize(w), sig.is_wire() && sig.as_wire()->is_signed); else sig.append(module->addWire(NEW_ID, n)); } diff --git a/passes/opt/opt_lut.cc b/passes/opt/opt_lut.cc index 07a91af8a..623101016 100644 --- a/passes/opt/opt_lut.cc +++ b/passes/opt/opt_lut.cc @@ -277,12 +277,13 @@ struct OptLutWorker module->connect(lut_output, value); sigmap.add(lut_output, value); - module->remove(lut); luts.erase(lut); luts_arity.erase(lut); luts_dlogics.erase(lut); luts_dlogic_inputs.erase(lut); + module->remove(lut); + eliminated_count++; if (limit > 0) limit--; @@ -493,11 +494,12 @@ struct OptLutWorker luts_arity[lutM] = lutM_arity; luts.erase(lutR); luts_arity.erase(lutR); - lutR->module->remove(lutR); worklist.insert(lutM); worklist.erase(lutR); + lutR->module->remove(lutR); + combined_count++; if (limit > 0) limit--; diff --git a/passes/opt/opt_share.cc b/passes/opt/opt_share.cc index 53296699c..62a478673 100644 --- a/passes/opt/opt_share.cc +++ b/passes/opt/opt_share.cc @@ -244,8 +244,8 @@ void merge_operators(RTLIL::Module *module, RTLIL::Cell *mux, const std::vector< } if (shared_op->type.in(ID($alu))) { - shared_op->setPort(ID::X, module->addWire(NEW_ID, GetSize(new_sig_out))); - shared_op->setPort(ID::CO, module->addWire(NEW_ID, GetSize(new_sig_out))); + shared_op->setPort(ID::X, module->addWire(NEW_ID, GetSize(new_out))); + shared_op->setPort(ID::CO, module->addWire(NEW_ID, GetSize(new_out))); } bool is_fine = shared_op->type.in(FINE_BITWISE_OPS); diff --git a/passes/pmgen/pmgen.py b/passes/pmgen/pmgen.py index 592a26fa6..6e2fabeeb 100644 --- a/passes/pmgen/pmgen.py +++ b/passes/pmgen/pmgen.py @@ -451,7 +451,9 @@ with open(outfile, "w") as f: current_pattern = None print(" SigSpec port(Cell *cell, IdString portname) {", file=f) - print(" return sigmap(cell->getPort(portname));", file=f) + print(" try {", file=f) + print(" return sigmap(cell->getPort(portname));", file=f) + print(" } catch(std::out_of_range&) { log_error(\"Accessing non existing port %s\\n\",portname.c_str()); }", file=f) print(" }", file=f) print("", file=f) print(" SigSpec port(Cell *cell, IdString portname, const SigSpec& defval) {", file=f) @@ -460,7 +462,9 @@ with open(outfile, "w") as f: print("", file=f) print(" Const param(Cell *cell, IdString paramname) {", file=f) - print(" return cell->getParam(paramname);", file=f) + print(" try {", file=f) + print(" return cell->getParam(paramname);", file=f) + print(" } catch(std::out_of_range&) { log_error(\"Accessing non existing parameter %s\\n\",paramname.c_str()); }", file=f) print(" }", file=f) print("", file=f) print(" Const param(Cell *cell, IdString paramname, const Const& defval) {", file=f) diff --git a/passes/sat/freduce.cc b/passes/sat/freduce.cc index 762edfdfb..f87b85da9 100644 --- a/passes/sat/freduce.cc +++ b/passes/sat/freduce.cc @@ -27,6 +27,7 @@ #include <stdio.h> #include <string.h> #include <algorithm> +#include <limits> USING_YOSYS_NAMESPACE PRIVATE_NAMESPACE_BEGIN diff --git a/passes/techmap/abc.cc b/passes/techmap/abc.cc index 192e39372..1169e3da0 100644 --- a/passes/techmap/abc.cc +++ b/passes/techmap/abc.cc @@ -54,6 +54,7 @@ #include <cerrno> #include <sstream> #include <climits> +#include <vector> #ifndef _WIN32 # include <unistd.h> @@ -654,7 +655,7 @@ struct abc_output_filter }; void abc_module(RTLIL::Design *design, RTLIL::Module *current_module, std::string script_file, std::string exe_file, - std::string liberty_file, std::string constr_file, bool cleanup, vector<int> lut_costs, bool dff_mode, std::string clk_str, + std::vector<std::string> &liberty_files, std::string constr_file, bool cleanup, vector<int> lut_costs, bool dff_mode, std::string clk_str, bool keepff, std::string delay_target, std::string sop_inputs, std::string sop_products, std::string lutin_shared, bool fast_mode, const std::vector<RTLIL::Cell*> &cells, bool show_tempdir, bool sop_mode, bool abc_dress) { @@ -709,8 +710,8 @@ void abc_module(RTLIL::Design *design, RTLIL::Module *current_module, std::strin std::string abc_script = stringf("read_blif %s/input.blif; ", tempdir_name.c_str()); - if (!liberty_file.empty()) { - abc_script += stringf("read_lib -w %s; ", liberty_file.c_str()); + if (!liberty_files.empty()) { + for (std::string liberty_file : liberty_files) abc_script += stringf("read_lib -w %s; ", liberty_file.c_str()); if (!constr_file.empty()) abc_script += stringf("read_constr -v %s; ", constr_file.c_str()); } else @@ -738,7 +739,7 @@ void abc_module(RTLIL::Design *design, RTLIL::Module *current_module, std::strin abc_script += fast_mode ? ABC_FAST_COMMAND_LUT : ABC_COMMAND_LUT; if (all_luts_cost_same && !fast_mode) abc_script += "; lutpack {S}"; - } else if (!liberty_file.empty()) + } else if (!liberty_files.empty()) abc_script += constr_file.empty() ? (fast_mode ? ABC_FAST_COMMAND_LIB : ABC_COMMAND_LIB) : (fast_mode ? ABC_FAST_COMMAND_CTR : ABC_COMMAND_CTR); else if (sop_mode) abc_script += fast_mode ? ABC_FAST_COMMAND_SOP : ABC_COMMAND_SOP; @@ -1019,7 +1020,7 @@ void abc_module(RTLIL::Design *design, RTLIL::Module *current_module, std::strin if (ifs.fail()) log_error("Can't open ABC output file `%s'.\n", buffer.c_str()); - bool builtin_lib = liberty_file.empty(); + bool builtin_lib = liberty_files.empty(); RTLIL::Design *mapped_design = new RTLIL::Design; parse_blif(mapped_design, ifs, builtin_lib ? ID(DFF) : ID(_dff_), false, sop_mode); @@ -1471,7 +1472,8 @@ struct AbcPass : public Pass { po_map.clear(); std::string exe_file = yosys_abc_executable; - std::string script_file, liberty_file, constr_file, clk_str; + std::string script_file, default_liberty_file, constr_file, clk_str; + std::vector<std::string> liberty_files; std::string delay_target, sop_inputs, sop_products, lutin_shared = "-S 1"; bool fast_mode = false, dff_mode = false, keepff = false, cleanup = true; bool show_tempdir = false, sop_mode = false; @@ -1489,7 +1491,7 @@ struct AbcPass : public Pass { std::string lut_arg, luts_arg, g_arg; exe_file = design->scratchpad_get_string("abc.exe", exe_file /* inherit default value if not set */); script_file = design->scratchpad_get_string("abc.script", script_file); - liberty_file = design->scratchpad_get_string("abc.liberty", liberty_file); + default_liberty_file = design->scratchpad_get_string("abc.liberty", default_liberty_file); constr_file = design->scratchpad_get_string("abc.constr", constr_file); if (design->scratchpad.count("abc.D")) { delay_target = "-D " + design->scratchpad_get_string("abc.D"); @@ -1551,7 +1553,7 @@ struct AbcPass : public Pass { continue; } if (arg == "-liberty" && argidx+1 < args.size()) { - liberty_file = args[++argidx]; + liberty_files.push_back(args[++argidx]); continue; } if (arg == "-constr" && argidx+1 < args.size()) { @@ -1643,12 +1645,16 @@ struct AbcPass : public Pass { } extra_args(args, argidx, design); + if (liberty_files.empty() && !default_liberty_file.empty()) liberty_files.push_back(default_liberty_file); + rewrite_filename(script_file); if (!script_file.empty() && !is_absolute_path(script_file) && script_file[0] != '+') script_file = std::string(pwd) + "/" + script_file; - rewrite_filename(liberty_file); - if (!liberty_file.empty() && !is_absolute_path(liberty_file)) - liberty_file = std::string(pwd) + "/" + liberty_file; + for (int i = 0; i < GetSize(liberty_files); i++) { + rewrite_filename(liberty_files[i]); + if (!liberty_files[i].empty() && !is_absolute_path(liberty_files[i])) + liberty_files[i] = std::string(pwd) + "/" + liberty_files[i]; + } rewrite_filename(constr_file); if (!constr_file.empty() && !is_absolute_path(constr_file)) constr_file = std::string(pwd) + "/" + constr_file; @@ -1794,6 +1800,7 @@ struct AbcPass : public Pass { gate_list.push_back("OAI4"); gate_list.push_back("MUX"); gate_list.push_back("NMUX"); + goto ok_alias; } if (g_arg_from_cmd) cmd_error(args, g_argidx, stringf("Unsupported gate type: %s", g.c_str())); @@ -1811,9 +1818,9 @@ struct AbcPass : public Pass { } } - if (!lut_costs.empty() && !liberty_file.empty()) + if (!lut_costs.empty() && !liberty_files.empty()) log_cmd_error("Got -lut and -liberty! These two options are exclusive.\n"); - if (!constr_file.empty() && liberty_file.empty()) + if (!constr_file.empty() && liberty_files.empty()) log_cmd_error("Got -constr but no -liberty!\n"); if (enabled_gates.empty()) { @@ -1844,7 +1851,7 @@ struct AbcPass : public Pass { initvals.set(&assign_map, mod); if (!dff_mode || !clk_str.empty()) { - abc_module(design, mod, script_file, exe_file, liberty_file, constr_file, cleanup, lut_costs, dff_mode, clk_str, keepff, + abc_module(design, mod, script_file, exe_file, liberty_files, constr_file, cleanup, lut_costs, dff_mode, clk_str, keepff, delay_target, sop_inputs, sop_products, lutin_shared, fast_mode, mod->selected_cells(), show_tempdir, sop_mode, abc_dress); continue; } @@ -1989,7 +1996,7 @@ struct AbcPass : public Pass { clk_sig = assign_map(std::get<1>(it.first)); en_polarity = std::get<2>(it.first); en_sig = assign_map(std::get<3>(it.first)); - abc_module(design, mod, script_file, exe_file, liberty_file, constr_file, cleanup, lut_costs, !clk_sig.empty(), "$", + abc_module(design, mod, script_file, exe_file, liberty_files, constr_file, cleanup, lut_costs, !clk_sig.empty(), "$", keepff, delay_target, sop_inputs, sop_products, lutin_shared, fast_mode, it.second, show_tempdir, sop_mode, abc_dress); assign_map.set(mod); } diff --git a/passes/techmap/abc9.cc b/passes/techmap/abc9.cc index 7d017ac40..56bb15495 100644 --- a/passes/techmap/abc9.cc +++ b/passes/techmap/abc9.cc @@ -339,7 +339,7 @@ struct Abc9Pass : public ScriptPass if (check_label("pre")) { run("read_verilog -icells -lib -specify +/abc9_model.v"); - run("scc -set_attr abc9_scc_id {}"); + run("scc -specify -set_attr abc9_scc_id {}"); if (help_mode) run("abc9_ops -mark_scc -prep_delays -prep_xaiger [-dff]", "(option for -dff)"); else diff --git a/passes/techmap/flatten.cc b/passes/techmap/flatten.cc index 08978f446..f35b7ff60 100644 --- a/passes/techmap/flatten.cc +++ b/passes/techmap/flatten.cc @@ -180,12 +180,15 @@ struct FlattenWorker RTLIL::Wire *tpl_wire = tpl->wire(port_name); RTLIL::SigSig new_conn; + bool is_signed = false; if (tpl_wire->port_output && !tpl_wire->port_input) { new_conn.first = port_it.second; new_conn.second = tpl_wire; + is_signed = tpl_wire->is_signed; } else if (!tpl_wire->port_output && tpl_wire->port_input) { new_conn.first = tpl_wire; new_conn.second = port_it.second; + is_signed = new_conn.second.is_wire() && new_conn.second.as_wire()->is_signed; } else { SigSpec sig_tpl = tpl_wire, sig_mod = port_it.second; for (int i = 0; i < GetSize(sig_tpl) && i < GetSize(sig_mod); i++) { @@ -204,11 +207,11 @@ struct FlattenWorker if (new_conn.second.size() > new_conn.first.size()) new_conn.second.remove(new_conn.first.size(), new_conn.second.size() - new_conn.first.size()); if (new_conn.second.size() < new_conn.first.size()) - new_conn.second.append(RTLIL::SigSpec(RTLIL::State::S0, new_conn.first.size() - new_conn.second.size())); + new_conn.second.extend_u0(new_conn.first.size(), is_signed); log_assert(new_conn.first.size() == new_conn.second.size()); if (sigmap(new_conn.first).has_const()) - log_error("Mismatch in directionality for cell port %s.%s.%s: %s <= %s\n", + log_error("Cell port %s.%s.%s is driving constant bits: %s <= %s\n", log_id(module), log_id(cell), log_id(port_it.first), log_signal(new_conn.first), log_signal(new_conn.second)); module->connect(new_conn); diff --git a/passes/techmap/techmap.cc b/passes/techmap/techmap.cc index d43737c8d..96843d710 100644 --- a/passes/techmap/techmap.cc +++ b/passes/techmap/techmap.cc @@ -118,19 +118,14 @@ struct TechmapWorker return result; for (auto w : module->wires()) { - const char *p = w->name.c_str(); - if (*p == '$') + if (*w->name.c_str() == '$') continue; - const char *q = strrchr(p+1, '.'); - if (q) - p = q; - - if (!strncmp(p, "\\_TECHMAP_", 10)) { + if (w->name.contains("_TECHMAP_") && !w->name.contains("_TECHMAP_REPLACE_")) { TechmapWireData record; record.wire = w; record.value = w; - result[p].push_back(record); + result[w->name].push_back(record); w->set_bool_attribute(ID::keep); w->set_bool_attribute(ID::_techmap_special_); } @@ -165,7 +160,7 @@ struct TechmapWorker orig_cell_name = cell->name.str(); for (auto tpl_cell : tpl->cells()) - if (tpl_cell->name == ID::_TECHMAP_REPLACE_) { + if (tpl_cell->name.ends_with("_TECHMAP_REPLACE_")) { module->rename(cell, stringf("$techmap%d", autoidx++) + cell->name.str()); break; } @@ -226,8 +221,8 @@ struct TechmapWorker } design->select(module, w); - if (tpl_w->name.begins_with("\\_TECHMAP_REPLACE_.")) { - IdString replace_name = stringf("%s%s", orig_cell_name.c_str(), tpl_w->name.c_str() + strlen("\\_TECHMAP_REPLACE_")); + if (const char *p = strstr(tpl_w->name.c_str(), "_TECHMAP_REPLACE_.")) { + IdString replace_name = stringf("%s%s", orig_cell_name.c_str(), p + strlen("_TECHMAP_REPLACE_")); Wire *replace_w = module->addWire(replace_name, tpl_w); module->connect(replace_w, w); } @@ -327,12 +322,12 @@ struct TechmapWorker for (auto tpl_cell : tpl->cells()) { IdString c_name = tpl_cell->name; - bool techmap_replace_cell = (c_name == ID::_TECHMAP_REPLACE_); + bool techmap_replace_cell = c_name.ends_with("_TECHMAP_REPLACE_"); if (techmap_replace_cell) c_name = orig_cell_name; - else if (tpl_cell->name.begins_with("\\_TECHMAP_REPLACE_.")) - c_name = stringf("%s%s", orig_cell_name.c_str(), c_name.c_str() + strlen("\\_TECHMAP_REPLACE_")); + else if (const char *p = strstr(tpl_cell->name.c_str(), "_TECHMAP_REPLACE_.")) + c_name = stringf("%s%s", orig_cell_name.c_str(), p + strlen("_TECHMAP_REPLACE_")); else apply_prefix(cell->name, c_name); @@ -730,12 +725,16 @@ struct TechmapWorker for (auto &it : twd) techmap_wire_names.insert(it.first); - for (auto &it : twd[ID::_TECHMAP_FAIL_]) { - RTLIL::SigSpec value = it.value; - if (value.is_fully_const() && value.as_bool()) { - log("Not using module `%s' from techmap as it contains a %s marker wire with non-zero value %s.\n", - derived_name.c_str(), log_id(it.wire->name), log_signal(value)); - techmap_do_cache[tpl] = false; + for (auto &it : twd) { + if (!it.first.ends_with("_TECHMAP_FAIL_")) + continue; + for (const TechmapWireData &elem : it.second) { + RTLIL::SigSpec value = elem.value; + if (value.is_fully_const() && value.as_bool()) { + log("Not using module `%s' from techmap as it contains a %s marker wire with non-zero value %s.\n", + derived_name.c_str(), log_id(elem.wire->name), log_signal(value)); + techmap_do_cache[tpl] = false; + } } } @@ -744,7 +743,7 @@ struct TechmapWorker for (auto &it : twd) { - if (!it.first.begins_with("\\_TECHMAP_DO_") || it.second.empty()) + if (!it.first.contains("_TECHMAP_DO_") || it.second.empty()) continue; auto &data = it.second.front(); @@ -756,7 +755,7 @@ struct TechmapWorker const char *p = data.wire->name.c_str(); const char *q = strrchr(p+1, '.'); - q = q ? q : p+1; + q = q ? q+1 : p+1; std::string cmd_string = data.value.as_const().decode_string(); @@ -873,7 +872,7 @@ struct TechmapWorker TechmapWires twd = techmap_find_special_wires(tpl); for (auto &it : twd) { - if (it.first != ID::_TECHMAP_FAIL_ && (!it.first.begins_with("\\_TECHMAP_REMOVEINIT_") || !it.first.ends_with("_")) && !it.first.begins_with("\\_TECHMAP_DO_") && !it.first.begins_with("\\_TECHMAP_DONE_")) + if (!it.first.ends_with("_TECHMAP_FAIL_") && (!it.first.begins_with("\\_TECHMAP_REMOVEINIT_") || !it.first.ends_with("_")) && !it.first.contains("_TECHMAP_DO_") && !it.first.contains("_TECHMAP_DONE_")) log_error("Techmap yielded unknown config wire %s.\n", log_id(it.first)); if (techmap_do_cache[tpl]) for (auto &it2 : it.second) diff --git a/techlibs/common/cmp2lcu.v b/techlibs/common/cmp2lcu.v index a221727e7..4e62039e9 100644 --- a/techlibs/common/cmp2lcu.v +++ b/techlibs/common/cmp2lcu.v @@ -41,10 +41,7 @@ generate wire [WIDTH-1:0] BB = {{(WIDTH-B_WIDTH){B_SIGNED ? B[B_WIDTH-1] : 1'b0}}, B}; // For $ge operation, start with the assumption that A and B are // equal (propagating this equality if A and B turn out to be so) - if (_TECHMAP_CELLTYPE_ == "$ge") - localparam CI = 1'b1; - else - localparam CI = 1'b0; + localparam CI = _TECHMAP_CELLTYPE_ == "$ge"; $__CMP2LCU #(.AB_WIDTH(WIDTH), .AB_SIGNED(A_SIGNED && B_SIGNED), .LCU_WIDTH(1), .BUDGET(`LUT_WIDTH), .CI(CI)) _TECHMAP_REPLACE_ (.A(AA), .B(BB), .P(1'b1), .G(1'b0), .Y(Y)); end @@ -81,12 +78,12 @@ generate assign Y = CO[LCU_WIDTH-1]; end else begin - if (_TECHMAP_CONSTMSK_A_[AB_WIDTH-1:0] && _TECHMAP_CONSTMSK_B_[AB_WIDTH-1:0]) - localparam COST = 0; - else if (_TECHMAP_CONSTMSK_A_[AB_WIDTH-1:0] || _TECHMAP_CONSTMSK_B_[AB_WIDTH-1:0]) - localparam COST = 1; - else - localparam COST = 2; + localparam COST = + _TECHMAP_CONSTMSK_A_[AB_WIDTH-1:0] && _TECHMAP_CONSTMSK_B_[AB_WIDTH-1:0] + ? 0 + : (_TECHMAP_CONSTMSK_A_[AB_WIDTH-1:0] || _TECHMAP_CONSTMSK_B_[AB_WIDTH-1:0] + ? 1 + : 2); if (BUDGET < COST) $__CMP2LCU #(.AB_WIDTH(AB_WIDTH), .AB_SIGNED(AB_SIGNED), .LCU_WIDTH(LCU_WIDTH+1), .BUDGET(`LUT_WIDTH), .CI(CI)) @@ -104,21 +101,21 @@ generate // from MSB down, deferring to less significant bits if the // MSBs are equal assign GG = P[0] & (A[AB_WIDTH-1] & ~B[AB_WIDTH-1]); + (* force_downto *) + wire [LCU_WIDTH-1:0] P_, G_; if (LCU_WIDTH == 1) begin // Propagate only if all pairs are equal // (inconclusive evidence to say A >= B) - wire P_ = P[0] & PP; + assign P_ = P[0] & PP; // Generate if any comparisons call for it - wire G_ = G[0] | GG; + assign G_ = G[0] | GG; end else begin // Propagate only if all pairs are equal // (inconclusive evidence to say A >= B) - (* force_downto *) - wire [LCU_WIDTH-1:0] P_ = {P[LCU_WIDTH-1:1], P[0] & PP}; + assign P_ = {P[LCU_WIDTH-1:1], P[0] & PP}; // Generate if any comparisons call for it - (* force_downto *) - wire [LCU_WIDTH-1:0] G_ = {G[LCU_WIDTH-1:1], G[0] | GG}; + assign G_ = {G[LCU_WIDTH-1:1], G[0] | GG}; end if (AB_WIDTH == 1) $__CMP2LCU #(.AB_WIDTH(AB_WIDTH-1), .AB_SIGNED(1'b0), .LCU_WIDTH(LCU_WIDTH), .BUDGET(BUDGET-COST), .CI(CI)) diff --git a/techlibs/common/cmp2lut.v b/techlibs/common/cmp2lut.v index ec8f98e8d..c753bd2f1 100644 --- a/techlibs/common/cmp2lut.v +++ b/techlibs/common/cmp2lut.v @@ -66,14 +66,12 @@ function automatic [(1 << `LUT_WIDTH)-1:0] gen_lut; endfunction generate - if (_TECHMAP_CELLTYPE_ == "$lt") - localparam operation = 0; - if (_TECHMAP_CELLTYPE_ == "$le") - localparam operation = 1; - if (_TECHMAP_CELLTYPE_ == "$gt") - localparam operation = 2; - if (_TECHMAP_CELLTYPE_ == "$ge") - localparam operation = 3; + localparam operation = + _TECHMAP_CELLTYPE_ == "$lt" ? 0 : + _TECHMAP_CELLTYPE_ == "$le" ? 1 : + _TECHMAP_CELLTYPE_ == "$gt" ? 2 : + _TECHMAP_CELLTYPE_ == "$ge" ? 3 : + -1; if (A_WIDTH > `LUT_WIDTH || B_WIDTH > `LUT_WIDTH || Y_WIDTH != 1) wire _TECHMAP_FAIL_ = 1; diff --git a/techlibs/common/mul2dsp.v b/techlibs/common/mul2dsp.v index bec47d01f..f22f47b4a 100644 --- a/techlibs/common/mul2dsp.v +++ b/techlibs/common/mul2dsp.v @@ -121,7 +121,7 @@ module _80_mul (A, B, Y); localparam partial_Y_WIDTH = `MIN(Y_WIDTH, B_WIDTH+`DSP_A_MAXWIDTH_PARTIAL);
localparam last_A_WIDTH = A_WIDTH-n*(`DSP_A_MAXWIDTH_PARTIAL-sign_headroom);
localparam last_Y_WIDTH = B_WIDTH+last_A_WIDTH;
- if (A_SIGNED && B_SIGNED) begin
+ if (A_SIGNED && B_SIGNED) begin : blk
(* force_downto *)
wire signed [partial_Y_WIDTH-1:0] partial [n-1:0];
(* force_downto *)
@@ -129,7 +129,7 @@ module _80_mul (A, B, Y); (* force_downto *)
wire signed [Y_WIDTH-1:0] partial_sum [n:0];
end
- else begin
+ else begin : blk
(* force_downto *)
wire [partial_Y_WIDTH-1:0] partial [n-1:0];
(* force_downto *)
@@ -148,15 +148,15 @@ module _80_mul (A, B, Y); ) mul (
.A({{sign_headroom{1'b0}}, A[i*(`DSP_A_MAXWIDTH_PARTIAL-sign_headroom) +: `DSP_A_MAXWIDTH_PARTIAL-sign_headroom]}),
.B(B),
- .Y(partial[i])
+ .Y(blk.partial[i])
);
// TODO: Currently a 'cascade' approach to summing the partial
// products is taken here, but a more efficient 'binary
// reduction' approach also exists...
if (i == 0)
- assign partial_sum[i] = partial[i];
+ assign blk.partial_sum[i] = blk.partial[i];
else
- assign partial_sum[i] = (partial[i] << (* mul2dsp *) i*(`DSP_A_MAXWIDTH_PARTIAL-sign_headroom)) + (* mul2dsp *) partial_sum[i-1];
+ assign blk.partial_sum[i] = (blk.partial[i] << (* mul2dsp *) i*(`DSP_A_MAXWIDTH_PARTIAL-sign_headroom)) + (* mul2dsp *) blk.partial_sum[i-1];
end
\$__mul #(
@@ -168,17 +168,17 @@ module _80_mul (A, B, Y); ) sliceA.last (
.A(A[A_WIDTH-1 -: last_A_WIDTH]),
.B(B),
- .Y(last_partial)
+ .Y(blk.last_partial)
);
- assign partial_sum[n] = (last_partial << (* mul2dsp *) n*(`DSP_A_MAXWIDTH_PARTIAL-sign_headroom)) + (* mul2dsp *) partial_sum[n-1];
- assign Y = partial_sum[n];
+ assign blk.partial_sum[n] = (blk.last_partial << (* mul2dsp *) n*(`DSP_A_MAXWIDTH_PARTIAL-sign_headroom)) + (* mul2dsp *) blk.partial_sum[n-1];
+ assign Y = blk.partial_sum[n];
end
else if (B_WIDTH > `DSP_B_MAXWIDTH) begin
localparam n = (B_WIDTH-`DSP_B_MAXWIDTH+`DSP_B_MAXWIDTH_PARTIAL-sign_headroom-1) / (`DSP_B_MAXWIDTH_PARTIAL-sign_headroom);
localparam partial_Y_WIDTH = `MIN(Y_WIDTH, A_WIDTH+`DSP_B_MAXWIDTH_PARTIAL);
localparam last_B_WIDTH = B_WIDTH-n*(`DSP_B_MAXWIDTH_PARTIAL-sign_headroom);
localparam last_Y_WIDTH = A_WIDTH+last_B_WIDTH;
- if (A_SIGNED && B_SIGNED) begin
+ if (A_SIGNED && B_SIGNED) begin : blk
(* force_downto *)
wire signed [partial_Y_WIDTH-1:0] partial [n-1:0];
(* force_downto *)
@@ -186,7 +186,7 @@ module _80_mul (A, B, Y); (* force_downto *)
wire signed [Y_WIDTH-1:0] partial_sum [n:0];
end
- else begin
+ else begin : blk
(* force_downto *)
wire [partial_Y_WIDTH-1:0] partial [n-1:0];
(* force_downto *)
@@ -205,15 +205,15 @@ module _80_mul (A, B, Y); ) mul (
.A(A),
.B({{sign_headroom{1'b0}}, B[i*(`DSP_B_MAXWIDTH_PARTIAL-sign_headroom) +: `DSP_B_MAXWIDTH_PARTIAL-sign_headroom]}),
- .Y(partial[i])
+ .Y(blk.partial[i])
);
// TODO: Currently a 'cascade' approach to summing the partial
// products is taken here, but a more efficient 'binary
// reduction' approach also exists...
if (i == 0)
- assign partial_sum[i] = partial[i];
+ assign blk.partial_sum[i] = blk.partial[i];
else
- assign partial_sum[i] = (partial[i] << (* mul2dsp *) i*(`DSP_B_MAXWIDTH_PARTIAL-sign_headroom)) + (* mul2dsp *) partial_sum[i-1];
+ assign blk.partial_sum[i] = (blk.partial[i] << (* mul2dsp *) i*(`DSP_B_MAXWIDTH_PARTIAL-sign_headroom)) + (* mul2dsp *) blk.partial_sum[i-1];
end
\$__mul #(
@@ -225,20 +225,24 @@ module _80_mul (A, B, Y); ) mul_sliceB_last (
.A(A),
.B(B[B_WIDTH-1 -: last_B_WIDTH]),
- .Y(last_partial)
+ .Y(blk.last_partial)
);
- assign partial_sum[n] = (last_partial << (* mul2dsp *) n*(`DSP_B_MAXWIDTH_PARTIAL-sign_headroom)) + (* mul2dsp *) partial_sum[n-1];
- assign Y = partial_sum[n];
+ assign blk.partial_sum[n] = (blk.last_partial << (* mul2dsp *) n*(`DSP_B_MAXWIDTH_PARTIAL-sign_headroom)) + (* mul2dsp *) blk.partial_sum[n-1];
+ assign Y = blk.partial_sum[n];
end
else begin
- if (A_SIGNED)
+ if (A_SIGNED) begin : blkA
wire signed [`DSP_A_MAXWIDTH-1:0] Aext = $signed(A);
- else
+ end
+ else begin : blkA
wire [`DSP_A_MAXWIDTH-1:0] Aext = A;
- if (B_SIGNED)
+ end
+ if (B_SIGNED) begin : blkB
wire signed [`DSP_B_MAXWIDTH-1:0] Bext = $signed(B);
- else
+ end
+ else begin : blkB
wire [`DSP_B_MAXWIDTH-1:0] Bext = B;
+ end
`DSP_NAME #(
.A_SIGNED(A_SIGNED),
@@ -247,8 +251,8 @@ module _80_mul (A, B, Y); .B_WIDTH(`DSP_B_MAXWIDTH),
.Y_WIDTH(`MIN(Y_WIDTH,`DSP_A_MAXWIDTH+`DSP_B_MAXWIDTH)),
) _TECHMAP_REPLACE_ (
- .A(Aext),
- .B(Bext),
+ .A(blkA.Aext),
+ .B(blkB.Bext),
.Y(Y)
);
end
diff --git a/techlibs/common/simlib.v b/techlibs/common/simlib.v index e94884025..5c9efad27 100644 --- a/techlibs/common/simlib.v +++ b/techlibs/common/simlib.v @@ -237,7 +237,7 @@ endmodule // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| //- -//- $reduce_and (A, B, Y) +//- $reduce_and (A, Y) //- //- An AND reduction. This corresponds to the Verilog unary prefix '&' operator. //- @@ -264,7 +264,7 @@ endmodule // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| //- -//- $reduce_or (A, B, Y) +//- $reduce_or (A, Y) //- //- An OR reduction. This corresponds to the Verilog unary prefix '|' operator. //- @@ -291,7 +291,7 @@ endmodule // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| //- -//- $reduce_xor (A, B, Y) +//- $reduce_xor (A, Y) //- //- A XOR reduction. This corresponds to the Verilog unary prefix '^' operator. //- @@ -318,7 +318,7 @@ endmodule // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| //- -//- $reduce_xnor (A, B, Y) +//- $reduce_xnor (A, Y) //- //- A XNOR reduction. This corresponds to the Verilog unary prefix '~^' operator. //- @@ -345,7 +345,7 @@ endmodule // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| //- -//- $reduce_bool (A, B, Y) +//- $reduce_bool (A, Y) //- //- An OR reduction. This cell type is used instead of $reduce_or when a signal is //- implicitly converted to a boolean signal, e.g. for operands of '&&' and '||'. diff --git a/techlibs/ice40/brams_map.v b/techlibs/ice40/brams_map.v index ad3bccd21..db9f5d8ce 100644 --- a/techlibs/ice40/brams_map.v +++ b/techlibs/ice40/brams_map.v @@ -254,6 +254,41 @@ module \$__ICE40_RAM4K_M123 (CLK2, CLK3, A1ADDR, A1DATA, A1EN, B1ADDR, B1DATA, B wire [15:0] A1DATA_16, B1DATA_16; +`define INSTANCE \ + \$__ICE40_RAM4K #( \ + .READ_MODE(MODE), \ + .WRITE_MODE(MODE), \ + .NEGCLK_R(!CLKPOL2), \ + .NEGCLK_W(!CLKPOL3), \ + .INIT_0(INIT_0), \ + .INIT_1(INIT_1), \ + .INIT_2(INIT_2), \ + .INIT_3(INIT_3), \ + .INIT_4(INIT_4), \ + .INIT_5(INIT_5), \ + .INIT_6(INIT_6), \ + .INIT_7(INIT_7), \ + .INIT_8(INIT_8), \ + .INIT_9(INIT_9), \ + .INIT_A(INIT_A), \ + .INIT_B(INIT_B), \ + .INIT_C(INIT_C), \ + .INIT_D(INIT_D), \ + .INIT_E(INIT_E), \ + .INIT_F(INIT_F) \ + ) _TECHMAP_REPLACE_ ( \ + .RDATA(A1DATA_16), \ + .RADDR(A1ADDR_11), \ + .RCLK(CLK2), \ + .RCLKE(A1EN), \ + .RE(1'b1), \ + .WDATA(B1DATA_16), \ + .WADDR(B1ADDR_11), \ + .WCLK(CLK3), \ + .WCLKE(|B1EN), \ + .WE(1'b1) \ + ); + generate if (MODE == 1) begin assign A1DATA = {A1DATA_16[14], A1DATA_16[12], A1DATA_16[10], A1DATA_16[ 8], @@ -261,51 +296,23 @@ module \$__ICE40_RAM4K_M123 (CLK2, CLK3, A1ADDR, A1DATA, A1EN, B1ADDR, B1DATA, B assign {B1DATA_16[14], B1DATA_16[12], B1DATA_16[10], B1DATA_16[ 8], B1DATA_16[ 6], B1DATA_16[ 4], B1DATA_16[ 2], B1DATA_16[ 0]} = B1DATA; `include "brams_init1.vh" + `INSTANCE end if (MODE == 2) begin assign A1DATA = {A1DATA_16[13], A1DATA_16[9], A1DATA_16[5], A1DATA_16[1]}; assign {B1DATA_16[13], B1DATA_16[9], B1DATA_16[5], B1DATA_16[1]} = B1DATA; `include "brams_init2.vh" + `INSTANCE end if (MODE == 3) begin assign A1DATA = {A1DATA_16[11], A1DATA_16[3]}; assign {B1DATA_16[11], B1DATA_16[3]} = B1DATA; `include "brams_init3.vh" + `INSTANCE end endgenerate - \$__ICE40_RAM4K #( - .READ_MODE(MODE), - .WRITE_MODE(MODE), - .NEGCLK_R(!CLKPOL2), - .NEGCLK_W(!CLKPOL3), - .INIT_0(INIT_0), - .INIT_1(INIT_1), - .INIT_2(INIT_2), - .INIT_3(INIT_3), - .INIT_4(INIT_4), - .INIT_5(INIT_5), - .INIT_6(INIT_6), - .INIT_7(INIT_7), - .INIT_8(INIT_8), - .INIT_9(INIT_9), - .INIT_A(INIT_A), - .INIT_B(INIT_B), - .INIT_C(INIT_C), - .INIT_D(INIT_D), - .INIT_E(INIT_E), - .INIT_F(INIT_F) - ) _TECHMAP_REPLACE_ ( - .RDATA(A1DATA_16), - .RADDR(A1ADDR_11), - .RCLK(CLK2), - .RCLKE(A1EN), - .RE(1'b1), - .WDATA(B1DATA_16), - .WADDR(B1ADDR_11), - .WCLK(CLK3), - .WCLKE(|B1EN), - .WE(1'b1) - ); +`undef INSTANCE + endmodule diff --git a/techlibs/xilinx/arith_map.v b/techlibs/xilinx/arith_map.v index eb8a04bde..63be7563e 100644 --- a/techlibs/xilinx/arith_map.v +++ b/techlibs/xilinx/arith_map.v @@ -151,6 +151,8 @@ generate if (`LUT_SIZE == 4) begin ); end endgenerate + assign X = S; + end else begin localparam CARRY4_COUNT = (Y_WIDTH + 3) / 4; @@ -193,8 +195,8 @@ end else begin end end endgenerate -end endgenerate - assign X = S; + +end endgenerate endmodule diff --git a/techlibs/xilinx/cells_sim.v b/techlibs/xilinx/cells_sim.v index 4162160bb..a079f1c95 100644 --- a/techlibs/xilinx/cells_sim.v +++ b/techlibs/xilinx/cells_sim.v @@ -633,6 +633,41 @@ module FDRSE ( Q <= d; endmodule +module FDRSE_1 ( + output reg Q, + (* clkbuf_sink *) + (* invertible_pin = "IS_C_INVERTED" *) + input C, + (* invertible_pin = "IS_CE_INVERTED" *) + input CE, + (* invertible_pin = "IS_D_INVERTED" *) + input D, + (* invertible_pin = "IS_R_INVERTED" *) + input R, + (* invertible_pin = "IS_S_INVERTED" *) + input S +); + parameter [0:0] INIT = 1'b0; + parameter [0:0] IS_C_INVERTED = 1'b0; + parameter [0:0] IS_CE_INVERTED = 1'b0; + parameter [0:0] IS_D_INVERTED = 1'b0; + parameter [0:0] IS_R_INVERTED = 1'b0; + parameter [0:0] IS_S_INVERTED = 1'b0; + initial Q <= INIT; + wire c = C ^ IS_C_INVERTED; + wire ce = CE ^ IS_CE_INVERTED; + wire d = D ^ IS_D_INVERTED; + wire r = R ^ IS_R_INVERTED; + wire s = S ^ IS_S_INVERTED; + always @(negedge c) + if (r) + Q <= 0; + else if (s) + Q <= 1; + else if (ce) + Q <= d; +endmodule + (* abc9_box, lib_whitebox *) module FDCE ( output reg Q, @@ -837,6 +872,51 @@ module FDCPE ( assign Q = qs ? qp : qc; endmodule +module FDCPE_1 ( + output wire Q, + (* clkbuf_sink *) + (* invertible_pin = "IS_C_INVERTED" *) + input C, + input CE, + (* invertible_pin = "IS_CLR_INVERTED" *) + input CLR, + input D, + (* invertible_pin = "IS_PRE_INVERTED" *) + input PRE +); + parameter [0:0] INIT = 1'b0; + parameter [0:0] IS_C_INVERTED = 1'b0; + parameter [0:0] IS_CLR_INVERTED = 1'b0; + parameter [0:0] IS_PRE_INVERTED = 1'b0; + wire c = C ^ IS_C_INVERTED; + wire clr = CLR ^ IS_CLR_INVERTED; + wire pre = PRE ^ IS_PRE_INVERTED; + // Hacky model to avoid simulation-synthesis mismatches. + reg qc, qp, qs; + initial qc = INIT; + initial qp = INIT; + initial qs = 0; + always @(negedge c, posedge clr) begin + if (clr) + qc <= 0; + else if (CE) + qc <= D; + end + always @(negedge c, posedge pre) begin + if (pre) + qp <= 1; + else if (CE) + qp <= D; + end + always @* begin + if (clr) + qs <= 0; + else if (pre) + qs <= 1; + end + assign Q = qs ? qp : qc; +endmodule + module LDCE ( output reg Q, (* invertible_pin = "IS_CLR_INVERTED" *) @@ -2023,6 +2103,105 @@ module RAM64M8 ( end endmodule +module RAM32X16DR8 ( + output DOA, + output DOB, + output DOC, + output DOD, + output DOE, + output DOF, + output DOG, + output [1:0] DOH, + input [5:0] ADDRA, ADDRB, ADDRC, ADDRD, ADDRE, ADDRF, ADDRG, + input [4:0] ADDRH, + input [1:0] DIA, + input [1:0] DIB, + input [1:0] DIC, + input [1:0] DID, + input [1:0] DIE, + input [1:0] DIF, + input [1:0] DIG, + input [1:0] DIH, + (* clkbuf_sink *) + (* invertible_pin = "IS_WCLK_INVERTED" *) + input WCLK, + input WE +); + parameter [0:0] IS_WCLK_INVERTED = 1'b0; + reg [63:0] mem_a, mem_b, mem_c, mem_d, mem_e, mem_f, mem_g, mem_h; + assign DOA = mem_a[ADDRA]; + assign DOB = mem_b[ADDRB]; + assign DOC = mem_c[ADDRC]; + assign DOD = mem_d[ADDRD]; + assign DOE = mem_e[ADDRE]; + assign DOF = mem_f[ADDRF]; + assign DOG = mem_g[ADDRG]; + assign DOH = mem_h[2*ADDRH+:2]; + wire clk = WCLK ^ IS_WCLK_INVERTED; + always @(posedge clk) + if (WE) begin + mem_a[2*ADDRH+:2] <= DIA; + mem_b[2*ADDRH+:2] <= DIB; + mem_c[2*ADDRH+:2] <= DIC; + mem_d[2*ADDRH+:2] <= DID; + mem_e[2*ADDRH+:2] <= DIE; + mem_f[2*ADDRH+:2] <= DIF; + mem_g[2*ADDRH+:2] <= DIG; + mem_h[2*ADDRH+:2] <= DIH; + end +endmodule + +module RAM64X8SW ( + output [7:0] O, + input [5:0] A, + input D, + (* clkbuf_sink *) + (* invertible_pin = "IS_WCLK_INVERTED" *) + input WCLK, + input WE, + input [2:0] WSEL +); + parameter [63:0] INIT_A = 64'h0000000000000000; + parameter [63:0] INIT_B = 64'h0000000000000000; + parameter [63:0] INIT_C = 64'h0000000000000000; + parameter [63:0] INIT_D = 64'h0000000000000000; + parameter [63:0] INIT_E = 64'h0000000000000000; + parameter [63:0] INIT_F = 64'h0000000000000000; + parameter [63:0] INIT_G = 64'h0000000000000000; + parameter [63:0] INIT_H = 64'h0000000000000000; + parameter [0:0] IS_WCLK_INVERTED = 1'b0; + reg [63:0] mem_a = INIT_A; + reg [63:0] mem_b = INIT_B; + reg [63:0] mem_c = INIT_C; + reg [63:0] mem_d = INIT_D; + reg [63:0] mem_e = INIT_E; + reg [63:0] mem_f = INIT_F; + reg [63:0] mem_g = INIT_G; + reg [63:0] mem_h = INIT_H; + assign O[7] = mem_a[A]; + assign O[6] = mem_b[A]; + assign O[5] = mem_c[A]; + assign O[4] = mem_d[A]; + assign O[3] = mem_e[A]; + assign O[2] = mem_f[A]; + assign O[1] = mem_g[A]; + assign O[0] = mem_h[A]; + wire clk = WCLK ^ IS_WCLK_INVERTED; + always @(posedge clk) + if (WE) begin + case (WSEL) + 3'b111: mem_a[A] <= D; + 3'b110: mem_b[A] <= D; + 3'b101: mem_c[A] <= D; + 3'b100: mem_d[A] <= D; + 3'b011: mem_e[A] <= D; + 3'b010: mem_f[A] <= D; + 3'b001: mem_g[A] <= D; + 3'b000: mem_h[A] <= D; + endcase + end +endmodule + // ROM. module ROM16X1 ( diff --git a/techlibs/xilinx/cells_xtra.py b/techlibs/xilinx/cells_xtra.py index f086291ab..cb23b9787 100644 --- a/techlibs/xilinx/cells_xtra.py +++ b/techlibs/xilinx/cells_xtra.py @@ -57,6 +57,8 @@ CELLS = [ # Cell('RAM32M16', port_attrs={'WCLK': ['clkbuf_sink']}), # Cell('RAM64M', port_attrs={'WCLK': ['clkbuf_sink']}), # Cell('RAM64M8', port_attrs={'WCLK': ['clkbuf_sink']}), + # Cell('RAM32X16DR8', port_attrs={'WCLK': ['clkbuf_sink']}), + # Cell('RAM64X8SW', port_attrs={'WCLK': ['clkbuf_sink']}), # Cell('ROM16X1'), # Cell('ROM32X1'), # Cell('ROM64X1'), @@ -188,6 +190,11 @@ CELLS = [ # I/O logic. # Virtex 2, Spartan 3. + # Note: these two are not officially listed in the HDL library guide, but + # they are more fundamental than OFDDR* and are necessary to construct + # differential DDR outputs (OFDDR* can only do single-ended). + Cell('FDDRCPE', port_attrs={'C0': ['clkbuf_sink'], 'C1': ['clkbuf_sink']}), + Cell('FDDRRSE', port_attrs={'C0': ['clkbuf_sink'], 'C1': ['clkbuf_sink']}), Cell('IFDDRCPE', port_attrs={'C0': ['clkbuf_sink'], 'C1': ['clkbuf_sink'], 'D': ['iopad_external_pin']}), Cell('IFDDRRSE', port_attrs={'C0': ['clkbuf_sink'], 'C1': ['clkbuf_sink'], 'D': ['iopad_external_pin']}), Cell('OFDDRCPE', port_attrs={'C0': ['clkbuf_sink'], 'C1': ['clkbuf_sink'], 'Q': ['iopad_external_pin']}), @@ -238,12 +245,12 @@ CELLS = [ 'CLKDIVP': ['clkbuf_sink'], }), Cell('OSERDESE2', port_attrs={'CLK': ['clkbuf_sink'], 'CLKDIV': ['clkbuf_sink']}), - Cell('PHASER_IN'), - Cell('PHASER_IN_PHY'), - Cell('PHASER_OUT'), - Cell('PHASER_OUT_PHY'), - Cell('PHASER_REF'), - Cell('PHY_CONTROL'), + Cell('PHASER_IN', keep=True), + Cell('PHASER_IN_PHY', keep=True), + Cell('PHASER_OUT', keep=True), + Cell('PHASER_OUT_PHY', keep=True), + Cell('PHASER_REF', keep=True), + Cell('PHY_CONTROL', keep=True), # Ultrascale. Cell('IDDRE1', port_attrs={'C': ['clkbuf_sink'], 'CB': ['clkbuf_sink']}), Cell('ODDRE1', port_attrs={'C': ['clkbuf_sink']}), @@ -257,7 +264,7 @@ CELLS = [ }), Cell('OSERDESE3', port_attrs={'CLK': ['clkbuf_sink'], 'CLKDIV': ['clkbuf_sink']}), Cell('BITSLICE_CONTROL', keep=True), - Cell('RIU_OR'), + Cell('RIU_OR', keep=True), Cell('RX_BITSLICE'), Cell('RXTX_BITSLICE'), Cell('TX_BITSLICE'), @@ -322,7 +329,7 @@ CELLS = [ Cell('PULLUP'), # Misc. Cell('DCIRESET', keep=True), - Cell('HPIO_VREF'), # Ultrascale + Cell('HPIO_VREF', keep=True), # Ultrascale # Clock buffers (global). # Cell('BUFG', port_attrs={'O': ['clkbuf_driver']}), @@ -451,6 +458,7 @@ CELLS = [ Cell('FRAME_ECC_VIRTEX6'), Cell('FRAME_ECCE2'), # Series 7 Cell('FRAME_ECCE3'), # Ultrascale + Cell('FRAME_ECCE4'), # Ultrascale+ # AXSS command access. Cell('USR_ACCESS_VIRTEX4'), Cell('USR_ACCESS_VIRTEX5'), @@ -465,10 +473,10 @@ CELLS = [ Cell('EFUSE_USR'), # ADC. - Cell('SYSMON'), # Virtex 5/6 - Cell('XADC'), # Series 7 - Cell('SYSMONE1'), # Ultrascale - Cell('SYSMONE4'), # Ultrascale+ + Cell('SYSMON', keep=True), # Virtex 5/6 + Cell('XADC', keep=True), # Series 7 + Cell('SYSMONE1', keep=True), # Ultrascale + Cell('SYSMONE4', keep=True), # Ultrascale+ # Gigabit transceivers. # Spartan 6. @@ -502,18 +510,30 @@ CELLS = [ # Ultrascale. Cell('GTHE3_CHANNEL'), Cell('GTHE3_COMMON'), - Cell('GTHE4_CHANNEL'), - Cell('GTHE4_COMMON'), Cell('GTYE3_CHANNEL'), Cell('GTYE3_COMMON'), - Cell('GTYE4_CHANNEL'), - Cell('GTYE4_COMMON'), Cell('IBUFDS_GTE3', port_attrs={'I': ['iopad_external_pin'], 'IB': ['iopad_external_pin']}), - Cell('IBUFDS_GTE4', port_attrs={'I': ['iopad_external_pin'], 'IB': ['iopad_external_pin']}), Cell('OBUFDS_GTE3', port_attrs={'O': ['iopad_external_pin'], 'OB': ['iopad_external_pin']}), Cell('OBUFDS_GTE3_ADV', port_attrs={'O': ['iopad_external_pin'], 'OB': ['iopad_external_pin']}), + # Ultrascale+. + Cell('GTHE4_CHANNEL'), + Cell('GTHE4_COMMON'), + Cell('GTYE4_CHANNEL'), + Cell('GTYE4_COMMON'), + Cell('IBUFDS_GTE4', port_attrs={'I': ['iopad_external_pin'], 'IB': ['iopad_external_pin']}), Cell('OBUFDS_GTE4', port_attrs={'O': ['iopad_external_pin'], 'OB': ['iopad_external_pin']}), Cell('OBUFDS_GTE4_ADV', port_attrs={'O': ['iopad_external_pin'], 'OB': ['iopad_external_pin']}), + # Ultrascale+ GTM. + Cell('GTM_DUAL'), # not in the libraries guide + Cell('IBUFDS_GTM', port_attrs={'I': ['iopad_external_pin'], 'IB': ['iopad_external_pin']}), + Cell('OBUFDS_GTM', port_attrs={'O': ['iopad_external_pin'], 'OB': ['iopad_external_pin']}), + Cell('OBUFDS_GTM_ADV', port_attrs={'O': ['iopad_external_pin'], 'OB': ['iopad_external_pin']}), + + # High-speed ADC/DAC. + Cell('HSDAC'), # not in libraries guide + Cell('HSADC'), # not in libraries guide + Cell('RFDAC'), # not in libraries guide + Cell('RFADC'), # not in libraries guide # PCIE IP. Cell('PCIE_A1'), # Spartan 6 @@ -523,6 +543,7 @@ CELLS = [ Cell('PCIE_3_0'), # Series 7 Cell('PCIE_3_1'), # Ultrascale Cell('PCIE40E4'), # Ultrascale+ + Cell('PCIE4CE4'), # Ultrascale+ v2 (not in the libraries guide) # Ethernet IP. Cell('EMAC'), # Virtex 4 @@ -531,17 +552,29 @@ CELLS = [ Cell('CMAC'), # Ultrascale Cell('CMACE4'), # Ultrsacale+ + # Hard memory controllers. + Cell('MCB'), # Spartan 6 Memory Controller Block + Cell('HBM_REF_CLK', keep=True), # not in liraries guide + # not sure how the following relate to the hw + Cell('HBM_SNGLBLI_INTF_APB', keep=True), # not in liraries guide + Cell('HBM_SNGLBLI_INTF_AXI', keep=True), # not in liraries guide + Cell('HBM_ONE_STACK_INTF', keep=True), # not in liraries guide + Cell('HBM_TWO_STACK_INTF', keep=True), # not in liraries guide + # PowerPC. # TODO PPC405 (Virtex 2) Cell('PPC405_ADV'), # Virtex 4 Cell('PPC440'), # Virtex 5 + # ARM. + Cell('PS7', keep=True), # The Zynq 7000 ARM Processor System (not in libraries guide). + Cell('PS8', keep=True), # The Zynq Ultrascale+ ARM Processor System (not in libraries guide). + # Misc hard IP. - Cell('MCB'), # Spartan 6 Memory Controller Block - Cell('PS7', keep=True), # The Zynq 7000 ARM Processor System. - Cell('PS8', keep=True), # The Zynq Ultrascale+ ARM Processor System. Cell('ILKN'), # Ultrascale Interlaken Cell('ILKNE4'), # Ultrascale+ Interlaken + Cell('VCU', keep=True), # Zynq MPSoC Video Codec Unit (not in libraries guide). + Cell('FE'), # Zynq RFSoC Forward Error Correction (not in libraries guide). ] @@ -554,100 +587,101 @@ class State(Enum): def xtract_cell_decl(cell, dirs, outf): for dir in dirs: - fname = os.path.join(dir, cell.name + '.v') - try: - with open(fname) as f: - state = State.OUTSIDE - found = False - # Probably the most horrible Verilog "parser" ever written. - module_ports = [] - invertible_ports = set() - for l in f: - l = l.partition('//')[0] - l = l.strip() - if l == 'module {}'.format(cell.name) or l.startswith('module {} '.format(cell.name)): - if found: - print('Multiple modules in {}.'.format(fname)) - sys.exit(1) - elif state != State.OUTSIDE: - print('Nested modules in {}.'.format(fname)) - sys.exit(1) - found = True - state = State.IN_MODULE - if cell.keep: - outf.write('(* keep *)\n') - outf.write('module {} (...);\n'.format(cell.name)) - elif l.startswith('module '): - if state != State.OUTSIDE: - print('Nested modules in {}.'.format(fname)) - sys.exit(1) - state = State.IN_OTHER_MODULE - elif l.startswith('task '): - if state == State.IN_MODULE: - state = State.IN_TASK - elif l.startswith('function '): - if state == State.IN_MODULE: - state = State.IN_FUNCTION - elif l == 'endtask': - if state == State.IN_TASK: - state = State.IN_MODULE - elif l == 'endfunction': - if state == State.IN_FUNCTION: + for ext in ['.v', '.sv']: + fname = os.path.join(dir, cell.name + ext) + try: + with open(fname) as f: + state = State.OUTSIDE + found = False + # Probably the most horrible Verilog "parser" ever written. + module_ports = [] + invertible_ports = set() + for l in f: + l = l.partition('//')[0] + l = l.strip() + if l == 'module {}'.format(cell.name) or l.startswith('module {} '.format(cell.name)): + if found: + print('Multiple modules in {}.'.format(fname)) + sys.exit(1) + elif state != State.OUTSIDE: + print('Nested modules in {}.'.format(fname)) + sys.exit(1) + found = True state = State.IN_MODULE - elif l == 'endmodule': - if state == State.IN_MODULE: - for kind, rng, port in module_ports: - for attr in cell.port_attrs.get(port, []): - outf.write(' (* {} *)\n'.format(attr)) - if port in invertible_ports: - outf.write(' (* invertible_pin = "IS_{}_INVERTED" *)\n'.format(port)) - if rng is None: - outf.write(' {} {};\n'.format(kind, port)) + if cell.keep: + outf.write('(* keep *)\n') + outf.write('module {} (...);\n'.format(cell.name)) + elif l.startswith('module '): + if state != State.OUTSIDE: + print('Nested modules in {}.'.format(fname)) + sys.exit(1) + state = State.IN_OTHER_MODULE + elif l.startswith('task '): + if state == State.IN_MODULE: + state = State.IN_TASK + elif l.startswith('function '): + if state == State.IN_MODULE: + state = State.IN_FUNCTION + elif l == 'endtask': + if state == State.IN_TASK: + state = State.IN_MODULE + elif l == 'endfunction': + if state == State.IN_FUNCTION: + state = State.IN_MODULE + elif l == 'endmodule': + if state == State.IN_MODULE: + for kind, rng, port in module_ports: + for attr in cell.port_attrs.get(port, []): + outf.write(' (* {} *)\n'.format(attr)) + if port in invertible_ports: + outf.write(' (* invertible_pin = "IS_{}_INVERTED" *)\n'.format(port)) + if rng is None: + outf.write(' {} {};\n'.format(kind, port)) + else: + outf.write(' {} {} {};\n'.format(kind, rng, port)) + outf.write(l + '\n') + outf.write('\n') + elif state != State.IN_OTHER_MODULE: + print('endmodule in weird place in {}.'.format(cell.name, fname)) + sys.exit(1) + state = State.OUTSIDE + elif l.startswith(('input ', 'output ', 'inout ')) and state == State.IN_MODULE: + if l.endswith((';', ',')): + l = l[:-1] + if ';' in l: + print('Weird port line in {} [{}].'.format(fname, l)) + sys.exit(1) + kind, _, ports = l.partition(' ') + for port in ports.split(','): + port = port.strip() + if port.startswith('['): + rng, port = port.split() else: - outf.write(' {} {} {};\n'.format(kind, rng, port)) - outf.write(l + '\n') - outf.write('\n') - elif state != State.IN_OTHER_MODULE: - print('endmodule in weird place in {}.'.format(cell.name, fname)) - sys.exit(1) - state = State.OUTSIDE - elif l.startswith(('input ', 'output ', 'inout ')) and state == State.IN_MODULE: - if l.endswith((';', ',')): - l = l[:-1] - if ';' in l: - print('Weird port line in {} [{}].'.format(fname, l)) - sys.exit(1) - kind, _, ports = l.partition(' ') - for port in ports.split(','): - port = port.strip() - if port.startswith('['): - rng, port = port.split() - else: - rng = None - module_ports.append((kind, rng, port)) - elif l.startswith('parameter ') and state == State.IN_MODULE: - if 'UNPLACED' in l: - continue - if l.endswith((';', ',')): - l = l[:-1] - while ' ' in l: - l = l.replace(' ', ' ') - if ';' in l: - print('Weird parameter line in {} [{}].'.format(fname, l)) - sys.exit(1) - outf.write(' {};\n'.format(l)) - match = re.search('IS_([a-zA-Z0-9_]+)_INVERTED', l) - if match: - invertible_ports.add(match[1]) - if state != State.OUTSIDE: - print('endmodule not found in {}.'.format(fname)) - sys.exit(1) - if not found: - print('Cannot find module {} in {}.'.format(cell.name, fname)) - sys.exit(1) - return - except FileNotFoundError: - continue + rng = None + module_ports.append((kind, rng, port)) + elif l.startswith('parameter ') and state == State.IN_MODULE: + if 'UNPLACED' in l: + continue + if l.endswith((';', ',')): + l = l[:-1] + while ' ' in l: + l = l.replace(' ', ' ') + if ';' in l: + print('Weird parameter line in {} [{}].'.format(fname, l)) + sys.exit(1) + outf.write(' {};\n'.format(l)) + match = re.search('IS_([a-zA-Z0-9_]+)_INVERTED', l) + if match: + invertible_ports.add(match[1]) + if state != State.OUTSIDE: + print('endmodule not found in {}.'.format(fname)) + sys.exit(1) + if not found: + print('Cannot find module {} in {}.'.format(cell.name, fname)) + sys.exit(1) + return + except FileNotFoundError: + continue print('Cannot find {}.'.format(cell.name)) sys.exit(1) @@ -659,6 +693,7 @@ if __name__ == '__main__': dirs = [ os.path.join(args.vivado_dir, 'data/verilog/src/xeclib'), + os.path.join(args.vivado_dir, 'data/verilog/src/unisims'), os.path.join(args.vivado_dir, 'data/verilog/src/retarget'), os.path.join(args.ise_dir, 'ISE_DS/ISE/verilog/xeclib/unisims'), ] diff --git a/techlibs/xilinx/cells_xtra.v b/techlibs/xilinx/cells_xtra.v index 3021f6b5a..1187101fd 100644 --- a/techlibs/xilinx/cells_xtra.v +++ b/techlibs/xilinx/cells_xtra.v @@ -5301,6 +5301,34 @@ module DSP48E2 (...); input RSTP; endmodule +module FDDRCPE (...); + parameter INIT = 1'b0; + (* clkbuf_sink *) + input C0; + (* clkbuf_sink *) + input C1; + input CE; + input D0; + input D1; + input CLR; + input PRE; + output Q; +endmodule + +module FDDRRSE (...); + parameter INIT = 1'b0; + output Q; + (* clkbuf_sink *) + input C0; + (* clkbuf_sink *) + input C1; + input CE; + input D0; + input D1; + input R; + input S; +endmodule + module IFDDRCPE (...); output Q0; output Q1; @@ -5966,6 +5994,7 @@ module OSERDESE2 (...); input TCE; endmodule +(* keep *) module PHASER_IN (...); parameter integer CLKOUT_DIV = 4; parameter DQS_BIAS_MODE = "FALSE"; @@ -6002,6 +6031,7 @@ module PHASER_IN (...); input [5:0] COUNTERLOADVAL; endmodule +(* keep *) module PHASER_IN_PHY (...); parameter BURST_MODE = "FALSE"; parameter integer CLKOUT_DIV = 4; @@ -6046,6 +6076,7 @@ module PHASER_IN_PHY (...); input [5:0] COUNTERLOADVAL; endmodule +(* keep *) module PHASER_OUT (...); parameter integer CLKOUT_DIV = 4; parameter COARSE_BYPASS = "FALSE"; @@ -6087,6 +6118,7 @@ module PHASER_OUT (...); input [8:0] COUNTERLOADVAL; endmodule +(* keep *) module PHASER_OUT_PHY (...); parameter integer CLKOUT_DIV = 4; parameter COARSE_BYPASS = "FALSE"; @@ -6133,6 +6165,7 @@ module PHASER_OUT_PHY (...); input [8:0] COUNTERLOADVAL; endmodule +(* keep *) module PHASER_REF (...); parameter [0:0] IS_RST_INVERTED = 1'b0; parameter [0:0] IS_PWRDWN_INVERTED = 1'b0; @@ -6144,6 +6177,7 @@ module PHASER_REF (...); input RST; endmodule +(* keep *) module PHY_CONTROL (...); parameter integer AO_TOGGLE = 0; parameter [3:0] AO_WRLVL_EN = 4'b0000; @@ -6224,6 +6258,7 @@ module ODDRE1 (...); parameter [0:0] IS_C_INVERTED = 1'b0; parameter [0:0] IS_D1_INVERTED = 1'b0; parameter [0:0] IS_D2_INVERTED = 1'b0; + parameter SIM_DEVICE = "ULTRASCALE"; parameter [0:0] SRVAL = 1'b0; output Q; (* clkbuf_sink *) @@ -6437,6 +6472,7 @@ module BITSLICE_CONTROL (...); input [39:0] TX_BIT_CTRL_IN_TRI; endmodule +(* keep *) module RIU_OR (...); parameter SIM_DEVICE = "ULTRASCALE"; parameter real SIM_VERSION = 2.0; @@ -7246,6 +7282,7 @@ module DCIRESET (...); input RST; endmodule +(* keep *) module HPIO_VREF (...); parameter VREF_CNTR = "OFF"; output VREF; @@ -7256,6 +7293,8 @@ module BUFGCE (...); parameter CE_TYPE = "SYNC"; parameter [0:0] IS_CE_INVERTED = 1'b0; parameter [0:0] IS_I_INVERTED = 1'b0; + parameter SIM_DEVICE = "ULTRASCALE"; + parameter STARTUP_SYNC = "FALSE"; (* clkbuf_driver *) output O; (* invertible_pin = "IS_CE_INVERTED" *) @@ -7306,6 +7345,8 @@ module BUFGMUX_VIRTEX4 (...); endmodule module BUFG_GT (...); + parameter SIM_DEVICE = "ULTRASCALE"; + parameter STARTUP_SYNC = "FALSE"; (* clkbuf_driver *) output O; input CE; @@ -7325,6 +7366,8 @@ module BUFG_GT_SYNC (...); endmodule module BUFG_PS (...); + parameter SIM_DEVICE = "ULTRASCALE_PLUS"; + parameter STARTUP_SYNC = "FALSE"; (* clkbuf_driver *) output O; input I; @@ -7332,9 +7375,13 @@ endmodule module BUFGCE_DIV (...); parameter integer BUFGCE_DIVIDE = 1; + parameter CE_TYPE = "SYNC"; + parameter HARDSYNC_CLR = "FALSE"; parameter [0:0] IS_CE_INVERTED = 1'b0; parameter [0:0] IS_CLR_INVERTED = 1'b0; parameter [0:0] IS_I_INVERTED = 1'b0; + parameter SIM_DEVICE = "ULTRASCALE"; + parameter STARTUP_SYNC = "FALSE"; (* clkbuf_driver *) output O; (* invertible_pin = "IS_CE_INVERTED" *) @@ -7931,14 +7978,18 @@ module MMCM_BASE (...); endmodule module MMCME2_ADV (...); + parameter real CLKIN_FREQ_MAX = 1066.000; + parameter real CLKIN_FREQ_MIN = 10.000; + parameter real CLKPFD_FREQ_MAX = 550.000; + parameter real CLKPFD_FREQ_MIN = 10.000; + parameter real VCOCLK_FREQ_MAX = 1600.000; + parameter real VCOCLK_FREQ_MIN = 600.000; parameter BANDWIDTH = "OPTIMIZED"; parameter real CLKFBOUT_MULT_F = 5.000; parameter real CLKFBOUT_PHASE = 0.000; parameter CLKFBOUT_USE_FINE_PS = "FALSE"; parameter real CLKIN1_PERIOD = 0.000; parameter real CLKIN2_PERIOD = 0.000; - parameter real CLKIN_FREQ_MAX = 1066.000; - parameter real CLKIN_FREQ_MIN = 10.000; parameter real CLKOUT0_DIVIDE_F = 1.000; parameter real CLKOUT0_DUTY_CYCLE = 0.500; parameter real CLKOUT0_PHASE = 0.000; @@ -7968,8 +8019,6 @@ module MMCME2_ADV (...); parameter real CLKOUT6_DUTY_CYCLE = 0.500; parameter real CLKOUT6_PHASE = 0.000; parameter CLKOUT6_USE_FINE_PS = "FALSE"; - parameter real CLKPFD_FREQ_MAX = 550.000; - parameter real CLKPFD_FREQ_MIN = 10.000; parameter COMPENSATION = "ZHOLD"; parameter integer DIVCLK_DIVIDE = 1; parameter [0:0] IS_CLKINSEL_INVERTED = 1'b0; @@ -7983,9 +8032,6 @@ module MMCME2_ADV (...); parameter SS_MODE = "CENTER_HIGH"; parameter integer SS_MOD_PERIOD = 10000; parameter STARTUP_WAIT = "FALSE"; - parameter real VCOCLK_FREQ_MAX = 1600.000; - parameter real VCOCLK_FREQ_MIN = 600.000; - parameter STARTUP_WAIT = "FALSE"; output CLKFBOUT; output CLKFBOUTB; output CLKFBSTOPPED; @@ -8181,14 +8227,18 @@ module PLLE2_BASE (...); endmodule module MMCME3_ADV (...); + parameter real CLKIN_FREQ_MAX = 1066.000; + parameter real CLKIN_FREQ_MIN = 10.000; + parameter real CLKPFD_FREQ_MAX = 550.000; + parameter real CLKPFD_FREQ_MIN = 10.000; + parameter real VCOCLK_FREQ_MAX = 1600.000; + parameter real VCOCLK_FREQ_MIN = 600.000; parameter BANDWIDTH = "OPTIMIZED"; parameter real CLKFBOUT_MULT_F = 5.000; parameter real CLKFBOUT_PHASE = 0.000; parameter CLKFBOUT_USE_FINE_PS = "FALSE"; parameter real CLKIN1_PERIOD = 0.000; parameter real CLKIN2_PERIOD = 0.000; - parameter real CLKIN_FREQ_MAX = 1066.000; - parameter real CLKIN_FREQ_MIN = 10.000; parameter real CLKOUT0_DIVIDE_F = 1.000; parameter real CLKOUT0_DUTY_CYCLE = 0.500; parameter real CLKOUT0_PHASE = 0.000; @@ -8218,8 +8268,6 @@ module MMCME3_ADV (...); parameter real CLKOUT6_DUTY_CYCLE = 0.500; parameter real CLKOUT6_PHASE = 0.000; parameter CLKOUT6_USE_FINE_PS = "FALSE"; - parameter real CLKPFD_FREQ_MAX = 550.000; - parameter real CLKPFD_FREQ_MIN = 10.000; parameter COMPENSATION = "AUTO"; parameter integer DIVCLK_DIVIDE = 1; parameter [0:0] IS_CLKFBIN_INVERTED = 1'b0; @@ -8236,9 +8284,6 @@ module MMCME3_ADV (...); parameter SS_MODE = "CENTER_HIGH"; parameter integer SS_MOD_PERIOD = 10000; parameter STARTUP_WAIT = "FALSE"; - parameter real VCOCLK_FREQ_MAX = 1600.000; - parameter real VCOCLK_FREQ_MIN = 600.000; - parameter STARTUP_WAIT = "FALSE"; output CDDCDONE; output CLKFBOUT; output CLKFBOUTB; @@ -8343,10 +8388,14 @@ module MMCME3_BASE (...); endmodule module PLLE3_ADV (...); - parameter integer CLKFBOUT_MULT = 5; - parameter real CLKFBOUT_PHASE = 0.000; parameter real CLKIN_FREQ_MAX = 1066.000; parameter real CLKIN_FREQ_MIN = 70.000; + parameter real CLKPFD_FREQ_MAX = 667.500; + parameter real CLKPFD_FREQ_MIN = 70.000; + parameter real VCOCLK_FREQ_MAX = 1335.000; + parameter real VCOCLK_FREQ_MIN = 600.000; + parameter integer CLKFBOUT_MULT = 5; + parameter real CLKFBOUT_PHASE = 0.000; parameter real CLKIN_PERIOD = 0.000; parameter integer CLKOUT0_DIVIDE = 1; parameter real CLKOUT0_DUTY_CYCLE = 0.500; @@ -8355,8 +8404,6 @@ module PLLE3_ADV (...); parameter real CLKOUT1_DUTY_CYCLE = 0.500; parameter real CLKOUT1_PHASE = 0.000; parameter CLKOUTPHY_MODE = "VCO_2X"; - parameter real CLKPFD_FREQ_MAX = 667.500; - parameter real CLKPFD_FREQ_MIN = 70.000; parameter COMPENSATION = "AUTO"; parameter integer DIVCLK_DIVIDE = 1; parameter [0:0] IS_CLKFBIN_INVERTED = 1'b0; @@ -8365,9 +8412,6 @@ module PLLE3_ADV (...); parameter [0:0] IS_RST_INVERTED = 1'b0; parameter real REF_JITTER = 0.010; parameter STARTUP_WAIT = "FALSE"; - parameter real VCOCLK_FREQ_MAX = 1335.000; - parameter real VCOCLK_FREQ_MIN = 600.000; - parameter STARTUP_WAIT = "FALSE"; output CLKFBOUT; output CLKOUT0; output CLKOUT0B; @@ -8430,14 +8474,18 @@ module PLLE3_BASE (...); endmodule module MMCME4_ADV (...); + parameter real CLKIN_FREQ_MAX = 1066.000; + parameter real CLKIN_FREQ_MIN = 10.000; + parameter real CLKPFD_FREQ_MAX = 550.000; + parameter real CLKPFD_FREQ_MIN = 10.000; + parameter real VCOCLK_FREQ_MAX = 1600.000; + parameter real VCOCLK_FREQ_MIN = 800.000; parameter BANDWIDTH = "OPTIMIZED"; parameter real CLKFBOUT_MULT_F = 5.000; parameter real CLKFBOUT_PHASE = 0.000; parameter CLKFBOUT_USE_FINE_PS = "FALSE"; parameter real CLKIN1_PERIOD = 0.000; parameter real CLKIN2_PERIOD = 0.000; - parameter real CLKIN_FREQ_MAX = 1066.000; - parameter real CLKIN_FREQ_MIN = 10.000; parameter real CLKOUT0_DIVIDE_F = 1.000; parameter real CLKOUT0_DUTY_CYCLE = 0.500; parameter real CLKOUT0_PHASE = 0.000; @@ -8467,8 +8515,6 @@ module MMCME4_ADV (...); parameter real CLKOUT6_DUTY_CYCLE = 0.500; parameter real CLKOUT6_PHASE = 0.000; parameter CLKOUT6_USE_FINE_PS = "FALSE"; - parameter real CLKPFD_FREQ_MAX = 550.000; - parameter real CLKPFD_FREQ_MIN = 10.000; parameter COMPENSATION = "AUTO"; parameter integer DIVCLK_DIVIDE = 1; parameter [0:0] IS_CLKFBIN_INVERTED = 1'b0; @@ -8485,9 +8531,6 @@ module MMCME4_ADV (...); parameter SS_MODE = "CENTER_HIGH"; parameter integer SS_MOD_PERIOD = 10000; parameter STARTUP_WAIT = "FALSE"; - parameter real VCOCLK_FREQ_MAX = 1600.000; - parameter real VCOCLK_FREQ_MIN = 800.000; - parameter STARTUP_WAIT = "FALSE"; output CDDCDONE; output CLKFBOUT; output CLKFBOUTB; @@ -8592,10 +8635,14 @@ module MMCME4_BASE (...); endmodule module PLLE4_ADV (...); - parameter integer CLKFBOUT_MULT = 5; - parameter real CLKFBOUT_PHASE = 0.000; parameter real CLKIN_FREQ_MAX = 1066.000; parameter real CLKIN_FREQ_MIN = 70.000; + parameter real CLKPFD_FREQ_MAX = 667.500; + parameter real CLKPFD_FREQ_MIN = 70.000; + parameter real VCOCLK_FREQ_MAX = 1500.000; + parameter real VCOCLK_FREQ_MIN = 750.000; + parameter integer CLKFBOUT_MULT = 5; + parameter real CLKFBOUT_PHASE = 0.000; parameter real CLKIN_PERIOD = 0.000; parameter integer CLKOUT0_DIVIDE = 1; parameter real CLKOUT0_DUTY_CYCLE = 0.500; @@ -8604,8 +8651,6 @@ module PLLE4_ADV (...); parameter real CLKOUT1_DUTY_CYCLE = 0.500; parameter real CLKOUT1_PHASE = 0.000; parameter CLKOUTPHY_MODE = "VCO_2X"; - parameter real CLKPFD_FREQ_MAX = 667.500; - parameter real CLKPFD_FREQ_MIN = 70.000; parameter COMPENSATION = "AUTO"; parameter integer DIVCLK_DIVIDE = 1; parameter [0:0] IS_CLKFBIN_INVERTED = 1'b0; @@ -8614,9 +8659,6 @@ module PLLE4_ADV (...); parameter [0:0] IS_RST_INVERTED = 1'b0; parameter real REF_JITTER = 0.010; parameter STARTUP_WAIT = "FALSE"; - parameter real VCOCLK_FREQ_MAX = 1500.000; - parameter real VCOCLK_FREQ_MIN = 750.000; - parameter STARTUP_WAIT = "FALSE"; output CLKFBOUT; output CLKOUT0; output CLKOUT0B; @@ -9198,6 +9240,18 @@ module FRAME_ECCE3 (...); input ICAPTOPCLK; endmodule +module FRAME_ECCE4 (...); + output CRCERROR; + output ECCERRORNOTSINGLE; + output ECCERRORSINGLE; + output ENDOFFRAME; + output ENDOFSCAN; + output [26:0] FAR; + input [1:0] FARSEL; + input ICAPBOTCLK; + input ICAPTOPCLK; +endmodule + module USR_ACCESS_VIRTEX4 (...); output [31:0] DATA; output DATAVALID; @@ -9263,6 +9317,7 @@ module EFUSE_USR (...); output [31:0] EFUSEUSR; endmodule +(* keep *) module SYSMON (...); parameter [15:0] INIT_40 = 16'h0; parameter [15:0] INIT_41 = 16'h0; @@ -9315,6 +9370,7 @@ module SYSMON (...); input [6:0] DADDR; endmodule +(* keep *) module XADC (...); parameter [15:0] INIT_40 = 16'h0; parameter [15:0] INIT_41 = 16'h0; @@ -9380,6 +9436,7 @@ module XADC (...); input [6:0] DADDR; endmodule +(* keep *) module SYSMONE1 (...); parameter [15:0] INIT_40 = 16'h0; parameter [15:0] INIT_41 = 16'h0; @@ -9488,6 +9545,7 @@ module SYSMONE1 (...); input VP; endmodule +(* keep *) module SYSMONE4 (...); parameter [15:0] COMMON_N_SOURCE = 16'hFFFF; parameter [15:0] INIT_40 = 16'h0000; @@ -15129,13 +15187,13 @@ module GTHE3_COMMON (...); input RCALENB; endmodule -module GTHE4_CHANNEL (...); +module GTYE3_CHANNEL (...); parameter [0:0] ACJTAG_DEBUG_MODE = 1'b0; parameter [0:0] ACJTAG_MODE = 1'b0; parameter [0:0] ACJTAG_RESET = 1'b0; parameter [15:0] ADAPT_CFG0 = 16'h9200; parameter [15:0] ADAPT_CFG1 = 16'h801C; - parameter [15:0] ADAPT_CFG2 = 16'h0000; + parameter [15:0] ADAPT_CFG2 = 16'b0000000000000000; parameter ALIGN_COMMA_DOUBLE = "FALSE"; parameter [9:0] ALIGN_COMMA_ENABLE = 10'b0001111111; parameter integer ALIGN_COMMA_WORD = 1; @@ -15143,15 +15201,14 @@ module GTHE4_CHANNEL (...); parameter [9:0] ALIGN_MCOMMA_VALUE = 10'b1010000011; parameter ALIGN_PCOMMA_DET = "TRUE"; parameter [9:0] ALIGN_PCOMMA_VALUE = 10'b0101111100; + parameter [0:0] AUTO_BW_SEL_BYPASS = 1'b0; parameter [0:0] A_RXOSCALRESET = 1'b0; parameter [0:0] A_RXPROGDIVRESET = 1'b0; - parameter [0:0] A_RXTERMINATION = 1'b1; parameter [4:0] A_TXDIFFCTRL = 5'b01100; parameter [0:0] A_TXPROGDIVRESET = 1'b0; parameter [0:0] CAPBYPASS_FORCE = 1'b0; parameter CBCC_DATA_SOURCE_SEL = "DECODED"; parameter [0:0] CDR_SWAP_MODE_EN = 1'b0; - parameter [0:0] CFOK_PWRSVE_EN = 1'b1; parameter CHAN_BOND_KEEP_ALIGN = "FALSE"; parameter integer CHAN_BOND_MAX_SKEW = 7; parameter [9:0] CHAN_BOND_SEQ_1_1 = 10'b0101111100; @@ -15166,7 +15223,7 @@ module GTHE4_CHANNEL (...); parameter [3:0] CHAN_BOND_SEQ_2_ENABLE = 4'b1111; parameter CHAN_BOND_SEQ_2_USE = "FALSE"; parameter integer CHAN_BOND_SEQ_LEN = 2; - parameter [15:0] CH_HSPMUX = 16'h2424; + parameter [15:0] CH_HSPMUX = 16'h0000; parameter [15:0] CKCAL1_CFG_0 = 16'b0000000000000000; parameter [15:0] CKCAL1_CFG_1 = 16'b0000000000000000; parameter [15:0] CKCAL1_CFG_2 = 16'b0000000000000000; @@ -15176,7 +15233,7 @@ module GTHE4_CHANNEL (...); parameter [15:0] CKCAL2_CFG_2 = 16'b0000000000000000; parameter [15:0] CKCAL2_CFG_3 = 16'b0000000000000000; parameter [15:0] CKCAL2_CFG_4 = 16'b0000000000000000; - parameter [15:0] CKCAL_RSVD0 = 16'h4000; + parameter [15:0] CKCAL_RSVD0 = 16'h0000; parameter [15:0] CKCAL_RSVD1 = 16'h0000; parameter CLK_CORRECT_USE = "TRUE"; parameter CLK_COR_KEEP_IDLE = "FALSE"; @@ -15196,13 +15253,14 @@ module GTHE4_CHANNEL (...); parameter [3:0] CLK_COR_SEQ_2_ENABLE = 4'b1111; parameter CLK_COR_SEQ_2_USE = "FALSE"; parameter integer CLK_COR_SEQ_LEN = 2; - parameter [15:0] CPLL_CFG0 = 16'h01FA; - parameter [15:0] CPLL_CFG1 = 16'h24A9; - parameter [15:0] CPLL_CFG2 = 16'h6807; - parameter [15:0] CPLL_CFG3 = 16'h0000; + parameter [15:0] CPLL_CFG0 = 16'h20F8; + parameter [15:0] CPLL_CFG1 = 16'hA494; + parameter [15:0] CPLL_CFG2 = 16'hF001; + parameter [5:0] CPLL_CFG3 = 6'h00; parameter integer CPLL_FBDIV = 4; parameter integer CPLL_FBDIV_45 = 4; parameter [15:0] CPLL_INIT_CFG0 = 16'h001E; + parameter [7:0] CPLL_INIT_CFG1 = 8'h00; parameter [15:0] CPLL_LOCK_CFG = 16'h01E8; parameter integer CPLL_REFCLK_DIV = 1; parameter [2:0] CTLE3_OCAP_EXT_CTRL = 3'b000; @@ -15212,14 +15270,16 @@ module GTHE4_CHANNEL (...); parameter DEC_MCOMMA_DETECT = "TRUE"; parameter DEC_PCOMMA_DETECT = "TRUE"; parameter DEC_VALID_COMMA_ONLY = "TRUE"; - parameter [0:0] DELAY_ELEC = 1'b0; + parameter [0:0] DFE_D_X_REL_POS = 1'b0; + parameter [0:0] DFE_VCM_COMP_EN = 1'b0; parameter [9:0] DMONITOR_CFG0 = 10'h000; parameter [7:0] DMONITOR_CFG1 = 8'h00; parameter [0:0] ES_CLK_PHASE_SEL = 1'b0; parameter [5:0] ES_CONTROL = 6'b000000; parameter ES_ERRDET_EN = "FALSE"; parameter ES_EYE_SCAN_EN = "FALSE"; - parameter [11:0] ES_HORZ_OFFSET = 12'h800; + parameter [11:0] ES_HORZ_OFFSET = 12'h000; + parameter [9:0] ES_PMA_CFG = 10'b0000000000; parameter [4:0] ES_PRESCALE = 5'b00000; parameter [15:0] ES_QUALIFIER0 = 16'h0000; parameter [15:0] ES_QUALIFIER1 = 16'h0000; @@ -15251,19 +15311,32 @@ module GTHE4_CHANNEL (...); parameter [15:0] ES_SDATA_MASK7 = 16'h0000; parameter [15:0] ES_SDATA_MASK8 = 16'h0000; parameter [15:0] ES_SDATA_MASK9 = 16'h0000; + parameter [10:0] EVODD_PHI_CFG = 11'b00000000000; parameter [0:0] EYE_SCAN_SWAP_EN = 1'b0; parameter [3:0] FTS_DESKEW_SEQ_ENABLE = 4'b1111; parameter [3:0] FTS_LANE_DESKEW_CFG = 4'b1111; parameter FTS_LANE_DESKEW_EN = "FALSE"; parameter [4:0] GEARBOX_MODE = 5'b00000; + parameter [0:0] GM_BIAS_SELECT = 1'b0; parameter [0:0] ISCAN_CK_PH_SEL2 = 1'b0; parameter [0:0] LOCAL_MASTER = 1'b0; + parameter [15:0] LOOP0_CFG = 16'h0000; + parameter [15:0] LOOP10_CFG = 16'h0000; + parameter [15:0] LOOP11_CFG = 16'h0000; + parameter [15:0] LOOP12_CFG = 16'h0000; + parameter [15:0] LOOP13_CFG = 16'h0000; + parameter [15:0] LOOP1_CFG = 16'h0000; + parameter [15:0] LOOP2_CFG = 16'h0000; + parameter [15:0] LOOP3_CFG = 16'h0000; + parameter [15:0] LOOP4_CFG = 16'h0000; + parameter [15:0] LOOP5_CFG = 16'h0000; + parameter [15:0] LOOP6_CFG = 16'h0000; + parameter [15:0] LOOP7_CFG = 16'h0000; + parameter [15:0] LOOP8_CFG = 16'h0000; + parameter [15:0] LOOP9_CFG = 16'h0000; parameter [2:0] LPBK_BIAS_CTRL = 3'b000; parameter [0:0] LPBK_EN_RCAL_B = 1'b0; parameter [3:0] LPBK_EXT_RCAL = 4'b0000; - parameter [2:0] LPBK_IND_CTRL0 = 3'b000; - parameter [2:0] LPBK_IND_CTRL1 = 3'b000; - parameter [2:0] LPBK_IND_CTRL2 = 3'b000; parameter [3:0] LPBK_RG_CTRL = 4'b0000; parameter [1:0] OOBDIVCTL = 2'b00; parameter [0:0] OOB_PWRUP = 1'b0; @@ -15276,32 +15349,25 @@ module GTHE4_CHANNEL (...); parameter [5:0] PCI3_RX_ELECIDLE_HI_COUNT = 6'b000000; parameter [0:0] PCI3_RX_ELECIDLE_LP4_DISABLE = 1'b0; parameter [0:0] PCI3_RX_FIFO_DISABLE = 1'b0; - parameter [4:0] PCIE3_CLK_COR_EMPTY_THRSH = 5'b00000; - parameter [5:0] PCIE3_CLK_COR_FULL_THRSH = 6'b010000; - parameter [4:0] PCIE3_CLK_COR_MAX_LAT = 5'b01000; - parameter [4:0] PCIE3_CLK_COR_MIN_LAT = 5'b00100; - parameter [5:0] PCIE3_CLK_COR_THRSH_TIMER = 6'b001000; parameter [15:0] PCIE_BUFG_DIV_CTRL = 16'h0000; - parameter [1:0] PCIE_PLL_SEL_MODE_GEN12 = 2'h0; - parameter [1:0] PCIE_PLL_SEL_MODE_GEN3 = 2'h0; - parameter [1:0] PCIE_PLL_SEL_MODE_GEN4 = 2'h0; parameter [15:0] PCIE_RXPCS_CFG_GEN3 = 16'h0000; parameter [15:0] PCIE_RXPMA_CFG = 16'h0000; parameter [15:0] PCIE_TXPCS_CFG_GEN3 = 16'h0000; parameter [15:0] PCIE_TXPMA_CFG = 16'h0000; parameter PCS_PCIE_EN = "FALSE"; parameter [15:0] PCS_RSVD0 = 16'b0000000000000000; + parameter [2:0] PCS_RSVD1 = 3'b000; parameter [11:0] PD_TRANS_TIME_FROM_P2 = 12'h03C; parameter [7:0] PD_TRANS_TIME_NONE_P2 = 8'h19; parameter [7:0] PD_TRANS_TIME_TO_P2 = 8'h64; + parameter [1:0] PLL_SEL_MODE_GEN12 = 2'h0; + parameter [1:0] PLL_SEL_MODE_GEN3 = 2'h0; + parameter [15:0] PMA_RSV0 = 16'h0000; + parameter [15:0] PMA_RSV1 = 16'h0000; parameter integer PREIQ_FREQ_BST = 0; parameter [2:0] PROCESS_PAR = 3'b010; parameter [0:0] RATE_SW_USE_DRP = 1'b0; - parameter [0:0] RCLK_SIPO_DLY_ENB = 1'b0; - parameter [0:0] RCLK_SIPO_INV_EN = 1'b0; parameter [0:0] RESET_POWERSAVE_DISABLE = 1'b0; - parameter [2:0] RTX_BUF_CML_CTRL = 3'b010; - parameter [1:0] RTX_BUF_TERM_CTRL = 2'b00; parameter [4:0] RXBUFRESET_TIME = 5'b00001; parameter RXBUF_ADDR_MODE = "FULL"; parameter [3:0] RXBUF_EIDLE_HI_CNT = 4'b1000; @@ -15316,48 +15382,37 @@ module GTHE4_CHANNEL (...); parameter integer RXBUF_THRESH_UNDFLW = 4; parameter [4:0] RXCDRFREQRESET_TIME = 5'b00001; parameter [4:0] RXCDRPHRESET_TIME = 5'b00001; - parameter [15:0] RXCDR_CFG0 = 16'h0003; - parameter [15:0] RXCDR_CFG0_GEN3 = 16'h0003; - parameter [15:0] RXCDR_CFG1 = 16'h0000; - parameter [15:0] RXCDR_CFG1_GEN3 = 16'h0000; - parameter [15:0] RXCDR_CFG2 = 16'h0164; - parameter [9:0] RXCDR_CFG2_GEN2 = 10'h164; - parameter [15:0] RXCDR_CFG2_GEN3 = 16'h0034; - parameter [15:0] RXCDR_CFG2_GEN4 = 16'h0034; - parameter [15:0] RXCDR_CFG3 = 16'h0024; - parameter [5:0] RXCDR_CFG3_GEN2 = 6'h24; - parameter [15:0] RXCDR_CFG3_GEN3 = 16'h0024; - parameter [15:0] RXCDR_CFG3_GEN4 = 16'h0024; - parameter [15:0] RXCDR_CFG4 = 16'h5CF6; - parameter [15:0] RXCDR_CFG4_GEN3 = 16'h5CF6; - parameter [15:0] RXCDR_CFG5 = 16'hB46B; - parameter [15:0] RXCDR_CFG5_GEN3 = 16'h146B; + parameter [15:0] RXCDR_CFG0 = 16'h0000; + parameter [15:0] RXCDR_CFG0_GEN3 = 16'h0000; + parameter [15:0] RXCDR_CFG1 = 16'h0300; + parameter [15:0] RXCDR_CFG1_GEN3 = 16'h0300; + parameter [15:0] RXCDR_CFG2 = 16'h0060; + parameter [15:0] RXCDR_CFG2_GEN3 = 16'h0060; + parameter [15:0] RXCDR_CFG3 = 16'h0000; + parameter [15:0] RXCDR_CFG3_GEN3 = 16'h0000; + parameter [15:0] RXCDR_CFG4 = 16'h0002; + parameter [15:0] RXCDR_CFG4_GEN3 = 16'h0002; + parameter [15:0] RXCDR_CFG5 = 16'h0000; + parameter [15:0] RXCDR_CFG5_GEN3 = 16'h0000; parameter [0:0] RXCDR_FR_RESET_ON_EIDLE = 1'b0; parameter [0:0] RXCDR_HOLD_DURING_EIDLE = 1'b0; - parameter [15:0] RXCDR_LOCK_CFG0 = 16'h0040; - parameter [15:0] RXCDR_LOCK_CFG1 = 16'h8000; + parameter [15:0] RXCDR_LOCK_CFG0 = 16'h0001; + parameter [15:0] RXCDR_LOCK_CFG1 = 16'h0000; parameter [15:0] RXCDR_LOCK_CFG2 = 16'h0000; parameter [15:0] RXCDR_LOCK_CFG3 = 16'h0000; - parameter [15:0] RXCDR_LOCK_CFG4 = 16'h0000; parameter [0:0] RXCDR_PH_RESET_ON_EIDLE = 1'b0; - parameter [15:0] RXCFOK_CFG0 = 16'h0000; - parameter [15:0] RXCFOK_CFG1 = 16'h0002; + parameter [1:0] RXCFOKDONE_SRC = 2'b00; + parameter [15:0] RXCFOK_CFG0 = 16'h3E00; + parameter [15:0] RXCFOK_CFG1 = 16'h0042; parameter [15:0] RXCFOK_CFG2 = 16'h002D; - parameter [15:0] RXCKCAL1_IQ_LOOP_RST_CFG = 16'h0000; - parameter [15:0] RXCKCAL1_I_LOOP_RST_CFG = 16'h0000; - parameter [15:0] RXCKCAL1_Q_LOOP_RST_CFG = 16'h0000; - parameter [15:0] RXCKCAL2_DX_LOOP_RST_CFG = 16'h0000; - parameter [15:0] RXCKCAL2_D_LOOP_RST_CFG = 16'h0000; - parameter [15:0] RXCKCAL2_S_LOOP_RST_CFG = 16'h0000; - parameter [15:0] RXCKCAL2_X_LOOP_RST_CFG = 16'h0000; parameter [6:0] RXDFELPMRESET_TIME = 7'b0001111; parameter [15:0] RXDFELPM_KL_CFG0 = 16'h0000; parameter [15:0] RXDFELPM_KL_CFG1 = 16'h0022; parameter [15:0] RXDFELPM_KL_CFG2 = 16'h0100; - parameter [15:0] RXDFE_CFG0 = 16'h4000; + parameter [15:0] RXDFE_CFG0 = 16'h4C00; parameter [15:0] RXDFE_CFG1 = 16'h0000; - parameter [15:0] RXDFE_GC_CFG0 = 16'h0000; - parameter [15:0] RXDFE_GC_CFG1 = 16'h0000; + parameter [15:0] RXDFE_GC_CFG0 = 16'h1E00; + parameter [15:0] RXDFE_GC_CFG1 = 16'h1900; parameter [15:0] RXDFE_GC_CFG2 = 16'h0000; parameter [15:0] RXDFE_H2_CFG0 = 16'h0000; parameter [15:0] RXDFE_H2_CFG1 = 16'h0002; @@ -15387,31 +15442,26 @@ module GTHE4_CHANNEL (...); parameter [15:0] RXDFE_HE_CFG1 = 16'h0002; parameter [15:0] RXDFE_HF_CFG0 = 16'h0000; parameter [15:0] RXDFE_HF_CFG1 = 16'h0002; - parameter [15:0] RXDFE_KH_CFG0 = 16'h0000; - parameter [15:0] RXDFE_KH_CFG1 = 16'h0000; - parameter [15:0] RXDFE_KH_CFG2 = 16'h0000; - parameter [15:0] RXDFE_KH_CFG3 = 16'h0000; parameter [15:0] RXDFE_OS_CFG0 = 16'h0000; - parameter [15:0] RXDFE_OS_CFG1 = 16'h0002; + parameter [15:0] RXDFE_OS_CFG1 = 16'h0200; parameter [0:0] RXDFE_PWR_SAVING = 1'b0; parameter [15:0] RXDFE_UT_CFG0 = 16'h0000; parameter [15:0] RXDFE_UT_CFG1 = 16'h0002; - parameter [15:0] RXDFE_UT_CFG2 = 16'h0000; parameter [15:0] RXDFE_VP_CFG0 = 16'h0000; parameter [15:0] RXDFE_VP_CFG1 = 16'h0022; - parameter [15:0] RXDLY_CFG = 16'h0010; + parameter [15:0] RXDLY_CFG = 16'h001F; parameter [15:0] RXDLY_LCFG = 16'h0030; parameter RXELECIDLE_CFG = "SIGCFG_4"; parameter integer RXGBOX_FIFO_INIT_RD_ADDR = 4; parameter RXGEARBOX_EN = "FALSE"; parameter [4:0] RXISCANRESET_TIME = 5'b00001; parameter [15:0] RXLPM_CFG = 16'h0000; - parameter [15:0] RXLPM_GC_CFG = 16'h1000; + parameter [15:0] RXLPM_GC_CFG = 16'h0200; parameter [15:0] RXLPM_KH_CFG0 = 16'h0000; parameter [15:0] RXLPM_KH_CFG1 = 16'h0002; - parameter [15:0] RXLPM_OS_CFG0 = 16'h0000; + parameter [15:0] RXLPM_OS_CFG0 = 16'h0400; parameter [15:0] RXLPM_OS_CFG1 = 16'h0000; - parameter [8:0] RXOOB_CFG = 9'b000110000; + parameter [8:0] RXOOB_CFG = 9'b000000110; parameter RXOOB_CLK_CFG = "PMA"; parameter [4:0] RXOSCALRESET_TIME = 5'b00011; parameter integer RXOUT_DIV = 4; @@ -15422,9 +15472,9 @@ module GTHE4_CHANNEL (...); parameter [15:0] RXPHSLIP_CFG = 16'h9933; parameter [4:0] RXPH_MONITOR_SEL = 5'b00000; parameter [0:0] RXPI_AUTO_BW_SEL_BYPASS = 1'b0; - parameter [15:0] RXPI_CFG0 = 16'h0002; - parameter [15:0] RXPI_CFG1 = 16'b0000000000000000; + parameter [15:0] RXPI_CFG = 16'h0100; parameter [0:0] RXPI_LPM = 1'b0; + parameter [15:0] RXPI_RSV0 = 16'h0000; parameter [1:0] RXPI_SEL_LC = 2'b00; parameter [1:0] RXPI_STARTCODE = 2'b00; parameter [0:0] RXPI_VREFSEL = 1'b0; @@ -15432,14 +15482,13 @@ module GTHE4_CHANNEL (...); parameter [4:0] RXPMARESET_TIME = 5'b00001; parameter [0:0] RXPRBS_ERR_LOOPBACK = 1'b0; parameter integer RXPRBS_LINKACQ_CNT = 15; - parameter [0:0] RXREFCLKDIV2_SEL = 1'b0; parameter integer RXSLIDE_AUTO_WAIT = 7; parameter RXSLIDE_MODE = "OFF"; parameter [0:0] RXSYNC_MULTILANE = 1'b0; parameter [0:0] RXSYNC_OVRD = 1'b0; parameter [0:0] RXSYNC_SKIP_DA = 1'b0; parameter [0:0] RX_AFE_CM_EN = 1'b0; - parameter [15:0] RX_BIAS_CFG0 = 16'h12B0; + parameter [15:0] RX_BIAS_CFG0 = 16'h1534; parameter [5:0] RX_BUFFER_CFG = 6'b000000; parameter [0:0] RX_CAPFF_SARC_ENB = 1'b0; parameter integer RX_CLK25_DIV = 8; @@ -15448,27 +15497,29 @@ module GTHE4_CHANNEL (...); parameter [3:0] RX_CM_BUF_CFG = 4'b1010; parameter [0:0] RX_CM_BUF_PD = 1'b0; parameter integer RX_CM_SEL = 3; - parameter integer RX_CM_TRIM = 12; - parameter [7:0] RX_CTLE3_LPF = 8'b00000000; + parameter integer RX_CM_TRIM = 10; + parameter [0:0] RX_CTLE1_KHKL = 1'b0; + parameter [0:0] RX_CTLE2_KHKL = 1'b0; + parameter [0:0] RX_CTLE3_AGC = 1'b0; parameter integer RX_DATA_WIDTH = 20; parameter [5:0] RX_DDI_SEL = 6'b000000; parameter RX_DEFER_RESET_BUF_EN = "TRUE"; - parameter [2:0] RX_DEGEN_CTRL = 3'b011; - parameter integer RX_DFELPM_CFG0 = 0; - parameter [0:0] RX_DFELPM_CFG1 = 1'b1; + parameter [2:0] RX_DEGEN_CTRL = 3'b010; + parameter integer RX_DFELPM_CFG0 = 6; + parameter [0:0] RX_DFELPM_CFG1 = 1'b0; parameter [0:0] RX_DFELPM_KLKH_AGC_STUP_EN = 1'b1; parameter [1:0] RX_DFE_AGC_CFG0 = 2'b00; parameter integer RX_DFE_AGC_CFG1 = 4; parameter integer RX_DFE_KL_LPM_KH_CFG0 = 1; - parameter integer RX_DFE_KL_LPM_KH_CFG1 = 4; + parameter integer RX_DFE_KL_LPM_KH_CFG1 = 2; parameter [1:0] RX_DFE_KL_LPM_KL_CFG0 = 2'b01; - parameter integer RX_DFE_KL_LPM_KL_CFG1 = 4; + parameter [2:0] RX_DFE_KL_LPM_KL_CFG1 = 3'b010; parameter [0:0] RX_DFE_LPM_HOLD_DURING_EIDLE = 1'b0; parameter RX_DISPERR_SEQ_MATCH = "TRUE"; parameter [0:0] RX_DIV2_MODE_B = 1'b0; parameter [4:0] RX_DIVRESET_TIME = 5'b00001; parameter [0:0] RX_EN_CTLE_RCAL_B = 1'b0; - parameter [0:0] RX_EN_HI_LR = 1'b1; + parameter [0:0] RX_EN_HI_LR = 1'b0; parameter [8:0] RX_EXT_RL_CTRL = 9'b000000000; parameter [6:0] RX_EYESCAN_VS_CODE = 7'b0000000; parameter [0:0] RX_EYESCAN_VS_NEG_DIR = 1'b0; @@ -15477,7 +15528,6 @@ module GTHE4_CHANNEL (...); parameter [0:0] RX_FABINT_USRCLK_FLOP = 1'b0; parameter integer RX_INT_DATAWIDTH = 1; parameter [0:0] RX_PMA_POWER_SAVE = 1'b0; - parameter [15:0] RX_PMA_RSV0 = 16'h0000; parameter real RX_PROGDIV_CFG = 0.0; parameter [15:0] RX_PROGDIV_RATE = 16'h0001; parameter [3:0] RX_RESLOAD_CTRL = 4'b0000; @@ -15485,32 +15535,34 @@ module GTHE4_CHANNEL (...); parameter [2:0] RX_SAMPLE_PERIOD = 3'b101; parameter integer RX_SIG_VALID_DLY = 11; parameter [0:0] RX_SUM_DFETAPREP_EN = 1'b0; - parameter [3:0] RX_SUM_IREF_TUNE = 4'b1001; - parameter [3:0] RX_SUM_RESLOAD_CTRL = 4'b0000; - parameter [3:0] RX_SUM_VCMTUNE = 4'b1010; + parameter [3:0] RX_SUM_IREF_TUNE = 4'b0000; + parameter [3:0] RX_SUM_VCMTUNE = 4'b1000; parameter [0:0] RX_SUM_VCM_OVWR = 1'b0; parameter [2:0] RX_SUM_VREF_TUNE = 3'b100; parameter [1:0] RX_TUNE_AFE_OS = 2'b00; parameter [2:0] RX_VREG_CTRL = 3'b101; parameter [0:0] RX_VREG_PDB = 1'b1; parameter [1:0] RX_WIDEMODE_CDR = 2'b01; - parameter [1:0] RX_WIDEMODE_CDR_GEN3 = 2'b01; - parameter [1:0] RX_WIDEMODE_CDR_GEN4 = 2'b01; parameter RX_XCLK_SEL = "RXDES"; parameter [0:0] RX_XMODE_SEL = 1'b0; - parameter [0:0] SAMPLE_CLK_PHASE = 1'b0; - parameter [0:0] SAS_12G_MODE = 1'b0; + parameter integer SAS_MAX_COM = 64; + parameter integer SAS_MIN_COM = 36; parameter [3:0] SATA_BURST_SEQ_LEN = 4'b1111; parameter [2:0] SATA_BURST_VAL = 3'b100; parameter SATA_CPLL_CFG = "VCO_3000MHZ"; parameter [2:0] SATA_EIDLE_VAL = 3'b100; + parameter integer SATA_MAX_BURST = 8; + parameter integer SATA_MAX_INIT = 21; + parameter integer SATA_MAX_WAKE = 7; + parameter integer SATA_MIN_BURST = 4; + parameter integer SATA_MIN_INIT = 12; + parameter integer SATA_MIN_WAKE = 4; parameter SHOW_REALIGN_COMMA = "TRUE"; - parameter SIM_DEVICE = "ULTRASCALE_PLUS"; parameter SIM_MODE = "FAST"; parameter SIM_RECEIVER_DETECT_PASS = "TRUE"; parameter SIM_RESET_SPEEDUP = "TRUE"; - parameter SIM_TX_EIDLE_DRIVE_LEVEL = "Z"; - parameter [0:0] SRSTMODE = 1'b0; + parameter [0:0] SIM_TX_EIDLE_DRIVE_LEVEL = 1'b0; + parameter integer SIM_VERSION = 2; parameter [1:0] TAPDLY_SET_TX = 2'h0; parameter [3:0] TEMPERATURE_PAR = 4'b0010; parameter [14:0] TERM_RCAL_CFG = 15'b100001000010000; @@ -15520,20 +15572,18 @@ module GTHE4_CHANNEL (...); parameter [7:0] TST_RSV1 = 8'h00; parameter TXBUF_EN = "TRUE"; parameter TXBUF_RESET_ON_RATE_CHANGE = "FALSE"; - parameter [15:0] TXDLY_CFG = 16'h0010; + parameter [15:0] TXDLY_CFG = 16'h001F; parameter [15:0] TXDLY_LCFG = 16'h0030; - parameter [3:0] TXDRVBIAS_N = 4'b1010; parameter TXFIFO_ADDR_CFG = "LOW"; parameter integer TXGBOX_FIFO_INIT_RD_ADDR = 4; parameter TXGEARBOX_EN = "FALSE"; parameter integer TXOUT_DIV = 4; parameter [4:0] TXPCSRESET_TIME = 5'b00001; - parameter [15:0] TXPHDLY_CFG0 = 16'h6020; - parameter [15:0] TXPHDLY_CFG1 = 16'h0002; + parameter [15:0] TXPHDLY_CFG0 = 16'h2020; + parameter [15:0] TXPHDLY_CFG1 = 16'h0001; parameter [15:0] TXPH_CFG = 16'h0123; parameter [15:0] TXPH_CFG2 = 16'h0000; parameter [4:0] TXPH_MONITOR_SEL = 5'b00000; - parameter [15:0] TXPI_CFG = 16'h0000; parameter [1:0] TXPI_CFG0 = 2'b00; parameter [1:0] TXPI_CFG1 = 2'b00; parameter [1:0] TXPI_CFG2 = 2'b00; @@ -15543,29 +15593,30 @@ module GTHE4_CHANNEL (...); parameter [0:0] TXPI_GRAY_SEL = 1'b0; parameter [0:0] TXPI_INVSTROBE_SEL = 1'b0; parameter [0:0] TXPI_LPM = 1'b0; - parameter [0:0] TXPI_PPM = 1'b0; parameter TXPI_PPMCLK_SEL = "TXUSRCLK2"; parameter [7:0] TXPI_PPM_CFG = 8'b00000000; + parameter [15:0] TXPI_RSV0 = 16'h0000; parameter [2:0] TXPI_SYNFREQ_PPM = 3'b000; parameter [0:0] TXPI_VREFSEL = 1'b0; parameter [4:0] TXPMARESET_TIME = 5'b00001; - parameter [0:0] TXREFCLKDIV2_SEL = 1'b0; parameter [0:0] TXSYNC_MULTILANE = 1'b0; parameter [0:0] TXSYNC_OVRD = 1'b0; parameter [0:0] TXSYNC_SKIP_DA = 1'b0; parameter integer TX_CLK25_DIV = 8; parameter [0:0] TX_CLKMUX_EN = 1'b1; + parameter [0:0] TX_CLKREG_PDB = 1'b0; + parameter [2:0] TX_CLKREG_SET = 3'b000; parameter integer TX_DATA_WIDTH = 20; - parameter [15:0] TX_DCC_LOOP_RST_CFG = 16'h0000; + parameter [5:0] TX_DCD_CFG = 6'b000010; + parameter [0:0] TX_DCD_EN = 1'b0; parameter [5:0] TX_DEEMPH0 = 6'b000000; parameter [5:0] TX_DEEMPH1 = 6'b000000; - parameter [5:0] TX_DEEMPH2 = 6'b000000; - parameter [5:0] TX_DEEMPH3 = 6'b000000; parameter [4:0] TX_DIVRESET_TIME = 5'b00001; parameter TX_DRIVE_MODE = "DIRECT"; parameter integer TX_DRVMUX_CTRL = 2; parameter [2:0] TX_EIDLE_ASSERT_DELAY = 3'b110; parameter [2:0] TX_EIDLE_DEASSERT_DELAY = 3'b100; + parameter [0:0] TX_EML_PHI_TUNE = 1'b0; parameter [0:0] TX_FABINT_USRCLK_FLOP = 1'b0; parameter [0:0] TX_FIFO_BYP_EN = 1'b0; parameter [0:0] TX_IDLE_DATA_ZERO = 1'b0; @@ -15582,75 +15633,44 @@ module GTHE4_CHANNEL (...); parameter [6:0] TX_MARGIN_LOW_2 = 7'b1000010; parameter [6:0] TX_MARGIN_LOW_3 = 7'b1000000; parameter [6:0] TX_MARGIN_LOW_4 = 7'b1000000; + parameter [2:0] TX_MODE_SEL = 3'b000; parameter [15:0] TX_PHICAL_CFG0 = 16'h0000; - parameter [15:0] TX_PHICAL_CFG1 = 16'h003F; + parameter [15:0] TX_PHICAL_CFG1 = 16'h7E00; parameter [15:0] TX_PHICAL_CFG2 = 16'h0000; parameter integer TX_PI_BIASSET = 0; - parameter [1:0] TX_PI_IBIAS_MID = 2'b00; + parameter [15:0] TX_PI_CFG0 = 16'h0000; + parameter [15:0] TX_PI_CFG1 = 16'h0000; + parameter [0:0] TX_PI_DIV2_MODE_B = 1'b0; + parameter [0:0] TX_PI_SEL_QPLL0 = 1'b0; + parameter [0:0] TX_PI_SEL_QPLL1 = 1'b0; parameter [0:0] TX_PMADATA_OPT = 1'b0; parameter [0:0] TX_PMA_POWER_SAVE = 1'b0; - parameter [15:0] TX_PMA_RSV0 = 16'h0008; parameter integer TX_PREDRV_CTRL = 2; parameter TX_PROGCLK_SEL = "POSTPI"; parameter real TX_PROGDIV_CFG = 0.0; parameter [15:0] TX_PROGDIV_RATE = 16'h0001; - parameter [0:0] TX_QPI_STATUS_EN = 1'b0; parameter [13:0] TX_RXDETECT_CFG = 14'h0032; - parameter integer TX_RXDETECT_REF = 3; + parameter integer TX_RXDETECT_REF = 4; parameter [2:0] TX_SAMPLE_PERIOD = 3'b101; parameter [0:0] TX_SARC_LPBK_ENB = 1'b0; - parameter [1:0] TX_SW_MEAS = 2'b00; - parameter [2:0] TX_VREG_CTRL = 3'b000; - parameter [0:0] TX_VREG_PDB = 1'b0; - parameter [1:0] TX_VREG_VREFSEL = 2'b00; parameter TX_XCLK_SEL = "TXOUT"; - parameter [0:0] USB_BOTH_BURST_IDLE = 1'b0; - parameter [6:0] USB_BURSTMAX_U3WAKE = 7'b1111111; - parameter [6:0] USB_BURSTMIN_U3WAKE = 7'b1100011; - parameter [0:0] USB_CLK_COR_EQ_EN = 1'b0; - parameter [0:0] USB_EXT_CNTL = 1'b1; - parameter [9:0] USB_IDLEMAX_POLLING = 10'b1010111011; - parameter [9:0] USB_IDLEMIN_POLLING = 10'b0100101011; - parameter [8:0] USB_LFPSPING_BURST = 9'b000000101; - parameter [8:0] USB_LFPSPOLLING_BURST = 9'b000110001; - parameter [8:0] USB_LFPSPOLLING_IDLE_MS = 9'b000000100; - parameter [8:0] USB_LFPSU1EXIT_BURST = 9'b000011101; - parameter [8:0] USB_LFPSU2LPEXIT_BURST_MS = 9'b001100011; - parameter [8:0] USB_LFPSU3WAKE_BURST_MS = 9'b111110011; - parameter [3:0] USB_LFPS_TPERIOD = 4'b0011; - parameter [0:0] USB_LFPS_TPERIOD_ACCURATE = 1'b1; - parameter [0:0] USB_MODE = 1'b0; - parameter [0:0] USB_PCIE_ERR_REP_DIS = 1'b0; - parameter integer USB_PING_SATA_MAX_INIT = 21; - parameter integer USB_PING_SATA_MIN_INIT = 12; - parameter integer USB_POLL_SATA_MAX_BURST = 8; - parameter integer USB_POLL_SATA_MIN_BURST = 4; - parameter [0:0] USB_RAW_ELEC = 1'b0; - parameter [0:0] USB_RXIDLE_P0_CTRL = 1'b1; - parameter [0:0] USB_TXIDLE_TUNE_ENABLE = 1'b1; - parameter integer USB_U1_SATA_MAX_WAKE = 7; - parameter integer USB_U1_SATA_MIN_WAKE = 4; - parameter integer USB_U2_SAS_MAX_COM = 64; - parameter integer USB_U2_SAS_MIN_COM = 36; parameter [0:0] USE_PCS_CLK_PHASE_SEL = 1'b0; - parameter [0:0] Y_ALL_MODE = 1'b0; - output BUFGTCE; + output [2:0] BUFGTCE; output [2:0] BUFGTCEMASK; output [8:0] BUFGTDIV; - output BUFGTRESET; + output [2:0] BUFGTRESET; output [2:0] BUFGTRSTMASK; output CPLLFBCLKLOST; output CPLLLOCK; output CPLLREFCLKLOST; - output [15:0] DMONITOROUT; - output DMONITOROUTCLK; + output [16:0] DMONITOROUT; output [15:0] DRPDO; output DRPRDY; output EYESCANDATAERROR; - output GTHTXN; - output GTHTXP; output GTPOWERGOOD; output GTREFCLKMONITOR; + output GTYTXN; + output GTYTXP; output PCIERATEGEN3; output PCIERATEIDLE; output [1:0] PCIERATEQPLLPD; @@ -15661,8 +15681,7 @@ module GTHE4_CHANNEL (...); output PCIEUSERRATESTART; output [15:0] PCSRSVDOUT; output PHYSTATUS; - output [15:0] PINRSRVDAS; - output POWERPRESENT; + output [7:0] PINRSRVDAS; output RESETEXCEPTION; output [2:0] RXBUFSTATUS; output RXBYTEISALIGNED; @@ -15690,10 +15709,7 @@ module GTHE4_CHANNEL (...); output RXELECIDLE; output [5:0] RXHEADER; output [1:0] RXHEADERVALID; - output RXLFPSTRESETDET; - output RXLFPSU2LPEXITDET; - output RXLFPSU3WAKEDET; - output [7:0] RXMONITOROUT; + output [6:0] RXMONITOROUT; output RXOSINTDONE; output RXOSINTSTARTED; output RXOSINTSTROBEDONE; @@ -15707,8 +15723,6 @@ module GTHE4_CHANNEL (...); output RXPRBSERR; output RXPRBSLOCKED; output RXPRGDIVRESETDONE; - output RXQPISENN; - output RXQPISENP; output RXRATEDONE; output RXRECCLKOUT; output RXRESETDONE; @@ -15732,8 +15746,6 @@ module GTHE4_CHANNEL (...); output TXPHINITDONE; output TXPMARESETDONE; output TXPRGDIVRESETDONE; - output TXQPISENN; - output TXQPISENP; output TXRATEDONE; output TXRESETDONE; output TXSYNCDONE; @@ -15744,7 +15756,6 @@ module GTHE4_CHANNEL (...); input CFGRESET; input CLKRSVD0; input CLKRSVD1; - input CPLLFREQLOCK; input CPLLLOCKDETCLK; input CPLLLOCKEN; input CPLLPD; @@ -15756,64 +15767,65 @@ module GTHE4_CHANNEL (...); input DRPCLK; input [15:0] DRPDI; input DRPEN; - input DRPRST; input DRPWE; + input ELPCALDVORWREN; + input ELPCALPAORWREN; + input EVODDPHICALDONE; + input EVODDPHICALSTART; + input EVODDPHIDRDEN; + input EVODDPHIDWREN; + input EVODDPHIXRDEN; + input EVODDPHIXWREN; + input EYESCANMODE; input EYESCANRESET; input EYESCANTRIGGER; - input FREQOS; input GTGREFCLK; - input GTHRXN; - input GTHRXP; input GTNORTHREFCLK0; input GTNORTHREFCLK1; input GTREFCLK0; input GTREFCLK1; + input GTRESETSEL; input [15:0] GTRSVD; input GTRXRESET; - input GTRXRESETSEL; input GTSOUTHREFCLK0; input GTSOUTHREFCLK1; input GTTXRESET; - input GTTXRESETSEL; - input INCPCTRL; + input GTYRXN; + input GTYRXP; input [2:0] LOOPBACK; + input [15:0] LOOPRSVD; + input LPBKRXTXSEREN; + input LPBKTXRXSEREN; input PCIEEQRXEQADAPTDONE; input PCIERSTIDLE; input PCIERSTTXSYNCSTART; input PCIEUSERRATEDONE; input [15:0] PCSRSVDIN; + input [4:0] PCSRSVDIN2; + input [4:0] PMARSVDIN; input QPLL0CLK; - input QPLL0FREQLOCK; input QPLL0REFCLK; input QPLL1CLK; - input QPLL1FREQLOCK; input QPLL1REFCLK; input RESETOVRD; + input RSTCLKENTX; input RX8B10BEN; - input RXAFECFOKEN; input RXBUFRESET; input RXCDRFREQRESET; input RXCDRHOLD; input RXCDROVRDEN; input RXCDRRESET; + input RXCDRRESETRSV; input RXCHBONDEN; input [4:0] RXCHBONDI; input [2:0] RXCHBONDLEVEL; input RXCHBONDMASTER; input RXCHBONDSLAVE; input RXCKCALRESET; - input [6:0] RXCKCALSTART; input RXCOMMADETEN; - input [1:0] RXDFEAGCCTRL; + input RXDCCFORCESTART; input RXDFEAGCHOLD; input RXDFEAGCOVRDEN; - input [3:0] RXDFECFOKFCNUM; - input RXDFECFOKFEN; - input RXDFECFOKFPULSE; - input RXDFECFOKHOLD; - input RXDFECFOKOVREN; - input RXDFEKHHOLD; - input RXDFEKHOVRDEN; input RXDFELFHOLD; input RXDFELFOVRDEN; input RXDFELPMRESET; @@ -15849,13 +15861,13 @@ module GTHE4_CHANNEL (...); input RXDFEUTOVRDEN; input RXDFEVPHOLD; input RXDFEVPOVRDEN; + input RXDFEVSEN; input RXDFEXYDEN; input RXDLYBYPASS; input RXDLYEN; input RXDLYOVRDEN; input RXDLYSRESET; input [1:0] RXELECIDLEMODE; - input RXEQTRAINING; input RXGEARBOXSLIP; input RXLATCLK; input RXLPMEN; @@ -15872,6 +15884,12 @@ module GTHE4_CHANNEL (...); input RXOOBRESET; input RXOSCALRESET; input RXOSHOLD; + input [3:0] RXOSINTCFG; + input RXOSINTEN; + input RXOSINTHOLD; + input RXOSINTOVRDEN; + input RXOSINTSTROBE; + input RXOSINTTESTOVRDEN; input RXOSOVRDEN; input [2:0] RXOUTCLKSEL; input RXPCOMMAALIGNEN; @@ -15888,7 +15906,6 @@ module GTHE4_CHANNEL (...); input RXPRBSCNTRESET; input [3:0] RXPRBSSEL; input RXPROGDIVRESET; - input RXQPIEN; input [2:0] RXRATE; input RXRATEMODE; input RXSLIDE; @@ -15898,7 +15915,6 @@ module GTHE4_CHANNEL (...); input RXSYNCIN; input RXSYNCMODE; input [1:0] RXSYSCLKSEL; - input RXTERMINATION; input RXUSERRDY; input RXUSRCLK; input RXUSRCLK2; @@ -15906,6 +15922,7 @@ module GTHE4_CHANNEL (...); input [19:0] TSTIN; input [7:0] TX8B10BBYPASS; input TX8B10BEN; + input [2:0] TXBUFDIFFCTRL; input TXCOMINIT; input TXCOMSAS; input TXCOMWAKE; @@ -15916,9 +15933,10 @@ module GTHE4_CHANNEL (...); input [7:0] TXDATAEXTENDRSVD; input TXDCCFORCESTART; input TXDCCRESET; - input [1:0] TXDEEMPH; + input TXDEEMPH; input TXDETECTRX; input [4:0] TXDIFFCTRL; + input TXDIFFPD; input TXDLYBYPASS; input TXDLYEN; input TXDLYHOLD; @@ -15926,17 +15944,12 @@ module GTHE4_CHANNEL (...); input TXDLYSRESET; input TXDLYUPDOWN; input TXELECIDLE; + input TXELFORCESTART; input [5:0] TXHEADER; input TXINHIBIT; input TXLATCLK; - input TXLFPSTRESET; - input TXLFPSU2LPEXIT; - input TXLFPSU3WAKE; input [6:0] TXMAINCURSOR; input [2:0] TXMARGIN; - input TXMUXDCDEXHOLD; - input TXMUXDCDORWREN; - input TXONESZEROS; input [2:0] TXOUTCLKSEL; input TXPCSRESET; input [1:0] TXPD; @@ -15962,8 +15975,6 @@ module GTHE4_CHANNEL (...); input [3:0] TXPRBSSEL; input [4:0] TXPRECURSOR; input TXPROGDIVRESET; - input TXQPIBIASEN; - input TXQPIWEAKPUP; input [2:0] TXRATE; input TXRATEMODE; input [6:0] TXSEQUENCE; @@ -15977,34 +15988,28 @@ module GTHE4_CHANNEL (...); input TXUSRCLK2; endmodule -module GTHE4_COMMON (...); - parameter [0:0] AEN_QPLL0_FBDIV = 1'b1; - parameter [0:0] AEN_QPLL1_FBDIV = 1'b1; - parameter [0:0] AEN_SDM0TOGGLE = 1'b0; - parameter [0:0] AEN_SDM1TOGGLE = 1'b0; - parameter [0:0] A_SDM0TOGGLE = 1'b0; - parameter [8:0] A_SDM1DATA_HIGH = 9'b000000000; - parameter [15:0] A_SDM1DATA_LOW = 16'b0000000000000000; - parameter [0:0] A_SDM1TOGGLE = 1'b0; +module GTYE3_COMMON (...); + parameter [15:0] A_SDM1DATA1_0 = 16'b0000000000000000; + parameter [8:0] A_SDM1DATA1_1 = 9'b000000000; parameter [15:0] BIAS_CFG0 = 16'h0000; parameter [15:0] BIAS_CFG1 = 16'h0000; parameter [15:0] BIAS_CFG2 = 16'h0000; parameter [15:0] BIAS_CFG3 = 16'h0000; parameter [15:0] BIAS_CFG4 = 16'h0000; - parameter [15:0] BIAS_CFG_RSVD = 16'h0000; + parameter [9:0] BIAS_CFG_RSVD = 10'b0000000000; parameter [15:0] COMMON_CFG0 = 16'h0000; parameter [15:0] COMMON_CFG1 = 16'h0000; - parameter [15:0] POR_CFG = 16'h0000; - parameter [15:0] PPF0_CFG = 16'h0F00; - parameter [15:0] PPF1_CFG = 16'h0F00; + parameter [15:0] POR_CFG = 16'h0004; + parameter [15:0] PPF0_CFG = 16'h0FFF; + parameter [15:0] PPF1_CFG = 16'h0FFF; parameter QPLL0CLKOUT_RATE = "FULL"; - parameter [15:0] QPLL0_CFG0 = 16'h391C; + parameter [15:0] QPLL0_CFG0 = 16'h301C; parameter [15:0] QPLL0_CFG1 = 16'h0000; parameter [15:0] QPLL0_CFG1_G3 = 16'h0020; - parameter [15:0] QPLL0_CFG2 = 16'h0F80; - parameter [15:0] QPLL0_CFG2_G3 = 16'h0F80; + parameter [15:0] QPLL0_CFG2 = 16'h0780; + parameter [15:0] QPLL0_CFG2_G3 = 16'h0780; parameter [15:0] QPLL0_CFG3 = 16'h0120; - parameter [15:0] QPLL0_CFG4 = 16'h0002; + parameter [15:0] QPLL0_CFG4 = 16'h0021; parameter [9:0] QPLL0_CP = 10'b0000011111; parameter [9:0] QPLL0_CP_G3 = 10'b0000011111; parameter integer QPLL0_FBDIV = 66; @@ -16013,22 +16018,20 @@ module GTHE4_COMMON (...); parameter [7:0] QPLL0_INIT_CFG1 = 8'h00; parameter [15:0] QPLL0_LOCK_CFG = 16'h01E8; parameter [15:0] QPLL0_LOCK_CFG_G3 = 16'h21E8; - parameter [9:0] QPLL0_LPF = 10'b1011111111; + parameter [9:0] QPLL0_LPF = 10'b1111111111; parameter [9:0] QPLL0_LPF_G3 = 10'b1111111111; - parameter [0:0] QPLL0_PCI_EN = 1'b0; - parameter [0:0] QPLL0_RATE_SW_USE_DRP = 1'b0; - parameter integer QPLL0_REFCLK_DIV = 1; + parameter integer QPLL0_REFCLK_DIV = 2; parameter [15:0] QPLL0_SDM_CFG0 = 16'h0040; parameter [15:0] QPLL0_SDM_CFG1 = 16'h0000; parameter [15:0] QPLL0_SDM_CFG2 = 16'h0000; parameter QPLL1CLKOUT_RATE = "FULL"; - parameter [15:0] QPLL1_CFG0 = 16'h691C; - parameter [15:0] QPLL1_CFG1 = 16'h0020; + parameter [15:0] QPLL1_CFG0 = 16'h301C; + parameter [15:0] QPLL1_CFG1 = 16'h0000; parameter [15:0] QPLL1_CFG1_G3 = 16'h0020; - parameter [15:0] QPLL1_CFG2 = 16'h0F80; - parameter [15:0] QPLL1_CFG2_G3 = 16'h0F80; + parameter [15:0] QPLL1_CFG2 = 16'h0780; + parameter [15:0] QPLL1_CFG2_G3 = 16'h0780; parameter [15:0] QPLL1_CFG3 = 16'h0120; - parameter [15:0] QPLL1_CFG4 = 16'h0002; + parameter [15:0] QPLL1_CFG4 = 16'h0021; parameter [9:0] QPLL1_CP = 10'b0000011111; parameter [9:0] QPLL1_CP_G3 = 10'b0000011111; parameter integer QPLL1_FBDIV = 66; @@ -16037,12 +16040,10 @@ module GTHE4_COMMON (...); parameter [7:0] QPLL1_INIT_CFG1 = 8'h00; parameter [15:0] QPLL1_LOCK_CFG = 16'h01E8; parameter [15:0] QPLL1_LOCK_CFG_G3 = 16'h21E8; - parameter [9:0] QPLL1_LPF = 10'b1011111111; + parameter [9:0] QPLL1_LPF = 10'b1111111111; parameter [9:0] QPLL1_LPF_G3 = 10'b1111111111; - parameter [0:0] QPLL1_PCI_EN = 1'b0; - parameter [0:0] QPLL1_RATE_SW_USE_DRP = 1'b0; - parameter integer QPLL1_REFCLK_DIV = 1; - parameter [15:0] QPLL1_SDM_CFG0 = 16'h0000; + parameter integer QPLL1_REFCLK_DIV = 2; + parameter [15:0] QPLL1_SDM_CFG0 = 16'h0040; parameter [15:0] QPLL1_SDM_CFG1 = 16'h0000; parameter [15:0] QPLL1_SDM_CFG2 = 16'h0000; parameter [15:0] RSVD_ATTR0 = 16'h0000; @@ -16051,15 +16052,15 @@ module GTHE4_COMMON (...); parameter [15:0] RSVD_ATTR3 = 16'h0000; parameter [1:0] RXRECCLKOUT0_SEL = 2'b00; parameter [1:0] RXRECCLKOUT1_SEL = 2'b00; - parameter [0:0] SARC_ENB = 1'b0; + parameter [0:0] SARC_EN = 1'b1; parameter [0:0] SARC_SEL = 1'b0; parameter [15:0] SDM0INITSEED0_0 = 16'b0000000000000000; parameter [8:0] SDM0INITSEED0_1 = 9'b000000000; parameter [15:0] SDM1INITSEED0_0 = 16'b0000000000000000; parameter [8:0] SDM1INITSEED0_1 = 9'b000000000; - parameter SIM_DEVICE = "ULTRASCALE_PLUS"; parameter SIM_MODE = "FAST"; parameter SIM_RESET_SPEEDUP = "TRUE"; + parameter integer SIM_VERSION = 2; output [15:0] DRPDO; output DRPRDY; output [7:0] PMARSVDOUT0; @@ -16078,20 +16079,18 @@ module GTHE4_COMMON (...); output [7:0] QPLLDMONITOR1; output REFCLKOUTMONITOR0; output REFCLKOUTMONITOR1; - output [1:0] RXRECCLK0SEL; - output [1:0] RXRECCLK1SEL; + output [1:0] RXRECCLK0_SEL; + output [1:0] RXRECCLK1_SEL; output [3:0] SDM0FINALOUT; output [14:0] SDM0TESTDATA; output [3:0] SDM1FINALOUT; output [14:0] SDM1TESTDATA; - output [9:0] TCONGPO; - output TCONRSVDOUT0; input BGBYPASSB; input BGMONITORENB; input BGPDB; input [4:0] BGRCALOVRD; input BGRCALOVRDENB; - input [15:0] DRPADDR; + input [9:0] DRPADDR; input DRPCLK; input [15:0] DRPDI; input DRPEN; @@ -16110,21 +16109,15 @@ module GTHE4_COMMON (...); input GTSOUTHREFCLK01; input GTSOUTHREFCLK10; input GTSOUTHREFCLK11; - input [2:0] PCIERATEQPLL0; - input [2:0] PCIERATEQPLL1; input [7:0] PMARSVD0; input [7:0] PMARSVD1; input QPLL0CLKRSVD0; - input QPLL0CLKRSVD1; - input [7:0] QPLL0FBDIV; input QPLL0LOCKDETCLK; input QPLL0LOCKEN; input QPLL0PD; input [2:0] QPLL0REFCLKSEL; input QPLL0RESET; input QPLL1CLKRSVD0; - input QPLL1CLKRSVD1; - input [7:0] QPLL1FBDIV; input QPLL1LOCKDETCLK; input QPLL1LOCKEN; input QPLL1PD; @@ -16137,25 +16130,55 @@ module GTHE4_COMMON (...); input RCALENB; input [24:0] SDM0DATA; input SDM0RESET; - input SDM0TOGGLE; input [1:0] SDM0WIDTH; input [24:0] SDM1DATA; input SDM1RESET; - input SDM1TOGGLE; input [1:0] SDM1WIDTH; - input [9:0] TCONGPI; - input TCONPOWERUP; - input [1:0] TCONRESET; - input [1:0] TCONRSVDIN1; endmodule -module GTYE3_CHANNEL (...); +module IBUFDS_GTE3 (...); + parameter [0:0] REFCLK_EN_TX_PATH = 1'b0; + parameter [1:0] REFCLK_HROW_CK_SEL = 2'b00; + parameter [1:0] REFCLK_ICNTL_RX = 2'b00; + output O; + output ODIV2; + input CEB; + (* iopad_external_pin *) + input I; + (* iopad_external_pin *) + input IB; +endmodule + +module OBUFDS_GTE3 (...); + parameter [0:0] REFCLK_EN_TX_PATH = 1'b0; + parameter [4:0] REFCLK_ICNTL_TX = 5'b00000; + (* iopad_external_pin *) + output O; + (* iopad_external_pin *) + output OB; + input CEB; + input I; +endmodule + +module OBUFDS_GTE3_ADV (...); + parameter [0:0] REFCLK_EN_TX_PATH = 1'b0; + parameter [4:0] REFCLK_ICNTL_TX = 5'b00000; + (* iopad_external_pin *) + output O; + (* iopad_external_pin *) + output OB; + input CEB; + input [3:0] I; + input [1:0] RXRECCLK_SEL; +endmodule + +module GTHE4_CHANNEL (...); parameter [0:0] ACJTAG_DEBUG_MODE = 1'b0; parameter [0:0] ACJTAG_MODE = 1'b0; parameter [0:0] ACJTAG_RESET = 1'b0; parameter [15:0] ADAPT_CFG0 = 16'h9200; parameter [15:0] ADAPT_CFG1 = 16'h801C; - parameter [15:0] ADAPT_CFG2 = 16'b0000000000000000; + parameter [15:0] ADAPT_CFG2 = 16'h0000; parameter ALIGN_COMMA_DOUBLE = "FALSE"; parameter [9:0] ALIGN_COMMA_ENABLE = 10'b0001111111; parameter integer ALIGN_COMMA_WORD = 1; @@ -16163,14 +16186,15 @@ module GTYE3_CHANNEL (...); parameter [9:0] ALIGN_MCOMMA_VALUE = 10'b1010000011; parameter ALIGN_PCOMMA_DET = "TRUE"; parameter [9:0] ALIGN_PCOMMA_VALUE = 10'b0101111100; - parameter [0:0] AUTO_BW_SEL_BYPASS = 1'b0; parameter [0:0] A_RXOSCALRESET = 1'b0; parameter [0:0] A_RXPROGDIVRESET = 1'b0; + parameter [0:0] A_RXTERMINATION = 1'b1; parameter [4:0] A_TXDIFFCTRL = 5'b01100; parameter [0:0] A_TXPROGDIVRESET = 1'b0; parameter [0:0] CAPBYPASS_FORCE = 1'b0; parameter CBCC_DATA_SOURCE_SEL = "DECODED"; parameter [0:0] CDR_SWAP_MODE_EN = 1'b0; + parameter [0:0] CFOK_PWRSVE_EN = 1'b1; parameter CHAN_BOND_KEEP_ALIGN = "FALSE"; parameter integer CHAN_BOND_MAX_SKEW = 7; parameter [9:0] CHAN_BOND_SEQ_1_1 = 10'b0101111100; @@ -16185,7 +16209,7 @@ module GTYE3_CHANNEL (...); parameter [3:0] CHAN_BOND_SEQ_2_ENABLE = 4'b1111; parameter CHAN_BOND_SEQ_2_USE = "FALSE"; parameter integer CHAN_BOND_SEQ_LEN = 2; - parameter [15:0] CH_HSPMUX = 16'h0000; + parameter [15:0] CH_HSPMUX = 16'h2424; parameter [15:0] CKCAL1_CFG_0 = 16'b0000000000000000; parameter [15:0] CKCAL1_CFG_1 = 16'b0000000000000000; parameter [15:0] CKCAL1_CFG_2 = 16'b0000000000000000; @@ -16195,7 +16219,7 @@ module GTYE3_CHANNEL (...); parameter [15:0] CKCAL2_CFG_2 = 16'b0000000000000000; parameter [15:0] CKCAL2_CFG_3 = 16'b0000000000000000; parameter [15:0] CKCAL2_CFG_4 = 16'b0000000000000000; - parameter [15:0] CKCAL_RSVD0 = 16'h0000; + parameter [15:0] CKCAL_RSVD0 = 16'h4000; parameter [15:0] CKCAL_RSVD1 = 16'h0000; parameter CLK_CORRECT_USE = "TRUE"; parameter CLK_COR_KEEP_IDLE = "FALSE"; @@ -16215,14 +16239,13 @@ module GTYE3_CHANNEL (...); parameter [3:0] CLK_COR_SEQ_2_ENABLE = 4'b1111; parameter CLK_COR_SEQ_2_USE = "FALSE"; parameter integer CLK_COR_SEQ_LEN = 2; - parameter [15:0] CPLL_CFG0 = 16'h20F8; - parameter [15:0] CPLL_CFG1 = 16'hA494; - parameter [15:0] CPLL_CFG2 = 16'hF001; - parameter [5:0] CPLL_CFG3 = 6'h00; + parameter [15:0] CPLL_CFG0 = 16'h01FA; + parameter [15:0] CPLL_CFG1 = 16'h24A9; + parameter [15:0] CPLL_CFG2 = 16'h6807; + parameter [15:0] CPLL_CFG3 = 16'h0000; parameter integer CPLL_FBDIV = 4; parameter integer CPLL_FBDIV_45 = 4; parameter [15:0] CPLL_INIT_CFG0 = 16'h001E; - parameter [7:0] CPLL_INIT_CFG1 = 8'h00; parameter [15:0] CPLL_LOCK_CFG = 16'h01E8; parameter integer CPLL_REFCLK_DIV = 1; parameter [2:0] CTLE3_OCAP_EXT_CTRL = 3'b000; @@ -16232,16 +16255,14 @@ module GTYE3_CHANNEL (...); parameter DEC_MCOMMA_DETECT = "TRUE"; parameter DEC_PCOMMA_DETECT = "TRUE"; parameter DEC_VALID_COMMA_ONLY = "TRUE"; - parameter [0:0] DFE_D_X_REL_POS = 1'b0; - parameter [0:0] DFE_VCM_COMP_EN = 1'b0; + parameter [0:0] DELAY_ELEC = 1'b0; parameter [9:0] DMONITOR_CFG0 = 10'h000; parameter [7:0] DMONITOR_CFG1 = 8'h00; parameter [0:0] ES_CLK_PHASE_SEL = 1'b0; parameter [5:0] ES_CONTROL = 6'b000000; parameter ES_ERRDET_EN = "FALSE"; parameter ES_EYE_SCAN_EN = "FALSE"; - parameter [11:0] ES_HORZ_OFFSET = 12'h000; - parameter [9:0] ES_PMA_CFG = 10'b0000000000; + parameter [11:0] ES_HORZ_OFFSET = 12'h800; parameter [4:0] ES_PRESCALE = 5'b00000; parameter [15:0] ES_QUALIFIER0 = 16'h0000; parameter [15:0] ES_QUALIFIER1 = 16'h0000; @@ -16273,32 +16294,19 @@ module GTYE3_CHANNEL (...); parameter [15:0] ES_SDATA_MASK7 = 16'h0000; parameter [15:0] ES_SDATA_MASK8 = 16'h0000; parameter [15:0] ES_SDATA_MASK9 = 16'h0000; - parameter [10:0] EVODD_PHI_CFG = 11'b00000000000; parameter [0:0] EYE_SCAN_SWAP_EN = 1'b0; parameter [3:0] FTS_DESKEW_SEQ_ENABLE = 4'b1111; parameter [3:0] FTS_LANE_DESKEW_CFG = 4'b1111; parameter FTS_LANE_DESKEW_EN = "FALSE"; parameter [4:0] GEARBOX_MODE = 5'b00000; - parameter [0:0] GM_BIAS_SELECT = 1'b0; parameter [0:0] ISCAN_CK_PH_SEL2 = 1'b0; parameter [0:0] LOCAL_MASTER = 1'b0; - parameter [15:0] LOOP0_CFG = 16'h0000; - parameter [15:0] LOOP10_CFG = 16'h0000; - parameter [15:0] LOOP11_CFG = 16'h0000; - parameter [15:0] LOOP12_CFG = 16'h0000; - parameter [15:0] LOOP13_CFG = 16'h0000; - parameter [15:0] LOOP1_CFG = 16'h0000; - parameter [15:0] LOOP2_CFG = 16'h0000; - parameter [15:0] LOOP3_CFG = 16'h0000; - parameter [15:0] LOOP4_CFG = 16'h0000; - parameter [15:0] LOOP5_CFG = 16'h0000; - parameter [15:0] LOOP6_CFG = 16'h0000; - parameter [15:0] LOOP7_CFG = 16'h0000; - parameter [15:0] LOOP8_CFG = 16'h0000; - parameter [15:0] LOOP9_CFG = 16'h0000; parameter [2:0] LPBK_BIAS_CTRL = 3'b000; parameter [0:0] LPBK_EN_RCAL_B = 1'b0; parameter [3:0] LPBK_EXT_RCAL = 4'b0000; + parameter [2:0] LPBK_IND_CTRL0 = 3'b000; + parameter [2:0] LPBK_IND_CTRL1 = 3'b000; + parameter [2:0] LPBK_IND_CTRL2 = 3'b000; parameter [3:0] LPBK_RG_CTRL = 4'b0000; parameter [1:0] OOBDIVCTL = 2'b00; parameter [0:0] OOB_PWRUP = 1'b0; @@ -16311,25 +16319,32 @@ module GTYE3_CHANNEL (...); parameter [5:0] PCI3_RX_ELECIDLE_HI_COUNT = 6'b000000; parameter [0:0] PCI3_RX_ELECIDLE_LP4_DISABLE = 1'b0; parameter [0:0] PCI3_RX_FIFO_DISABLE = 1'b0; + parameter [4:0] PCIE3_CLK_COR_EMPTY_THRSH = 5'b00000; + parameter [5:0] PCIE3_CLK_COR_FULL_THRSH = 6'b010000; + parameter [4:0] PCIE3_CLK_COR_MAX_LAT = 5'b01000; + parameter [4:0] PCIE3_CLK_COR_MIN_LAT = 5'b00100; + parameter [5:0] PCIE3_CLK_COR_THRSH_TIMER = 6'b001000; parameter [15:0] PCIE_BUFG_DIV_CTRL = 16'h0000; + parameter [1:0] PCIE_PLL_SEL_MODE_GEN12 = 2'h0; + parameter [1:0] PCIE_PLL_SEL_MODE_GEN3 = 2'h0; + parameter [1:0] PCIE_PLL_SEL_MODE_GEN4 = 2'h0; parameter [15:0] PCIE_RXPCS_CFG_GEN3 = 16'h0000; parameter [15:0] PCIE_RXPMA_CFG = 16'h0000; parameter [15:0] PCIE_TXPCS_CFG_GEN3 = 16'h0000; parameter [15:0] PCIE_TXPMA_CFG = 16'h0000; parameter PCS_PCIE_EN = "FALSE"; parameter [15:0] PCS_RSVD0 = 16'b0000000000000000; - parameter [2:0] PCS_RSVD1 = 3'b000; parameter [11:0] PD_TRANS_TIME_FROM_P2 = 12'h03C; parameter [7:0] PD_TRANS_TIME_NONE_P2 = 8'h19; parameter [7:0] PD_TRANS_TIME_TO_P2 = 8'h64; - parameter [1:0] PLL_SEL_MODE_GEN12 = 2'h0; - parameter [1:0] PLL_SEL_MODE_GEN3 = 2'h0; - parameter [15:0] PMA_RSV0 = 16'h0000; - parameter [15:0] PMA_RSV1 = 16'h0000; parameter integer PREIQ_FREQ_BST = 0; parameter [2:0] PROCESS_PAR = 3'b010; parameter [0:0] RATE_SW_USE_DRP = 1'b0; + parameter [0:0] RCLK_SIPO_DLY_ENB = 1'b0; + parameter [0:0] RCLK_SIPO_INV_EN = 1'b0; parameter [0:0] RESET_POWERSAVE_DISABLE = 1'b0; + parameter [2:0] RTX_BUF_CML_CTRL = 3'b010; + parameter [1:0] RTX_BUF_TERM_CTRL = 2'b00; parameter [4:0] RXBUFRESET_TIME = 5'b00001; parameter RXBUF_ADDR_MODE = "FULL"; parameter [3:0] RXBUF_EIDLE_HI_CNT = 4'b1000; @@ -16344,37 +16359,48 @@ module GTYE3_CHANNEL (...); parameter integer RXBUF_THRESH_UNDFLW = 4; parameter [4:0] RXCDRFREQRESET_TIME = 5'b00001; parameter [4:0] RXCDRPHRESET_TIME = 5'b00001; - parameter [15:0] RXCDR_CFG0 = 16'h0000; - parameter [15:0] RXCDR_CFG0_GEN3 = 16'h0000; - parameter [15:0] RXCDR_CFG1 = 16'h0300; - parameter [15:0] RXCDR_CFG1_GEN3 = 16'h0300; - parameter [15:0] RXCDR_CFG2 = 16'h0060; - parameter [15:0] RXCDR_CFG2_GEN3 = 16'h0060; - parameter [15:0] RXCDR_CFG3 = 16'h0000; - parameter [15:0] RXCDR_CFG3_GEN3 = 16'h0000; - parameter [15:0] RXCDR_CFG4 = 16'h0002; - parameter [15:0] RXCDR_CFG4_GEN3 = 16'h0002; - parameter [15:0] RXCDR_CFG5 = 16'h0000; - parameter [15:0] RXCDR_CFG5_GEN3 = 16'h0000; + parameter [15:0] RXCDR_CFG0 = 16'h0003; + parameter [15:0] RXCDR_CFG0_GEN3 = 16'h0003; + parameter [15:0] RXCDR_CFG1 = 16'h0000; + parameter [15:0] RXCDR_CFG1_GEN3 = 16'h0000; + parameter [15:0] RXCDR_CFG2 = 16'h0164; + parameter [9:0] RXCDR_CFG2_GEN2 = 10'h164; + parameter [15:0] RXCDR_CFG2_GEN3 = 16'h0034; + parameter [15:0] RXCDR_CFG2_GEN4 = 16'h0034; + parameter [15:0] RXCDR_CFG3 = 16'h0024; + parameter [5:0] RXCDR_CFG3_GEN2 = 6'h24; + parameter [15:0] RXCDR_CFG3_GEN3 = 16'h0024; + parameter [15:0] RXCDR_CFG3_GEN4 = 16'h0024; + parameter [15:0] RXCDR_CFG4 = 16'h5CF6; + parameter [15:0] RXCDR_CFG4_GEN3 = 16'h5CF6; + parameter [15:0] RXCDR_CFG5 = 16'hB46B; + parameter [15:0] RXCDR_CFG5_GEN3 = 16'h146B; parameter [0:0] RXCDR_FR_RESET_ON_EIDLE = 1'b0; parameter [0:0] RXCDR_HOLD_DURING_EIDLE = 1'b0; - parameter [15:0] RXCDR_LOCK_CFG0 = 16'h0001; - parameter [15:0] RXCDR_LOCK_CFG1 = 16'h0000; + parameter [15:0] RXCDR_LOCK_CFG0 = 16'h0040; + parameter [15:0] RXCDR_LOCK_CFG1 = 16'h8000; parameter [15:0] RXCDR_LOCK_CFG2 = 16'h0000; parameter [15:0] RXCDR_LOCK_CFG3 = 16'h0000; + parameter [15:0] RXCDR_LOCK_CFG4 = 16'h0000; parameter [0:0] RXCDR_PH_RESET_ON_EIDLE = 1'b0; - parameter [1:0] RXCFOKDONE_SRC = 2'b00; - parameter [15:0] RXCFOK_CFG0 = 16'h3E00; - parameter [15:0] RXCFOK_CFG1 = 16'h0042; + parameter [15:0] RXCFOK_CFG0 = 16'h0000; + parameter [15:0] RXCFOK_CFG1 = 16'h0002; parameter [15:0] RXCFOK_CFG2 = 16'h002D; + parameter [15:0] RXCKCAL1_IQ_LOOP_RST_CFG = 16'h0000; + parameter [15:0] RXCKCAL1_I_LOOP_RST_CFG = 16'h0000; + parameter [15:0] RXCKCAL1_Q_LOOP_RST_CFG = 16'h0000; + parameter [15:0] RXCKCAL2_DX_LOOP_RST_CFG = 16'h0000; + parameter [15:0] RXCKCAL2_D_LOOP_RST_CFG = 16'h0000; + parameter [15:0] RXCKCAL2_S_LOOP_RST_CFG = 16'h0000; + parameter [15:0] RXCKCAL2_X_LOOP_RST_CFG = 16'h0000; parameter [6:0] RXDFELPMRESET_TIME = 7'b0001111; parameter [15:0] RXDFELPM_KL_CFG0 = 16'h0000; parameter [15:0] RXDFELPM_KL_CFG1 = 16'h0022; parameter [15:0] RXDFELPM_KL_CFG2 = 16'h0100; - parameter [15:0] RXDFE_CFG0 = 16'h4C00; + parameter [15:0] RXDFE_CFG0 = 16'h4000; parameter [15:0] RXDFE_CFG1 = 16'h0000; - parameter [15:0] RXDFE_GC_CFG0 = 16'h1E00; - parameter [15:0] RXDFE_GC_CFG1 = 16'h1900; + parameter [15:0] RXDFE_GC_CFG0 = 16'h0000; + parameter [15:0] RXDFE_GC_CFG1 = 16'h0000; parameter [15:0] RXDFE_GC_CFG2 = 16'h0000; parameter [15:0] RXDFE_H2_CFG0 = 16'h0000; parameter [15:0] RXDFE_H2_CFG1 = 16'h0002; @@ -16404,26 +16430,31 @@ module GTYE3_CHANNEL (...); parameter [15:0] RXDFE_HE_CFG1 = 16'h0002; parameter [15:0] RXDFE_HF_CFG0 = 16'h0000; parameter [15:0] RXDFE_HF_CFG1 = 16'h0002; + parameter [15:0] RXDFE_KH_CFG0 = 16'h0000; + parameter [15:0] RXDFE_KH_CFG1 = 16'h0000; + parameter [15:0] RXDFE_KH_CFG2 = 16'h0000; + parameter [15:0] RXDFE_KH_CFG3 = 16'h0000; parameter [15:0] RXDFE_OS_CFG0 = 16'h0000; - parameter [15:0] RXDFE_OS_CFG1 = 16'h0200; + parameter [15:0] RXDFE_OS_CFG1 = 16'h0002; parameter [0:0] RXDFE_PWR_SAVING = 1'b0; parameter [15:0] RXDFE_UT_CFG0 = 16'h0000; parameter [15:0] RXDFE_UT_CFG1 = 16'h0002; + parameter [15:0] RXDFE_UT_CFG2 = 16'h0000; parameter [15:0] RXDFE_VP_CFG0 = 16'h0000; parameter [15:0] RXDFE_VP_CFG1 = 16'h0022; - parameter [15:0] RXDLY_CFG = 16'h001F; + parameter [15:0] RXDLY_CFG = 16'h0010; parameter [15:0] RXDLY_LCFG = 16'h0030; parameter RXELECIDLE_CFG = "SIGCFG_4"; parameter integer RXGBOX_FIFO_INIT_RD_ADDR = 4; parameter RXGEARBOX_EN = "FALSE"; parameter [4:0] RXISCANRESET_TIME = 5'b00001; parameter [15:0] RXLPM_CFG = 16'h0000; - parameter [15:0] RXLPM_GC_CFG = 16'h0200; + parameter [15:0] RXLPM_GC_CFG = 16'h1000; parameter [15:0] RXLPM_KH_CFG0 = 16'h0000; parameter [15:0] RXLPM_KH_CFG1 = 16'h0002; - parameter [15:0] RXLPM_OS_CFG0 = 16'h0400; + parameter [15:0] RXLPM_OS_CFG0 = 16'h0000; parameter [15:0] RXLPM_OS_CFG1 = 16'h0000; - parameter [8:0] RXOOB_CFG = 9'b000000110; + parameter [8:0] RXOOB_CFG = 9'b000110000; parameter RXOOB_CLK_CFG = "PMA"; parameter [4:0] RXOSCALRESET_TIME = 5'b00011; parameter integer RXOUT_DIV = 4; @@ -16434,9 +16465,9 @@ module GTYE3_CHANNEL (...); parameter [15:0] RXPHSLIP_CFG = 16'h9933; parameter [4:0] RXPH_MONITOR_SEL = 5'b00000; parameter [0:0] RXPI_AUTO_BW_SEL_BYPASS = 1'b0; - parameter [15:0] RXPI_CFG = 16'h0100; + parameter [15:0] RXPI_CFG0 = 16'h0002; + parameter [15:0] RXPI_CFG1 = 16'b0000000000000000; parameter [0:0] RXPI_LPM = 1'b0; - parameter [15:0] RXPI_RSV0 = 16'h0000; parameter [1:0] RXPI_SEL_LC = 2'b00; parameter [1:0] RXPI_STARTCODE = 2'b00; parameter [0:0] RXPI_VREFSEL = 1'b0; @@ -16444,13 +16475,14 @@ module GTYE3_CHANNEL (...); parameter [4:0] RXPMARESET_TIME = 5'b00001; parameter [0:0] RXPRBS_ERR_LOOPBACK = 1'b0; parameter integer RXPRBS_LINKACQ_CNT = 15; + parameter [0:0] RXREFCLKDIV2_SEL = 1'b0; parameter integer RXSLIDE_AUTO_WAIT = 7; parameter RXSLIDE_MODE = "OFF"; parameter [0:0] RXSYNC_MULTILANE = 1'b0; parameter [0:0] RXSYNC_OVRD = 1'b0; parameter [0:0] RXSYNC_SKIP_DA = 1'b0; parameter [0:0] RX_AFE_CM_EN = 1'b0; - parameter [15:0] RX_BIAS_CFG0 = 16'h1534; + parameter [15:0] RX_BIAS_CFG0 = 16'h12B0; parameter [5:0] RX_BUFFER_CFG = 6'b000000; parameter [0:0] RX_CAPFF_SARC_ENB = 1'b0; parameter integer RX_CLK25_DIV = 8; @@ -16459,29 +16491,27 @@ module GTYE3_CHANNEL (...); parameter [3:0] RX_CM_BUF_CFG = 4'b1010; parameter [0:0] RX_CM_BUF_PD = 1'b0; parameter integer RX_CM_SEL = 3; - parameter integer RX_CM_TRIM = 10; - parameter [0:0] RX_CTLE1_KHKL = 1'b0; - parameter [0:0] RX_CTLE2_KHKL = 1'b0; - parameter [0:0] RX_CTLE3_AGC = 1'b0; + parameter integer RX_CM_TRIM = 12; + parameter [7:0] RX_CTLE3_LPF = 8'b00000000; parameter integer RX_DATA_WIDTH = 20; parameter [5:0] RX_DDI_SEL = 6'b000000; parameter RX_DEFER_RESET_BUF_EN = "TRUE"; - parameter [2:0] RX_DEGEN_CTRL = 3'b010; - parameter integer RX_DFELPM_CFG0 = 6; - parameter [0:0] RX_DFELPM_CFG1 = 1'b0; + parameter [2:0] RX_DEGEN_CTRL = 3'b011; + parameter integer RX_DFELPM_CFG0 = 0; + parameter [0:0] RX_DFELPM_CFG1 = 1'b1; parameter [0:0] RX_DFELPM_KLKH_AGC_STUP_EN = 1'b1; parameter [1:0] RX_DFE_AGC_CFG0 = 2'b00; parameter integer RX_DFE_AGC_CFG1 = 4; parameter integer RX_DFE_KL_LPM_KH_CFG0 = 1; - parameter integer RX_DFE_KL_LPM_KH_CFG1 = 2; + parameter integer RX_DFE_KL_LPM_KH_CFG1 = 4; parameter [1:0] RX_DFE_KL_LPM_KL_CFG0 = 2'b01; - parameter [2:0] RX_DFE_KL_LPM_KL_CFG1 = 3'b010; + parameter integer RX_DFE_KL_LPM_KL_CFG1 = 4; parameter [0:0] RX_DFE_LPM_HOLD_DURING_EIDLE = 1'b0; parameter RX_DISPERR_SEQ_MATCH = "TRUE"; parameter [0:0] RX_DIV2_MODE_B = 1'b0; parameter [4:0] RX_DIVRESET_TIME = 5'b00001; parameter [0:0] RX_EN_CTLE_RCAL_B = 1'b0; - parameter [0:0] RX_EN_HI_LR = 1'b0; + parameter [0:0] RX_EN_HI_LR = 1'b1; parameter [8:0] RX_EXT_RL_CTRL = 9'b000000000; parameter [6:0] RX_EYESCAN_VS_CODE = 7'b0000000; parameter [0:0] RX_EYESCAN_VS_NEG_DIR = 1'b0; @@ -16490,6 +16520,7 @@ module GTYE3_CHANNEL (...); parameter [0:0] RX_FABINT_USRCLK_FLOP = 1'b0; parameter integer RX_INT_DATAWIDTH = 1; parameter [0:0] RX_PMA_POWER_SAVE = 1'b0; + parameter [15:0] RX_PMA_RSV0 = 16'h0000; parameter real RX_PROGDIV_CFG = 0.0; parameter [15:0] RX_PROGDIV_RATE = 16'h0001; parameter [3:0] RX_RESLOAD_CTRL = 4'b0000; @@ -16497,34 +16528,32 @@ module GTYE3_CHANNEL (...); parameter [2:0] RX_SAMPLE_PERIOD = 3'b101; parameter integer RX_SIG_VALID_DLY = 11; parameter [0:0] RX_SUM_DFETAPREP_EN = 1'b0; - parameter [3:0] RX_SUM_IREF_TUNE = 4'b0000; - parameter [3:0] RX_SUM_VCMTUNE = 4'b1000; + parameter [3:0] RX_SUM_IREF_TUNE = 4'b1001; + parameter [3:0] RX_SUM_RESLOAD_CTRL = 4'b0000; + parameter [3:0] RX_SUM_VCMTUNE = 4'b1010; parameter [0:0] RX_SUM_VCM_OVWR = 1'b0; parameter [2:0] RX_SUM_VREF_TUNE = 3'b100; parameter [1:0] RX_TUNE_AFE_OS = 2'b00; parameter [2:0] RX_VREG_CTRL = 3'b101; parameter [0:0] RX_VREG_PDB = 1'b1; parameter [1:0] RX_WIDEMODE_CDR = 2'b01; + parameter [1:0] RX_WIDEMODE_CDR_GEN3 = 2'b01; + parameter [1:0] RX_WIDEMODE_CDR_GEN4 = 2'b01; parameter RX_XCLK_SEL = "RXDES"; parameter [0:0] RX_XMODE_SEL = 1'b0; - parameter integer SAS_MAX_COM = 64; - parameter integer SAS_MIN_COM = 36; + parameter [0:0] SAMPLE_CLK_PHASE = 1'b0; + parameter [0:0] SAS_12G_MODE = 1'b0; parameter [3:0] SATA_BURST_SEQ_LEN = 4'b1111; parameter [2:0] SATA_BURST_VAL = 3'b100; parameter SATA_CPLL_CFG = "VCO_3000MHZ"; parameter [2:0] SATA_EIDLE_VAL = 3'b100; - parameter integer SATA_MAX_BURST = 8; - parameter integer SATA_MAX_INIT = 21; - parameter integer SATA_MAX_WAKE = 7; - parameter integer SATA_MIN_BURST = 4; - parameter integer SATA_MIN_INIT = 12; - parameter integer SATA_MIN_WAKE = 4; parameter SHOW_REALIGN_COMMA = "TRUE"; + parameter SIM_DEVICE = "ULTRASCALE_PLUS"; parameter SIM_MODE = "FAST"; parameter SIM_RECEIVER_DETECT_PASS = "TRUE"; parameter SIM_RESET_SPEEDUP = "TRUE"; - parameter [0:0] SIM_TX_EIDLE_DRIVE_LEVEL = 1'b0; - parameter integer SIM_VERSION = 2; + parameter SIM_TX_EIDLE_DRIVE_LEVEL = "Z"; + parameter [0:0] SRSTMODE = 1'b0; parameter [1:0] TAPDLY_SET_TX = 2'h0; parameter [3:0] TEMPERATURE_PAR = 4'b0010; parameter [14:0] TERM_RCAL_CFG = 15'b100001000010000; @@ -16534,18 +16563,20 @@ module GTYE3_CHANNEL (...); parameter [7:0] TST_RSV1 = 8'h00; parameter TXBUF_EN = "TRUE"; parameter TXBUF_RESET_ON_RATE_CHANGE = "FALSE"; - parameter [15:0] TXDLY_CFG = 16'h001F; + parameter [15:0] TXDLY_CFG = 16'h0010; parameter [15:0] TXDLY_LCFG = 16'h0030; + parameter [3:0] TXDRVBIAS_N = 4'b1010; parameter TXFIFO_ADDR_CFG = "LOW"; parameter integer TXGBOX_FIFO_INIT_RD_ADDR = 4; parameter TXGEARBOX_EN = "FALSE"; parameter integer TXOUT_DIV = 4; parameter [4:0] TXPCSRESET_TIME = 5'b00001; - parameter [15:0] TXPHDLY_CFG0 = 16'h2020; - parameter [15:0] TXPHDLY_CFG1 = 16'h0001; + parameter [15:0] TXPHDLY_CFG0 = 16'h6020; + parameter [15:0] TXPHDLY_CFG1 = 16'h0002; parameter [15:0] TXPH_CFG = 16'h0123; parameter [15:0] TXPH_CFG2 = 16'h0000; parameter [4:0] TXPH_MONITOR_SEL = 5'b00000; + parameter [15:0] TXPI_CFG = 16'h0000; parameter [1:0] TXPI_CFG0 = 2'b00; parameter [1:0] TXPI_CFG1 = 2'b00; parameter [1:0] TXPI_CFG2 = 2'b00; @@ -16555,30 +16586,29 @@ module GTYE3_CHANNEL (...); parameter [0:0] TXPI_GRAY_SEL = 1'b0; parameter [0:0] TXPI_INVSTROBE_SEL = 1'b0; parameter [0:0] TXPI_LPM = 1'b0; + parameter [0:0] TXPI_PPM = 1'b0; parameter TXPI_PPMCLK_SEL = "TXUSRCLK2"; parameter [7:0] TXPI_PPM_CFG = 8'b00000000; - parameter [15:0] TXPI_RSV0 = 16'h0000; parameter [2:0] TXPI_SYNFREQ_PPM = 3'b000; parameter [0:0] TXPI_VREFSEL = 1'b0; parameter [4:0] TXPMARESET_TIME = 5'b00001; + parameter [0:0] TXREFCLKDIV2_SEL = 1'b0; parameter [0:0] TXSYNC_MULTILANE = 1'b0; parameter [0:0] TXSYNC_OVRD = 1'b0; parameter [0:0] TXSYNC_SKIP_DA = 1'b0; parameter integer TX_CLK25_DIV = 8; parameter [0:0] TX_CLKMUX_EN = 1'b1; - parameter [0:0] TX_CLKREG_PDB = 1'b0; - parameter [2:0] TX_CLKREG_SET = 3'b000; parameter integer TX_DATA_WIDTH = 20; - parameter [5:0] TX_DCD_CFG = 6'b000010; - parameter [0:0] TX_DCD_EN = 1'b0; + parameter [15:0] TX_DCC_LOOP_RST_CFG = 16'h0000; parameter [5:0] TX_DEEMPH0 = 6'b000000; parameter [5:0] TX_DEEMPH1 = 6'b000000; + parameter [5:0] TX_DEEMPH2 = 6'b000000; + parameter [5:0] TX_DEEMPH3 = 6'b000000; parameter [4:0] TX_DIVRESET_TIME = 5'b00001; parameter TX_DRIVE_MODE = "DIRECT"; parameter integer TX_DRVMUX_CTRL = 2; parameter [2:0] TX_EIDLE_ASSERT_DELAY = 3'b110; parameter [2:0] TX_EIDLE_DEASSERT_DELAY = 3'b100; - parameter [0:0] TX_EML_PHI_TUNE = 1'b0; parameter [0:0] TX_FABINT_USRCLK_FLOP = 1'b0; parameter [0:0] TX_FIFO_BYP_EN = 1'b0; parameter [0:0] TX_IDLE_DATA_ZERO = 1'b0; @@ -16595,44 +16625,75 @@ module GTYE3_CHANNEL (...); parameter [6:0] TX_MARGIN_LOW_2 = 7'b1000010; parameter [6:0] TX_MARGIN_LOW_3 = 7'b1000000; parameter [6:0] TX_MARGIN_LOW_4 = 7'b1000000; - parameter [2:0] TX_MODE_SEL = 3'b000; parameter [15:0] TX_PHICAL_CFG0 = 16'h0000; - parameter [15:0] TX_PHICAL_CFG1 = 16'h7E00; + parameter [15:0] TX_PHICAL_CFG1 = 16'h003F; parameter [15:0] TX_PHICAL_CFG2 = 16'h0000; parameter integer TX_PI_BIASSET = 0; - parameter [15:0] TX_PI_CFG0 = 16'h0000; - parameter [15:0] TX_PI_CFG1 = 16'h0000; - parameter [0:0] TX_PI_DIV2_MODE_B = 1'b0; - parameter [0:0] TX_PI_SEL_QPLL0 = 1'b0; - parameter [0:0] TX_PI_SEL_QPLL1 = 1'b0; + parameter [1:0] TX_PI_IBIAS_MID = 2'b00; parameter [0:0] TX_PMADATA_OPT = 1'b0; parameter [0:0] TX_PMA_POWER_SAVE = 1'b0; + parameter [15:0] TX_PMA_RSV0 = 16'h0008; parameter integer TX_PREDRV_CTRL = 2; parameter TX_PROGCLK_SEL = "POSTPI"; parameter real TX_PROGDIV_CFG = 0.0; parameter [15:0] TX_PROGDIV_RATE = 16'h0001; + parameter [0:0] TX_QPI_STATUS_EN = 1'b0; parameter [13:0] TX_RXDETECT_CFG = 14'h0032; - parameter integer TX_RXDETECT_REF = 4; + parameter integer TX_RXDETECT_REF = 3; parameter [2:0] TX_SAMPLE_PERIOD = 3'b101; parameter [0:0] TX_SARC_LPBK_ENB = 1'b0; + parameter [1:0] TX_SW_MEAS = 2'b00; + parameter [2:0] TX_VREG_CTRL = 3'b000; + parameter [0:0] TX_VREG_PDB = 1'b0; + parameter [1:0] TX_VREG_VREFSEL = 2'b00; parameter TX_XCLK_SEL = "TXOUT"; + parameter [0:0] USB_BOTH_BURST_IDLE = 1'b0; + parameter [6:0] USB_BURSTMAX_U3WAKE = 7'b1111111; + parameter [6:0] USB_BURSTMIN_U3WAKE = 7'b1100011; + parameter [0:0] USB_CLK_COR_EQ_EN = 1'b0; + parameter [0:0] USB_EXT_CNTL = 1'b1; + parameter [9:0] USB_IDLEMAX_POLLING = 10'b1010111011; + parameter [9:0] USB_IDLEMIN_POLLING = 10'b0100101011; + parameter [8:0] USB_LFPSPING_BURST = 9'b000000101; + parameter [8:0] USB_LFPSPOLLING_BURST = 9'b000110001; + parameter [8:0] USB_LFPSPOLLING_IDLE_MS = 9'b000000100; + parameter [8:0] USB_LFPSU1EXIT_BURST = 9'b000011101; + parameter [8:0] USB_LFPSU2LPEXIT_BURST_MS = 9'b001100011; + parameter [8:0] USB_LFPSU3WAKE_BURST_MS = 9'b111110011; + parameter [3:0] USB_LFPS_TPERIOD = 4'b0011; + parameter [0:0] USB_LFPS_TPERIOD_ACCURATE = 1'b1; + parameter [0:0] USB_MODE = 1'b0; + parameter [0:0] USB_PCIE_ERR_REP_DIS = 1'b0; + parameter integer USB_PING_SATA_MAX_INIT = 21; + parameter integer USB_PING_SATA_MIN_INIT = 12; + parameter integer USB_POLL_SATA_MAX_BURST = 8; + parameter integer USB_POLL_SATA_MIN_BURST = 4; + parameter [0:0] USB_RAW_ELEC = 1'b0; + parameter [0:0] USB_RXIDLE_P0_CTRL = 1'b1; + parameter [0:0] USB_TXIDLE_TUNE_ENABLE = 1'b1; + parameter integer USB_U1_SATA_MAX_WAKE = 7; + parameter integer USB_U1_SATA_MIN_WAKE = 4; + parameter integer USB_U2_SAS_MAX_COM = 64; + parameter integer USB_U2_SAS_MIN_COM = 36; parameter [0:0] USE_PCS_CLK_PHASE_SEL = 1'b0; - output [2:0] BUFGTCE; + parameter [0:0] Y_ALL_MODE = 1'b0; + output BUFGTCE; output [2:0] BUFGTCEMASK; output [8:0] BUFGTDIV; - output [2:0] BUFGTRESET; + output BUFGTRESET; output [2:0] BUFGTRSTMASK; output CPLLFBCLKLOST; output CPLLLOCK; output CPLLREFCLKLOST; - output [16:0] DMONITOROUT; + output [15:0] DMONITOROUT; + output DMONITOROUTCLK; output [15:0] DRPDO; output DRPRDY; output EYESCANDATAERROR; + output GTHTXN; + output GTHTXP; output GTPOWERGOOD; output GTREFCLKMONITOR; - output GTYTXN; - output GTYTXP; output PCIERATEGEN3; output PCIERATEIDLE; output [1:0] PCIERATEQPLLPD; @@ -16643,7 +16704,8 @@ module GTYE3_CHANNEL (...); output PCIEUSERRATESTART; output [15:0] PCSRSVDOUT; output PHYSTATUS; - output [7:0] PINRSRVDAS; + output [15:0] PINRSRVDAS; + output POWERPRESENT; output RESETEXCEPTION; output [2:0] RXBUFSTATUS; output RXBYTEISALIGNED; @@ -16671,7 +16733,10 @@ module GTYE3_CHANNEL (...); output RXELECIDLE; output [5:0] RXHEADER; output [1:0] RXHEADERVALID; - output [6:0] RXMONITOROUT; + output RXLFPSTRESETDET; + output RXLFPSU2LPEXITDET; + output RXLFPSU3WAKEDET; + output [7:0] RXMONITOROUT; output RXOSINTDONE; output RXOSINTSTARTED; output RXOSINTSTROBEDONE; @@ -16685,6 +16750,8 @@ module GTYE3_CHANNEL (...); output RXPRBSERR; output RXPRBSLOCKED; output RXPRGDIVRESETDONE; + output RXQPISENN; + output RXQPISENP; output RXRATEDONE; output RXRECCLKOUT; output RXRESETDONE; @@ -16708,6 +16775,8 @@ module GTYE3_CHANNEL (...); output TXPHINITDONE; output TXPMARESETDONE; output TXPRGDIVRESETDONE; + output TXQPISENN; + output TXQPISENP; output TXRATEDONE; output TXRESETDONE; output TXSYNCDONE; @@ -16718,6 +16787,7 @@ module GTYE3_CHANNEL (...); input CFGRESET; input CLKRSVD0; input CLKRSVD1; + input CPLLFREQLOCK; input CPLLLOCKDETCLK; input CPLLLOCKEN; input CPLLPD; @@ -16729,65 +16799,64 @@ module GTYE3_CHANNEL (...); input DRPCLK; input [15:0] DRPDI; input DRPEN; + input DRPRST; input DRPWE; - input ELPCALDVORWREN; - input ELPCALPAORWREN; - input EVODDPHICALDONE; - input EVODDPHICALSTART; - input EVODDPHIDRDEN; - input EVODDPHIDWREN; - input EVODDPHIXRDEN; - input EVODDPHIXWREN; - input EYESCANMODE; input EYESCANRESET; input EYESCANTRIGGER; + input FREQOS; input GTGREFCLK; + input GTHRXN; + input GTHRXP; input GTNORTHREFCLK0; input GTNORTHREFCLK1; input GTREFCLK0; input GTREFCLK1; - input GTRESETSEL; input [15:0] GTRSVD; input GTRXRESET; + input GTRXRESETSEL; input GTSOUTHREFCLK0; input GTSOUTHREFCLK1; input GTTXRESET; - input GTYRXN; - input GTYRXP; + input GTTXRESETSEL; + input INCPCTRL; input [2:0] LOOPBACK; - input [15:0] LOOPRSVD; - input LPBKRXTXSEREN; - input LPBKTXRXSEREN; input PCIEEQRXEQADAPTDONE; input PCIERSTIDLE; input PCIERSTTXSYNCSTART; input PCIEUSERRATEDONE; input [15:0] PCSRSVDIN; - input [4:0] PCSRSVDIN2; - input [4:0] PMARSVDIN; input QPLL0CLK; + input QPLL0FREQLOCK; input QPLL0REFCLK; input QPLL1CLK; + input QPLL1FREQLOCK; input QPLL1REFCLK; input RESETOVRD; - input RSTCLKENTX; input RX8B10BEN; + input RXAFECFOKEN; input RXBUFRESET; input RXCDRFREQRESET; input RXCDRHOLD; input RXCDROVRDEN; input RXCDRRESET; - input RXCDRRESETRSV; input RXCHBONDEN; input [4:0] RXCHBONDI; input [2:0] RXCHBONDLEVEL; input RXCHBONDMASTER; input RXCHBONDSLAVE; input RXCKCALRESET; + input [6:0] RXCKCALSTART; input RXCOMMADETEN; - input RXDCCFORCESTART; + input [1:0] RXDFEAGCCTRL; input RXDFEAGCHOLD; input RXDFEAGCOVRDEN; + input [3:0] RXDFECFOKFCNUM; + input RXDFECFOKFEN; + input RXDFECFOKFPULSE; + input RXDFECFOKHOLD; + input RXDFECFOKOVREN; + input RXDFEKHHOLD; + input RXDFEKHOVRDEN; input RXDFELFHOLD; input RXDFELFOVRDEN; input RXDFELPMRESET; @@ -16823,13 +16892,13 @@ module GTYE3_CHANNEL (...); input RXDFEUTOVRDEN; input RXDFEVPHOLD; input RXDFEVPOVRDEN; - input RXDFEVSEN; input RXDFEXYDEN; input RXDLYBYPASS; input RXDLYEN; input RXDLYOVRDEN; input RXDLYSRESET; input [1:0] RXELECIDLEMODE; + input RXEQTRAINING; input RXGEARBOXSLIP; input RXLATCLK; input RXLPMEN; @@ -16846,12 +16915,6 @@ module GTYE3_CHANNEL (...); input RXOOBRESET; input RXOSCALRESET; input RXOSHOLD; - input [3:0] RXOSINTCFG; - input RXOSINTEN; - input RXOSINTHOLD; - input RXOSINTOVRDEN; - input RXOSINTSTROBE; - input RXOSINTTESTOVRDEN; input RXOSOVRDEN; input [2:0] RXOUTCLKSEL; input RXPCOMMAALIGNEN; @@ -16868,6 +16931,7 @@ module GTYE3_CHANNEL (...); input RXPRBSCNTRESET; input [3:0] RXPRBSSEL; input RXPROGDIVRESET; + input RXQPIEN; input [2:0] RXRATE; input RXRATEMODE; input RXSLIDE; @@ -16877,6 +16941,7 @@ module GTYE3_CHANNEL (...); input RXSYNCIN; input RXSYNCMODE; input [1:0] RXSYSCLKSEL; + input RXTERMINATION; input RXUSERRDY; input RXUSRCLK; input RXUSRCLK2; @@ -16884,7 +16949,6 @@ module GTYE3_CHANNEL (...); input [19:0] TSTIN; input [7:0] TX8B10BBYPASS; input TX8B10BEN; - input [2:0] TXBUFDIFFCTRL; input TXCOMINIT; input TXCOMSAS; input TXCOMWAKE; @@ -16895,10 +16959,9 @@ module GTYE3_CHANNEL (...); input [7:0] TXDATAEXTENDRSVD; input TXDCCFORCESTART; input TXDCCRESET; - input TXDEEMPH; + input [1:0] TXDEEMPH; input TXDETECTRX; input [4:0] TXDIFFCTRL; - input TXDIFFPD; input TXDLYBYPASS; input TXDLYEN; input TXDLYHOLD; @@ -16906,12 +16969,17 @@ module GTYE3_CHANNEL (...); input TXDLYSRESET; input TXDLYUPDOWN; input TXELECIDLE; - input TXELFORCESTART; input [5:0] TXHEADER; input TXINHIBIT; input TXLATCLK; + input TXLFPSTRESET; + input TXLFPSU2LPEXIT; + input TXLFPSU3WAKE; input [6:0] TXMAINCURSOR; input [2:0] TXMARGIN; + input TXMUXDCDEXHOLD; + input TXMUXDCDORWREN; + input TXONESZEROS; input [2:0] TXOUTCLKSEL; input TXPCSRESET; input [1:0] TXPD; @@ -16937,6 +17005,8 @@ module GTYE3_CHANNEL (...); input [3:0] TXPRBSSEL; input [4:0] TXPRECURSOR; input TXPROGDIVRESET; + input TXQPIBIASEN; + input TXQPIWEAKPUP; input [2:0] TXRATE; input TXRATEMODE; input [6:0] TXSEQUENCE; @@ -16950,28 +17020,34 @@ module GTYE3_CHANNEL (...); input TXUSRCLK2; endmodule -module GTYE3_COMMON (...); - parameter [15:0] A_SDM1DATA1_0 = 16'b0000000000000000; - parameter [8:0] A_SDM1DATA1_1 = 9'b000000000; +module GTHE4_COMMON (...); + parameter [0:0] AEN_QPLL0_FBDIV = 1'b1; + parameter [0:0] AEN_QPLL1_FBDIV = 1'b1; + parameter [0:0] AEN_SDM0TOGGLE = 1'b0; + parameter [0:0] AEN_SDM1TOGGLE = 1'b0; + parameter [0:0] A_SDM0TOGGLE = 1'b0; + parameter [8:0] A_SDM1DATA_HIGH = 9'b000000000; + parameter [15:0] A_SDM1DATA_LOW = 16'b0000000000000000; + parameter [0:0] A_SDM1TOGGLE = 1'b0; parameter [15:0] BIAS_CFG0 = 16'h0000; parameter [15:0] BIAS_CFG1 = 16'h0000; parameter [15:0] BIAS_CFG2 = 16'h0000; parameter [15:0] BIAS_CFG3 = 16'h0000; parameter [15:0] BIAS_CFG4 = 16'h0000; - parameter [9:0] BIAS_CFG_RSVD = 10'b0000000000; + parameter [15:0] BIAS_CFG_RSVD = 16'h0000; parameter [15:0] COMMON_CFG0 = 16'h0000; parameter [15:0] COMMON_CFG1 = 16'h0000; - parameter [15:0] POR_CFG = 16'h0004; - parameter [15:0] PPF0_CFG = 16'h0FFF; - parameter [15:0] PPF1_CFG = 16'h0FFF; + parameter [15:0] POR_CFG = 16'h0000; + parameter [15:0] PPF0_CFG = 16'h0F00; + parameter [15:0] PPF1_CFG = 16'h0F00; parameter QPLL0CLKOUT_RATE = "FULL"; - parameter [15:0] QPLL0_CFG0 = 16'h301C; + parameter [15:0] QPLL0_CFG0 = 16'h391C; parameter [15:0] QPLL0_CFG1 = 16'h0000; parameter [15:0] QPLL0_CFG1_G3 = 16'h0020; - parameter [15:0] QPLL0_CFG2 = 16'h0780; - parameter [15:0] QPLL0_CFG2_G3 = 16'h0780; + parameter [15:0] QPLL0_CFG2 = 16'h0F80; + parameter [15:0] QPLL0_CFG2_G3 = 16'h0F80; parameter [15:0] QPLL0_CFG3 = 16'h0120; - parameter [15:0] QPLL0_CFG4 = 16'h0021; + parameter [15:0] QPLL0_CFG4 = 16'h0002; parameter [9:0] QPLL0_CP = 10'b0000011111; parameter [9:0] QPLL0_CP_G3 = 10'b0000011111; parameter integer QPLL0_FBDIV = 66; @@ -16980,20 +17056,22 @@ module GTYE3_COMMON (...); parameter [7:0] QPLL0_INIT_CFG1 = 8'h00; parameter [15:0] QPLL0_LOCK_CFG = 16'h01E8; parameter [15:0] QPLL0_LOCK_CFG_G3 = 16'h21E8; - parameter [9:0] QPLL0_LPF = 10'b1111111111; + parameter [9:0] QPLL0_LPF = 10'b1011111111; parameter [9:0] QPLL0_LPF_G3 = 10'b1111111111; - parameter integer QPLL0_REFCLK_DIV = 2; + parameter [0:0] QPLL0_PCI_EN = 1'b0; + parameter [0:0] QPLL0_RATE_SW_USE_DRP = 1'b0; + parameter integer QPLL0_REFCLK_DIV = 1; parameter [15:0] QPLL0_SDM_CFG0 = 16'h0040; parameter [15:0] QPLL0_SDM_CFG1 = 16'h0000; parameter [15:0] QPLL0_SDM_CFG2 = 16'h0000; parameter QPLL1CLKOUT_RATE = "FULL"; - parameter [15:0] QPLL1_CFG0 = 16'h301C; - parameter [15:0] QPLL1_CFG1 = 16'h0000; + parameter [15:0] QPLL1_CFG0 = 16'h691C; + parameter [15:0] QPLL1_CFG1 = 16'h0020; parameter [15:0] QPLL1_CFG1_G3 = 16'h0020; - parameter [15:0] QPLL1_CFG2 = 16'h0780; - parameter [15:0] QPLL1_CFG2_G3 = 16'h0780; + parameter [15:0] QPLL1_CFG2 = 16'h0F80; + parameter [15:0] QPLL1_CFG2_G3 = 16'h0F80; parameter [15:0] QPLL1_CFG3 = 16'h0120; - parameter [15:0] QPLL1_CFG4 = 16'h0021; + parameter [15:0] QPLL1_CFG4 = 16'h0002; parameter [9:0] QPLL1_CP = 10'b0000011111; parameter [9:0] QPLL1_CP_G3 = 10'b0000011111; parameter integer QPLL1_FBDIV = 66; @@ -17002,10 +17080,12 @@ module GTYE3_COMMON (...); parameter [7:0] QPLL1_INIT_CFG1 = 8'h00; parameter [15:0] QPLL1_LOCK_CFG = 16'h01E8; parameter [15:0] QPLL1_LOCK_CFG_G3 = 16'h21E8; - parameter [9:0] QPLL1_LPF = 10'b1111111111; + parameter [9:0] QPLL1_LPF = 10'b1011111111; parameter [9:0] QPLL1_LPF_G3 = 10'b1111111111; - parameter integer QPLL1_REFCLK_DIV = 2; - parameter [15:0] QPLL1_SDM_CFG0 = 16'h0040; + parameter [0:0] QPLL1_PCI_EN = 1'b0; + parameter [0:0] QPLL1_RATE_SW_USE_DRP = 1'b0; + parameter integer QPLL1_REFCLK_DIV = 1; + parameter [15:0] QPLL1_SDM_CFG0 = 16'h0000; parameter [15:0] QPLL1_SDM_CFG1 = 16'h0000; parameter [15:0] QPLL1_SDM_CFG2 = 16'h0000; parameter [15:0] RSVD_ATTR0 = 16'h0000; @@ -17014,15 +17094,15 @@ module GTYE3_COMMON (...); parameter [15:0] RSVD_ATTR3 = 16'h0000; parameter [1:0] RXRECCLKOUT0_SEL = 2'b00; parameter [1:0] RXRECCLKOUT1_SEL = 2'b00; - parameter [0:0] SARC_EN = 1'b1; + parameter [0:0] SARC_ENB = 1'b0; parameter [0:0] SARC_SEL = 1'b0; parameter [15:0] SDM0INITSEED0_0 = 16'b0000000000000000; parameter [8:0] SDM0INITSEED0_1 = 9'b000000000; parameter [15:0] SDM1INITSEED0_0 = 16'b0000000000000000; parameter [8:0] SDM1INITSEED0_1 = 9'b000000000; + parameter SIM_DEVICE = "ULTRASCALE_PLUS"; parameter SIM_MODE = "FAST"; parameter SIM_RESET_SPEEDUP = "TRUE"; - parameter integer SIM_VERSION = 2; output [15:0] DRPDO; output DRPRDY; output [7:0] PMARSVDOUT0; @@ -17041,18 +17121,20 @@ module GTYE3_COMMON (...); output [7:0] QPLLDMONITOR1; output REFCLKOUTMONITOR0; output REFCLKOUTMONITOR1; - output [1:0] RXRECCLK0_SEL; - output [1:0] RXRECCLK1_SEL; + output [1:0] RXRECCLK0SEL; + output [1:0] RXRECCLK1SEL; output [3:0] SDM0FINALOUT; output [14:0] SDM0TESTDATA; output [3:0] SDM1FINALOUT; output [14:0] SDM1TESTDATA; + output [9:0] TCONGPO; + output TCONRSVDOUT0; input BGBYPASSB; input BGMONITORENB; input BGPDB; input [4:0] BGRCALOVRD; input BGRCALOVRDENB; - input [9:0] DRPADDR; + input [15:0] DRPADDR; input DRPCLK; input [15:0] DRPDI; input DRPEN; @@ -17071,15 +17153,21 @@ module GTYE3_COMMON (...); input GTSOUTHREFCLK01; input GTSOUTHREFCLK10; input GTSOUTHREFCLK11; + input [2:0] PCIERATEQPLL0; + input [2:0] PCIERATEQPLL1; input [7:0] PMARSVD0; input [7:0] PMARSVD1; input QPLL0CLKRSVD0; + input QPLL0CLKRSVD1; + input [7:0] QPLL0FBDIV; input QPLL0LOCKDETCLK; input QPLL0LOCKEN; input QPLL0PD; input [2:0] QPLL0REFCLKSEL; input QPLL0RESET; input QPLL1CLKRSVD0; + input QPLL1CLKRSVD1; + input [7:0] QPLL1FBDIV; input QPLL1LOCKDETCLK; input QPLL1LOCKEN; input QPLL1PD; @@ -17092,10 +17180,16 @@ module GTYE3_COMMON (...); input RCALENB; input [24:0] SDM0DATA; input SDM0RESET; + input SDM0TOGGLE; input [1:0] SDM0WIDTH; input [24:0] SDM1DATA; input SDM1RESET; + input SDM1TOGGLE; input [1:0] SDM1WIDTH; + input [9:0] TCONGPI; + input TCONPOWERUP; + input [1:0] TCONRESET; + input [1:0] TCONRSVDIN1; endmodule module GTYE4_CHANNEL (...); @@ -17357,7 +17451,7 @@ module GTYE4_CHANNEL (...); parameter [15:0] RXDFE_KH_CFG0 = 16'h0000; parameter [15:0] RXDFE_KH_CFG1 = 16'h0000; parameter [15:0] RXDFE_KH_CFG2 = 16'h0000; - parameter [15:0] RXDFE_KH_CFG3 = 16'h0000; + parameter [15:0] RXDFE_KH_CFG3 = 16'h2000; parameter [15:0] RXDFE_OS_CFG0 = 16'h0000; parameter [15:0] RXDFE_OS_CFG1 = 16'h0000; parameter [15:0] RXDFE_UT_CFG0 = 16'h0000; @@ -17408,7 +17502,7 @@ module GTYE4_CHANNEL (...); parameter [4:0] RX_CLK_SLIP_OVRD = 5'b00000; parameter [3:0] RX_CM_BUF_CFG = 4'b1010; parameter [0:0] RX_CM_BUF_PD = 1'b0; - parameter integer RX_CM_SEL = 3; + parameter integer RX_CM_SEL = 2; parameter integer RX_CM_TRIM = 12; parameter [0:0] RX_CTLE_PWR_SAVING = 1'b0; parameter [3:0] RX_CTLE_RES_CTRL = 4'b0000; @@ -17416,12 +17510,12 @@ module GTYE4_CHANNEL (...); parameter [5:0] RX_DDI_SEL = 6'b000000; parameter RX_DEFER_RESET_BUF_EN = "TRUE"; parameter [2:0] RX_DEGEN_CTRL = 3'b100; - parameter integer RX_DFELPM_CFG0 = 0; + parameter integer RX_DFELPM_CFG0 = 10; parameter [0:0] RX_DFELPM_CFG1 = 1'b1; parameter [0:0] RX_DFELPM_KLKH_AGC_STUP_EN = 1'b1; parameter integer RX_DFE_AGC_CFG1 = 4; parameter integer RX_DFE_KL_LPM_KH_CFG0 = 1; - parameter integer RX_DFE_KL_LPM_KH_CFG1 = 4; + parameter integer RX_DFE_KL_LPM_KH_CFG1 = 2; parameter [1:0] RX_DFE_KL_LPM_KL_CFG0 = 2'b01; parameter integer RX_DFE_KL_LPM_KL_CFG1 = 4; parameter [0:0] RX_DFE_LPM_HOLD_DURING_EIDLE = 1'b0; @@ -17437,7 +17531,7 @@ module GTYE4_CHANNEL (...); parameter [0:0] RX_I2V_FILTER_EN = 1'b1; parameter integer RX_INT_DATAWIDTH = 1; parameter [0:0] RX_PMA_POWER_SAVE = 1'b0; - parameter [15:0] RX_PMA_RSV0 = 16'h000F; + parameter [15:0] RX_PMA_RSV0 = 16'h002F; parameter real RX_PROGDIV_CFG = 0.0; parameter [15:0] RX_PROGDIV_RATE = 16'h0001; parameter [3:0] RX_RESLOAD_CTRL = 4'b0000; @@ -17468,11 +17562,11 @@ module GTYE4_CHANNEL (...); parameter SATA_CPLL_CFG = "VCO_3000MHZ"; parameter [2:0] SATA_EIDLE_VAL = 3'b100; parameter SHOW_REALIGN_COMMA = "TRUE"; + parameter SIM_DEVICE = "ULTRASCALE_PLUS"; parameter SIM_MODE = "FAST"; parameter SIM_RECEIVER_DETECT_PASS = "TRUE"; parameter SIM_RESET_SPEEDUP = "TRUE"; parameter SIM_TX_EIDLE_DRIVE_LEVEL = "Z"; - parameter SIM_DEVICE = "ULTRASCALE_PLUS"; parameter [0:0] SRSTMODE = 1'b0; parameter [1:0] TAPDLY_SET_TX = 2'h0; parameter [14:0] TERM_RCAL_CFG = 15'b100001000010000; @@ -18004,9 +18098,9 @@ module GTYE4_COMMON (...); parameter [8:0] SDM0INITSEED0_1 = 9'b000000000; parameter [15:0] SDM1INITSEED0_0 = 16'b0000000000000000; parameter [8:0] SDM1INITSEED0_1 = 9'b000000000; + parameter SIM_DEVICE = "ULTRASCALE_PLUS"; parameter SIM_MODE = "FAST"; parameter SIM_RESET_SPEEDUP = "TRUE"; - parameter SIM_DEVICE = "ULTRASCALE_PLUS"; parameter [15:0] UB_CFG0 = 16'h0000; parameter [15:0] UB_CFG1 = 16'h0000; parameter [15:0] UB_CFG2 = 16'h0000; @@ -18120,19 +18214,6 @@ module GTYE4_COMMON (...); input UBMDMTDI; endmodule -module IBUFDS_GTE3 (...); - parameter [0:0] REFCLK_EN_TX_PATH = 1'b0; - parameter [1:0] REFCLK_HROW_CK_SEL = 2'b00; - parameter [1:0] REFCLK_ICNTL_RX = 2'b00; - output O; - output ODIV2; - input CEB; - (* iopad_external_pin *) - input I; - (* iopad_external_pin *) - input IB; -endmodule - module IBUFDS_GTE4 (...); parameter [0:0] REFCLK_EN_TX_PATH = 1'b0; parameter [1:0] REFCLK_HROW_CK_SEL = 2'b00; @@ -18146,7 +18227,7 @@ module IBUFDS_GTE4 (...); input IB; endmodule -module OBUFDS_GTE3 (...); +module OBUFDS_GTE4 (...); parameter [0:0] REFCLK_EN_TX_PATH = 1'b0; parameter [4:0] REFCLK_ICNTL_TX = 5'b00000; (* iopad_external_pin *) @@ -18157,7 +18238,7 @@ module OBUFDS_GTE3 (...); input I; endmodule -module OBUFDS_GTE3_ADV (...); +module OBUFDS_GTE4_ADV (...); parameter [0:0] REFCLK_EN_TX_PATH = 1'b0; parameter [4:0] REFCLK_ICNTL_TX = 5'b00000; (* iopad_external_pin *) @@ -18169,9 +18250,669 @@ module OBUFDS_GTE3_ADV (...); input [1:0] RXRECCLK_SEL; endmodule -module OBUFDS_GTE4 (...); +module GTM_DUAL (...); + parameter [15:0] A_CFG = 16'b0000100001000000; + parameter [15:0] A_SDM_DATA_CFG0 = 16'b0000000011010000; + parameter [15:0] A_SDM_DATA_CFG1 = 16'b0000000011010000; + parameter [15:0] BIAS_CFG0 = 16'b0000000000000000; + parameter [15:0] BIAS_CFG1 = 16'b0000000000000000; + parameter [15:0] BIAS_CFG2 = 16'b0001000000000000; + parameter [15:0] BIAS_CFG3 = 16'b0000000000000001; + parameter [15:0] BIAS_CFG4 = 16'b0000000000000000; + parameter [15:0] BIAS_CFG5 = 16'b0000000000000000; + parameter [15:0] BIAS_CFG6 = 16'b0000000010000000; + parameter [15:0] BIAS_CFG7 = 16'b0000000000000000; + parameter [15:0] CH0_A_CH_CFG0 = 16'b0000000000000011; + parameter [15:0] CH0_A_CH_CFG1 = 16'b0000000000000000; + parameter [15:0] CH0_A_CH_CFG2 = 16'b0111101111110000; + parameter [15:0] CH0_A_CH_CFG3 = 16'b0000000000000000; + parameter [15:0] CH0_A_CH_CFG4 = 16'b0000000000000000; + parameter [15:0] CH0_A_CH_CFG5 = 16'b0000000000000000; + parameter [15:0] CH0_A_CH_CFG6 = 16'b0000000000000000; + parameter [15:0] CH0_RST_LP_CFG0 = 16'b0001000000010000; + parameter [15:0] CH0_RST_LP_CFG1 = 16'b0011001000010000; + parameter [15:0] CH0_RST_LP_CFG2 = 16'b0110010100000100; + parameter [15:0] CH0_RST_LP_CFG3 = 16'b0011001000010000; + parameter [15:0] CH0_RST_LP_CFG4 = 16'b0000000001000100; + parameter [15:0] CH0_RST_LP_ID_CFG0 = 16'b0011000001110000; + parameter [15:0] CH0_RST_LP_ID_CFG1 = 16'b0001000000010000; + parameter [15:0] CH0_RST_TIME_CFG0 = 16'b0000010000100001; + parameter [15:0] CH0_RST_TIME_CFG1 = 16'b0000010000100001; + parameter [15:0] CH0_RST_TIME_CFG2 = 16'b0000010000100001; + parameter [15:0] CH0_RST_TIME_CFG3 = 16'b0000010000100000; + parameter [15:0] CH0_RST_TIME_CFG4 = 16'b0000010000100001; + parameter [15:0] CH0_RST_TIME_CFG5 = 16'b0000000000000001; + parameter [15:0] CH0_RST_TIME_CFG6 = 16'b0000000000100001; + parameter [15:0] CH0_RX_ADC_CFG0 = 16'b0011010010001111; + parameter [15:0] CH0_RX_ADC_CFG1 = 16'b0011111001010101; + parameter [15:0] CH0_RX_ANA_CFG0 = 16'b1000000000011101; + parameter [15:0] CH0_RX_ANA_CFG1 = 16'b1110100010000000; + parameter [15:0] CH0_RX_ANA_CFG2 = 16'b0000000010001010; + parameter [15:0] CH0_RX_APT_CFG0A = 16'b0000000001110000; + parameter [15:0] CH0_RX_APT_CFG0B = 16'b0000000001110000; + parameter [15:0] CH0_RX_APT_CFG10A = 16'b0000000001110000; + parameter [15:0] CH0_RX_APT_CFG10B = 16'b0000000001010000; + parameter [15:0] CH0_RX_APT_CFG11A = 16'b0000000001000000; + parameter [15:0] CH0_RX_APT_CFG11B = 16'b0000000001110000; + parameter [15:0] CH0_RX_APT_CFG12A = 16'b0000000001010000; + parameter [15:0] CH0_RX_APT_CFG12B = 16'b0000000000000000; + parameter [15:0] CH0_RX_APT_CFG13A = 16'b0000000000000000; + parameter [15:0] CH0_RX_APT_CFG13B = 16'b0000000000000000; + parameter [15:0] CH0_RX_APT_CFG14A = 16'b0000000000000000; + parameter [15:0] CH0_RX_APT_CFG14B = 16'b0000000000000000; + parameter [15:0] CH0_RX_APT_CFG15A = 16'b0000000000000000; + parameter [15:0] CH0_RX_APT_CFG15B = 16'b0000100000000000; + parameter [15:0] CH0_RX_APT_CFG16A = 16'b0000000000000000; + parameter [15:0] CH0_RX_APT_CFG16B = 16'b0010000000000000; + parameter [15:0] CH0_RX_APT_CFG17A = 16'b0000000000000000; + parameter [15:0] CH0_RX_APT_CFG17B = 16'b0001000001000000; + parameter [15:0] CH0_RX_APT_CFG18A = 16'b0000100000100000; + parameter [15:0] CH0_RX_APT_CFG18B = 16'b0000000000000000; + parameter [15:0] CH0_RX_APT_CFG19A = 16'b0000000000000000; + parameter [15:0] CH0_RX_APT_CFG19B = 16'b0000100000000000; + parameter [15:0] CH0_RX_APT_CFG1A = 16'b0000000001110000; + parameter [15:0] CH0_RX_APT_CFG1B = 16'b0000000001110000; + parameter [15:0] CH0_RX_APT_CFG20A = 16'b1110000000100000; + parameter [15:0] CH0_RX_APT_CFG20B = 16'b0000000001000000; + parameter [15:0] CH0_RX_APT_CFG21A = 16'b0001000000000100; + parameter [15:0] CH0_RX_APT_CFG21B = 16'b0000000000000000; + parameter [15:0] CH0_RX_APT_CFG22A = 16'b0000000001110000; + parameter [15:0] CH0_RX_APT_CFG22B = 16'b0000000001110000; + parameter [15:0] CH0_RX_APT_CFG23A = 16'b0000100000000000; + parameter [15:0] CH0_RX_APT_CFG23B = 16'b0000000000000000; + parameter [15:0] CH0_RX_APT_CFG24A = 16'b0000000000000000; + parameter [15:0] CH0_RX_APT_CFG24B = 16'b0000000000000000; + parameter [15:0] CH0_RX_APT_CFG25A = 16'b0000000000000000; + parameter [15:0] CH0_RX_APT_CFG25B = 16'b0000000000000000; + parameter [15:0] CH0_RX_APT_CFG26A = 16'b0000000000000000; + parameter [15:0] CH0_RX_APT_CFG26B = 16'b0000000000000000; + parameter [15:0] CH0_RX_APT_CFG27A = 16'b0100000000000000; + parameter [15:0] CH0_RX_APT_CFG27B = 16'b0000000000000000; + parameter [15:0] CH0_RX_APT_CFG28A = 16'b0000000000000000; + parameter [15:0] CH0_RX_APT_CFG28B = 16'b1000000000000000; + parameter [15:0] CH0_RX_APT_CFG2A = 16'b0000000001110000; + parameter [15:0] CH0_RX_APT_CFG2B = 16'b0000000001110000; + parameter [15:0] CH0_RX_APT_CFG3A = 16'b0000000001110000; + parameter [15:0] CH0_RX_APT_CFG3B = 16'b0000000001110000; + parameter [15:0] CH0_RX_APT_CFG4A = 16'b0000000001110000; + parameter [15:0] CH0_RX_APT_CFG4B = 16'b0000000001110000; + parameter [15:0] CH0_RX_APT_CFG5A = 16'b0000000001110000; + parameter [15:0] CH0_RX_APT_CFG5B = 16'b0000000001110000; + parameter [15:0] CH0_RX_APT_CFG6A = 16'b0000000001110000; + parameter [15:0] CH0_RX_APT_CFG6B = 16'b0000000001110000; + parameter [15:0] CH0_RX_APT_CFG7A = 16'b0000000001110000; + parameter [15:0] CH0_RX_APT_CFG7B = 16'b0000000001110000; + parameter [15:0] CH0_RX_APT_CFG8A = 16'b0000100000000000; + parameter [15:0] CH0_RX_APT_CFG8B = 16'b0000100000000000; + parameter [15:0] CH0_RX_APT_CFG9A = 16'b0000000001110000; + parameter [15:0] CH0_RX_APT_CFG9B = 16'b0000000001110000; + parameter [15:0] CH0_RX_APT_CTRL_CFG2 = 16'b0000000000000100; + parameter [15:0] CH0_RX_APT_CTRL_CFG3 = 16'b0000000000000000; + parameter [15:0] CH0_RX_CAL_CFG0A = 16'b0000000000000000; + parameter [15:0] CH0_RX_CAL_CFG0B = 16'b0011001100110000; + parameter [15:0] CH0_RX_CAL_CFG1A = 16'b1110111011100001; + parameter [15:0] CH0_RX_CAL_CFG1B = 16'b1111111100000100; + parameter [15:0] CH0_RX_CAL_CFG2A = 16'b0000000000000000; + parameter [15:0] CH0_RX_CAL_CFG2B = 16'b0011000000000000; + parameter [15:0] CH0_RX_CDR_CFG0A = 16'b0000000000000011; + parameter [15:0] CH0_RX_CDR_CFG0B = 16'b0000000000000000; + parameter [15:0] CH0_RX_CDR_CFG1A = 16'b0000000000000000; + parameter [15:0] CH0_RX_CDR_CFG1B = 16'b0000000000000000; + parameter [15:0] CH0_RX_CDR_CFG2A = 16'b1001000101100100; + parameter [15:0] CH0_RX_CDR_CFG2B = 16'b0000000100100100; + parameter [15:0] CH0_RX_CDR_CFG3A = 16'b0101110011110110; + parameter [15:0] CH0_RX_CDR_CFG3B = 16'b0000000000001011; + parameter [15:0] CH0_RX_CDR_CFG4A = 16'b0000000000000110; + parameter [15:0] CH0_RX_CDR_CFG4B = 16'b0000000000000000; + parameter [15:0] CH0_RX_CLKGN_CFG0 = 16'b1100000000000000; + parameter [15:0] CH0_RX_CLKGN_CFG1 = 16'b0000000110000000; + parameter [15:0] CH0_RX_CTLE_CFG0 = 16'b0011010010001000; + parameter [15:0] CH0_RX_CTLE_CFG1 = 16'b0010000000100010; + parameter [15:0] CH0_RX_CTLE_CFG2 = 16'b0000101000000000; + parameter [15:0] CH0_RX_CTLE_CFG3 = 16'b1111001001000000; + parameter [15:0] CH0_RX_DSP_CFG = 16'b0000000000000000; + parameter [15:0] CH0_RX_MON_CFG = 16'b0000000000000000; + parameter [15:0] CH0_RX_PAD_CFG0 = 16'b0001111000000000; + parameter [15:0] CH0_RX_PAD_CFG1 = 16'b0001100000001010; + parameter [15:0] CH0_RX_PCS_CFG0 = 16'b0000000100000000; + parameter [15:0] CH0_RX_PCS_CFG1 = 16'b0000000000000000; + parameter [15:0] CH0_TX_ANA_CFG0 = 16'b0000001010101111; + parameter [15:0] CH0_TX_ANA_CFG1 = 16'b0000000100000000; + parameter [15:0] CH0_TX_ANA_CFG2 = 16'b1000000000010100; + parameter [15:0] CH0_TX_ANA_CFG3 = 16'b0000101000100010; + parameter [15:0] CH0_TX_ANA_CFG4 = 16'b0000000000000000; + parameter [15:0] CH0_TX_CAL_CFG0 = 16'b0000000000100000; + parameter [15:0] CH0_TX_CAL_CFG1 = 16'b0000000001000000; + parameter [15:0] CH0_TX_DRV_CFG0 = 16'b0000000000000000; + parameter [15:0] CH0_TX_DRV_CFG1 = 16'b0000000000100111; + parameter [15:0] CH0_TX_DRV_CFG2 = 16'b0000000000000000; + parameter [15:0] CH0_TX_DRV_CFG3 = 16'b0110110000000000; + parameter [15:0] CH0_TX_DRV_CFG4 = 16'b0000000011000101; + parameter [15:0] CH0_TX_DRV_CFG5 = 16'b0000000000000000; + parameter [15:0] CH0_TX_LPBK_CFG0 = 16'b0000000000000011; + parameter [15:0] CH0_TX_LPBK_CFG1 = 16'b0000000000000000; + parameter [15:0] CH0_TX_PCS_CFG0 = 16'b0000000101100000; + parameter [15:0] CH0_TX_PCS_CFG1 = 16'b0000000000000000; + parameter [15:0] CH0_TX_PCS_CFG10 = 16'b0000000000000000; + parameter [15:0] CH0_TX_PCS_CFG11 = 16'b0000000000000000; + parameter [15:0] CH0_TX_PCS_CFG12 = 16'b0000000000000000; + parameter [15:0] CH0_TX_PCS_CFG13 = 16'b0000000000000000; + parameter [15:0] CH0_TX_PCS_CFG14 = 16'b0000000000000000; + parameter [15:0] CH0_TX_PCS_CFG15 = 16'b0000000000000000; + parameter [15:0] CH0_TX_PCS_CFG16 = 16'b0000000000000000; + parameter [15:0] CH0_TX_PCS_CFG17 = 16'b0000000000000000; + parameter [15:0] CH0_TX_PCS_CFG2 = 16'b0000000000000000; + parameter [15:0] CH0_TX_PCS_CFG3 = 16'b0000000000000000; + parameter [15:0] CH0_TX_PCS_CFG4 = 16'b0000000000000000; + parameter [15:0] CH0_TX_PCS_CFG5 = 16'b0000000000000000; + parameter [15:0] CH0_TX_PCS_CFG6 = 16'b0000000000000000; + parameter [15:0] CH0_TX_PCS_CFG7 = 16'b0000000000000000; + parameter [15:0] CH0_TX_PCS_CFG8 = 16'b0000000000000000; + parameter [15:0] CH0_TX_PCS_CFG9 = 16'b0000000000000000; + parameter [15:0] CH1_A_CH_CFG0 = 16'b0000000000000011; + parameter [15:0] CH1_A_CH_CFG1 = 16'b0000000000000000; + parameter [15:0] CH1_A_CH_CFG2 = 16'b0111101111110000; + parameter [15:0] CH1_A_CH_CFG3 = 16'b0000000000000000; + parameter [15:0] CH1_A_CH_CFG4 = 16'b0000000000000000; + parameter [15:0] CH1_A_CH_CFG5 = 16'b0000000000000000; + parameter [15:0] CH1_A_CH_CFG6 = 16'b0000000000000000; + parameter [15:0] CH1_RST_LP_CFG0 = 16'b0001000000010000; + parameter [15:0] CH1_RST_LP_CFG1 = 16'b0011001000010000; + parameter [15:0] CH1_RST_LP_CFG2 = 16'b0110010100000100; + parameter [15:0] CH1_RST_LP_CFG3 = 16'b0011001000010000; + parameter [15:0] CH1_RST_LP_CFG4 = 16'b0000000001000100; + parameter [15:0] CH1_RST_LP_ID_CFG0 = 16'b0011000001110000; + parameter [15:0] CH1_RST_LP_ID_CFG1 = 16'b0001000000010000; + parameter [15:0] CH1_RST_TIME_CFG0 = 16'b0000010000100001; + parameter [15:0] CH1_RST_TIME_CFG1 = 16'b0000010000100001; + parameter [15:0] CH1_RST_TIME_CFG2 = 16'b0000010000100001; + parameter [15:0] CH1_RST_TIME_CFG3 = 16'b0000010000100000; + parameter [15:0] CH1_RST_TIME_CFG4 = 16'b0000010000100001; + parameter [15:0] CH1_RST_TIME_CFG5 = 16'b0000000000000001; + parameter [15:0] CH1_RST_TIME_CFG6 = 16'b0000000000100001; + parameter [15:0] CH1_RX_ADC_CFG0 = 16'b0011010010001111; + parameter [15:0] CH1_RX_ADC_CFG1 = 16'b0011111001010101; + parameter [15:0] CH1_RX_ANA_CFG0 = 16'b1000000000011101; + parameter [15:0] CH1_RX_ANA_CFG1 = 16'b1110100010000000; + parameter [15:0] CH1_RX_ANA_CFG2 = 16'b0000000010001010; + parameter [15:0] CH1_RX_APT_CFG0A = 16'b0000000001110000; + parameter [15:0] CH1_RX_APT_CFG0B = 16'b0000000001110000; + parameter [15:0] CH1_RX_APT_CFG10A = 16'b0000000001110000; + parameter [15:0] CH1_RX_APT_CFG10B = 16'b0000000001010000; + parameter [15:0] CH1_RX_APT_CFG11A = 16'b0000000001000000; + parameter [15:0] CH1_RX_APT_CFG11B = 16'b0000000001110000; + parameter [15:0] CH1_RX_APT_CFG12A = 16'b0000000001010000; + parameter [15:0] CH1_RX_APT_CFG12B = 16'b0000000000000000; + parameter [15:0] CH1_RX_APT_CFG13A = 16'b0000000000000000; + parameter [15:0] CH1_RX_APT_CFG13B = 16'b0000000000000000; + parameter [15:0] CH1_RX_APT_CFG14A = 16'b0000000000000000; + parameter [15:0] CH1_RX_APT_CFG14B = 16'b0000000000000000; + parameter [15:0] CH1_RX_APT_CFG15A = 16'b0000000000000000; + parameter [15:0] CH1_RX_APT_CFG15B = 16'b0000100000000000; + parameter [15:0] CH1_RX_APT_CFG16A = 16'b0000000000000000; + parameter [15:0] CH1_RX_APT_CFG16B = 16'b0010000000000000; + parameter [15:0] CH1_RX_APT_CFG17A = 16'b0000000000000000; + parameter [15:0] CH1_RX_APT_CFG17B = 16'b0001000001000000; + parameter [15:0] CH1_RX_APT_CFG18A = 16'b0000100000100000; + parameter [15:0] CH1_RX_APT_CFG18B = 16'b0000100010000000; + parameter [15:0] CH1_RX_APT_CFG19A = 16'b0000000000000000; + parameter [15:0] CH1_RX_APT_CFG19B = 16'b0000100000000000; + parameter [15:0] CH1_RX_APT_CFG1A = 16'b0000000001110000; + parameter [15:0] CH1_RX_APT_CFG1B = 16'b0000000001110000; + parameter [15:0] CH1_RX_APT_CFG20A = 16'b1110000000100000; + parameter [15:0] CH1_RX_APT_CFG20B = 16'b0000000001000000; + parameter [15:0] CH1_RX_APT_CFG21A = 16'b0001000000000100; + parameter [15:0] CH1_RX_APT_CFG21B = 16'b0000000000000000; + parameter [15:0] CH1_RX_APT_CFG22A = 16'b0000000001110000; + parameter [15:0] CH1_RX_APT_CFG22B = 16'b0000000001110000; + parameter [15:0] CH1_RX_APT_CFG23A = 16'b0000100000000000; + parameter [15:0] CH1_RX_APT_CFG23B = 16'b0000100000000000; + parameter [15:0] CH1_RX_APT_CFG24A = 16'b0000000000000000; + parameter [15:0] CH1_RX_APT_CFG24B = 16'b0000000000000000; + parameter [15:0] CH1_RX_APT_CFG25A = 16'b0000000000000000; + parameter [15:0] CH1_RX_APT_CFG25B = 16'b0000000000000000; + parameter [15:0] CH1_RX_APT_CFG26A = 16'b0000000000000000; + parameter [15:0] CH1_RX_APT_CFG26B = 16'b0000000000000000; + parameter [15:0] CH1_RX_APT_CFG27A = 16'b0100000000000000; + parameter [15:0] CH1_RX_APT_CFG27B = 16'b0000000000000000; + parameter [15:0] CH1_RX_APT_CFG28A = 16'b0000000000000000; + parameter [15:0] CH1_RX_APT_CFG28B = 16'b1000000000000000; + parameter [15:0] CH1_RX_APT_CFG2A = 16'b0000000001110000; + parameter [15:0] CH1_RX_APT_CFG2B = 16'b0000000001110000; + parameter [15:0] CH1_RX_APT_CFG3A = 16'b0000000001110000; + parameter [15:0] CH1_RX_APT_CFG3B = 16'b0000000001110000; + parameter [15:0] CH1_RX_APT_CFG4A = 16'b0000000001110000; + parameter [15:0] CH1_RX_APT_CFG4B = 16'b0000000001110000; + parameter [15:0] CH1_RX_APT_CFG5A = 16'b0000000001110000; + parameter [15:0] CH1_RX_APT_CFG5B = 16'b0000000001110000; + parameter [15:0] CH1_RX_APT_CFG6A = 16'b0000000001110000; + parameter [15:0] CH1_RX_APT_CFG6B = 16'b0000000001110000; + parameter [15:0] CH1_RX_APT_CFG7A = 16'b0000000001110000; + parameter [15:0] CH1_RX_APT_CFG7B = 16'b0000000001110000; + parameter [15:0] CH1_RX_APT_CFG8A = 16'b0000100000000000; + parameter [15:0] CH1_RX_APT_CFG8B = 16'b0000100000000000; + parameter [15:0] CH1_RX_APT_CFG9A = 16'b0000000001110000; + parameter [15:0] CH1_RX_APT_CFG9B = 16'b0000000001110000; + parameter [15:0] CH1_RX_APT_CTRL_CFG2 = 16'b0000000000000100; + parameter [15:0] CH1_RX_APT_CTRL_CFG3 = 16'b0000000000000000; + parameter [15:0] CH1_RX_CAL_CFG0A = 16'b0000000000000000; + parameter [15:0] CH1_RX_CAL_CFG0B = 16'b0011001100110000; + parameter [15:0] CH1_RX_CAL_CFG1A = 16'b1110111011100001; + parameter [15:0] CH1_RX_CAL_CFG1B = 16'b1111111100000100; + parameter [15:0] CH1_RX_CAL_CFG2A = 16'b0000000000000000; + parameter [15:0] CH1_RX_CAL_CFG2B = 16'b0011000000000000; + parameter [15:0] CH1_RX_CDR_CFG0A = 16'b0000000000000011; + parameter [15:0] CH1_RX_CDR_CFG0B = 16'b0000000000000000; + parameter [15:0] CH1_RX_CDR_CFG1A = 16'b0000000000000000; + parameter [15:0] CH1_RX_CDR_CFG1B = 16'b0000000000000000; + parameter [15:0] CH1_RX_CDR_CFG2A = 16'b1001000101100100; + parameter [15:0] CH1_RX_CDR_CFG2B = 16'b0000000100100100; + parameter [15:0] CH1_RX_CDR_CFG3A = 16'b0101110011110110; + parameter [15:0] CH1_RX_CDR_CFG3B = 16'b0000000000001011; + parameter [15:0] CH1_RX_CDR_CFG4A = 16'b0000000000000110; + parameter [15:0] CH1_RX_CDR_CFG4B = 16'b0000000000000000; + parameter [15:0] CH1_RX_CLKGN_CFG0 = 16'b1100000000000000; + parameter [15:0] CH1_RX_CLKGN_CFG1 = 16'b0000000110000000; + parameter [15:0] CH1_RX_CTLE_CFG0 = 16'b0011010010001000; + parameter [15:0] CH1_RX_CTLE_CFG1 = 16'b0010000000100010; + parameter [15:0] CH1_RX_CTLE_CFG2 = 16'b0000101000000000; + parameter [15:0] CH1_RX_CTLE_CFG3 = 16'b1111001001000000; + parameter [15:0] CH1_RX_DSP_CFG = 16'b0000000000000000; + parameter [15:0] CH1_RX_MON_CFG = 16'b0000000000000000; + parameter [15:0] CH1_RX_PAD_CFG0 = 16'b0001111000000000; + parameter [15:0] CH1_RX_PAD_CFG1 = 16'b0001100000001010; + parameter [15:0] CH1_RX_PCS_CFG0 = 16'b0000000100000000; + parameter [15:0] CH1_RX_PCS_CFG1 = 16'b0000000000000000; + parameter [15:0] CH1_TX_ANA_CFG0 = 16'b0000001010101111; + parameter [15:0] CH1_TX_ANA_CFG1 = 16'b0000000100000000; + parameter [15:0] CH1_TX_ANA_CFG2 = 16'b1000000000010100; + parameter [15:0] CH1_TX_ANA_CFG3 = 16'b0000101000100010; + parameter [15:0] CH1_TX_ANA_CFG4 = 16'b0000000000000000; + parameter [15:0] CH1_TX_CAL_CFG0 = 16'b0000000000100000; + parameter [15:0] CH1_TX_CAL_CFG1 = 16'b0000000001000000; + parameter [15:0] CH1_TX_DRV_CFG0 = 16'b0000000000000000; + parameter [15:0] CH1_TX_DRV_CFG1 = 16'b0000000000100111; + parameter [15:0] CH1_TX_DRV_CFG2 = 16'b0000000000000000; + parameter [15:0] CH1_TX_DRV_CFG3 = 16'b0110110000000000; + parameter [15:0] CH1_TX_DRV_CFG4 = 16'b0000000011000101; + parameter [15:0] CH1_TX_DRV_CFG5 = 16'b0000000000000000; + parameter [15:0] CH1_TX_LPBK_CFG0 = 16'b0000000000000011; + parameter [15:0] CH1_TX_LPBK_CFG1 = 16'b0000000000000000; + parameter [15:0] CH1_TX_PCS_CFG0 = 16'b0000000101100000; + parameter [15:0] CH1_TX_PCS_CFG1 = 16'b0000000000000000; + parameter [15:0] CH1_TX_PCS_CFG10 = 16'b0000000000000000; + parameter [15:0] CH1_TX_PCS_CFG11 = 16'b0000000000000000; + parameter [15:0] CH1_TX_PCS_CFG12 = 16'b0000000000000000; + parameter [15:0] CH1_TX_PCS_CFG13 = 16'b0000000000000000; + parameter [15:0] CH1_TX_PCS_CFG14 = 16'b0000000000000000; + parameter [15:0] CH1_TX_PCS_CFG15 = 16'b0000000000000000; + parameter [15:0] CH1_TX_PCS_CFG16 = 16'b0000000000000000; + parameter [15:0] CH1_TX_PCS_CFG17 = 16'b0000000000000000; + parameter [15:0] CH1_TX_PCS_CFG2 = 16'b0000000000000000; + parameter [15:0] CH1_TX_PCS_CFG3 = 16'b0000000000000000; + parameter [15:0] CH1_TX_PCS_CFG4 = 16'b0000000000000000; + parameter [15:0] CH1_TX_PCS_CFG5 = 16'b0000000000000000; + parameter [15:0] CH1_TX_PCS_CFG6 = 16'b0000000000000000; + parameter [15:0] CH1_TX_PCS_CFG7 = 16'b0000000000000000; + parameter [15:0] CH1_TX_PCS_CFG8 = 16'b0000000000000000; + parameter [15:0] CH1_TX_PCS_CFG9 = 16'b0000000000000000; + parameter real DATARATE = 10.000; + parameter [15:0] DRPEN_CFG = 16'b0000000000000000; + parameter [15:0] FEC_CFG0 = 16'b0000000000000000; + parameter [15:0] FEC_CFG1 = 16'b0000000000000000; + parameter [15:0] FEC_CFG10 = 16'b0000000000000000; + parameter [15:0] FEC_CFG11 = 16'b0000000000000000; + parameter [15:0] FEC_CFG12 = 16'b0000000000000000; + parameter [15:0] FEC_CFG13 = 16'b0000000000000000; + parameter [15:0] FEC_CFG14 = 16'b0000000000000000; + parameter [15:0] FEC_CFG15 = 16'b0000000000000000; + parameter [15:0] FEC_CFG16 = 16'b0000000000000000; + parameter [15:0] FEC_CFG17 = 16'b0000000000000000; + parameter [15:0] FEC_CFG18 = 16'b0000000000000000; + parameter [15:0] FEC_CFG19 = 16'b0000000000000000; + parameter [15:0] FEC_CFG2 = 16'b0000000000000000; + parameter [15:0] FEC_CFG20 = 16'b0000000000000000; + parameter [15:0] FEC_CFG21 = 16'b0000000000000000; + parameter [15:0] FEC_CFG22 = 16'b0000000000000000; + parameter [15:0] FEC_CFG23 = 16'b0000000000000000; + parameter [15:0] FEC_CFG24 = 16'b0000000000000000; + parameter [15:0] FEC_CFG25 = 16'b0000000000000000; + parameter [15:0] FEC_CFG26 = 16'b0000000000000000; + parameter [15:0] FEC_CFG27 = 16'b0000000000000000; + parameter [15:0] FEC_CFG3 = 16'b0000000000000000; + parameter [15:0] FEC_CFG4 = 16'b0000000000000000; + parameter [15:0] FEC_CFG5 = 16'b0000000000000000; + parameter [15:0] FEC_CFG6 = 16'b0000000000000000; + parameter [15:0] FEC_CFG7 = 16'b0000000000000000; + parameter [15:0] FEC_CFG8 = 16'b0000000000000000; + parameter [15:0] FEC_CFG9 = 16'b0000000000000000; + parameter FEC_MODE = "BYPASS"; + parameter real INS_LOSS_NYQ = 20.000; + parameter integer INTERFACE_WIDTH = 64; + parameter MODULATION_MODE = "NRZ"; + parameter [15:0] PLL_CFG0 = 16'b0001100111110000; + parameter [15:0] PLL_CFG1 = 16'b0000111101110000; + parameter [15:0] PLL_CFG2 = 16'b1000000111101000; + parameter [15:0] PLL_CFG3 = 16'b0100000000000000; + parameter [15:0] PLL_CFG4 = 16'b0111111111101010; + parameter [15:0] PLL_CFG5 = 16'b0100101100111000; + parameter [15:0] PLL_CFG6 = 16'b0000000000100101; + parameter [15:0] PLL_CRS_CTRL_CFG0 = 16'b0000101100100000; + parameter [15:0] PLL_CRS_CTRL_CFG1 = 16'b1100010111010100; + parameter [0:0] PLL_IPS_PIN_EN = 1'b1; + parameter integer PLL_IPS_REFCLK_SEL = 0; + parameter [0:0] RCALSAP_TESTEN = 1'b0; + parameter [0:0] RCAL_APROBE = 1'b0; + parameter [15:0] RST_CFG = 16'b0000000000000010; + parameter [15:0] RST_PLL_CFG0 = 16'b0111011000010100; + parameter [15:0] SAP_CFG0 = 16'b0000000000000000; + parameter [15:0] SDM_CFG0 = 16'b0001100001000000; + parameter [15:0] SDM_CFG1 = 16'b0000000000000000; + parameter [15:0] SDM_CFG2 = 16'b0000000000000000; + parameter [15:0] SDM_SEED_CFG0 = 16'b0000000000000000; + parameter [15:0] SDM_SEED_CFG1 = 16'b0000000000000000; + parameter SIM_DEVICE = "ULTRASCALE_PLUS_ES1"; + parameter SIM_RESET_SPEEDUP = "TRUE"; + parameter integer TX_AMPLITUDE_SWING = 250; + output [27:0] CH0_AXISTDATA; + output CH0_AXISTLAST; + output CH0_AXISTVALID; + output [31:0] CH0_DMONITOROUT; + output CH0_DMONITOROUTCLK; + output CH0_GTMTXN; + output CH0_GTMTXP; + output [15:0] CH0_PCSRSVDOUT; + output [15:0] CH0_PMARSVDOUT; + output CH0_RESETEXCEPTION; + output [2:0] CH0_RXBUFSTATUS; + output [255:0] CH0_RXDATA; + output [3:0] CH0_RXDATAFLAGS; + output CH0_RXDATAISAM; + output CH0_RXDATASTART; + output CH0_RXOUTCLK; + output CH0_RXPMARESETDONE; + output CH0_RXPRBSERR; + output CH0_RXPRBSLOCKED; + output CH0_RXPRGDIVRESETDONE; + output CH0_RXPROGDIVCLK; + output CH0_RXRESETDONE; + output [1:0] CH0_TXBUFSTATUS; + output CH0_TXOUTCLK; + output CH0_TXPMARESETDONE; + output CH0_TXPRGDIVRESETDONE; + output CH0_TXPROGDIVCLK; + output CH0_TXRESETDONE; + output [27:0] CH1_AXISTDATA; + output CH1_AXISTLAST; + output CH1_AXISTVALID; + output [31:0] CH1_DMONITOROUT; + output CH1_DMONITOROUTCLK; + output CH1_GTMTXN; + output CH1_GTMTXP; + output [15:0] CH1_PCSRSVDOUT; + output [15:0] CH1_PMARSVDOUT; + output CH1_RESETEXCEPTION; + output [2:0] CH1_RXBUFSTATUS; + output [255:0] CH1_RXDATA; + output [3:0] CH1_RXDATAFLAGS; + output CH1_RXDATAISAM; + output CH1_RXDATASTART; + output CH1_RXOUTCLK; + output CH1_RXPMARESETDONE; + output CH1_RXPRBSERR; + output CH1_RXPRBSLOCKED; + output CH1_RXPRGDIVRESETDONE; + output CH1_RXPROGDIVCLK; + output CH1_RXRESETDONE; + output [1:0] CH1_TXBUFSTATUS; + output CH1_TXOUTCLK; + output CH1_TXPMARESETDONE; + output CH1_TXPRGDIVRESETDONE; + output CH1_TXPROGDIVCLK; + output CH1_TXRESETDONE; + output CLKTESTSIG2PAD; + output DMONITOROUTPLLCLK; + output [15:0] DRPDO; + output DRPRDY; + output FECRX0ALIGNED; + output FECRX0CORRCWINC; + output FECRX0CWINC; + output FECRX0UNCORRCWINC; + output FECRX1ALIGNED; + output FECRX1CORRCWINC; + output FECRX1CWINC; + output FECRX1UNCORRCWINC; + output [7:0] FECRXLN0BITERR0TO1INC; + output [7:0] FECRXLN0BITERR1TO0INC; + output [14:0] FECRXLN0DLY; + output [3:0] FECRXLN0ERRCNTINC; + output [1:0] FECRXLN0MAPPING; + output [7:0] FECRXLN1BITERR0TO1INC; + output [7:0] FECRXLN1BITERR1TO0INC; + output [14:0] FECRXLN1DLY; + output [3:0] FECRXLN1ERRCNTINC; + output [1:0] FECRXLN1MAPPING; + output [7:0] FECRXLN2BITERR0TO1INC; + output [7:0] FECRXLN2BITERR1TO0INC; + output [14:0] FECRXLN2DLY; + output [3:0] FECRXLN2ERRCNTINC; + output [1:0] FECRXLN2MAPPING; + output [7:0] FECRXLN3BITERR0TO1INC; + output [7:0] FECRXLN3BITERR1TO0INC; + output [14:0] FECRXLN3DLY; + output [3:0] FECRXLN3ERRCNTINC; + output [1:0] FECRXLN3MAPPING; + output FECTRXLN0LOCK; + output FECTRXLN1LOCK; + output FECTRXLN2LOCK; + output FECTRXLN3LOCK; + output GTPOWERGOOD; + output PLLFBCLKLOST; + output PLLLOCK; + output PLLREFCLKLOST; + output PLLREFCLKMONITOR; + output PLLRESETDONE; + output [15:0] PLLRSVDOUT; + output RCALCMP; + output [4:0] RCALOUT; + output RXRECCLK0; + output RXRECCLK1; + input BGBYPASSB; + input BGMONITORENB; + input BGPDB; + input [4:0] BGRCALOVRD; + input BGRCALOVRDENB; + input CH0_AXISEN; + input CH0_AXISRST; + input CH0_AXISTRDY; + input CH0_CFGRESET; + input CH0_DMONFIFORESET; + input CH0_DMONITORCLK; + input CH0_GTMRXN; + input CH0_GTMRXP; + input CH0_GTRXRESET; + input CH0_GTTXRESET; + input [2:0] CH0_LOOPBACK; + input [15:0] CH0_PCSRSVDIN; + input [15:0] CH0_PMARSVDIN; + input CH0_RESETOVRD; + input CH0_RXADAPTRESET; + input CH0_RXADCCALRESET; + input CH0_RXADCCLKGENRESET; + input CH0_RXBUFRESET; + input CH0_RXCDRFREQOS; + input CH0_RXCDRFRRESET; + input CH0_RXCDRHOLD; + input CH0_RXCDRINCPCTRL; + input CH0_RXCDROVRDEN; + input CH0_RXCDRPHRESET; + input CH0_RXDFERESET; + input CH0_RXDSPRESET; + input CH0_RXEQTRAINING; + input CH0_RXEYESCANRESET; + input CH0_RXFECRESET; + input [2:0] CH0_RXOUTCLKSEL; + input CH0_RXPCSRESET; + input [3:0] CH0_RXPCSRESETMASK; + input CH0_RXPMARESET; + input [7:0] CH0_RXPMARESETMASK; + input CH0_RXPOLARITY; + input CH0_RXPRBSCNTSTOP; + input CH0_RXPRBSCSCNTRST; + input [3:0] CH0_RXPRBSPTN; + input CH0_RXPROGDIVRESET; + input CH0_RXQPRBSEN; + input [1:0] CH0_RXRESETMODE; + input CH0_RXSPCSEQADV; + input CH0_RXUSRCLK; + input CH0_RXUSRCLK2; + input CH0_RXUSRRDY; + input CH0_RXUSRSTART; + input CH0_RXUSRSTOP; + input CH0_TXCKALRESET; + input [5:0] CH0_TXCTLFIRDAT; + input [255:0] CH0_TXDATA; + input CH0_TXDATASTART; + input [4:0] CH0_TXDRVAMP; + input [5:0] CH0_TXEMPMAIN; + input [4:0] CH0_TXEMPPOST; + input [4:0] CH0_TXEMPPRE; + input [3:0] CH0_TXEMPPRE2; + input CH0_TXFECRESET; + input CH0_TXINHIBIT; + input CH0_TXMUXDCDEXHOLD; + input CH0_TXMUXDCDORWREN; + input [2:0] CH0_TXOUTCLKSEL; + input CH0_TXPCSRESET; + input [1:0] CH0_TXPCSRESETMASK; + input CH0_TXPMARESET; + input [1:0] CH0_TXPMARESETMASK; + input CH0_TXPOLARITY; + input CH0_TXPRBSINERR; + input [3:0] CH0_TXPRBSPTN; + input CH0_TXPROGDIVRESET; + input CH0_TXQPRBSEN; + input [1:0] CH0_TXRESETMODE; + input CH0_TXSPCSEQADV; + input CH0_TXUSRCLK; + input CH0_TXUSRCLK2; + input CH0_TXUSRRDY; + input CH1_AXISEN; + input CH1_AXISRST; + input CH1_AXISTRDY; + input CH1_CFGRESET; + input CH1_DMONFIFORESET; + input CH1_DMONITORCLK; + input CH1_GTMRXN; + input CH1_GTMRXP; + input CH1_GTRXRESET; + input CH1_GTTXRESET; + input [2:0] CH1_LOOPBACK; + input [15:0] CH1_PCSRSVDIN; + input [15:0] CH1_PMARSVDIN; + input CH1_RESETOVRD; + input CH1_RXADAPTRESET; + input CH1_RXADCCALRESET; + input CH1_RXADCCLKGENRESET; + input CH1_RXBUFRESET; + input CH1_RXCDRFREQOS; + input CH1_RXCDRFRRESET; + input CH1_RXCDRHOLD; + input CH1_RXCDRINCPCTRL; + input CH1_RXCDROVRDEN; + input CH1_RXCDRPHRESET; + input CH1_RXDFERESET; + input CH1_RXDSPRESET; + input CH1_RXEQTRAINING; + input CH1_RXEYESCANRESET; + input CH1_RXFECRESET; + input [2:0] CH1_RXOUTCLKSEL; + input CH1_RXPCSRESET; + input [3:0] CH1_RXPCSRESETMASK; + input CH1_RXPMARESET; + input [7:0] CH1_RXPMARESETMASK; + input CH1_RXPOLARITY; + input CH1_RXPRBSCNTSTOP; + input CH1_RXPRBSCSCNTRST; + input [3:0] CH1_RXPRBSPTN; + input CH1_RXPROGDIVRESET; + input CH1_RXQPRBSEN; + input [1:0] CH1_RXRESETMODE; + input CH1_RXSPCSEQADV; + input CH1_RXUSRCLK; + input CH1_RXUSRCLK2; + input CH1_RXUSRRDY; + input CH1_RXUSRSTART; + input CH1_RXUSRSTOP; + input CH1_TXCKALRESET; + input [5:0] CH1_TXCTLFIRDAT; + input [255:0] CH1_TXDATA; + input CH1_TXDATASTART; + input [4:0] CH1_TXDRVAMP; + input [5:0] CH1_TXEMPMAIN; + input [4:0] CH1_TXEMPPOST; + input [4:0] CH1_TXEMPPRE; + input [3:0] CH1_TXEMPPRE2; + input CH1_TXFECRESET; + input CH1_TXINHIBIT; + input CH1_TXMUXDCDEXHOLD; + input CH1_TXMUXDCDORWREN; + input [2:0] CH1_TXOUTCLKSEL; + input CH1_TXPCSRESET; + input [1:0] CH1_TXPCSRESETMASK; + input CH1_TXPMARESET; + input [1:0] CH1_TXPMARESETMASK; + input CH1_TXPOLARITY; + input CH1_TXPRBSINERR; + input [3:0] CH1_TXPRBSPTN; + input CH1_TXPROGDIVRESET; + input CH1_TXQPRBSEN; + input [1:0] CH1_TXRESETMODE; + input CH1_TXSPCSEQADV; + input CH1_TXUSRCLK; + input CH1_TXUSRCLK2; + input CH1_TXUSRRDY; + input [10:0] DRPADDR; + input DRPCLK; + input [15:0] DRPDI; + input DRPEN; + input DRPRST; + input DRPWE; + input FECCTRLRX0BITSLIPFS; + input FECCTRLRX1BITSLIPFS; + input GTGREFCLK2PLL; + input GTNORTHREFCLK; + input GTREFCLK; + input GTSOUTHREFCLK; + input [7:0] PLLFBDIV; + input PLLMONCLK; + input PLLPD; + input [2:0] PLLREFCLKSEL; + input PLLRESET; + input PLLRESETBYPASSMODE; + input [1:0] PLLRESETMASK; + input [15:0] PLLRSVDIN; + input RCALENB; + input [25:0] SDMDATA; + input SDMTOGGLE; +endmodule + +module IBUFDS_GTM (...); parameter [0:0] REFCLK_EN_TX_PATH = 1'b0; - parameter [4:0] REFCLK_ICNTL_TX = 5'b00000; + parameter integer REFCLK_HROW_CK_SEL = 0; + parameter integer REFCLK_ICNTL_RX = 0; + output O; + output ODIV2; + input CEB; + (* iopad_external_pin *) + input I; + (* iopad_external_pin *) + input IB; +endmodule + +module OBUFDS_GTM (...); + parameter [0:0] REFCLK_EN_TX_PATH = 1'b0; + parameter integer REFCLK_ICNTL_TX = 0; (* iopad_external_pin *) output O; (* iopad_external_pin *) @@ -18180,16 +18921,259 @@ module OBUFDS_GTE4 (...); input I; endmodule -module OBUFDS_GTE4_ADV (...); +module OBUFDS_GTM_ADV (...); parameter [0:0] REFCLK_EN_TX_PATH = 1'b0; - parameter [4:0] REFCLK_ICNTL_TX = 5'b00000; + parameter integer REFCLK_ICNTL_TX = 0; + parameter [1:0] RXRECCLK_SEL = 2'b00; (* iopad_external_pin *) output O; (* iopad_external_pin *) output OB; input CEB; input [3:0] I; - input [1:0] RXRECCLK_SEL; +endmodule + +module HSDAC (...); + parameter SIM_DEVICE = "ULTRASCALE_PLUS"; + parameter integer XPA_CFG0 = 0; + parameter integer XPA_CFG1 = 0; + parameter integer XPA_NUM_DACS = 0; + parameter integer XPA_NUM_DUCS = 0; + parameter XPA_PLL_USED = "No"; + parameter integer XPA_SAMPLE_RATE_MSPS = 0; + output CLK_DAC; + output [15:0] DOUT; + output DRDY; + output PLL_DMON_OUT; + output PLL_REFCLK_OUT; + output [15:0] STATUS_COMMON; + output [15:0] STATUS_DAC0; + output [15:0] STATUS_DAC1; + output [15:0] STATUS_DAC2; + output [15:0] STATUS_DAC3; + output SYSREF_OUT_NORTH; + output SYSREF_OUT_SOUTH; + output VOUT0_N; + output VOUT0_P; + output VOUT1_N; + output VOUT1_P; + output VOUT2_N; + output VOUT2_P; + output VOUT3_N; + output VOUT3_P; + input CLK_FIFO_LM; + input [15:0] CONTROL_COMMON; + input [15:0] CONTROL_DAC0; + input [15:0] CONTROL_DAC1; + input [15:0] CONTROL_DAC2; + input [15:0] CONTROL_DAC3; + input DAC_CLK_N; + input DAC_CLK_P; + input [11:0] DADDR; + input [255:0] DATA_DAC0; + input [255:0] DATA_DAC1; + input [255:0] DATA_DAC2; + input [255:0] DATA_DAC3; + input DCLK; + input DEN; + input [15:0] DI; + input DWE; + input FABRIC_CLK; + input PLL_MONCLK; + input PLL_REFCLK_IN; + input SYSREF_IN_NORTH; + input SYSREF_IN_SOUTH; + input SYSREF_N; + input SYSREF_P; +endmodule + +module HSADC (...); + parameter SIM_DEVICE = "ULTRASCALE_PLUS"; + parameter integer XPA_CFG0 = 0; + parameter integer XPA_CFG1 = 0; + parameter XPA_NUM_ADCS = "0"; + parameter integer XPA_NUM_DDCS = 0; + parameter XPA_PLL_USED = "No"; + parameter integer XPA_SAMPLE_RATE_MSPS = 0; + output CLK_ADC; + output [127:0] DATA_ADC0; + output [127:0] DATA_ADC1; + output [127:0] DATA_ADC2; + output [127:0] DATA_ADC3; + output [15:0] DOUT; + output DRDY; + output PLL_DMON_OUT; + output PLL_REFCLK_OUT; + output [15:0] STATUS_ADC0; + output [15:0] STATUS_ADC1; + output [15:0] STATUS_ADC2; + output [15:0] STATUS_ADC3; + output [15:0] STATUS_COMMON; + output SYSREF_OUT_NORTH; + output SYSREF_OUT_SOUTH; + input ADC_CLK_N; + input ADC_CLK_P; + input CLK_FIFO_LM; + input [15:0] CONTROL_ADC0; + input [15:0] CONTROL_ADC1; + input [15:0] CONTROL_ADC2; + input [15:0] CONTROL_ADC3; + input [15:0] CONTROL_COMMON; + input [11:0] DADDR; + input DCLK; + input DEN; + input [15:0] DI; + input DWE; + input FABRIC_CLK; + input PLL_MONCLK; + input PLL_REFCLK_IN; + input SYSREF_IN_NORTH; + input SYSREF_IN_SOUTH; + input SYSREF_N; + input SYSREF_P; + input VIN0_N; + input VIN0_P; + input VIN1_N; + input VIN1_P; + input VIN2_N; + input VIN2_P; + input VIN3_N; + input VIN3_P; + input VIN_I01_N; + input VIN_I01_P; + input VIN_I23_N; + input VIN_I23_P; +endmodule + +module RFDAC (...); + parameter integer OPT_CLK_DIST = 0; + parameter SIM_DEVICE = "ULTRASCALE_PLUS"; + parameter integer XPA_ACTIVE_DUTYCYCLE = 100; + parameter integer XPA_CFG0 = 0; + parameter integer XPA_CFG1 = 0; + parameter integer XPA_CFG2 = 0; + parameter integer XPA_NUM_DACS = 0; + parameter integer XPA_NUM_DUCS = 0; + parameter XPA_PLL_USED = "EXTERNAL"; + parameter integer XPA_SAMPLE_RATE_MSPS = 0; + output CLK_DAC; + output CLK_DIST_OUT_NORTH; + output CLK_DIST_OUT_SOUTH; + output [15:0] DOUT; + output DRDY; + output PLL_DMON_OUT; + output PLL_REFCLK_OUT; + output [23:0] STATUS_COMMON; + output [23:0] STATUS_DAC0; + output [23:0] STATUS_DAC1; + output [23:0] STATUS_DAC2; + output [23:0] STATUS_DAC3; + output SYSREF_OUT_NORTH; + output SYSREF_OUT_SOUTH; + output T1_ALLOWED_SOUTH; + output VOUT0_N; + output VOUT0_P; + output VOUT1_N; + output VOUT1_P; + output VOUT2_N; + output VOUT2_P; + output VOUT3_N; + output VOUT3_P; + input CLK_DIST_IN_NORTH; + input CLK_DIST_IN_SOUTH; + input CLK_FIFO_LM; + input [15:0] CONTROL_COMMON; + input [15:0] CONTROL_DAC0; + input [15:0] CONTROL_DAC1; + input [15:0] CONTROL_DAC2; + input [15:0] CONTROL_DAC3; + input DAC_CLK_N; + input DAC_CLK_P; + input [11:0] DADDR; + input [255:0] DATA_DAC0; + input [255:0] DATA_DAC1; + input [255:0] DATA_DAC2; + input [255:0] DATA_DAC3; + input DCLK; + input DEN; + input [15:0] DI; + input DWE; + input FABRIC_CLK; + input PLL_MONCLK; + input PLL_REFCLK_IN; + input SYSREF_IN_NORTH; + input SYSREF_IN_SOUTH; + input SYSREF_N; + input SYSREF_P; + input T1_ALLOWED_NORTH; +endmodule + +module RFADC (...); + parameter integer OPT_ANALOG = 0; + parameter integer OPT_CLK_DIST = 0; + parameter SIM_DEVICE = "ULTRASCALE_PLUS"; + parameter integer XPA_ACTIVE_DUTYCYCLE = 100; + parameter integer XPA_CFG0 = 0; + parameter integer XPA_CFG1 = 0; + parameter integer XPA_CFG2 = 0; + parameter XPA_NUM_ADCS = "0"; + parameter integer XPA_NUM_DDCS = 0; + parameter XPA_PLL_USED = "EXTERNAL"; + parameter integer XPA_SAMPLE_RATE_MSPS = 0; + output CLK_ADC; + output CLK_DIST_OUT_NORTH; + output CLK_DIST_OUT_SOUTH; + output [191:0] DATA_ADC0; + output [191:0] DATA_ADC1; + output [191:0] DATA_ADC2; + output [191:0] DATA_ADC3; + output [15:0] DOUT; + output DRDY; + output PLL_DMON_OUT; + output PLL_REFCLK_OUT; + output [23:0] STATUS_ADC0; + output [23:0] STATUS_ADC1; + output [23:0] STATUS_ADC2; + output [23:0] STATUS_ADC3; + output [23:0] STATUS_COMMON; + output SYSREF_OUT_NORTH; + output SYSREF_OUT_SOUTH; + output T1_ALLOWED_SOUTH; + input ADC_CLK_N; + input ADC_CLK_P; + input CLK_DIST_IN_NORTH; + input CLK_DIST_IN_SOUTH; + input CLK_FIFO_LM; + input [15:0] CONTROL_ADC0; + input [15:0] CONTROL_ADC1; + input [15:0] CONTROL_ADC2; + input [15:0] CONTROL_ADC3; + input [15:0] CONTROL_COMMON; + input [11:0] DADDR; + input DCLK; + input DEN; + input [15:0] DI; + input DWE; + input FABRIC_CLK; + input PLL_MONCLK; + input PLL_REFCLK_IN; + input SYSREF_IN_NORTH; + input SYSREF_IN_SOUTH; + input SYSREF_N; + input SYSREF_P; + input T1_ALLOWED_NORTH; + input VIN0_N; + input VIN0_P; + input VIN1_N; + input VIN1_P; + input VIN2_N; + input VIN2_P; + input VIN3_N; + input VIN3_P; + input VIN_I01_N; + input VIN_I01_P; + input VIN_I23_N; + input VIN_I23_P; endmodule module PCIE_A1 (...); @@ -23569,6 +24553,1312 @@ module PCIE40E4 (...); input [31:0] USERSPAREIN; endmodule +module PCIE4CE4 (...); + parameter ARI_CAP_ENABLE = "FALSE"; + parameter AUTO_FLR_RESPONSE = "FALSE"; + parameter [7:0] AXISTEN_IF_CCIX_RX_CREDIT_LIMIT = 8'h08; + parameter [7:0] AXISTEN_IF_CCIX_TX_CREDIT_LIMIT = 8'h08; + parameter AXISTEN_IF_CCIX_TX_REGISTERED_TREADY = "FALSE"; + parameter [1:0] AXISTEN_IF_CC_ALIGNMENT_MODE = 2'h0; + parameter [23:0] AXISTEN_IF_COMPL_TIMEOUT_REG0 = 24'hBEBC20; + parameter [27:0] AXISTEN_IF_COMPL_TIMEOUT_REG1 = 28'h2FAF080; + parameter [1:0] AXISTEN_IF_CQ_ALIGNMENT_MODE = 2'h0; + parameter AXISTEN_IF_CQ_EN_POISONED_MEM_WR = "FALSE"; + parameter AXISTEN_IF_ENABLE_256_TAGS = "FALSE"; + parameter AXISTEN_IF_ENABLE_CLIENT_TAG = "FALSE"; + parameter AXISTEN_IF_ENABLE_INTERNAL_MSIX_TABLE = "FALSE"; + parameter AXISTEN_IF_ENABLE_MESSAGE_RID_CHECK = "TRUE"; + parameter [17:0] AXISTEN_IF_ENABLE_MSG_ROUTE = 18'h00000; + parameter AXISTEN_IF_ENABLE_RX_MSG_INTFC = "FALSE"; + parameter AXISTEN_IF_EXT_512 = "FALSE"; + parameter AXISTEN_IF_EXT_512_CC_STRADDLE = "FALSE"; + parameter AXISTEN_IF_EXT_512_CQ_STRADDLE = "FALSE"; + parameter AXISTEN_IF_EXT_512_RC_STRADDLE = "FALSE"; + parameter AXISTEN_IF_EXT_512_RQ_STRADDLE = "FALSE"; + parameter AXISTEN_IF_LEGACY_MODE_ENABLE = "FALSE"; + parameter AXISTEN_IF_MSIX_FROM_RAM_PIPELINE = "FALSE"; + parameter AXISTEN_IF_MSIX_RX_PARITY_EN = "TRUE"; + parameter AXISTEN_IF_MSIX_TO_RAM_PIPELINE = "FALSE"; + parameter [1:0] AXISTEN_IF_RC_ALIGNMENT_MODE = 2'h0; + parameter AXISTEN_IF_RC_STRADDLE = "FALSE"; + parameter [1:0] AXISTEN_IF_RQ_ALIGNMENT_MODE = 2'h0; + parameter AXISTEN_IF_RX_PARITY_EN = "TRUE"; + parameter AXISTEN_IF_SIM_SHORT_CPL_TIMEOUT = "FALSE"; + parameter AXISTEN_IF_TX_PARITY_EN = "TRUE"; + parameter [1:0] AXISTEN_IF_WIDTH = 2'h2; + parameter CCIX_DIRECT_ATTACH_MODE = "FALSE"; + parameter CCIX_ENABLE = "FALSE"; + parameter [15:0] CCIX_VENDOR_ID = 16'h0000; + parameter CFG_BYPASS_MODE_ENABLE = "FALSE"; + parameter CRM_CORE_CLK_FREQ_500 = "TRUE"; + parameter [1:0] CRM_USER_CLK_FREQ = 2'h2; + parameter [15:0] DEBUG_AXI4ST_SPARE = 16'h0000; + parameter [7:0] DEBUG_AXIST_DISABLE_FEATURE_BIT = 8'h00; + parameter [3:0] DEBUG_CAR_SPARE = 4'h0; + parameter [15:0] DEBUG_CFG_SPARE = 16'h0000; + parameter [15:0] DEBUG_LL_SPARE = 16'h0000; + parameter DEBUG_PL_DISABLE_LES_UPDATE_ON_DEFRAMER_ERROR = "FALSE"; + parameter DEBUG_PL_DISABLE_LES_UPDATE_ON_SKP_ERROR = "FALSE"; + parameter DEBUG_PL_DISABLE_LES_UPDATE_ON_SKP_PARITY_ERROR = "FALSE"; + parameter DEBUG_PL_DISABLE_REC_ENTRY_ON_DYNAMIC_DSKEW_FAIL = "FALSE"; + parameter DEBUG_PL_DISABLE_REC_ENTRY_ON_RX_BUFFER_UNDER_OVER_FLOW = "FALSE"; + parameter DEBUG_PL_DISABLE_SCRAMBLING = "FALSE"; + parameter DEBUG_PL_SIM_RESET_LFSR = "FALSE"; + parameter [15:0] DEBUG_PL_SPARE = 16'h0000; + parameter DEBUG_TL_DISABLE_FC_TIMEOUT = "FALSE"; + parameter DEBUG_TL_DISABLE_RX_TLP_ORDER_CHECKS = "FALSE"; + parameter [15:0] DEBUG_TL_SPARE = 16'h0000; + parameter [7:0] DNSTREAM_LINK_NUM = 8'h00; + parameter DSN_CAP_ENABLE = "FALSE"; + parameter EXTENDED_CFG_EXTEND_INTERFACE_ENABLE = "FALSE"; + parameter HEADER_TYPE_OVERRIDE = "FALSE"; + parameter IS_SWITCH_PORT = "FALSE"; + parameter LEGACY_CFG_EXTEND_INTERFACE_ENABLE = "FALSE"; + parameter [8:0] LL_ACK_TIMEOUT = 9'h000; + parameter LL_ACK_TIMEOUT_EN = "FALSE"; + parameter integer LL_ACK_TIMEOUT_FUNC = 0; + parameter LL_DISABLE_SCHED_TX_NAK = "FALSE"; + parameter LL_REPLAY_FROM_RAM_PIPELINE = "FALSE"; + parameter [8:0] LL_REPLAY_TIMEOUT = 9'h000; + parameter LL_REPLAY_TIMEOUT_EN = "FALSE"; + parameter integer LL_REPLAY_TIMEOUT_FUNC = 0; + parameter LL_REPLAY_TO_RAM_PIPELINE = "FALSE"; + parameter LL_RX_TLP_PARITY_GEN = "TRUE"; + parameter LL_TX_TLP_PARITY_CHK = "TRUE"; + parameter [15:0] LL_USER_SPARE = 16'h0000; + parameter [9:0] LTR_TX_MESSAGE_MINIMUM_INTERVAL = 10'h250; + parameter LTR_TX_MESSAGE_ON_FUNC_POWER_STATE_CHANGE = "FALSE"; + parameter LTR_TX_MESSAGE_ON_LTR_ENABLE = "FALSE"; + parameter [11:0] MCAP_CAP_NEXTPTR = 12'h000; + parameter MCAP_CONFIGURE_OVERRIDE = "FALSE"; + parameter MCAP_ENABLE = "FALSE"; + parameter MCAP_EOS_DESIGN_SWITCH = "FALSE"; + parameter [31:0] MCAP_FPGA_BITSTREAM_VERSION = 32'h00000000; + parameter MCAP_GATE_IO_ENABLE_DESIGN_SWITCH = "FALSE"; + parameter MCAP_GATE_MEM_ENABLE_DESIGN_SWITCH = "FALSE"; + parameter MCAP_INPUT_GATE_DESIGN_SWITCH = "FALSE"; + parameter MCAP_INTERRUPT_ON_MCAP_EOS = "FALSE"; + parameter MCAP_INTERRUPT_ON_MCAP_ERROR = "FALSE"; + parameter [15:0] MCAP_VSEC_ID = 16'h0000; + parameter [11:0] MCAP_VSEC_LEN = 12'h02C; + parameter [3:0] MCAP_VSEC_REV = 4'h0; + parameter PF0_AER_CAP_ECRC_GEN_AND_CHECK_CAPABLE = "FALSE"; + parameter [11:0] PF0_AER_CAP_NEXTPTR = 12'h000; + parameter [11:0] PF0_ARI_CAP_NEXTPTR = 12'h000; + parameter [7:0] PF0_ARI_CAP_NEXT_FUNC = 8'h00; + parameter [3:0] PF0_ARI_CAP_VER = 4'h1; + parameter [4:0] PF0_ATS_CAP_INV_QUEUE_DEPTH = 5'h00; + parameter [11:0] PF0_ATS_CAP_NEXTPTR = 12'h000; + parameter PF0_ATS_CAP_ON = "FALSE"; + parameter [5:0] PF0_BAR0_APERTURE_SIZE = 6'h03; + parameter [2:0] PF0_BAR0_CONTROL = 3'h4; + parameter [4:0] PF0_BAR1_APERTURE_SIZE = 5'h00; + parameter [2:0] PF0_BAR1_CONTROL = 3'h0; + parameter [5:0] PF0_BAR2_APERTURE_SIZE = 6'h03; + parameter [2:0] PF0_BAR2_CONTROL = 3'h4; + parameter [4:0] PF0_BAR3_APERTURE_SIZE = 5'h03; + parameter [2:0] PF0_BAR3_CONTROL = 3'h0; + parameter [5:0] PF0_BAR4_APERTURE_SIZE = 6'h03; + parameter [2:0] PF0_BAR4_CONTROL = 3'h4; + parameter [4:0] PF0_BAR5_APERTURE_SIZE = 5'h03; + parameter [2:0] PF0_BAR5_CONTROL = 3'h0; + parameter [7:0] PF0_CAPABILITY_POINTER = 8'h80; + parameter [23:0] PF0_CLASS_CODE = 24'h000000; + parameter PF0_DEV_CAP2_128B_CAS_ATOMIC_COMPLETER_SUPPORT = "TRUE"; + parameter PF0_DEV_CAP2_32B_ATOMIC_COMPLETER_SUPPORT = "TRUE"; + parameter PF0_DEV_CAP2_64B_ATOMIC_COMPLETER_SUPPORT = "TRUE"; + parameter PF0_DEV_CAP2_ARI_FORWARD_ENABLE = "FALSE"; + parameter PF0_DEV_CAP2_CPL_TIMEOUT_DISABLE = "TRUE"; + parameter PF0_DEV_CAP2_LTR_SUPPORT = "TRUE"; + parameter [1:0] PF0_DEV_CAP2_OBFF_SUPPORT = 2'h0; + parameter PF0_DEV_CAP2_TPH_COMPLETER_SUPPORT = "FALSE"; + parameter integer PF0_DEV_CAP_ENDPOINT_L0S_LATENCY = 0; + parameter integer PF0_DEV_CAP_ENDPOINT_L1_LATENCY = 0; + parameter PF0_DEV_CAP_EXT_TAG_SUPPORTED = "TRUE"; + parameter PF0_DEV_CAP_FUNCTION_LEVEL_RESET_CAPABLE = "TRUE"; + parameter [2:0] PF0_DEV_CAP_MAX_PAYLOAD_SIZE = 3'h3; + parameter [11:0] PF0_DSN_CAP_NEXTPTR = 12'h10C; + parameter [4:0] PF0_EXPANSION_ROM_APERTURE_SIZE = 5'h03; + parameter PF0_EXPANSION_ROM_ENABLE = "FALSE"; + parameter [2:0] PF0_INTERRUPT_PIN = 3'h1; + parameter integer PF0_LINK_CAP_ASPM_SUPPORT = 0; + parameter integer PF0_LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN1 = 7; + parameter integer PF0_LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN2 = 7; + parameter integer PF0_LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN3 = 7; + parameter integer PF0_LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN4 = 7; + parameter integer PF0_LINK_CAP_L0S_EXIT_LATENCY_GEN1 = 7; + parameter integer PF0_LINK_CAP_L0S_EXIT_LATENCY_GEN2 = 7; + parameter integer PF0_LINK_CAP_L0S_EXIT_LATENCY_GEN3 = 7; + parameter integer PF0_LINK_CAP_L0S_EXIT_LATENCY_GEN4 = 7; + parameter integer PF0_LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN1 = 7; + parameter integer PF0_LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN2 = 7; + parameter integer PF0_LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN3 = 7; + parameter integer PF0_LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN4 = 7; + parameter integer PF0_LINK_CAP_L1_EXIT_LATENCY_GEN1 = 7; + parameter integer PF0_LINK_CAP_L1_EXIT_LATENCY_GEN2 = 7; + parameter integer PF0_LINK_CAP_L1_EXIT_LATENCY_GEN3 = 7; + parameter integer PF0_LINK_CAP_L1_EXIT_LATENCY_GEN4 = 7; + parameter [0:0] PF0_LINK_CONTROL_RCB = 1'h0; + parameter PF0_LINK_STATUS_SLOT_CLOCK_CONFIG = "TRUE"; + parameter [9:0] PF0_LTR_CAP_MAX_NOSNOOP_LAT = 10'h000; + parameter [9:0] PF0_LTR_CAP_MAX_SNOOP_LAT = 10'h000; + parameter [11:0] PF0_LTR_CAP_NEXTPTR = 12'h000; + parameter [3:0] PF0_LTR_CAP_VER = 4'h1; + parameter [7:0] PF0_MSIX_CAP_NEXTPTR = 8'h00; + parameter integer PF0_MSIX_CAP_PBA_BIR = 0; + parameter [28:0] PF0_MSIX_CAP_PBA_OFFSET = 29'h00000050; + parameter integer PF0_MSIX_CAP_TABLE_BIR = 0; + parameter [28:0] PF0_MSIX_CAP_TABLE_OFFSET = 29'h00000040; + parameter [10:0] PF0_MSIX_CAP_TABLE_SIZE = 11'h000; + parameter [5:0] PF0_MSIX_VECTOR_COUNT = 6'h04; + parameter integer PF0_MSI_CAP_MULTIMSGCAP = 0; + parameter [7:0] PF0_MSI_CAP_NEXTPTR = 8'h00; + parameter PF0_MSI_CAP_PERVECMASKCAP = "FALSE"; + parameter [7:0] PF0_PCIE_CAP_NEXTPTR = 8'h00; + parameter [7:0] PF0_PM_CAP_ID = 8'h01; + parameter [7:0] PF0_PM_CAP_NEXTPTR = 8'h00; + parameter PF0_PM_CAP_PMESUPPORT_D0 = "TRUE"; + parameter PF0_PM_CAP_PMESUPPORT_D1 = "TRUE"; + parameter PF0_PM_CAP_PMESUPPORT_D3HOT = "TRUE"; + parameter PF0_PM_CAP_SUPP_D1_STATE = "TRUE"; + parameter [2:0] PF0_PM_CAP_VER_ID = 3'h3; + parameter PF0_PM_CSR_NOSOFTRESET = "TRUE"; + parameter [11:0] PF0_PRI_CAP_NEXTPTR = 12'h000; + parameter PF0_PRI_CAP_ON = "FALSE"; + parameter [31:0] PF0_PRI_OST_PR_CAPACITY = 32'h00000000; + parameter [11:0] PF0_SECONDARY_PCIE_CAP_NEXTPTR = 12'h000; + parameter PF0_SRIOV_ARI_CAPBL_HIER_PRESERVED = "FALSE"; + parameter [5:0] PF0_SRIOV_BAR0_APERTURE_SIZE = 6'h03; + parameter [2:0] PF0_SRIOV_BAR0_CONTROL = 3'h4; + parameter [4:0] PF0_SRIOV_BAR1_APERTURE_SIZE = 5'h00; + parameter [2:0] PF0_SRIOV_BAR1_CONTROL = 3'h0; + parameter [5:0] PF0_SRIOV_BAR2_APERTURE_SIZE = 6'h03; + parameter [2:0] PF0_SRIOV_BAR2_CONTROL = 3'h4; + parameter [4:0] PF0_SRIOV_BAR3_APERTURE_SIZE = 5'h03; + parameter [2:0] PF0_SRIOV_BAR3_CONTROL = 3'h0; + parameter [5:0] PF0_SRIOV_BAR4_APERTURE_SIZE = 6'h03; + parameter [2:0] PF0_SRIOV_BAR4_CONTROL = 3'h4; + parameter [4:0] PF0_SRIOV_BAR5_APERTURE_SIZE = 5'h03; + parameter [2:0] PF0_SRIOV_BAR5_CONTROL = 3'h0; + parameter [15:0] PF0_SRIOV_CAP_INITIAL_VF = 16'h0000; + parameter [11:0] PF0_SRIOV_CAP_NEXTPTR = 12'h000; + parameter [15:0] PF0_SRIOV_CAP_TOTAL_VF = 16'h0000; + parameter [3:0] PF0_SRIOV_CAP_VER = 4'h1; + parameter [15:0] PF0_SRIOV_FIRST_VF_OFFSET = 16'h0000; + parameter [15:0] PF0_SRIOV_FUNC_DEP_LINK = 16'h0000; + parameter [31:0] PF0_SRIOV_SUPPORTED_PAGE_SIZE = 32'h00000000; + parameter [15:0] PF0_SRIOV_VF_DEVICE_ID = 16'h0000; + parameter PF0_TPHR_CAP_DEV_SPECIFIC_MODE = "TRUE"; + parameter PF0_TPHR_CAP_ENABLE = "FALSE"; + parameter PF0_TPHR_CAP_INT_VEC_MODE = "TRUE"; + parameter [11:0] PF0_TPHR_CAP_NEXTPTR = 12'h000; + parameter [2:0] PF0_TPHR_CAP_ST_MODE_SEL = 3'h0; + parameter [1:0] PF0_TPHR_CAP_ST_TABLE_LOC = 2'h0; + parameter [10:0] PF0_TPHR_CAP_ST_TABLE_SIZE = 11'h000; + parameter [3:0] PF0_TPHR_CAP_VER = 4'h1; + parameter [3:0] PF0_VC_ARB_CAPABILITY = 4'h0; + parameter [7:0] PF0_VC_ARB_TBL_OFFSET = 8'h00; + parameter PF0_VC_CAP_ENABLE = "FALSE"; + parameter [11:0] PF0_VC_CAP_NEXTPTR = 12'h000; + parameter [3:0] PF0_VC_CAP_VER = 4'h1; + parameter PF0_VC_EXTENDED_COUNT = "FALSE"; + parameter PF0_VC_LOW_PRIORITY_EXTENDED_COUNT = "FALSE"; + parameter [11:0] PF1_AER_CAP_NEXTPTR = 12'h000; + parameter [11:0] PF1_ARI_CAP_NEXTPTR = 12'h000; + parameter [7:0] PF1_ARI_CAP_NEXT_FUNC = 8'h00; + parameter [4:0] PF1_ATS_CAP_INV_QUEUE_DEPTH = 5'h00; + parameter [11:0] PF1_ATS_CAP_NEXTPTR = 12'h000; + parameter PF1_ATS_CAP_ON = "FALSE"; + parameter [5:0] PF1_BAR0_APERTURE_SIZE = 6'h03; + parameter [2:0] PF1_BAR0_CONTROL = 3'h4; + parameter [4:0] PF1_BAR1_APERTURE_SIZE = 5'h00; + parameter [2:0] PF1_BAR1_CONTROL = 3'h0; + parameter [5:0] PF1_BAR2_APERTURE_SIZE = 6'h03; + parameter [2:0] PF1_BAR2_CONTROL = 3'h4; + parameter [4:0] PF1_BAR3_APERTURE_SIZE = 5'h03; + parameter [2:0] PF1_BAR3_CONTROL = 3'h0; + parameter [5:0] PF1_BAR4_APERTURE_SIZE = 6'h03; + parameter [2:0] PF1_BAR4_CONTROL = 3'h4; + parameter [4:0] PF1_BAR5_APERTURE_SIZE = 5'h03; + parameter [2:0] PF1_BAR5_CONTROL = 3'h0; + parameter [7:0] PF1_CAPABILITY_POINTER = 8'h80; + parameter [23:0] PF1_CLASS_CODE = 24'h000000; + parameter [2:0] PF1_DEV_CAP_MAX_PAYLOAD_SIZE = 3'h3; + parameter [11:0] PF1_DSN_CAP_NEXTPTR = 12'h10C; + parameter [4:0] PF1_EXPANSION_ROM_APERTURE_SIZE = 5'h03; + parameter PF1_EXPANSION_ROM_ENABLE = "FALSE"; + parameter [2:0] PF1_INTERRUPT_PIN = 3'h1; + parameter [7:0] PF1_MSIX_CAP_NEXTPTR = 8'h00; + parameter integer PF1_MSIX_CAP_PBA_BIR = 0; + parameter [28:0] PF1_MSIX_CAP_PBA_OFFSET = 29'h00000050; + parameter integer PF1_MSIX_CAP_TABLE_BIR = 0; + parameter [28:0] PF1_MSIX_CAP_TABLE_OFFSET = 29'h00000040; + parameter [10:0] PF1_MSIX_CAP_TABLE_SIZE = 11'h000; + parameter integer PF1_MSI_CAP_MULTIMSGCAP = 0; + parameter [7:0] PF1_MSI_CAP_NEXTPTR = 8'h00; + parameter PF1_MSI_CAP_PERVECMASKCAP = "FALSE"; + parameter [7:0] PF1_PCIE_CAP_NEXTPTR = 8'h00; + parameter [7:0] PF1_PM_CAP_NEXTPTR = 8'h00; + parameter [11:0] PF1_PRI_CAP_NEXTPTR = 12'h000; + parameter PF1_PRI_CAP_ON = "FALSE"; + parameter [31:0] PF1_PRI_OST_PR_CAPACITY = 32'h00000000; + parameter PF1_SRIOV_ARI_CAPBL_HIER_PRESERVED = "FALSE"; + parameter [5:0] PF1_SRIOV_BAR0_APERTURE_SIZE = 6'h03; + parameter [2:0] PF1_SRIOV_BAR0_CONTROL = 3'h4; + parameter [4:0] PF1_SRIOV_BAR1_APERTURE_SIZE = 5'h00; + parameter [2:0] PF1_SRIOV_BAR1_CONTROL = 3'h0; + parameter [5:0] PF1_SRIOV_BAR2_APERTURE_SIZE = 6'h03; + parameter [2:0] PF1_SRIOV_BAR2_CONTROL = 3'h4; + parameter [4:0] PF1_SRIOV_BAR3_APERTURE_SIZE = 5'h03; + parameter [2:0] PF1_SRIOV_BAR3_CONTROL = 3'h0; + parameter [5:0] PF1_SRIOV_BAR4_APERTURE_SIZE = 6'h03; + parameter [2:0] PF1_SRIOV_BAR4_CONTROL = 3'h4; + parameter [4:0] PF1_SRIOV_BAR5_APERTURE_SIZE = 5'h03; + parameter [2:0] PF1_SRIOV_BAR5_CONTROL = 3'h0; + parameter [15:0] PF1_SRIOV_CAP_INITIAL_VF = 16'h0000; + parameter [11:0] PF1_SRIOV_CAP_NEXTPTR = 12'h000; + parameter [15:0] PF1_SRIOV_CAP_TOTAL_VF = 16'h0000; + parameter [3:0] PF1_SRIOV_CAP_VER = 4'h1; + parameter [15:0] PF1_SRIOV_FIRST_VF_OFFSET = 16'h0000; + parameter [15:0] PF1_SRIOV_FUNC_DEP_LINK = 16'h0000; + parameter [31:0] PF1_SRIOV_SUPPORTED_PAGE_SIZE = 32'h00000000; + parameter [15:0] PF1_SRIOV_VF_DEVICE_ID = 16'h0000; + parameter [11:0] PF1_TPHR_CAP_NEXTPTR = 12'h000; + parameter [2:0] PF1_TPHR_CAP_ST_MODE_SEL = 3'h0; + parameter [11:0] PF2_AER_CAP_NEXTPTR = 12'h000; + parameter [11:0] PF2_ARI_CAP_NEXTPTR = 12'h000; + parameter [7:0] PF2_ARI_CAP_NEXT_FUNC = 8'h00; + parameter [4:0] PF2_ATS_CAP_INV_QUEUE_DEPTH = 5'h00; + parameter [11:0] PF2_ATS_CAP_NEXTPTR = 12'h000; + parameter PF2_ATS_CAP_ON = "FALSE"; + parameter [5:0] PF2_BAR0_APERTURE_SIZE = 6'h03; + parameter [2:0] PF2_BAR0_CONTROL = 3'h4; + parameter [4:0] PF2_BAR1_APERTURE_SIZE = 5'h00; + parameter [2:0] PF2_BAR1_CONTROL = 3'h0; + parameter [5:0] PF2_BAR2_APERTURE_SIZE = 6'h03; + parameter [2:0] PF2_BAR2_CONTROL = 3'h4; + parameter [4:0] PF2_BAR3_APERTURE_SIZE = 5'h03; + parameter [2:0] PF2_BAR3_CONTROL = 3'h0; + parameter [5:0] PF2_BAR4_APERTURE_SIZE = 6'h03; + parameter [2:0] PF2_BAR4_CONTROL = 3'h4; + parameter [4:0] PF2_BAR5_APERTURE_SIZE = 5'h03; + parameter [2:0] PF2_BAR5_CONTROL = 3'h0; + parameter [7:0] PF2_CAPABILITY_POINTER = 8'h80; + parameter [23:0] PF2_CLASS_CODE = 24'h000000; + parameter [2:0] PF2_DEV_CAP_MAX_PAYLOAD_SIZE = 3'h3; + parameter [11:0] PF2_DSN_CAP_NEXTPTR = 12'h10C; + parameter [4:0] PF2_EXPANSION_ROM_APERTURE_SIZE = 5'h03; + parameter PF2_EXPANSION_ROM_ENABLE = "FALSE"; + parameter [2:0] PF2_INTERRUPT_PIN = 3'h1; + parameter [7:0] PF2_MSIX_CAP_NEXTPTR = 8'h00; + parameter integer PF2_MSIX_CAP_PBA_BIR = 0; + parameter [28:0] PF2_MSIX_CAP_PBA_OFFSET = 29'h00000050; + parameter integer PF2_MSIX_CAP_TABLE_BIR = 0; + parameter [28:0] PF2_MSIX_CAP_TABLE_OFFSET = 29'h00000040; + parameter [10:0] PF2_MSIX_CAP_TABLE_SIZE = 11'h000; + parameter integer PF2_MSI_CAP_MULTIMSGCAP = 0; + parameter [7:0] PF2_MSI_CAP_NEXTPTR = 8'h00; + parameter PF2_MSI_CAP_PERVECMASKCAP = "FALSE"; + parameter [7:0] PF2_PCIE_CAP_NEXTPTR = 8'h00; + parameter [7:0] PF2_PM_CAP_NEXTPTR = 8'h00; + parameter [11:0] PF2_PRI_CAP_NEXTPTR = 12'h000; + parameter PF2_PRI_CAP_ON = "FALSE"; + parameter [31:0] PF2_PRI_OST_PR_CAPACITY = 32'h00000000; + parameter PF2_SRIOV_ARI_CAPBL_HIER_PRESERVED = "FALSE"; + parameter [5:0] PF2_SRIOV_BAR0_APERTURE_SIZE = 6'h03; + parameter [2:0] PF2_SRIOV_BAR0_CONTROL = 3'h4; + parameter [4:0] PF2_SRIOV_BAR1_APERTURE_SIZE = 5'h00; + parameter [2:0] PF2_SRIOV_BAR1_CONTROL = 3'h0; + parameter [5:0] PF2_SRIOV_BAR2_APERTURE_SIZE = 6'h03; + parameter [2:0] PF2_SRIOV_BAR2_CONTROL = 3'h4; + parameter [4:0] PF2_SRIOV_BAR3_APERTURE_SIZE = 5'h03; + parameter [2:0] PF2_SRIOV_BAR3_CONTROL = 3'h0; + parameter [5:0] PF2_SRIOV_BAR4_APERTURE_SIZE = 6'h03; + parameter [2:0] PF2_SRIOV_BAR4_CONTROL = 3'h4; + parameter [4:0] PF2_SRIOV_BAR5_APERTURE_SIZE = 5'h03; + parameter [2:0] PF2_SRIOV_BAR5_CONTROL = 3'h0; + parameter [15:0] PF2_SRIOV_CAP_INITIAL_VF = 16'h0000; + parameter [11:0] PF2_SRIOV_CAP_NEXTPTR = 12'h000; + parameter [15:0] PF2_SRIOV_CAP_TOTAL_VF = 16'h0000; + parameter [3:0] PF2_SRIOV_CAP_VER = 4'h1; + parameter [15:0] PF2_SRIOV_FIRST_VF_OFFSET = 16'h0000; + parameter [15:0] PF2_SRIOV_FUNC_DEP_LINK = 16'h0000; + parameter [31:0] PF2_SRIOV_SUPPORTED_PAGE_SIZE = 32'h00000000; + parameter [15:0] PF2_SRIOV_VF_DEVICE_ID = 16'h0000; + parameter [11:0] PF2_TPHR_CAP_NEXTPTR = 12'h000; + parameter [2:0] PF2_TPHR_CAP_ST_MODE_SEL = 3'h0; + parameter [11:0] PF3_AER_CAP_NEXTPTR = 12'h000; + parameter [11:0] PF3_ARI_CAP_NEXTPTR = 12'h000; + parameter [7:0] PF3_ARI_CAP_NEXT_FUNC = 8'h00; + parameter [4:0] PF3_ATS_CAP_INV_QUEUE_DEPTH = 5'h00; + parameter [11:0] PF3_ATS_CAP_NEXTPTR = 12'h000; + parameter PF3_ATS_CAP_ON = "FALSE"; + parameter [5:0] PF3_BAR0_APERTURE_SIZE = 6'h03; + parameter [2:0] PF3_BAR0_CONTROL = 3'h4; + parameter [4:0] PF3_BAR1_APERTURE_SIZE = 5'h00; + parameter [2:0] PF3_BAR1_CONTROL = 3'h0; + parameter [5:0] PF3_BAR2_APERTURE_SIZE = 6'h03; + parameter [2:0] PF3_BAR2_CONTROL = 3'h4; + parameter [4:0] PF3_BAR3_APERTURE_SIZE = 5'h03; + parameter [2:0] PF3_BAR3_CONTROL = 3'h0; + parameter [5:0] PF3_BAR4_APERTURE_SIZE = 6'h03; + parameter [2:0] PF3_BAR4_CONTROL = 3'h4; + parameter [4:0] PF3_BAR5_APERTURE_SIZE = 5'h03; + parameter [2:0] PF3_BAR5_CONTROL = 3'h0; + parameter [7:0] PF3_CAPABILITY_POINTER = 8'h80; + parameter [23:0] PF3_CLASS_CODE = 24'h000000; + parameter [2:0] PF3_DEV_CAP_MAX_PAYLOAD_SIZE = 3'h3; + parameter [11:0] PF3_DSN_CAP_NEXTPTR = 12'h10C; + parameter [4:0] PF3_EXPANSION_ROM_APERTURE_SIZE = 5'h03; + parameter PF3_EXPANSION_ROM_ENABLE = "FALSE"; + parameter [2:0] PF3_INTERRUPT_PIN = 3'h1; + parameter [7:0] PF3_MSIX_CAP_NEXTPTR = 8'h00; + parameter integer PF3_MSIX_CAP_PBA_BIR = 0; + parameter [28:0] PF3_MSIX_CAP_PBA_OFFSET = 29'h00000050; + parameter integer PF3_MSIX_CAP_TABLE_BIR = 0; + parameter [28:0] PF3_MSIX_CAP_TABLE_OFFSET = 29'h00000040; + parameter [10:0] PF3_MSIX_CAP_TABLE_SIZE = 11'h000; + parameter integer PF3_MSI_CAP_MULTIMSGCAP = 0; + parameter [7:0] PF3_MSI_CAP_NEXTPTR = 8'h00; + parameter PF3_MSI_CAP_PERVECMASKCAP = "FALSE"; + parameter [7:0] PF3_PCIE_CAP_NEXTPTR = 8'h00; + parameter [7:0] PF3_PM_CAP_NEXTPTR = 8'h00; + parameter [11:0] PF3_PRI_CAP_NEXTPTR = 12'h000; + parameter PF3_PRI_CAP_ON = "FALSE"; + parameter [31:0] PF3_PRI_OST_PR_CAPACITY = 32'h00000000; + parameter PF3_SRIOV_ARI_CAPBL_HIER_PRESERVED = "FALSE"; + parameter [5:0] PF3_SRIOV_BAR0_APERTURE_SIZE = 6'h03; + parameter [2:0] PF3_SRIOV_BAR0_CONTROL = 3'h4; + parameter [4:0] PF3_SRIOV_BAR1_APERTURE_SIZE = 5'h00; + parameter [2:0] PF3_SRIOV_BAR1_CONTROL = 3'h0; + parameter [5:0] PF3_SRIOV_BAR2_APERTURE_SIZE = 6'h03; + parameter [2:0] PF3_SRIOV_BAR2_CONTROL = 3'h4; + parameter [4:0] PF3_SRIOV_BAR3_APERTURE_SIZE = 5'h03; + parameter [2:0] PF3_SRIOV_BAR3_CONTROL = 3'h0; + parameter [5:0] PF3_SRIOV_BAR4_APERTURE_SIZE = 6'h03; + parameter [2:0] PF3_SRIOV_BAR4_CONTROL = 3'h4; + parameter [4:0] PF3_SRIOV_BAR5_APERTURE_SIZE = 5'h03; + parameter [2:0] PF3_SRIOV_BAR5_CONTROL = 3'h0; + parameter [15:0] PF3_SRIOV_CAP_INITIAL_VF = 16'h0000; + parameter [11:0] PF3_SRIOV_CAP_NEXTPTR = 12'h000; + parameter [15:0] PF3_SRIOV_CAP_TOTAL_VF = 16'h0000; + parameter [3:0] PF3_SRIOV_CAP_VER = 4'h1; + parameter [15:0] PF3_SRIOV_FIRST_VF_OFFSET = 16'h0000; + parameter [15:0] PF3_SRIOV_FUNC_DEP_LINK = 16'h0000; + parameter [31:0] PF3_SRIOV_SUPPORTED_PAGE_SIZE = 32'h00000000; + parameter [15:0] PF3_SRIOV_VF_DEVICE_ID = 16'h0000; + parameter [11:0] PF3_TPHR_CAP_NEXTPTR = 12'h000; + parameter [2:0] PF3_TPHR_CAP_ST_MODE_SEL = 3'h0; + parameter PL_CFG_STATE_ROBUSTNESS_ENABLE = "TRUE"; + parameter PL_CTRL_SKP_GEN_ENABLE = "FALSE"; + parameter PL_CTRL_SKP_PARITY_AND_CRC_CHECK_DISABLE = "TRUE"; + parameter PL_DEEMPH_SOURCE_SELECT = "TRUE"; + parameter PL_DESKEW_ON_SKIP_IN_GEN12 = "FALSE"; + parameter PL_DISABLE_AUTO_EQ_SPEED_CHANGE_TO_GEN3 = "FALSE"; + parameter PL_DISABLE_AUTO_EQ_SPEED_CHANGE_TO_GEN4 = "FALSE"; + parameter PL_DISABLE_AUTO_SPEED_CHANGE_TO_GEN2 = "FALSE"; + parameter PL_DISABLE_DC_BALANCE = "FALSE"; + parameter PL_DISABLE_EI_INFER_IN_L0 = "FALSE"; + parameter PL_DISABLE_LANE_REVERSAL = "FALSE"; + parameter [1:0] PL_DISABLE_LFSR_UPDATE_ON_SKP = 2'h0; + parameter PL_DISABLE_RETRAIN_ON_EB_ERROR = "FALSE"; + parameter PL_DISABLE_RETRAIN_ON_FRAMING_ERROR = "FALSE"; + parameter [15:0] PL_DISABLE_RETRAIN_ON_SPECIFIC_FRAMING_ERROR = 16'h0000; + parameter PL_DISABLE_UPCONFIG_CAPABLE = "FALSE"; + parameter [1:0] PL_EQ_ADAPT_DISABLE_COEFF_CHECK = 2'h0; + parameter [1:0] PL_EQ_ADAPT_DISABLE_PRESET_CHECK = 2'h0; + parameter [4:0] PL_EQ_ADAPT_ITER_COUNT = 5'h02; + parameter [1:0] PL_EQ_ADAPT_REJECT_RETRY_COUNT = 2'h1; + parameter [1:0] PL_EQ_BYPASS_PHASE23 = 2'h0; + parameter [5:0] PL_EQ_DEFAULT_RX_PRESET_HINT = 6'h33; + parameter [7:0] PL_EQ_DEFAULT_TX_PRESET = 8'h44; + parameter PL_EQ_DISABLE_MISMATCH_CHECK = "TRUE"; + parameter [1:0] PL_EQ_RX_ADAPT_EQ_PHASE0 = 2'h0; + parameter [1:0] PL_EQ_RX_ADAPT_EQ_PHASE1 = 2'h0; + parameter PL_EQ_SHORT_ADAPT_PHASE = "FALSE"; + parameter PL_EQ_TX_8G_EQ_TS2_ENABLE = "FALSE"; + parameter PL_EXIT_LOOPBACK_ON_EI_ENTRY = "TRUE"; + parameter PL_INFER_EI_DISABLE_LPBK_ACTIVE = "TRUE"; + parameter PL_INFER_EI_DISABLE_REC_RC = "FALSE"; + parameter PL_INFER_EI_DISABLE_REC_SPD = "FALSE"; + parameter [31:0] PL_LANE0_EQ_CONTROL = 32'h00003F00; + parameter [31:0] PL_LANE10_EQ_CONTROL = 32'h00003F00; + parameter [31:0] PL_LANE11_EQ_CONTROL = 32'h00003F00; + parameter [31:0] PL_LANE12_EQ_CONTROL = 32'h00003F00; + parameter [31:0] PL_LANE13_EQ_CONTROL = 32'h00003F00; + parameter [31:0] PL_LANE14_EQ_CONTROL = 32'h00003F00; + parameter [31:0] PL_LANE15_EQ_CONTROL = 32'h00003F00; + parameter [31:0] PL_LANE1_EQ_CONTROL = 32'h00003F00; + parameter [31:0] PL_LANE2_EQ_CONTROL = 32'h00003F00; + parameter [31:0] PL_LANE3_EQ_CONTROL = 32'h00003F00; + parameter [31:0] PL_LANE4_EQ_CONTROL = 32'h00003F00; + parameter [31:0] PL_LANE5_EQ_CONTROL = 32'h00003F00; + parameter [31:0] PL_LANE6_EQ_CONTROL = 32'h00003F00; + parameter [31:0] PL_LANE7_EQ_CONTROL = 32'h00003F00; + parameter [31:0] PL_LANE8_EQ_CONTROL = 32'h00003F00; + parameter [31:0] PL_LANE9_EQ_CONTROL = 32'h00003F00; + parameter [3:0] PL_LINK_CAP_MAX_LINK_SPEED = 4'h4; + parameter [4:0] PL_LINK_CAP_MAX_LINK_WIDTH = 5'h08; + parameter integer PL_N_FTS = 255; + parameter PL_QUIESCE_GUARANTEE_DISABLE = "FALSE"; + parameter PL_REDO_EQ_SOURCE_SELECT = "TRUE"; + parameter [7:0] PL_REPORT_ALL_PHY_ERRORS = 8'h00; + parameter [1:0] PL_RX_ADAPT_TIMER_CLWS_CLOBBER_TX_TS = 2'h0; + parameter [3:0] PL_RX_ADAPT_TIMER_CLWS_GEN3 = 4'h0; + parameter [3:0] PL_RX_ADAPT_TIMER_CLWS_GEN4 = 4'h0; + parameter [1:0] PL_RX_ADAPT_TIMER_RRL_CLOBBER_TX_TS = 2'h0; + parameter [3:0] PL_RX_ADAPT_TIMER_RRL_GEN3 = 4'h0; + parameter [3:0] PL_RX_ADAPT_TIMER_RRL_GEN4 = 4'h0; + parameter [1:0] PL_RX_L0S_EXIT_TO_RECOVERY = 2'h0; + parameter [1:0] PL_SIM_FAST_LINK_TRAINING = 2'h0; + parameter PL_SRIS_ENABLE = "FALSE"; + parameter [6:0] PL_SRIS_SKPOS_GEN_SPD_VEC = 7'h00; + parameter [6:0] PL_SRIS_SKPOS_REC_SPD_VEC = 7'h00; + parameter PL_UPSTREAM_FACING = "TRUE"; + parameter [15:0] PL_USER_SPARE = 16'h0000; + parameter [15:0] PL_USER_SPARE2 = 16'h0000; + parameter [15:0] PM_ASPML0S_TIMEOUT = 16'h1500; + parameter [19:0] PM_ASPML1_ENTRY_DELAY = 20'h003E8; + parameter PM_ENABLE_L23_ENTRY = "FALSE"; + parameter PM_ENABLE_SLOT_POWER_CAPTURE = "TRUE"; + parameter [31:0] PM_L1_REENTRY_DELAY = 32'h00000100; + parameter [19:0] PM_PME_SERVICE_TIMEOUT_DELAY = 20'h00000; + parameter [15:0] PM_PME_TURNOFF_ACK_DELAY = 16'h0100; + parameter SIM_DEVICE = "ULTRASCALE_PLUS"; + parameter [31:0] SIM_JTAG_IDCODE = 32'h00000000; + parameter SIM_VERSION = "1.0"; + parameter SPARE_BIT0 = "FALSE"; + parameter integer SPARE_BIT1 = 0; + parameter integer SPARE_BIT2 = 0; + parameter SPARE_BIT3 = "FALSE"; + parameter integer SPARE_BIT4 = 0; + parameter integer SPARE_BIT5 = 0; + parameter integer SPARE_BIT6 = 0; + parameter integer SPARE_BIT7 = 0; + parameter integer SPARE_BIT8 = 0; + parameter [7:0] SPARE_BYTE0 = 8'h00; + parameter [7:0] SPARE_BYTE1 = 8'h00; + parameter [7:0] SPARE_BYTE2 = 8'h00; + parameter [7:0] SPARE_BYTE3 = 8'h00; + parameter [31:0] SPARE_WORD0 = 32'h00000000; + parameter [31:0] SPARE_WORD1 = 32'h00000000; + parameter [31:0] SPARE_WORD2 = 32'h00000000; + parameter [31:0] SPARE_WORD3 = 32'h00000000; + parameter [3:0] SRIOV_CAP_ENABLE = 4'h0; + parameter TL2CFG_IF_PARITY_CHK = "TRUE"; + parameter [1:0] TL_COMPLETION_RAM_NUM_TLPS = 2'h0; + parameter [1:0] TL_COMPLETION_RAM_SIZE = 2'h1; + parameter [11:0] TL_CREDITS_CD = 12'h000; + parameter [11:0] TL_CREDITS_CD_VC1 = 12'h000; + parameter [7:0] TL_CREDITS_CH = 8'h00; + parameter [7:0] TL_CREDITS_CH_VC1 = 8'h00; + parameter [11:0] TL_CREDITS_NPD = 12'h004; + parameter [11:0] TL_CREDITS_NPD_VC1 = 12'h000; + parameter [7:0] TL_CREDITS_NPH = 8'h20; + parameter [7:0] TL_CREDITS_NPH_VC1 = 8'h01; + parameter [11:0] TL_CREDITS_PD = 12'h0E0; + parameter [11:0] TL_CREDITS_PD_VC1 = 12'h3E0; + parameter [7:0] TL_CREDITS_PH = 8'h20; + parameter [7:0] TL_CREDITS_PH_VC1 = 8'h20; + parameter [4:0] TL_FC_UPDATE_MIN_INTERVAL_TIME = 5'h02; + parameter [4:0] TL_FC_UPDATE_MIN_INTERVAL_TIME_VC1 = 5'h02; + parameter [4:0] TL_FC_UPDATE_MIN_INTERVAL_TLP_COUNT = 5'h08; + parameter [4:0] TL_FC_UPDATE_MIN_INTERVAL_TLP_COUNT_VC1 = 5'h08; + parameter TL_FEATURE_ENABLE_FC_SCALING = "FALSE"; + parameter [1:0] TL_PF_ENABLE_REG = 2'h0; + parameter [0:0] TL_POSTED_RAM_SIZE = 1'h0; + parameter TL_RX_COMPLETION_FROM_RAM_READ_PIPELINE = "FALSE"; + parameter TL_RX_COMPLETION_TO_RAM_READ_PIPELINE = "FALSE"; + parameter TL_RX_COMPLETION_TO_RAM_WRITE_PIPELINE = "FALSE"; + parameter TL_RX_POSTED_FROM_RAM_READ_PIPELINE = "FALSE"; + parameter TL_RX_POSTED_TO_RAM_READ_PIPELINE = "FALSE"; + parameter TL_RX_POSTED_TO_RAM_WRITE_PIPELINE = "FALSE"; + parameter TL_TX_MUX_STRICT_PRIORITY = "TRUE"; + parameter TL_TX_TLP_STRADDLE_ENABLE = "FALSE"; + parameter TL_TX_TLP_TERMINATE_PARITY = "FALSE"; + parameter [15:0] TL_USER_SPARE = 16'h0000; + parameter TPH_FROM_RAM_PIPELINE = "FALSE"; + parameter TPH_TO_RAM_PIPELINE = "FALSE"; + parameter [7:0] VF0_CAPABILITY_POINTER = 8'h80; + parameter [11:0] VFG0_ARI_CAP_NEXTPTR = 12'h000; + parameter [4:0] VFG0_ATS_CAP_INV_QUEUE_DEPTH = 5'h00; + parameter [11:0] VFG0_ATS_CAP_NEXTPTR = 12'h000; + parameter VFG0_ATS_CAP_ON = "FALSE"; + parameter [7:0] VFG0_MSIX_CAP_NEXTPTR = 8'h00; + parameter integer VFG0_MSIX_CAP_PBA_BIR = 0; + parameter [28:0] VFG0_MSIX_CAP_PBA_OFFSET = 29'h00000050; + parameter integer VFG0_MSIX_CAP_TABLE_BIR = 0; + parameter [28:0] VFG0_MSIX_CAP_TABLE_OFFSET = 29'h00000040; + parameter [10:0] VFG0_MSIX_CAP_TABLE_SIZE = 11'h000; + parameter [7:0] VFG0_PCIE_CAP_NEXTPTR = 8'h00; + parameter [11:0] VFG0_TPHR_CAP_NEXTPTR = 12'h000; + parameter [2:0] VFG0_TPHR_CAP_ST_MODE_SEL = 3'h0; + parameter [11:0] VFG1_ARI_CAP_NEXTPTR = 12'h000; + parameter [4:0] VFG1_ATS_CAP_INV_QUEUE_DEPTH = 5'h00; + parameter [11:0] VFG1_ATS_CAP_NEXTPTR = 12'h000; + parameter VFG1_ATS_CAP_ON = "FALSE"; + parameter [7:0] VFG1_MSIX_CAP_NEXTPTR = 8'h00; + parameter integer VFG1_MSIX_CAP_PBA_BIR = 0; + parameter [28:0] VFG1_MSIX_CAP_PBA_OFFSET = 29'h00000050; + parameter integer VFG1_MSIX_CAP_TABLE_BIR = 0; + parameter [28:0] VFG1_MSIX_CAP_TABLE_OFFSET = 29'h00000040; + parameter [10:0] VFG1_MSIX_CAP_TABLE_SIZE = 11'h000; + parameter [7:0] VFG1_PCIE_CAP_NEXTPTR = 8'h00; + parameter [11:0] VFG1_TPHR_CAP_NEXTPTR = 12'h000; + parameter [2:0] VFG1_TPHR_CAP_ST_MODE_SEL = 3'h0; + parameter [11:0] VFG2_ARI_CAP_NEXTPTR = 12'h000; + parameter [4:0] VFG2_ATS_CAP_INV_QUEUE_DEPTH = 5'h00; + parameter [11:0] VFG2_ATS_CAP_NEXTPTR = 12'h000; + parameter VFG2_ATS_CAP_ON = "FALSE"; + parameter [7:0] VFG2_MSIX_CAP_NEXTPTR = 8'h00; + parameter integer VFG2_MSIX_CAP_PBA_BIR = 0; + parameter [28:0] VFG2_MSIX_CAP_PBA_OFFSET = 29'h00000050; + parameter integer VFG2_MSIX_CAP_TABLE_BIR = 0; + parameter [28:0] VFG2_MSIX_CAP_TABLE_OFFSET = 29'h00000040; + parameter [10:0] VFG2_MSIX_CAP_TABLE_SIZE = 11'h000; + parameter [7:0] VFG2_PCIE_CAP_NEXTPTR = 8'h00; + parameter [11:0] VFG2_TPHR_CAP_NEXTPTR = 12'h000; + parameter [2:0] VFG2_TPHR_CAP_ST_MODE_SEL = 3'h0; + parameter [11:0] VFG3_ARI_CAP_NEXTPTR = 12'h000; + parameter [4:0] VFG3_ATS_CAP_INV_QUEUE_DEPTH = 5'h00; + parameter [11:0] VFG3_ATS_CAP_NEXTPTR = 12'h000; + parameter VFG3_ATS_CAP_ON = "FALSE"; + parameter [7:0] VFG3_MSIX_CAP_NEXTPTR = 8'h00; + parameter integer VFG3_MSIX_CAP_PBA_BIR = 0; + parameter [28:0] VFG3_MSIX_CAP_PBA_OFFSET = 29'h00000050; + parameter integer VFG3_MSIX_CAP_TABLE_BIR = 0; + parameter [28:0] VFG3_MSIX_CAP_TABLE_OFFSET = 29'h00000040; + parameter [10:0] VFG3_MSIX_CAP_TABLE_SIZE = 11'h000; + parameter [7:0] VFG3_PCIE_CAP_NEXTPTR = 8'h00; + parameter [11:0] VFG3_TPHR_CAP_NEXTPTR = 12'h000; + parameter [2:0] VFG3_TPHR_CAP_ST_MODE_SEL = 3'h0; + output [7:0] AXIUSEROUT; + output CCIXTXCREDIT; + output [7:0] CFGBUSNUMBER; + output [1:0] CFGCURRENTSPEED; + output CFGERRCOROUT; + output CFGERRFATALOUT; + output CFGERRNONFATALOUT; + output [7:0] CFGEXTFUNCTIONNUMBER; + output CFGEXTREADRECEIVED; + output [9:0] CFGEXTREGISTERNUMBER; + output [3:0] CFGEXTWRITEBYTEENABLE; + output [31:0] CFGEXTWRITEDATA; + output CFGEXTWRITERECEIVED; + output [11:0] CFGFCCPLD; + output [7:0] CFGFCCPLH; + output [11:0] CFGFCNPD; + output [7:0] CFGFCNPH; + output [11:0] CFGFCPD; + output [7:0] CFGFCPH; + output [3:0] CFGFLRINPROCESS; + output [11:0] CFGFUNCTIONPOWERSTATE; + output [15:0] CFGFUNCTIONSTATUS; + output CFGHOTRESETOUT; + output [31:0] CFGINTERRUPTMSIDATA; + output [3:0] CFGINTERRUPTMSIENABLE; + output CFGINTERRUPTMSIFAIL; + output CFGINTERRUPTMSIMASKUPDATE; + output [11:0] CFGINTERRUPTMSIMMENABLE; + output CFGINTERRUPTMSISENT; + output [3:0] CFGINTERRUPTMSIXENABLE; + output [3:0] CFGINTERRUPTMSIXMASK; + output CFGINTERRUPTMSIXVECPENDINGSTATUS; + output CFGINTERRUPTSENT; + output [1:0] CFGLINKPOWERSTATE; + output [4:0] CFGLOCALERROROUT; + output CFGLOCALERRORVALID; + output CFGLTRENABLE; + output [5:0] CFGLTSSMSTATE; + output [1:0] CFGMAXPAYLOAD; + output [2:0] CFGMAXREADREQ; + output [31:0] CFGMGMTREADDATA; + output CFGMGMTREADWRITEDONE; + output CFGMSGRECEIVED; + output [7:0] CFGMSGRECEIVEDDATA; + output [4:0] CFGMSGRECEIVEDTYPE; + output CFGMSGTRANSMITDONE; + output [12:0] CFGMSIXRAMADDRESS; + output CFGMSIXRAMREADENABLE; + output [3:0] CFGMSIXRAMWRITEBYTEENABLE; + output [35:0] CFGMSIXRAMWRITEDATA; + output [2:0] CFGNEGOTIATEDWIDTH; + output [1:0] CFGOBFFENABLE; + output CFGPHYLINKDOWN; + output [1:0] CFGPHYLINKSTATUS; + output CFGPLSTATUSCHANGE; + output CFGPOWERSTATECHANGEINTERRUPT; + output [3:0] CFGRCBSTATUS; + output [1:0] CFGRXPMSTATE; + output [11:0] CFGTPHRAMADDRESS; + output CFGTPHRAMREADENABLE; + output [3:0] CFGTPHRAMWRITEBYTEENABLE; + output [35:0] CFGTPHRAMWRITEDATA; + output [3:0] CFGTPHREQUESTERENABLE; + output [11:0] CFGTPHSTMODE; + output [1:0] CFGTXPMSTATE; + output CFGVC1ENABLE; + output CFGVC1NEGOTIATIONPENDING; + output CONFMCAPDESIGNSWITCH; + output CONFMCAPEOS; + output CONFMCAPINUSEBYPCIE; + output CONFREQREADY; + output [31:0] CONFRESPRDATA; + output CONFRESPVALID; + output [129:0] DBGCCIXOUT; + output [31:0] DBGCTRL0OUT; + output [31:0] DBGCTRL1OUT; + output [255:0] DBGDATA0OUT; + output [255:0] DBGDATA1OUT; + output [15:0] DRPDO; + output DRPRDY; + output [45:0] MAXISCCIXRXTUSER; + output MAXISCCIXRXTVALID; + output [255:0] MAXISCQTDATA; + output [7:0] MAXISCQTKEEP; + output MAXISCQTLAST; + output [87:0] MAXISCQTUSER; + output MAXISCQTVALID; + output [255:0] MAXISRCTDATA; + output [7:0] MAXISRCTKEEP; + output MAXISRCTLAST; + output [74:0] MAXISRCTUSER; + output MAXISRCTVALID; + output [8:0] MIREPLAYRAMADDRESS0; + output [8:0] MIREPLAYRAMADDRESS1; + output MIREPLAYRAMREADENABLE0; + output MIREPLAYRAMREADENABLE1; + output [127:0] MIREPLAYRAMWRITEDATA0; + output [127:0] MIREPLAYRAMWRITEDATA1; + output MIREPLAYRAMWRITEENABLE0; + output MIREPLAYRAMWRITEENABLE1; + output [8:0] MIRXCOMPLETIONRAMREADADDRESS0; + output [8:0] MIRXCOMPLETIONRAMREADADDRESS1; + output [1:0] MIRXCOMPLETIONRAMREADENABLE0; + output [1:0] MIRXCOMPLETIONRAMREADENABLE1; + output [8:0] MIRXCOMPLETIONRAMWRITEADDRESS0; + output [8:0] MIRXCOMPLETIONRAMWRITEADDRESS1; + output [143:0] MIRXCOMPLETIONRAMWRITEDATA0; + output [143:0] MIRXCOMPLETIONRAMWRITEDATA1; + output [1:0] MIRXCOMPLETIONRAMWRITEENABLE0; + output [1:0] MIRXCOMPLETIONRAMWRITEENABLE1; + output [8:0] MIRXPOSTEDREQUESTRAMREADADDRESS0; + output [8:0] MIRXPOSTEDREQUESTRAMREADADDRESS1; + output MIRXPOSTEDREQUESTRAMREADENABLE0; + output MIRXPOSTEDREQUESTRAMREADENABLE1; + output [8:0] MIRXPOSTEDREQUESTRAMWRITEADDRESS0; + output [8:0] MIRXPOSTEDREQUESTRAMWRITEADDRESS1; + output [143:0] MIRXPOSTEDREQUESTRAMWRITEDATA0; + output [143:0] MIRXPOSTEDREQUESTRAMWRITEDATA1; + output MIRXPOSTEDREQUESTRAMWRITEENABLE0; + output MIRXPOSTEDREQUESTRAMWRITEENABLE1; + output [5:0] PCIECQNPREQCOUNT; + output PCIEPERST0B; + output PCIEPERST1B; + output [5:0] PCIERQSEQNUM0; + output [5:0] PCIERQSEQNUM1; + output PCIERQSEQNUMVLD0; + output PCIERQSEQNUMVLD1; + output [7:0] PCIERQTAG0; + output [7:0] PCIERQTAG1; + output [3:0] PCIERQTAGAV; + output PCIERQTAGVLD0; + output PCIERQTAGVLD1; + output [3:0] PCIETFCNPDAV; + output [3:0] PCIETFCNPHAV; + output [1:0] PIPERX00EQCONTROL; + output PIPERX00POLARITY; + output [1:0] PIPERX01EQCONTROL; + output PIPERX01POLARITY; + output [1:0] PIPERX02EQCONTROL; + output PIPERX02POLARITY; + output [1:0] PIPERX03EQCONTROL; + output PIPERX03POLARITY; + output [1:0] PIPERX04EQCONTROL; + output PIPERX04POLARITY; + output [1:0] PIPERX05EQCONTROL; + output PIPERX05POLARITY; + output [1:0] PIPERX06EQCONTROL; + output PIPERX06POLARITY; + output [1:0] PIPERX07EQCONTROL; + output PIPERX07POLARITY; + output [1:0] PIPERX08EQCONTROL; + output PIPERX08POLARITY; + output [1:0] PIPERX09EQCONTROL; + output PIPERX09POLARITY; + output [1:0] PIPERX10EQCONTROL; + output PIPERX10POLARITY; + output [1:0] PIPERX11EQCONTROL; + output PIPERX11POLARITY; + output [1:0] PIPERX12EQCONTROL; + output PIPERX12POLARITY; + output [1:0] PIPERX13EQCONTROL; + output PIPERX13POLARITY; + output [1:0] PIPERX14EQCONTROL; + output PIPERX14POLARITY; + output [1:0] PIPERX15EQCONTROL; + output PIPERX15POLARITY; + output [5:0] PIPERXEQLPLFFS; + output [3:0] PIPERXEQLPTXPRESET; + output [1:0] PIPETX00CHARISK; + output PIPETX00COMPLIANCE; + output [31:0] PIPETX00DATA; + output PIPETX00DATAVALID; + output PIPETX00ELECIDLE; + output [1:0] PIPETX00EQCONTROL; + output [5:0] PIPETX00EQDEEMPH; + output [1:0] PIPETX00POWERDOWN; + output PIPETX00STARTBLOCK; + output [1:0] PIPETX00SYNCHEADER; + output [1:0] PIPETX01CHARISK; + output PIPETX01COMPLIANCE; + output [31:0] PIPETX01DATA; + output PIPETX01DATAVALID; + output PIPETX01ELECIDLE; + output [1:0] PIPETX01EQCONTROL; + output [5:0] PIPETX01EQDEEMPH; + output [1:0] PIPETX01POWERDOWN; + output PIPETX01STARTBLOCK; + output [1:0] PIPETX01SYNCHEADER; + output [1:0] PIPETX02CHARISK; + output PIPETX02COMPLIANCE; + output [31:0] PIPETX02DATA; + output PIPETX02DATAVALID; + output PIPETX02ELECIDLE; + output [1:0] PIPETX02EQCONTROL; + output [5:0] PIPETX02EQDEEMPH; + output [1:0] PIPETX02POWERDOWN; + output PIPETX02STARTBLOCK; + output [1:0] PIPETX02SYNCHEADER; + output [1:0] PIPETX03CHARISK; + output PIPETX03COMPLIANCE; + output [31:0] PIPETX03DATA; + output PIPETX03DATAVALID; + output PIPETX03ELECIDLE; + output [1:0] PIPETX03EQCONTROL; + output [5:0] PIPETX03EQDEEMPH; + output [1:0] PIPETX03POWERDOWN; + output PIPETX03STARTBLOCK; + output [1:0] PIPETX03SYNCHEADER; + output [1:0] PIPETX04CHARISK; + output PIPETX04COMPLIANCE; + output [31:0] PIPETX04DATA; + output PIPETX04DATAVALID; + output PIPETX04ELECIDLE; + output [1:0] PIPETX04EQCONTROL; + output [5:0] PIPETX04EQDEEMPH; + output [1:0] PIPETX04POWERDOWN; + output PIPETX04STARTBLOCK; + output [1:0] PIPETX04SYNCHEADER; + output [1:0] PIPETX05CHARISK; + output PIPETX05COMPLIANCE; + output [31:0] PIPETX05DATA; + output PIPETX05DATAVALID; + output PIPETX05ELECIDLE; + output [1:0] PIPETX05EQCONTROL; + output [5:0] PIPETX05EQDEEMPH; + output [1:0] PIPETX05POWERDOWN; + output PIPETX05STARTBLOCK; + output [1:0] PIPETX05SYNCHEADER; + output [1:0] PIPETX06CHARISK; + output PIPETX06COMPLIANCE; + output [31:0] PIPETX06DATA; + output PIPETX06DATAVALID; + output PIPETX06ELECIDLE; + output [1:0] PIPETX06EQCONTROL; + output [5:0] PIPETX06EQDEEMPH; + output [1:0] PIPETX06POWERDOWN; + output PIPETX06STARTBLOCK; + output [1:0] PIPETX06SYNCHEADER; + output [1:0] PIPETX07CHARISK; + output PIPETX07COMPLIANCE; + output [31:0] PIPETX07DATA; + output PIPETX07DATAVALID; + output PIPETX07ELECIDLE; + output [1:0] PIPETX07EQCONTROL; + output [5:0] PIPETX07EQDEEMPH; + output [1:0] PIPETX07POWERDOWN; + output PIPETX07STARTBLOCK; + output [1:0] PIPETX07SYNCHEADER; + output [1:0] PIPETX08CHARISK; + output PIPETX08COMPLIANCE; + output [31:0] PIPETX08DATA; + output PIPETX08DATAVALID; + output PIPETX08ELECIDLE; + output [1:0] PIPETX08EQCONTROL; + output [5:0] PIPETX08EQDEEMPH; + output [1:0] PIPETX08POWERDOWN; + output PIPETX08STARTBLOCK; + output [1:0] PIPETX08SYNCHEADER; + output [1:0] PIPETX09CHARISK; + output PIPETX09COMPLIANCE; + output [31:0] PIPETX09DATA; + output PIPETX09DATAVALID; + output PIPETX09ELECIDLE; + output [1:0] PIPETX09EQCONTROL; + output [5:0] PIPETX09EQDEEMPH; + output [1:0] PIPETX09POWERDOWN; + output PIPETX09STARTBLOCK; + output [1:0] PIPETX09SYNCHEADER; + output [1:0] PIPETX10CHARISK; + output PIPETX10COMPLIANCE; + output [31:0] PIPETX10DATA; + output PIPETX10DATAVALID; + output PIPETX10ELECIDLE; + output [1:0] PIPETX10EQCONTROL; + output [5:0] PIPETX10EQDEEMPH; + output [1:0] PIPETX10POWERDOWN; + output PIPETX10STARTBLOCK; + output [1:0] PIPETX10SYNCHEADER; + output [1:0] PIPETX11CHARISK; + output PIPETX11COMPLIANCE; + output [31:0] PIPETX11DATA; + output PIPETX11DATAVALID; + output PIPETX11ELECIDLE; + output [1:0] PIPETX11EQCONTROL; + output [5:0] PIPETX11EQDEEMPH; + output [1:0] PIPETX11POWERDOWN; + output PIPETX11STARTBLOCK; + output [1:0] PIPETX11SYNCHEADER; + output [1:0] PIPETX12CHARISK; + output PIPETX12COMPLIANCE; + output [31:0] PIPETX12DATA; + output PIPETX12DATAVALID; + output PIPETX12ELECIDLE; + output [1:0] PIPETX12EQCONTROL; + output [5:0] PIPETX12EQDEEMPH; + output [1:0] PIPETX12POWERDOWN; + output PIPETX12STARTBLOCK; + output [1:0] PIPETX12SYNCHEADER; + output [1:0] PIPETX13CHARISK; + output PIPETX13COMPLIANCE; + output [31:0] PIPETX13DATA; + output PIPETX13DATAVALID; + output PIPETX13ELECIDLE; + output [1:0] PIPETX13EQCONTROL; + output [5:0] PIPETX13EQDEEMPH; + output [1:0] PIPETX13POWERDOWN; + output PIPETX13STARTBLOCK; + output [1:0] PIPETX13SYNCHEADER; + output [1:0] PIPETX14CHARISK; + output PIPETX14COMPLIANCE; + output [31:0] PIPETX14DATA; + output PIPETX14DATAVALID; + output PIPETX14ELECIDLE; + output [1:0] PIPETX14EQCONTROL; + output [5:0] PIPETX14EQDEEMPH; + output [1:0] PIPETX14POWERDOWN; + output PIPETX14STARTBLOCK; + output [1:0] PIPETX14SYNCHEADER; + output [1:0] PIPETX15CHARISK; + output PIPETX15COMPLIANCE; + output [31:0] PIPETX15DATA; + output PIPETX15DATAVALID; + output PIPETX15ELECIDLE; + output [1:0] PIPETX15EQCONTROL; + output [5:0] PIPETX15EQDEEMPH; + output [1:0] PIPETX15POWERDOWN; + output PIPETX15STARTBLOCK; + output [1:0] PIPETX15SYNCHEADER; + output PIPETXDEEMPH; + output [2:0] PIPETXMARGIN; + output [1:0] PIPETXRATE; + output PIPETXRCVRDET; + output PIPETXRESET; + output PIPETXSWING; + output PLEQINPROGRESS; + output [1:0] PLEQPHASE; + output PLGEN34EQMISMATCH; + output [3:0] SAXISCCTREADY; + output [3:0] SAXISRQTREADY; + output [23:0] USERSPAREOUT; + input [7:0] AXIUSERIN; + input CCIXOPTIMIZEDTLPTXANDRXENABLE; + input CCIXRXCORRECTABLEERRORDETECTED; + input CCIXRXFIFOOVERFLOW; + input CCIXRXTLPFORWARDED0; + input CCIXRXTLPFORWARDED1; + input [5:0] CCIXRXTLPFORWARDEDLENGTH0; + input [5:0] CCIXRXTLPFORWARDEDLENGTH1; + input CCIXRXUNCORRECTABLEERRORDETECTED; + input CFGCONFIGSPACEENABLE; + input [15:0] CFGDEVIDPF0; + input [15:0] CFGDEVIDPF1; + input [15:0] CFGDEVIDPF2; + input [15:0] CFGDEVIDPF3; + input [7:0] CFGDSBUSNUMBER; + input [4:0] CFGDSDEVICENUMBER; + input [2:0] CFGDSFUNCTIONNUMBER; + input [63:0] CFGDSN; + input [7:0] CFGDSPORTNUMBER; + input CFGERRCORIN; + input CFGERRUNCORIN; + input [31:0] CFGEXTREADDATA; + input CFGEXTREADDATAVALID; + input [2:0] CFGFCSEL; + input CFGFCVCSEL; + input [3:0] CFGFLRDONE; + input CFGHOTRESETIN; + input [3:0] CFGINTERRUPTINT; + input [2:0] CFGINTERRUPTMSIATTR; + input [7:0] CFGINTERRUPTMSIFUNCTIONNUMBER; + input [31:0] CFGINTERRUPTMSIINT; + input [31:0] CFGINTERRUPTMSIPENDINGSTATUS; + input CFGINTERRUPTMSIPENDINGSTATUSDATAENABLE; + input [1:0] CFGINTERRUPTMSIPENDINGSTATUSFUNCTIONNUM; + input [1:0] CFGINTERRUPTMSISELECT; + input CFGINTERRUPTMSITPHPRESENT; + input [7:0] CFGINTERRUPTMSITPHSTTAG; + input [1:0] CFGINTERRUPTMSITPHTYPE; + input [63:0] CFGINTERRUPTMSIXADDRESS; + input [31:0] CFGINTERRUPTMSIXDATA; + input CFGINTERRUPTMSIXINT; + input [1:0] CFGINTERRUPTMSIXVECPENDING; + input [3:0] CFGINTERRUPTPENDING; + input CFGLINKTRAININGENABLE; + input [9:0] CFGMGMTADDR; + input [3:0] CFGMGMTBYTEENABLE; + input CFGMGMTDEBUGACCESS; + input [7:0] CFGMGMTFUNCTIONNUMBER; + input CFGMGMTREAD; + input CFGMGMTWRITE; + input [31:0] CFGMGMTWRITEDATA; + input CFGMSGTRANSMIT; + input [31:0] CFGMSGTRANSMITDATA; + input [2:0] CFGMSGTRANSMITTYPE; + input [35:0] CFGMSIXRAMREADDATA; + input CFGPMASPML1ENTRYREJECT; + input CFGPMASPMTXL0SENTRYDISABLE; + input CFGPOWERSTATECHANGEACK; + input CFGREQPMTRANSITIONL23READY; + input [7:0] CFGREVIDPF0; + input [7:0] CFGREVIDPF1; + input [7:0] CFGREVIDPF2; + input [7:0] CFGREVIDPF3; + input [15:0] CFGSUBSYSIDPF0; + input [15:0] CFGSUBSYSIDPF1; + input [15:0] CFGSUBSYSIDPF2; + input [15:0] CFGSUBSYSIDPF3; + input [15:0] CFGSUBSYSVENDID; + input [35:0] CFGTPHRAMREADDATA; + input [15:0] CFGVENDID; + input CFGVFFLRDONE; + input [7:0] CFGVFFLRFUNCNUM; + input CONFMCAPREQUESTBYCONF; + input [31:0] CONFREQDATA; + input [3:0] CONFREQREGNUM; + input [1:0] CONFREQTYPE; + input CONFREQVALID; + input CORECLK; + input CORECLKCCIX; + input CORECLKMIREPLAYRAM0; + input CORECLKMIREPLAYRAM1; + input CORECLKMIRXCOMPLETIONRAM0; + input CORECLKMIRXCOMPLETIONRAM1; + input CORECLKMIRXPOSTEDREQUESTRAM0; + input CORECLKMIRXPOSTEDREQUESTRAM1; + input [5:0] DBGSEL0; + input [5:0] DBGSEL1; + input [9:0] DRPADDR; + input DRPCLK; + input [15:0] DRPDI; + input DRPEN; + input DRPWE; + input [21:0] MAXISCQTREADY; + input [21:0] MAXISRCTREADY; + input MCAPCLK; + input MCAPPERST0B; + input MCAPPERST1B; + input MGMTRESETN; + input MGMTSTICKYRESETN; + input [5:0] MIREPLAYRAMERRCOR; + input [5:0] MIREPLAYRAMERRUNCOR; + input [127:0] MIREPLAYRAMREADDATA0; + input [127:0] MIREPLAYRAMREADDATA1; + input [11:0] MIRXCOMPLETIONRAMERRCOR; + input [11:0] MIRXCOMPLETIONRAMERRUNCOR; + input [143:0] MIRXCOMPLETIONRAMREADDATA0; + input [143:0] MIRXCOMPLETIONRAMREADDATA1; + input [5:0] MIRXPOSTEDREQUESTRAMERRCOR; + input [5:0] MIRXPOSTEDREQUESTRAMERRUNCOR; + input [143:0] MIRXPOSTEDREQUESTRAMREADDATA0; + input [143:0] MIRXPOSTEDREQUESTRAMREADDATA1; + input [1:0] PCIECOMPLDELIVERED; + input [7:0] PCIECOMPLDELIVEREDTAG0; + input [7:0] PCIECOMPLDELIVEREDTAG1; + input [1:0] PCIECQNPREQ; + input PCIECQNPUSERCREDITRCVD; + input PCIECQPIPELINEEMPTY; + input PCIEPOSTEDREQDELIVERED; + input PIPECLK; + input PIPECLKEN; + input [5:0] PIPEEQFS; + input [5:0] PIPEEQLF; + input PIPERESETN; + input [1:0] PIPERX00CHARISK; + input [31:0] PIPERX00DATA; + input PIPERX00DATAVALID; + input PIPERX00ELECIDLE; + input PIPERX00EQDONE; + input PIPERX00EQLPADAPTDONE; + input PIPERX00EQLPLFFSSEL; + input [17:0] PIPERX00EQLPNEWTXCOEFFORPRESET; + input PIPERX00PHYSTATUS; + input [1:0] PIPERX00STARTBLOCK; + input [2:0] PIPERX00STATUS; + input [1:0] PIPERX00SYNCHEADER; + input PIPERX00VALID; + input [1:0] PIPERX01CHARISK; + input [31:0] PIPERX01DATA; + input PIPERX01DATAVALID; + input PIPERX01ELECIDLE; + input PIPERX01EQDONE; + input PIPERX01EQLPADAPTDONE; + input PIPERX01EQLPLFFSSEL; + input [17:0] PIPERX01EQLPNEWTXCOEFFORPRESET; + input PIPERX01PHYSTATUS; + input [1:0] PIPERX01STARTBLOCK; + input [2:0] PIPERX01STATUS; + input [1:0] PIPERX01SYNCHEADER; + input PIPERX01VALID; + input [1:0] PIPERX02CHARISK; + input [31:0] PIPERX02DATA; + input PIPERX02DATAVALID; + input PIPERX02ELECIDLE; + input PIPERX02EQDONE; + input PIPERX02EQLPADAPTDONE; + input PIPERX02EQLPLFFSSEL; + input [17:0] PIPERX02EQLPNEWTXCOEFFORPRESET; + input PIPERX02PHYSTATUS; + input [1:0] PIPERX02STARTBLOCK; + input [2:0] PIPERX02STATUS; + input [1:0] PIPERX02SYNCHEADER; + input PIPERX02VALID; + input [1:0] PIPERX03CHARISK; + input [31:0] PIPERX03DATA; + input PIPERX03DATAVALID; + input PIPERX03ELECIDLE; + input PIPERX03EQDONE; + input PIPERX03EQLPADAPTDONE; + input PIPERX03EQLPLFFSSEL; + input [17:0] PIPERX03EQLPNEWTXCOEFFORPRESET; + input PIPERX03PHYSTATUS; + input [1:0] PIPERX03STARTBLOCK; + input [2:0] PIPERX03STATUS; + input [1:0] PIPERX03SYNCHEADER; + input PIPERX03VALID; + input [1:0] PIPERX04CHARISK; + input [31:0] PIPERX04DATA; + input PIPERX04DATAVALID; + input PIPERX04ELECIDLE; + input PIPERX04EQDONE; + input PIPERX04EQLPADAPTDONE; + input PIPERX04EQLPLFFSSEL; + input [17:0] PIPERX04EQLPNEWTXCOEFFORPRESET; + input PIPERX04PHYSTATUS; + input [1:0] PIPERX04STARTBLOCK; + input [2:0] PIPERX04STATUS; + input [1:0] PIPERX04SYNCHEADER; + input PIPERX04VALID; + input [1:0] PIPERX05CHARISK; + input [31:0] PIPERX05DATA; + input PIPERX05DATAVALID; + input PIPERX05ELECIDLE; + input PIPERX05EQDONE; + input PIPERX05EQLPADAPTDONE; + input PIPERX05EQLPLFFSSEL; + input [17:0] PIPERX05EQLPNEWTXCOEFFORPRESET; + input PIPERX05PHYSTATUS; + input [1:0] PIPERX05STARTBLOCK; + input [2:0] PIPERX05STATUS; + input [1:0] PIPERX05SYNCHEADER; + input PIPERX05VALID; + input [1:0] PIPERX06CHARISK; + input [31:0] PIPERX06DATA; + input PIPERX06DATAVALID; + input PIPERX06ELECIDLE; + input PIPERX06EQDONE; + input PIPERX06EQLPADAPTDONE; + input PIPERX06EQLPLFFSSEL; + input [17:0] PIPERX06EQLPNEWTXCOEFFORPRESET; + input PIPERX06PHYSTATUS; + input [1:0] PIPERX06STARTBLOCK; + input [2:0] PIPERX06STATUS; + input [1:0] PIPERX06SYNCHEADER; + input PIPERX06VALID; + input [1:0] PIPERX07CHARISK; + input [31:0] PIPERX07DATA; + input PIPERX07DATAVALID; + input PIPERX07ELECIDLE; + input PIPERX07EQDONE; + input PIPERX07EQLPADAPTDONE; + input PIPERX07EQLPLFFSSEL; + input [17:0] PIPERX07EQLPNEWTXCOEFFORPRESET; + input PIPERX07PHYSTATUS; + input [1:0] PIPERX07STARTBLOCK; + input [2:0] PIPERX07STATUS; + input [1:0] PIPERX07SYNCHEADER; + input PIPERX07VALID; + input [1:0] PIPERX08CHARISK; + input [31:0] PIPERX08DATA; + input PIPERX08DATAVALID; + input PIPERX08ELECIDLE; + input PIPERX08EQDONE; + input PIPERX08EQLPADAPTDONE; + input PIPERX08EQLPLFFSSEL; + input [17:0] PIPERX08EQLPNEWTXCOEFFORPRESET; + input PIPERX08PHYSTATUS; + input [1:0] PIPERX08STARTBLOCK; + input [2:0] PIPERX08STATUS; + input [1:0] PIPERX08SYNCHEADER; + input PIPERX08VALID; + input [1:0] PIPERX09CHARISK; + input [31:0] PIPERX09DATA; + input PIPERX09DATAVALID; + input PIPERX09ELECIDLE; + input PIPERX09EQDONE; + input PIPERX09EQLPADAPTDONE; + input PIPERX09EQLPLFFSSEL; + input [17:0] PIPERX09EQLPNEWTXCOEFFORPRESET; + input PIPERX09PHYSTATUS; + input [1:0] PIPERX09STARTBLOCK; + input [2:0] PIPERX09STATUS; + input [1:0] PIPERX09SYNCHEADER; + input PIPERX09VALID; + input [1:0] PIPERX10CHARISK; + input [31:0] PIPERX10DATA; + input PIPERX10DATAVALID; + input PIPERX10ELECIDLE; + input PIPERX10EQDONE; + input PIPERX10EQLPADAPTDONE; + input PIPERX10EQLPLFFSSEL; + input [17:0] PIPERX10EQLPNEWTXCOEFFORPRESET; + input PIPERX10PHYSTATUS; + input [1:0] PIPERX10STARTBLOCK; + input [2:0] PIPERX10STATUS; + input [1:0] PIPERX10SYNCHEADER; + input PIPERX10VALID; + input [1:0] PIPERX11CHARISK; + input [31:0] PIPERX11DATA; + input PIPERX11DATAVALID; + input PIPERX11ELECIDLE; + input PIPERX11EQDONE; + input PIPERX11EQLPADAPTDONE; + input PIPERX11EQLPLFFSSEL; + input [17:0] PIPERX11EQLPNEWTXCOEFFORPRESET; + input PIPERX11PHYSTATUS; + input [1:0] PIPERX11STARTBLOCK; + input [2:0] PIPERX11STATUS; + input [1:0] PIPERX11SYNCHEADER; + input PIPERX11VALID; + input [1:0] PIPERX12CHARISK; + input [31:0] PIPERX12DATA; + input PIPERX12DATAVALID; + input PIPERX12ELECIDLE; + input PIPERX12EQDONE; + input PIPERX12EQLPADAPTDONE; + input PIPERX12EQLPLFFSSEL; + input [17:0] PIPERX12EQLPNEWTXCOEFFORPRESET; + input PIPERX12PHYSTATUS; + input [1:0] PIPERX12STARTBLOCK; + input [2:0] PIPERX12STATUS; + input [1:0] PIPERX12SYNCHEADER; + input PIPERX12VALID; + input [1:0] PIPERX13CHARISK; + input [31:0] PIPERX13DATA; + input PIPERX13DATAVALID; + input PIPERX13ELECIDLE; + input PIPERX13EQDONE; + input PIPERX13EQLPADAPTDONE; + input PIPERX13EQLPLFFSSEL; + input [17:0] PIPERX13EQLPNEWTXCOEFFORPRESET; + input PIPERX13PHYSTATUS; + input [1:0] PIPERX13STARTBLOCK; + input [2:0] PIPERX13STATUS; + input [1:0] PIPERX13SYNCHEADER; + input PIPERX13VALID; + input [1:0] PIPERX14CHARISK; + input [31:0] PIPERX14DATA; + input PIPERX14DATAVALID; + input PIPERX14ELECIDLE; + input PIPERX14EQDONE; + input PIPERX14EQLPADAPTDONE; + input PIPERX14EQLPLFFSSEL; + input [17:0] PIPERX14EQLPNEWTXCOEFFORPRESET; + input PIPERX14PHYSTATUS; + input [1:0] PIPERX14STARTBLOCK; + input [2:0] PIPERX14STATUS; + input [1:0] PIPERX14SYNCHEADER; + input PIPERX14VALID; + input [1:0] PIPERX15CHARISK; + input [31:0] PIPERX15DATA; + input PIPERX15DATAVALID; + input PIPERX15ELECIDLE; + input PIPERX15EQDONE; + input PIPERX15EQLPADAPTDONE; + input PIPERX15EQLPLFFSSEL; + input [17:0] PIPERX15EQLPNEWTXCOEFFORPRESET; + input PIPERX15PHYSTATUS; + input [1:0] PIPERX15STARTBLOCK; + input [2:0] PIPERX15STATUS; + input [1:0] PIPERX15SYNCHEADER; + input PIPERX15VALID; + input [17:0] PIPETX00EQCOEFF; + input PIPETX00EQDONE; + input [17:0] PIPETX01EQCOEFF; + input PIPETX01EQDONE; + input [17:0] PIPETX02EQCOEFF; + input PIPETX02EQDONE; + input [17:0] PIPETX03EQCOEFF; + input PIPETX03EQDONE; + input [17:0] PIPETX04EQCOEFF; + input PIPETX04EQDONE; + input [17:0] PIPETX05EQCOEFF; + input PIPETX05EQDONE; + input [17:0] PIPETX06EQCOEFF; + input PIPETX06EQDONE; + input [17:0] PIPETX07EQCOEFF; + input PIPETX07EQDONE; + input [17:0] PIPETX08EQCOEFF; + input PIPETX08EQDONE; + input [17:0] PIPETX09EQCOEFF; + input PIPETX09EQDONE; + input [17:0] PIPETX10EQCOEFF; + input PIPETX10EQDONE; + input [17:0] PIPETX11EQCOEFF; + input PIPETX11EQDONE; + input [17:0] PIPETX12EQCOEFF; + input PIPETX12EQDONE; + input [17:0] PIPETX13EQCOEFF; + input PIPETX13EQDONE; + input [17:0] PIPETX14EQCOEFF; + input PIPETX14EQDONE; + input [17:0] PIPETX15EQCOEFF; + input PIPETX15EQDONE; + input PLEQRESETEIEOSCOUNT; + input PLGEN2UPSTREAMPREFERDEEMPH; + input PLGEN34REDOEQSPEED; + input PLGEN34REDOEQUALIZATION; + input RESETN; + input [255:0] SAXISCCIXTXTDATA; + input [45:0] SAXISCCIXTXTUSER; + input SAXISCCIXTXTVALID; + input [255:0] SAXISCCTDATA; + input [7:0] SAXISCCTKEEP; + input SAXISCCTLAST; + input [32:0] SAXISCCTUSER; + input SAXISCCTVALID; + input [255:0] SAXISRQTDATA; + input [7:0] SAXISRQTKEEP; + input SAXISRQTLAST; + input [61:0] SAXISRQTUSER; + input SAXISRQTVALID; + input USERCLK; + input USERCLK2; + input USERCLKEN; + input [31:0] USERSPAREIN; +endmodule + module EMAC (...); parameter EMAC0_MODE = "RGMII"; parameter EMAC1_MODE = "RGMII"; @@ -25063,6 +27353,3069 @@ module CMACE4 (...); input TX_SOPIN3; endmodule +module MCB (...); + parameter integer ARB_NUM_TIME_SLOTS = 12; + parameter [17:0] ARB_TIME_SLOT_0 = 18'b111111111111111111; + parameter [17:0] ARB_TIME_SLOT_1 = 18'b111111111111111111; + parameter [17:0] ARB_TIME_SLOT_10 = 18'b111111111111111111; + parameter [17:0] ARB_TIME_SLOT_11 = 18'b111111111111111111; + parameter [17:0] ARB_TIME_SLOT_2 = 18'b111111111111111111; + parameter [17:0] ARB_TIME_SLOT_3 = 18'b111111111111111111; + parameter [17:0] ARB_TIME_SLOT_4 = 18'b111111111111111111; + parameter [17:0] ARB_TIME_SLOT_5 = 18'b111111111111111111; + parameter [17:0] ARB_TIME_SLOT_6 = 18'b111111111111111111; + parameter [17:0] ARB_TIME_SLOT_7 = 18'b111111111111111111; + parameter [17:0] ARB_TIME_SLOT_8 = 18'b111111111111111111; + parameter [17:0] ARB_TIME_SLOT_9 = 18'b111111111111111111; + parameter [2:0] CAL_BA = 3'h0; + parameter CAL_BYPASS = "YES"; + parameter [11:0] CAL_CA = 12'h000; + parameter CAL_CALIBRATION_MODE = "NOCALIBRATION"; + parameter integer CAL_CLK_DIV = 1; + parameter CAL_DELAY = "QUARTER"; + parameter [14:0] CAL_RA = 15'h0000; + parameter MEM_ADDR_ORDER = "BANK_ROW_COLUMN"; + parameter integer MEM_BA_SIZE = 3; + parameter integer MEM_BURST_LEN = 8; + parameter integer MEM_CAS_LATENCY = 4; + parameter integer MEM_CA_SIZE = 11; + parameter MEM_DDR1_2_ODS = "FULL"; + parameter MEM_DDR2_3_HIGH_TEMP_SR = "NORMAL"; + parameter MEM_DDR2_3_PA_SR = "FULL"; + parameter integer MEM_DDR2_ADD_LATENCY = 0; + parameter MEM_DDR2_DIFF_DQS_EN = "YES"; + parameter MEM_DDR2_RTT = "50OHMS"; + parameter integer MEM_DDR2_WRT_RECOVERY = 4; + parameter MEM_DDR3_ADD_LATENCY = "OFF"; + parameter MEM_DDR3_AUTO_SR = "ENABLED"; + parameter integer MEM_DDR3_CAS_LATENCY = 7; + parameter integer MEM_DDR3_CAS_WR_LATENCY = 5; + parameter MEM_DDR3_DYN_WRT_ODT = "OFF"; + parameter MEM_DDR3_ODS = "DIV7"; + parameter MEM_DDR3_RTT = "DIV2"; + parameter integer MEM_DDR3_WRT_RECOVERY = 7; + parameter MEM_MDDR_ODS = "FULL"; + parameter MEM_MOBILE_PA_SR = "FULL"; + parameter integer MEM_MOBILE_TC_SR = 0; + parameter integer MEM_RAS_VAL = 0; + parameter integer MEM_RA_SIZE = 13; + parameter integer MEM_RCD_VAL = 1; + parameter integer MEM_REFI_VAL = 0; + parameter integer MEM_RFC_VAL = 0; + parameter integer MEM_RP_VAL = 0; + parameter integer MEM_RTP_VAL = 0; + parameter MEM_TYPE = "DDR3"; + parameter integer MEM_WIDTH = 4; + parameter integer MEM_WR_VAL = 0; + parameter integer MEM_WTR_VAL = 3; + parameter PORT_CONFIG = "B32_B32_B32_B32"; + output CAS; + output CKE; + output DQIOWEN0; + output DQSIOWEN90N; + output DQSIOWEN90P; + output IOIDRPADD; + output IOIDRPBROADCAST; + output IOIDRPCLK; + output IOIDRPCS; + output IOIDRPSDO; + output IOIDRPTRAIN; + output IOIDRPUPDATE; + output LDMN; + output LDMP; + output ODT; + output P0CMDEMPTY; + output P0CMDFULL; + output P0RDEMPTY; + output P0RDERROR; + output P0RDFULL; + output P0RDOVERFLOW; + output P0WREMPTY; + output P0WRERROR; + output P0WRFULL; + output P0WRUNDERRUN; + output P1CMDEMPTY; + output P1CMDFULL; + output P1RDEMPTY; + output P1RDERROR; + output P1RDFULL; + output P1RDOVERFLOW; + output P1WREMPTY; + output P1WRERROR; + output P1WRFULL; + output P1WRUNDERRUN; + output P2CMDEMPTY; + output P2CMDFULL; + output P2EMPTY; + output P2ERROR; + output P2FULL; + output P2RDOVERFLOW; + output P2WRUNDERRUN; + output P3CMDEMPTY; + output P3CMDFULL; + output P3EMPTY; + output P3ERROR; + output P3FULL; + output P3RDOVERFLOW; + output P3WRUNDERRUN; + output P4CMDEMPTY; + output P4CMDFULL; + output P4EMPTY; + output P4ERROR; + output P4FULL; + output P4RDOVERFLOW; + output P4WRUNDERRUN; + output P5CMDEMPTY; + output P5CMDFULL; + output P5EMPTY; + output P5ERROR; + output P5FULL; + output P5RDOVERFLOW; + output P5WRUNDERRUN; + output RAS; + output RST; + output SELFREFRESHMODE; + output UDMN; + output UDMP; + output UOCALSTART; + output UOCMDREADYIN; + output UODATAVALID; + output UODONECAL; + output UOREFRSHFLAG; + output UOSDO; + output WE; + output [14:0] ADDR; + output [15:0] DQON; + output [15:0] DQOP; + output [2:0] BA; + output [31:0] P0RDDATA; + output [31:0] P1RDDATA; + output [31:0] P2RDDATA; + output [31:0] P3RDDATA; + output [31:0] P4RDDATA; + output [31:0] P5RDDATA; + output [31:0] STATUS; + output [4:0] IOIDRPADDR; + output [6:0] P0RDCOUNT; + output [6:0] P0WRCOUNT; + output [6:0] P1RDCOUNT; + output [6:0] P1WRCOUNT; + output [6:0] P2COUNT; + output [6:0] P3COUNT; + output [6:0] P4COUNT; + output [6:0] P5COUNT; + output [7:0] UODATA; + input DQSIOIN; + input DQSIOIP; + input IOIDRPSDI; + input P0ARBEN; + input P0CMDCLK; + input P0CMDEN; + input P0RDCLK; + input P0RDEN; + input P0WRCLK; + input P0WREN; + input P1ARBEN; + input P1CMDCLK; + input P1CMDEN; + input P1RDCLK; + input P1RDEN; + input P1WRCLK; + input P1WREN; + input P2ARBEN; + input P2CLK; + input P2CMDCLK; + input P2CMDEN; + input P2EN; + input P3ARBEN; + input P3CLK; + input P3CMDCLK; + input P3CMDEN; + input P3EN; + input P4ARBEN; + input P4CLK; + input P4CMDCLK; + input P4CMDEN; + input P4EN; + input P5ARBEN; + input P5CLK; + input P5CMDCLK; + input P5CMDEN; + input P5EN; + input PLLLOCK; + input RECAL; + input SELFREFRESHENTER; + input SYSRST; + input UDQSIOIN; + input UDQSIOIP; + input UIADD; + input UIBROADCAST; + input UICLK; + input UICMD; + input UICMDEN; + input UICMDIN; + input UICS; + input UIDONECAL; + input UIDQLOWERDEC; + input UIDQLOWERINC; + input UIDQUPPERDEC; + input UIDQUPPERINC; + input UIDRPUPDATE; + input UILDQSDEC; + input UILDQSINC; + input UIREAD; + input UISDI; + input UIUDQSDEC; + input UIUDQSINC; + input [11:0] P0CMDCA; + input [11:0] P1CMDCA; + input [11:0] P2CMDCA; + input [11:0] P3CMDCA; + input [11:0] P4CMDCA; + input [11:0] P5CMDCA; + input [14:0] P0CMDRA; + input [14:0] P1CMDRA; + input [14:0] P2CMDRA; + input [14:0] P3CMDRA; + input [14:0] P4CMDRA; + input [14:0] P5CMDRA; + input [15:0] DQI; + input [1:0] PLLCE; + input [1:0] PLLCLK; + input [2:0] P0CMDBA; + input [2:0] P0CMDINSTR; + input [2:0] P1CMDBA; + input [2:0] P1CMDINSTR; + input [2:0] P2CMDBA; + input [2:0] P2CMDINSTR; + input [2:0] P3CMDBA; + input [2:0] P3CMDINSTR; + input [2:0] P4CMDBA; + input [2:0] P4CMDINSTR; + input [2:0] P5CMDBA; + input [2:0] P5CMDINSTR; + input [31:0] P0WRDATA; + input [31:0] P1WRDATA; + input [31:0] P2WRDATA; + input [31:0] P3WRDATA; + input [31:0] P4WRDATA; + input [31:0] P5WRDATA; + input [3:0] P0RWRMASK; + input [3:0] P1RWRMASK; + input [3:0] P2WRMASK; + input [3:0] P3WRMASK; + input [3:0] P4WRMASK; + input [3:0] P5WRMASK; + input [3:0] UIDQCOUNT; + input [4:0] UIADDR; + input [5:0] P0CMDBL; + input [5:0] P1CMDBL; + input [5:0] P2CMDBL; + input [5:0] P3CMDBL; + input [5:0] P4CMDBL; + input [5:0] P5CMDBL; +endmodule + +(* keep *) +module HBM_REF_CLK (...); + input REF_CLK; +endmodule + +(* keep *) +module HBM_SNGLBLI_INTF_APB (...); + parameter CLK_SEL = "FALSE"; + parameter [0:0] IS_PCLK_INVERTED = 1'b0; + parameter [0:0] IS_PRESET_N_INVERTED = 1'b0; + parameter MC_ENABLE = "FALSE"; + parameter PHY_ENABLE = "FALSE"; + parameter PHY_PCLK_INVERT = "FALSE"; + parameter SWITCH_ENABLE = "FALSE"; + output CATTRIP_PIPE; + output [31:0] PRDATA_PIPE; + output PREADY_PIPE; + output PSLVERR_PIPE; + output [2:0] TEMP_PIPE; + input [21:0] PADDR; + (* invertible_pin = "IS_PCLK_INVERTED" *) + input PCLK; + input PENABLE; + (* invertible_pin = "IS_PRESET_N_INVERTED" *) + input PRESET_N; + input PSEL; + input [31:0] PWDATA; + input PWRITE; +endmodule + +(* keep *) +module HBM_SNGLBLI_INTF_AXI (...); + parameter CLK_SEL = "FALSE"; + parameter integer DATARATE = 1800; + parameter [0:0] IS_ACLK_INVERTED = 1'b0; + parameter [0:0] IS_ARESET_N_INVERTED = 1'b0; + parameter MC_ENABLE = "FALSE"; + parameter integer PAGEHIT_PERCENT = 75; + parameter PHY_ENABLE = "FALSE"; + parameter integer READ_PERCENT = 50; + parameter SWITCH_ENABLE = "FALSE"; + parameter integer WRITE_PERCENT = 50; + output ARREADY_PIPE; + output AWREADY_PIPE; + output [5:0] BID_PIPE; + output [1:0] BRESP_PIPE; + output BVALID_PIPE; + output [1:0] DFI_AW_AERR_N_PIPE; + output DFI_CLK_BUF; + output DFI_CTRLUPD_ACK_PIPE; + output [7:0] DFI_DBI_BYTE_DISABLE_PIPE; + output [20:0] DFI_DW_RDDATA_DBI_PIPE; + output [7:0] DFI_DW_RDDATA_DERR_PIPE; + output [1:0] DFI_DW_RDDATA_PAR_VALID_PIPE; + output [1:0] DFI_DW_RDDATA_VALID_PIPE; + output DFI_INIT_COMPLETE_PIPE; + output DFI_PHYUPD_REQ_PIPE; + output DFI_PHYUPD_TYPE_PIPE; + output DFI_PHY_LP_STATE_PIPE; + output DFI_RST_N_BUF; + output [5:0] MC_STATUS; + output [7:0] PHY_STATUS; + output [31:0] RDATA_PARITY_PIPE; + output [255:0] RDATA_PIPE; + output [5:0] RID_PIPE; + output RLAST_PIPE; + output [1:0] RRESP_PIPE; + output RVALID_PIPE; + output [5:0] STATUS; + output WREADY_PIPE; + (* invertible_pin = "IS_ACLK_INVERTED" *) + input ACLK; + input [36:0] ARADDR; + input [1:0] ARBURST; + (* invertible_pin = "IS_ARESET_N_INVERTED" *) + input ARESET_N; + input [5:0] ARID; + input [3:0] ARLEN; + input [2:0] ARSIZE; + input ARVALID; + input [36:0] AWADDR; + input [1:0] AWBURST; + input [5:0] AWID; + input [3:0] AWLEN; + input [2:0] AWSIZE; + input AWVALID; + input BREADY; + input BSCAN_CK; + input DFI_LP_PWR_X_REQ; + input MBIST_EN; + input RREADY; + input [255:0] WDATA; + input [31:0] WDATA_PARITY; + input WLAST; + input [31:0] WSTRB; + input WVALID; +endmodule + +(* keep *) +module HBM_ONE_STACK_INTF (...); + parameter CLK_SEL_00 = "FALSE"; + parameter CLK_SEL_01 = "FALSE"; + parameter CLK_SEL_02 = "FALSE"; + parameter CLK_SEL_03 = "FALSE"; + parameter CLK_SEL_04 = "FALSE"; + parameter CLK_SEL_05 = "FALSE"; + parameter CLK_SEL_06 = "FALSE"; + parameter CLK_SEL_07 = "FALSE"; + parameter CLK_SEL_08 = "FALSE"; + parameter CLK_SEL_09 = "FALSE"; + parameter CLK_SEL_10 = "FALSE"; + parameter CLK_SEL_11 = "FALSE"; + parameter CLK_SEL_12 = "FALSE"; + parameter CLK_SEL_13 = "FALSE"; + parameter CLK_SEL_14 = "FALSE"; + parameter CLK_SEL_15 = "FALSE"; + parameter integer DATARATE_00 = 1800; + parameter integer DATARATE_01 = 1800; + parameter integer DATARATE_02 = 1800; + parameter integer DATARATE_03 = 1800; + parameter integer DATARATE_04 = 1800; + parameter integer DATARATE_05 = 1800; + parameter integer DATARATE_06 = 1800; + parameter integer DATARATE_07 = 1800; + parameter DA_LOCKOUT = "FALSE"; + parameter [0:0] IS_APB_0_PCLK_INVERTED = 1'b0; + parameter [0:0] IS_APB_0_PRESET_N_INVERTED = 1'b0; + parameter [0:0] IS_AXI_00_ACLK_INVERTED = 1'b0; + parameter [0:0] IS_AXI_00_ARESET_N_INVERTED = 1'b0; + parameter [0:0] IS_AXI_01_ACLK_INVERTED = 1'b0; + parameter [0:0] IS_AXI_01_ARESET_N_INVERTED = 1'b0; + parameter [0:0] IS_AXI_02_ACLK_INVERTED = 1'b0; + parameter [0:0] IS_AXI_02_ARESET_N_INVERTED = 1'b0; + parameter [0:0] IS_AXI_03_ACLK_INVERTED = 1'b0; + parameter [0:0] IS_AXI_03_ARESET_N_INVERTED = 1'b0; + parameter [0:0] IS_AXI_04_ACLK_INVERTED = 1'b0; + parameter [0:0] IS_AXI_04_ARESET_N_INVERTED = 1'b0; + parameter [0:0] IS_AXI_05_ACLK_INVERTED = 1'b0; + parameter [0:0] IS_AXI_05_ARESET_N_INVERTED = 1'b0; + parameter [0:0] IS_AXI_06_ACLK_INVERTED = 1'b0; + parameter [0:0] IS_AXI_06_ARESET_N_INVERTED = 1'b0; + parameter [0:0] IS_AXI_07_ACLK_INVERTED = 1'b0; + parameter [0:0] IS_AXI_07_ARESET_N_INVERTED = 1'b0; + parameter [0:0] IS_AXI_08_ACLK_INVERTED = 1'b0; + parameter [0:0] IS_AXI_08_ARESET_N_INVERTED = 1'b0; + parameter [0:0] IS_AXI_09_ACLK_INVERTED = 1'b0; + parameter [0:0] IS_AXI_09_ARESET_N_INVERTED = 1'b0; + parameter [0:0] IS_AXI_10_ACLK_INVERTED = 1'b0; + parameter [0:0] IS_AXI_10_ARESET_N_INVERTED = 1'b0; + parameter [0:0] IS_AXI_11_ACLK_INVERTED = 1'b0; + parameter [0:0] IS_AXI_11_ARESET_N_INVERTED = 1'b0; + parameter [0:0] IS_AXI_12_ACLK_INVERTED = 1'b0; + parameter [0:0] IS_AXI_12_ARESET_N_INVERTED = 1'b0; + parameter [0:0] IS_AXI_13_ACLK_INVERTED = 1'b0; + parameter [0:0] IS_AXI_13_ARESET_N_INVERTED = 1'b0; + parameter [0:0] IS_AXI_14_ACLK_INVERTED = 1'b0; + parameter [0:0] IS_AXI_14_ARESET_N_INVERTED = 1'b0; + parameter [0:0] IS_AXI_15_ACLK_INVERTED = 1'b0; + parameter [0:0] IS_AXI_15_ARESET_N_INVERTED = 1'b0; + parameter MC_ENABLE_0 = "FALSE"; + parameter MC_ENABLE_1 = "FALSE"; + parameter MC_ENABLE_2 = "FALSE"; + parameter MC_ENABLE_3 = "FALSE"; + parameter MC_ENABLE_4 = "FALSE"; + parameter MC_ENABLE_5 = "FALSE"; + parameter MC_ENABLE_6 = "FALSE"; + parameter MC_ENABLE_7 = "FALSE"; + parameter MC_ENABLE_APB = "FALSE"; + parameter integer PAGEHIT_PERCENT_00 = 75; + parameter PHY_ENABLE_00 = "FALSE"; + parameter PHY_ENABLE_01 = "FALSE"; + parameter PHY_ENABLE_02 = "FALSE"; + parameter PHY_ENABLE_03 = "FALSE"; + parameter PHY_ENABLE_04 = "FALSE"; + parameter PHY_ENABLE_05 = "FALSE"; + parameter PHY_ENABLE_06 = "FALSE"; + parameter PHY_ENABLE_07 = "FALSE"; + parameter PHY_ENABLE_08 = "FALSE"; + parameter PHY_ENABLE_09 = "FALSE"; + parameter PHY_ENABLE_10 = "FALSE"; + parameter PHY_ENABLE_11 = "FALSE"; + parameter PHY_ENABLE_12 = "FALSE"; + parameter PHY_ENABLE_13 = "FALSE"; + parameter PHY_ENABLE_14 = "FALSE"; + parameter PHY_ENABLE_15 = "FALSE"; + parameter PHY_ENABLE_APB = "FALSE"; + parameter PHY_PCLK_INVERT_01 = "FALSE"; + parameter integer READ_PERCENT_00 = 50; + parameter integer READ_PERCENT_01 = 50; + parameter integer READ_PERCENT_02 = 50; + parameter integer READ_PERCENT_03 = 50; + parameter integer READ_PERCENT_04 = 50; + parameter integer READ_PERCENT_05 = 50; + parameter integer READ_PERCENT_06 = 50; + parameter integer READ_PERCENT_07 = 50; + parameter integer READ_PERCENT_08 = 50; + parameter integer READ_PERCENT_09 = 50; + parameter integer READ_PERCENT_10 = 50; + parameter integer READ_PERCENT_11 = 50; + parameter integer READ_PERCENT_12 = 50; + parameter integer READ_PERCENT_13 = 50; + parameter integer READ_PERCENT_14 = 50; + parameter integer READ_PERCENT_15 = 50; + parameter SIM_DEVICE = "ULTRASCALE_PLUS"; + parameter integer STACK_LOCATION = 0; + parameter SWITCH_ENABLE = "FALSE"; + parameter integer WRITE_PERCENT_00 = 50; + parameter integer WRITE_PERCENT_01 = 50; + parameter integer WRITE_PERCENT_02 = 50; + parameter integer WRITE_PERCENT_03 = 50; + parameter integer WRITE_PERCENT_04 = 50; + parameter integer WRITE_PERCENT_05 = 50; + parameter integer WRITE_PERCENT_06 = 50; + parameter integer WRITE_PERCENT_07 = 50; + parameter integer WRITE_PERCENT_08 = 50; + parameter integer WRITE_PERCENT_09 = 50; + parameter integer WRITE_PERCENT_10 = 50; + parameter integer WRITE_PERCENT_11 = 50; + parameter integer WRITE_PERCENT_12 = 50; + parameter integer WRITE_PERCENT_13 = 50; + parameter integer WRITE_PERCENT_14 = 50; + parameter integer WRITE_PERCENT_15 = 50; + output [31:0] APB_0_PRDATA; + output APB_0_PREADY; + output APB_0_PSLVERR; + output AXI_00_ARREADY; + output AXI_00_AWREADY; + output [5:0] AXI_00_BID; + output [1:0] AXI_00_BRESP; + output AXI_00_BVALID; + output [1:0] AXI_00_DFI_AW_AERR_N; + output AXI_00_DFI_CLK_BUF; + output [7:0] AXI_00_DFI_DBI_BYTE_DISABLE; + output [20:0] AXI_00_DFI_DW_RDDATA_DBI; + output [7:0] AXI_00_DFI_DW_RDDATA_DERR; + output [1:0] AXI_00_DFI_DW_RDDATA_VALID; + output AXI_00_DFI_INIT_COMPLETE; + output AXI_00_DFI_PHYUPD_REQ; + output AXI_00_DFI_PHY_LP_STATE; + output AXI_00_DFI_RST_N_BUF; + output [5:0] AXI_00_MC_STATUS; + output [7:0] AXI_00_PHY_STATUS; + output [255:0] AXI_00_RDATA; + output [31:0] AXI_00_RDATA_PARITY; + output [5:0] AXI_00_RID; + output AXI_00_RLAST; + output [1:0] AXI_00_RRESP; + output AXI_00_RVALID; + output AXI_00_WREADY; + output AXI_01_ARREADY; + output AXI_01_AWREADY; + output [5:0] AXI_01_BID; + output [1:0] AXI_01_BRESP; + output AXI_01_BVALID; + output [1:0] AXI_01_DFI_AW_AERR_N; + output AXI_01_DFI_CLK_BUF; + output [7:0] AXI_01_DFI_DBI_BYTE_DISABLE; + output [20:0] AXI_01_DFI_DW_RDDATA_DBI; + output [7:0] AXI_01_DFI_DW_RDDATA_DERR; + output [1:0] AXI_01_DFI_DW_RDDATA_VALID; + output AXI_01_DFI_INIT_COMPLETE; + output AXI_01_DFI_PHYUPD_REQ; + output AXI_01_DFI_PHY_LP_STATE; + output AXI_01_DFI_RST_N_BUF; + output [255:0] AXI_01_RDATA; + output [31:0] AXI_01_RDATA_PARITY; + output [5:0] AXI_01_RID; + output AXI_01_RLAST; + output [1:0] AXI_01_RRESP; + output AXI_01_RVALID; + output AXI_01_WREADY; + output AXI_02_ARREADY; + output AXI_02_AWREADY; + output [5:0] AXI_02_BID; + output [1:0] AXI_02_BRESP; + output AXI_02_BVALID; + output [1:0] AXI_02_DFI_AW_AERR_N; + output AXI_02_DFI_CLK_BUF; + output [7:0] AXI_02_DFI_DBI_BYTE_DISABLE; + output [20:0] AXI_02_DFI_DW_RDDATA_DBI; + output [7:0] AXI_02_DFI_DW_RDDATA_DERR; + output [1:0] AXI_02_DFI_DW_RDDATA_VALID; + output AXI_02_DFI_INIT_COMPLETE; + output AXI_02_DFI_PHYUPD_REQ; + output AXI_02_DFI_PHY_LP_STATE; + output AXI_02_DFI_RST_N_BUF; + output [5:0] AXI_02_MC_STATUS; + output [7:0] AXI_02_PHY_STATUS; + output [255:0] AXI_02_RDATA; + output [31:0] AXI_02_RDATA_PARITY; + output [5:0] AXI_02_RID; + output AXI_02_RLAST; + output [1:0] AXI_02_RRESP; + output AXI_02_RVALID; + output AXI_02_WREADY; + output AXI_03_ARREADY; + output AXI_03_AWREADY; + output [5:0] AXI_03_BID; + output [1:0] AXI_03_BRESP; + output AXI_03_BVALID; + output [1:0] AXI_03_DFI_AW_AERR_N; + output AXI_03_DFI_CLK_BUF; + output [7:0] AXI_03_DFI_DBI_BYTE_DISABLE; + output [20:0] AXI_03_DFI_DW_RDDATA_DBI; + output [7:0] AXI_03_DFI_DW_RDDATA_DERR; + output [1:0] AXI_03_DFI_DW_RDDATA_VALID; + output AXI_03_DFI_INIT_COMPLETE; + output AXI_03_DFI_PHYUPD_REQ; + output AXI_03_DFI_PHY_LP_STATE; + output AXI_03_DFI_RST_N_BUF; + output [255:0] AXI_03_RDATA; + output [31:0] AXI_03_RDATA_PARITY; + output [5:0] AXI_03_RID; + output AXI_03_RLAST; + output [1:0] AXI_03_RRESP; + output AXI_03_RVALID; + output AXI_03_WREADY; + output AXI_04_ARREADY; + output AXI_04_AWREADY; + output [5:0] AXI_04_BID; + output [1:0] AXI_04_BRESP; + output AXI_04_BVALID; + output [1:0] AXI_04_DFI_AW_AERR_N; + output AXI_04_DFI_CLK_BUF; + output [7:0] AXI_04_DFI_DBI_BYTE_DISABLE; + output [20:0] AXI_04_DFI_DW_RDDATA_DBI; + output [7:0] AXI_04_DFI_DW_RDDATA_DERR; + output [1:0] AXI_04_DFI_DW_RDDATA_VALID; + output AXI_04_DFI_INIT_COMPLETE; + output AXI_04_DFI_PHYUPD_REQ; + output AXI_04_DFI_PHY_LP_STATE; + output AXI_04_DFI_RST_N_BUF; + output [5:0] AXI_04_MC_STATUS; + output [7:0] AXI_04_PHY_STATUS; + output [255:0] AXI_04_RDATA; + output [31:0] AXI_04_RDATA_PARITY; + output [5:0] AXI_04_RID; + output AXI_04_RLAST; + output [1:0] AXI_04_RRESP; + output AXI_04_RVALID; + output AXI_04_WREADY; + output AXI_05_ARREADY; + output AXI_05_AWREADY; + output [5:0] AXI_05_BID; + output [1:0] AXI_05_BRESP; + output AXI_05_BVALID; + output [1:0] AXI_05_DFI_AW_AERR_N; + output AXI_05_DFI_CLK_BUF; + output [7:0] AXI_05_DFI_DBI_BYTE_DISABLE; + output [20:0] AXI_05_DFI_DW_RDDATA_DBI; + output [7:0] AXI_05_DFI_DW_RDDATA_DERR; + output [1:0] AXI_05_DFI_DW_RDDATA_VALID; + output AXI_05_DFI_INIT_COMPLETE; + output AXI_05_DFI_PHYUPD_REQ; + output AXI_05_DFI_PHY_LP_STATE; + output AXI_05_DFI_RST_N_BUF; + output [255:0] AXI_05_RDATA; + output [31:0] AXI_05_RDATA_PARITY; + output [5:0] AXI_05_RID; + output AXI_05_RLAST; + output [1:0] AXI_05_RRESP; + output AXI_05_RVALID; + output AXI_05_WREADY; + output AXI_06_ARREADY; + output AXI_06_AWREADY; + output [5:0] AXI_06_BID; + output [1:0] AXI_06_BRESP; + output AXI_06_BVALID; + output [1:0] AXI_06_DFI_AW_AERR_N; + output AXI_06_DFI_CLK_BUF; + output [7:0] AXI_06_DFI_DBI_BYTE_DISABLE; + output [20:0] AXI_06_DFI_DW_RDDATA_DBI; + output [7:0] AXI_06_DFI_DW_RDDATA_DERR; + output [1:0] AXI_06_DFI_DW_RDDATA_VALID; + output AXI_06_DFI_INIT_COMPLETE; + output AXI_06_DFI_PHYUPD_REQ; + output AXI_06_DFI_PHY_LP_STATE; + output AXI_06_DFI_RST_N_BUF; + output [5:0] AXI_06_MC_STATUS; + output [7:0] AXI_06_PHY_STATUS; + output [255:0] AXI_06_RDATA; + output [31:0] AXI_06_RDATA_PARITY; + output [5:0] AXI_06_RID; + output AXI_06_RLAST; + output [1:0] AXI_06_RRESP; + output AXI_06_RVALID; + output AXI_06_WREADY; + output AXI_07_ARREADY; + output AXI_07_AWREADY; + output [5:0] AXI_07_BID; + output [1:0] AXI_07_BRESP; + output AXI_07_BVALID; + output [1:0] AXI_07_DFI_AW_AERR_N; + output AXI_07_DFI_CLK_BUF; + output [7:0] AXI_07_DFI_DBI_BYTE_DISABLE; + output [20:0] AXI_07_DFI_DW_RDDATA_DBI; + output [7:0] AXI_07_DFI_DW_RDDATA_DERR; + output [1:0] AXI_07_DFI_DW_RDDATA_VALID; + output AXI_07_DFI_INIT_COMPLETE; + output AXI_07_DFI_PHYUPD_REQ; + output AXI_07_DFI_PHY_LP_STATE; + output AXI_07_DFI_RST_N_BUF; + output [255:0] AXI_07_RDATA; + output [31:0] AXI_07_RDATA_PARITY; + output [5:0] AXI_07_RID; + output AXI_07_RLAST; + output [1:0] AXI_07_RRESP; + output AXI_07_RVALID; + output AXI_07_WREADY; + output AXI_08_ARREADY; + output AXI_08_AWREADY; + output [5:0] AXI_08_BID; + output [1:0] AXI_08_BRESP; + output AXI_08_BVALID; + output [1:0] AXI_08_DFI_AW_AERR_N; + output AXI_08_DFI_CLK_BUF; + output [7:0] AXI_08_DFI_DBI_BYTE_DISABLE; + output [20:0] AXI_08_DFI_DW_RDDATA_DBI; + output [7:0] AXI_08_DFI_DW_RDDATA_DERR; + output [1:0] AXI_08_DFI_DW_RDDATA_VALID; + output AXI_08_DFI_INIT_COMPLETE; + output AXI_08_DFI_PHYUPD_REQ; + output AXI_08_DFI_PHY_LP_STATE; + output AXI_08_DFI_RST_N_BUF; + output [5:0] AXI_08_MC_STATUS; + output [7:0] AXI_08_PHY_STATUS; + output [255:0] AXI_08_RDATA; + output [31:0] AXI_08_RDATA_PARITY; + output [5:0] AXI_08_RID; + output AXI_08_RLAST; + output [1:0] AXI_08_RRESP; + output AXI_08_RVALID; + output AXI_08_WREADY; + output AXI_09_ARREADY; + output AXI_09_AWREADY; + output [5:0] AXI_09_BID; + output [1:0] AXI_09_BRESP; + output AXI_09_BVALID; + output [1:0] AXI_09_DFI_AW_AERR_N; + output AXI_09_DFI_CLK_BUF; + output [7:0] AXI_09_DFI_DBI_BYTE_DISABLE; + output [20:0] AXI_09_DFI_DW_RDDATA_DBI; + output [7:0] AXI_09_DFI_DW_RDDATA_DERR; + output [1:0] AXI_09_DFI_DW_RDDATA_VALID; + output AXI_09_DFI_INIT_COMPLETE; + output AXI_09_DFI_PHYUPD_REQ; + output AXI_09_DFI_PHY_LP_STATE; + output AXI_09_DFI_RST_N_BUF; + output [255:0] AXI_09_RDATA; + output [31:0] AXI_09_RDATA_PARITY; + output [5:0] AXI_09_RID; + output AXI_09_RLAST; + output [1:0] AXI_09_RRESP; + output AXI_09_RVALID; + output AXI_09_WREADY; + output AXI_10_ARREADY; + output AXI_10_AWREADY; + output [5:0] AXI_10_BID; + output [1:0] AXI_10_BRESP; + output AXI_10_BVALID; + output [1:0] AXI_10_DFI_AW_AERR_N; + output AXI_10_DFI_CLK_BUF; + output [7:0] AXI_10_DFI_DBI_BYTE_DISABLE; + output [20:0] AXI_10_DFI_DW_RDDATA_DBI; + output [7:0] AXI_10_DFI_DW_RDDATA_DERR; + output [1:0] AXI_10_DFI_DW_RDDATA_VALID; + output AXI_10_DFI_INIT_COMPLETE; + output AXI_10_DFI_PHYUPD_REQ; + output AXI_10_DFI_PHY_LP_STATE; + output AXI_10_DFI_RST_N_BUF; + output [5:0] AXI_10_MC_STATUS; + output [7:0] AXI_10_PHY_STATUS; + output [255:0] AXI_10_RDATA; + output [31:0] AXI_10_RDATA_PARITY; + output [5:0] AXI_10_RID; + output AXI_10_RLAST; + output [1:0] AXI_10_RRESP; + output AXI_10_RVALID; + output AXI_10_WREADY; + output AXI_11_ARREADY; + output AXI_11_AWREADY; + output [5:0] AXI_11_BID; + output [1:0] AXI_11_BRESP; + output AXI_11_BVALID; + output [1:0] AXI_11_DFI_AW_AERR_N; + output AXI_11_DFI_CLK_BUF; + output [7:0] AXI_11_DFI_DBI_BYTE_DISABLE; + output [20:0] AXI_11_DFI_DW_RDDATA_DBI; + output [7:0] AXI_11_DFI_DW_RDDATA_DERR; + output [1:0] AXI_11_DFI_DW_RDDATA_VALID; + output AXI_11_DFI_INIT_COMPLETE; + output AXI_11_DFI_PHYUPD_REQ; + output AXI_11_DFI_PHY_LP_STATE; + output AXI_11_DFI_RST_N_BUF; + output [255:0] AXI_11_RDATA; + output [31:0] AXI_11_RDATA_PARITY; + output [5:0] AXI_11_RID; + output AXI_11_RLAST; + output [1:0] AXI_11_RRESP; + output AXI_11_RVALID; + output AXI_11_WREADY; + output AXI_12_ARREADY; + output AXI_12_AWREADY; + output [5:0] AXI_12_BID; + output [1:0] AXI_12_BRESP; + output AXI_12_BVALID; + output [1:0] AXI_12_DFI_AW_AERR_N; + output AXI_12_DFI_CLK_BUF; + output [7:0] AXI_12_DFI_DBI_BYTE_DISABLE; + output [20:0] AXI_12_DFI_DW_RDDATA_DBI; + output [7:0] AXI_12_DFI_DW_RDDATA_DERR; + output [1:0] AXI_12_DFI_DW_RDDATA_VALID; + output AXI_12_DFI_INIT_COMPLETE; + output AXI_12_DFI_PHYUPD_REQ; + output AXI_12_DFI_PHY_LP_STATE; + output AXI_12_DFI_RST_N_BUF; + output [5:0] AXI_12_MC_STATUS; + output [7:0] AXI_12_PHY_STATUS; + output [255:0] AXI_12_RDATA; + output [31:0] AXI_12_RDATA_PARITY; + output [5:0] AXI_12_RID; + output AXI_12_RLAST; + output [1:0] AXI_12_RRESP; + output AXI_12_RVALID; + output AXI_12_WREADY; + output AXI_13_ARREADY; + output AXI_13_AWREADY; + output [5:0] AXI_13_BID; + output [1:0] AXI_13_BRESP; + output AXI_13_BVALID; + output [1:0] AXI_13_DFI_AW_AERR_N; + output AXI_13_DFI_CLK_BUF; + output [7:0] AXI_13_DFI_DBI_BYTE_DISABLE; + output [20:0] AXI_13_DFI_DW_RDDATA_DBI; + output [7:0] AXI_13_DFI_DW_RDDATA_DERR; + output [1:0] AXI_13_DFI_DW_RDDATA_VALID; + output AXI_13_DFI_INIT_COMPLETE; + output AXI_13_DFI_PHYUPD_REQ; + output AXI_13_DFI_PHY_LP_STATE; + output AXI_13_DFI_RST_N_BUF; + output [255:0] AXI_13_RDATA; + output [31:0] AXI_13_RDATA_PARITY; + output [5:0] AXI_13_RID; + output AXI_13_RLAST; + output [1:0] AXI_13_RRESP; + output AXI_13_RVALID; + output AXI_13_WREADY; + output AXI_14_ARREADY; + output AXI_14_AWREADY; + output [5:0] AXI_14_BID; + output [1:0] AXI_14_BRESP; + output AXI_14_BVALID; + output [1:0] AXI_14_DFI_AW_AERR_N; + output AXI_14_DFI_CLK_BUF; + output [7:0] AXI_14_DFI_DBI_BYTE_DISABLE; + output [20:0] AXI_14_DFI_DW_RDDATA_DBI; + output [7:0] AXI_14_DFI_DW_RDDATA_DERR; + output [1:0] AXI_14_DFI_DW_RDDATA_VALID; + output AXI_14_DFI_INIT_COMPLETE; + output AXI_14_DFI_PHYUPD_REQ; + output AXI_14_DFI_PHY_LP_STATE; + output AXI_14_DFI_RST_N_BUF; + output [5:0] AXI_14_MC_STATUS; + output [7:0] AXI_14_PHY_STATUS; + output [255:0] AXI_14_RDATA; + output [31:0] AXI_14_RDATA_PARITY; + output [5:0] AXI_14_RID; + output AXI_14_RLAST; + output [1:0] AXI_14_RRESP; + output AXI_14_RVALID; + output AXI_14_WREADY; + output AXI_15_ARREADY; + output AXI_15_AWREADY; + output [5:0] AXI_15_BID; + output [1:0] AXI_15_BRESP; + output AXI_15_BVALID; + output [1:0] AXI_15_DFI_AW_AERR_N; + output AXI_15_DFI_CLK_BUF; + output [7:0] AXI_15_DFI_DBI_BYTE_DISABLE; + output [20:0] AXI_15_DFI_DW_RDDATA_DBI; + output [7:0] AXI_15_DFI_DW_RDDATA_DERR; + output [1:0] AXI_15_DFI_DW_RDDATA_VALID; + output AXI_15_DFI_INIT_COMPLETE; + output AXI_15_DFI_PHYUPD_REQ; + output AXI_15_DFI_PHY_LP_STATE; + output AXI_15_DFI_RST_N_BUF; + output [255:0] AXI_15_RDATA; + output [31:0] AXI_15_RDATA_PARITY; + output [5:0] AXI_15_RID; + output AXI_15_RLAST; + output [1:0] AXI_15_RRESP; + output AXI_15_RVALID; + output AXI_15_WREADY; + output DRAM_0_STAT_CATTRIP; + output [2:0] DRAM_0_STAT_TEMP; + input [21:0] APB_0_PADDR; + (* invertible_pin = "IS_APB_0_PCLK_INVERTED" *) + input APB_0_PCLK; + input APB_0_PENABLE; + (* invertible_pin = "IS_APB_0_PRESET_N_INVERTED" *) + input APB_0_PRESET_N; + input APB_0_PSEL; + input [31:0] APB_0_PWDATA; + input APB_0_PWRITE; + (* invertible_pin = "IS_AXI_00_ACLK_INVERTED" *) + input AXI_00_ACLK; + input [36:0] AXI_00_ARADDR; + input [1:0] AXI_00_ARBURST; + (* invertible_pin = "IS_AXI_00_ARESET_N_INVERTED" *) + input AXI_00_ARESET_N; + input [5:0] AXI_00_ARID; + input [3:0] AXI_00_ARLEN; + input [2:0] AXI_00_ARSIZE; + input AXI_00_ARVALID; + input [36:0] AXI_00_AWADDR; + input [1:0] AXI_00_AWBURST; + input [5:0] AXI_00_AWID; + input [3:0] AXI_00_AWLEN; + input [2:0] AXI_00_AWSIZE; + input AXI_00_AWVALID; + input AXI_00_BREADY; + input AXI_00_DFI_LP_PWR_X_REQ; + input AXI_00_RREADY; + input [255:0] AXI_00_WDATA; + input [31:0] AXI_00_WDATA_PARITY; + input AXI_00_WLAST; + input [31:0] AXI_00_WSTRB; + input AXI_00_WVALID; + (* invertible_pin = "IS_AXI_01_ACLK_INVERTED" *) + input AXI_01_ACLK; + input [36:0] AXI_01_ARADDR; + input [1:0] AXI_01_ARBURST; + (* invertible_pin = "IS_AXI_01_ARESET_N_INVERTED" *) + input AXI_01_ARESET_N; + input [5:0] AXI_01_ARID; + input [3:0] AXI_01_ARLEN; + input [2:0] AXI_01_ARSIZE; + input AXI_01_ARVALID; + input [36:0] AXI_01_AWADDR; + input [1:0] AXI_01_AWBURST; + input [5:0] AXI_01_AWID; + input [3:0] AXI_01_AWLEN; + input [2:0] AXI_01_AWSIZE; + input AXI_01_AWVALID; + input AXI_01_BREADY; + input AXI_01_DFI_LP_PWR_X_REQ; + input AXI_01_RREADY; + input [255:0] AXI_01_WDATA; + input [31:0] AXI_01_WDATA_PARITY; + input AXI_01_WLAST; + input [31:0] AXI_01_WSTRB; + input AXI_01_WVALID; + (* invertible_pin = "IS_AXI_02_ACLK_INVERTED" *) + input AXI_02_ACLK; + input [36:0] AXI_02_ARADDR; + input [1:0] AXI_02_ARBURST; + (* invertible_pin = "IS_AXI_02_ARESET_N_INVERTED" *) + input AXI_02_ARESET_N; + input [5:0] AXI_02_ARID; + input [3:0] AXI_02_ARLEN; + input [2:0] AXI_02_ARSIZE; + input AXI_02_ARVALID; + input [36:0] AXI_02_AWADDR; + input [1:0] AXI_02_AWBURST; + input [5:0] AXI_02_AWID; + input [3:0] AXI_02_AWLEN; + input [2:0] AXI_02_AWSIZE; + input AXI_02_AWVALID; + input AXI_02_BREADY; + input AXI_02_DFI_LP_PWR_X_REQ; + input AXI_02_RREADY; + input [255:0] AXI_02_WDATA; + input [31:0] AXI_02_WDATA_PARITY; + input AXI_02_WLAST; + input [31:0] AXI_02_WSTRB; + input AXI_02_WVALID; + (* invertible_pin = "IS_AXI_03_ACLK_INVERTED" *) + input AXI_03_ACLK; + input [36:0] AXI_03_ARADDR; + input [1:0] AXI_03_ARBURST; + (* invertible_pin = "IS_AXI_03_ARESET_N_INVERTED" *) + input AXI_03_ARESET_N; + input [5:0] AXI_03_ARID; + input [3:0] AXI_03_ARLEN; + input [2:0] AXI_03_ARSIZE; + input AXI_03_ARVALID; + input [36:0] AXI_03_AWADDR; + input [1:0] AXI_03_AWBURST; + input [5:0] AXI_03_AWID; + input [3:0] AXI_03_AWLEN; + input [2:0] AXI_03_AWSIZE; + input AXI_03_AWVALID; + input AXI_03_BREADY; + input AXI_03_DFI_LP_PWR_X_REQ; + input AXI_03_RREADY; + input [255:0] AXI_03_WDATA; + input [31:0] AXI_03_WDATA_PARITY; + input AXI_03_WLAST; + input [31:0] AXI_03_WSTRB; + input AXI_03_WVALID; + (* invertible_pin = "IS_AXI_04_ACLK_INVERTED" *) + input AXI_04_ACLK; + input [36:0] AXI_04_ARADDR; + input [1:0] AXI_04_ARBURST; + (* invertible_pin = "IS_AXI_04_ARESET_N_INVERTED" *) + input AXI_04_ARESET_N; + input [5:0] AXI_04_ARID; + input [3:0] AXI_04_ARLEN; + input [2:0] AXI_04_ARSIZE; + input AXI_04_ARVALID; + input [36:0] AXI_04_AWADDR; + input [1:0] AXI_04_AWBURST; + input [5:0] AXI_04_AWID; + input [3:0] AXI_04_AWLEN; + input [2:0] AXI_04_AWSIZE; + input AXI_04_AWVALID; + input AXI_04_BREADY; + input AXI_04_DFI_LP_PWR_X_REQ; + input AXI_04_RREADY; + input [255:0] AXI_04_WDATA; + input [31:0] AXI_04_WDATA_PARITY; + input AXI_04_WLAST; + input [31:0] AXI_04_WSTRB; + input AXI_04_WVALID; + (* invertible_pin = "IS_AXI_05_ACLK_INVERTED" *) + input AXI_05_ACLK; + input [36:0] AXI_05_ARADDR; + input [1:0] AXI_05_ARBURST; + (* invertible_pin = "IS_AXI_05_ARESET_N_INVERTED" *) + input AXI_05_ARESET_N; + input [5:0] AXI_05_ARID; + input [3:0] AXI_05_ARLEN; + input [2:0] AXI_05_ARSIZE; + input AXI_05_ARVALID; + input [36:0] AXI_05_AWADDR; + input [1:0] AXI_05_AWBURST; + input [5:0] AXI_05_AWID; + input [3:0] AXI_05_AWLEN; + input [2:0] AXI_05_AWSIZE; + input AXI_05_AWVALID; + input AXI_05_BREADY; + input AXI_05_DFI_LP_PWR_X_REQ; + input AXI_05_RREADY; + input [255:0] AXI_05_WDATA; + input [31:0] AXI_05_WDATA_PARITY; + input AXI_05_WLAST; + input [31:0] AXI_05_WSTRB; + input AXI_05_WVALID; + (* invertible_pin = "IS_AXI_06_ACLK_INVERTED" *) + input AXI_06_ACLK; + input [36:0] AXI_06_ARADDR; + input [1:0] AXI_06_ARBURST; + (* invertible_pin = "IS_AXI_06_ARESET_N_INVERTED" *) + input AXI_06_ARESET_N; + input [5:0] AXI_06_ARID; + input [3:0] AXI_06_ARLEN; + input [2:0] AXI_06_ARSIZE; + input AXI_06_ARVALID; + input [36:0] AXI_06_AWADDR; + input [1:0] AXI_06_AWBURST; + input [5:0] AXI_06_AWID; + input [3:0] AXI_06_AWLEN; + input [2:0] AXI_06_AWSIZE; + input AXI_06_AWVALID; + input AXI_06_BREADY; + input AXI_06_DFI_LP_PWR_X_REQ; + input AXI_06_RREADY; + input [255:0] AXI_06_WDATA; + input [31:0] AXI_06_WDATA_PARITY; + input AXI_06_WLAST; + input [31:0] AXI_06_WSTRB; + input AXI_06_WVALID; + (* invertible_pin = "IS_AXI_07_ACLK_INVERTED" *) + input AXI_07_ACLK; + input [36:0] AXI_07_ARADDR; + input [1:0] AXI_07_ARBURST; + (* invertible_pin = "IS_AXI_07_ARESET_N_INVERTED" *) + input AXI_07_ARESET_N; + input [5:0] AXI_07_ARID; + input [3:0] AXI_07_ARLEN; + input [2:0] AXI_07_ARSIZE; + input AXI_07_ARVALID; + input [36:0] AXI_07_AWADDR; + input [1:0] AXI_07_AWBURST; + input [5:0] AXI_07_AWID; + input [3:0] AXI_07_AWLEN; + input [2:0] AXI_07_AWSIZE; + input AXI_07_AWVALID; + input AXI_07_BREADY; + input AXI_07_DFI_LP_PWR_X_REQ; + input AXI_07_RREADY; + input [255:0] AXI_07_WDATA; + input [31:0] AXI_07_WDATA_PARITY; + input AXI_07_WLAST; + input [31:0] AXI_07_WSTRB; + input AXI_07_WVALID; + (* invertible_pin = "IS_AXI_08_ACLK_INVERTED" *) + input AXI_08_ACLK; + input [36:0] AXI_08_ARADDR; + input [1:0] AXI_08_ARBURST; + (* invertible_pin = "IS_AXI_08_ARESET_N_INVERTED" *) + input AXI_08_ARESET_N; + input [5:0] AXI_08_ARID; + input [3:0] AXI_08_ARLEN; + input [2:0] AXI_08_ARSIZE; + input AXI_08_ARVALID; + input [36:0] AXI_08_AWADDR; + input [1:0] AXI_08_AWBURST; + input [5:0] AXI_08_AWID; + input [3:0] AXI_08_AWLEN; + input [2:0] AXI_08_AWSIZE; + input AXI_08_AWVALID; + input AXI_08_BREADY; + input AXI_08_DFI_LP_PWR_X_REQ; + input AXI_08_RREADY; + input [255:0] AXI_08_WDATA; + input [31:0] AXI_08_WDATA_PARITY; + input AXI_08_WLAST; + input [31:0] AXI_08_WSTRB; + input AXI_08_WVALID; + (* invertible_pin = "IS_AXI_09_ACLK_INVERTED" *) + input AXI_09_ACLK; + input [36:0] AXI_09_ARADDR; + input [1:0] AXI_09_ARBURST; + (* invertible_pin = "IS_AXI_09_ARESET_N_INVERTED" *) + input AXI_09_ARESET_N; + input [5:0] AXI_09_ARID; + input [3:0] AXI_09_ARLEN; + input [2:0] AXI_09_ARSIZE; + input AXI_09_ARVALID; + input [36:0] AXI_09_AWADDR; + input [1:0] AXI_09_AWBURST; + input [5:0] AXI_09_AWID; + input [3:0] AXI_09_AWLEN; + input [2:0] AXI_09_AWSIZE; + input AXI_09_AWVALID; + input AXI_09_BREADY; + input AXI_09_DFI_LP_PWR_X_REQ; + input AXI_09_RREADY; + input [255:0] AXI_09_WDATA; + input [31:0] AXI_09_WDATA_PARITY; + input AXI_09_WLAST; + input [31:0] AXI_09_WSTRB; + input AXI_09_WVALID; + (* invertible_pin = "IS_AXI_10_ACLK_INVERTED" *) + input AXI_10_ACLK; + input [36:0] AXI_10_ARADDR; + input [1:0] AXI_10_ARBURST; + (* invertible_pin = "IS_AXI_10_ARESET_N_INVERTED" *) + input AXI_10_ARESET_N; + input [5:0] AXI_10_ARID; + input [3:0] AXI_10_ARLEN; + input [2:0] AXI_10_ARSIZE; + input AXI_10_ARVALID; + input [36:0] AXI_10_AWADDR; + input [1:0] AXI_10_AWBURST; + input [5:0] AXI_10_AWID; + input [3:0] AXI_10_AWLEN; + input [2:0] AXI_10_AWSIZE; + input AXI_10_AWVALID; + input AXI_10_BREADY; + input AXI_10_DFI_LP_PWR_X_REQ; + input AXI_10_RREADY; + input [255:0] AXI_10_WDATA; + input [31:0] AXI_10_WDATA_PARITY; + input AXI_10_WLAST; + input [31:0] AXI_10_WSTRB; + input AXI_10_WVALID; + (* invertible_pin = "IS_AXI_11_ACLK_INVERTED" *) + input AXI_11_ACLK; + input [36:0] AXI_11_ARADDR; + input [1:0] AXI_11_ARBURST; + (* invertible_pin = "IS_AXI_11_ARESET_N_INVERTED" *) + input AXI_11_ARESET_N; + input [5:0] AXI_11_ARID; + input [3:0] AXI_11_ARLEN; + input [2:0] AXI_11_ARSIZE; + input AXI_11_ARVALID; + input [36:0] AXI_11_AWADDR; + input [1:0] AXI_11_AWBURST; + input [5:0] AXI_11_AWID; + input [3:0] AXI_11_AWLEN; + input [2:0] AXI_11_AWSIZE; + input AXI_11_AWVALID; + input AXI_11_BREADY; + input AXI_11_DFI_LP_PWR_X_REQ; + input AXI_11_RREADY; + input [255:0] AXI_11_WDATA; + input [31:0] AXI_11_WDATA_PARITY; + input AXI_11_WLAST; + input [31:0] AXI_11_WSTRB; + input AXI_11_WVALID; + (* invertible_pin = "IS_AXI_12_ACLK_INVERTED" *) + input AXI_12_ACLK; + input [36:0] AXI_12_ARADDR; + input [1:0] AXI_12_ARBURST; + (* invertible_pin = "IS_AXI_12_ARESET_N_INVERTED" *) + input AXI_12_ARESET_N; + input [5:0] AXI_12_ARID; + input [3:0] AXI_12_ARLEN; + input [2:0] AXI_12_ARSIZE; + input AXI_12_ARVALID; + input [36:0] AXI_12_AWADDR; + input [1:0] AXI_12_AWBURST; + input [5:0] AXI_12_AWID; + input [3:0] AXI_12_AWLEN; + input [2:0] AXI_12_AWSIZE; + input AXI_12_AWVALID; + input AXI_12_BREADY; + input AXI_12_DFI_LP_PWR_X_REQ; + input AXI_12_RREADY; + input [255:0] AXI_12_WDATA; + input [31:0] AXI_12_WDATA_PARITY; + input AXI_12_WLAST; + input [31:0] AXI_12_WSTRB; + input AXI_12_WVALID; + (* invertible_pin = "IS_AXI_13_ACLK_INVERTED" *) + input AXI_13_ACLK; + input [36:0] AXI_13_ARADDR; + input [1:0] AXI_13_ARBURST; + (* invertible_pin = "IS_AXI_13_ARESET_N_INVERTED" *) + input AXI_13_ARESET_N; + input [5:0] AXI_13_ARID; + input [3:0] AXI_13_ARLEN; + input [2:0] AXI_13_ARSIZE; + input AXI_13_ARVALID; + input [36:0] AXI_13_AWADDR; + input [1:0] AXI_13_AWBURST; + input [5:0] AXI_13_AWID; + input [3:0] AXI_13_AWLEN; + input [2:0] AXI_13_AWSIZE; + input AXI_13_AWVALID; + input AXI_13_BREADY; + input AXI_13_DFI_LP_PWR_X_REQ; + input AXI_13_RREADY; + input [255:0] AXI_13_WDATA; + input [31:0] AXI_13_WDATA_PARITY; + input AXI_13_WLAST; + input [31:0] AXI_13_WSTRB; + input AXI_13_WVALID; + (* invertible_pin = "IS_AXI_14_ACLK_INVERTED" *) + input AXI_14_ACLK; + input [36:0] AXI_14_ARADDR; + input [1:0] AXI_14_ARBURST; + (* invertible_pin = "IS_AXI_14_ARESET_N_INVERTED" *) + input AXI_14_ARESET_N; + input [5:0] AXI_14_ARID; + input [3:0] AXI_14_ARLEN; + input [2:0] AXI_14_ARSIZE; + input AXI_14_ARVALID; + input [36:0] AXI_14_AWADDR; + input [1:0] AXI_14_AWBURST; + input [5:0] AXI_14_AWID; + input [3:0] AXI_14_AWLEN; + input [2:0] AXI_14_AWSIZE; + input AXI_14_AWVALID; + input AXI_14_BREADY; + input AXI_14_DFI_LP_PWR_X_REQ; + input AXI_14_RREADY; + input [255:0] AXI_14_WDATA; + input [31:0] AXI_14_WDATA_PARITY; + input AXI_14_WLAST; + input [31:0] AXI_14_WSTRB; + input AXI_14_WVALID; + (* invertible_pin = "IS_AXI_15_ACLK_INVERTED" *) + input AXI_15_ACLK; + input [36:0] AXI_15_ARADDR; + input [1:0] AXI_15_ARBURST; + (* invertible_pin = "IS_AXI_15_ARESET_N_INVERTED" *) + input AXI_15_ARESET_N; + input [5:0] AXI_15_ARID; + input [3:0] AXI_15_ARLEN; + input [2:0] AXI_15_ARSIZE; + input AXI_15_ARVALID; + input [36:0] AXI_15_AWADDR; + input [1:0] AXI_15_AWBURST; + input [5:0] AXI_15_AWID; + input [3:0] AXI_15_AWLEN; + input [2:0] AXI_15_AWSIZE; + input AXI_15_AWVALID; + input AXI_15_BREADY; + input AXI_15_DFI_LP_PWR_X_REQ; + input AXI_15_RREADY; + input [255:0] AXI_15_WDATA; + input [31:0] AXI_15_WDATA_PARITY; + input AXI_15_WLAST; + input [31:0] AXI_15_WSTRB; + input AXI_15_WVALID; + input BSCAN_DRCK; + input BSCAN_TCK; + input HBM_REF_CLK; + input MBIST_EN_00; + input MBIST_EN_01; + input MBIST_EN_02; + input MBIST_EN_03; + input MBIST_EN_04; + input MBIST_EN_05; + input MBIST_EN_06; + input MBIST_EN_07; +endmodule + +(* keep *) +module HBM_TWO_STACK_INTF (...); + parameter CLK_SEL_00 = "FALSE"; + parameter CLK_SEL_01 = "FALSE"; + parameter CLK_SEL_02 = "FALSE"; + parameter CLK_SEL_03 = "FALSE"; + parameter CLK_SEL_04 = "FALSE"; + parameter CLK_SEL_05 = "FALSE"; + parameter CLK_SEL_06 = "FALSE"; + parameter CLK_SEL_07 = "FALSE"; + parameter CLK_SEL_08 = "FALSE"; + parameter CLK_SEL_09 = "FALSE"; + parameter CLK_SEL_10 = "FALSE"; + parameter CLK_SEL_11 = "FALSE"; + parameter CLK_SEL_12 = "FALSE"; + parameter CLK_SEL_13 = "FALSE"; + parameter CLK_SEL_14 = "FALSE"; + parameter CLK_SEL_15 = "FALSE"; + parameter CLK_SEL_16 = "FALSE"; + parameter CLK_SEL_17 = "FALSE"; + parameter CLK_SEL_18 = "FALSE"; + parameter CLK_SEL_19 = "FALSE"; + parameter CLK_SEL_20 = "FALSE"; + parameter CLK_SEL_21 = "FALSE"; + parameter CLK_SEL_22 = "FALSE"; + parameter CLK_SEL_23 = "FALSE"; + parameter CLK_SEL_24 = "FALSE"; + parameter CLK_SEL_25 = "FALSE"; + parameter CLK_SEL_26 = "FALSE"; + parameter CLK_SEL_27 = "FALSE"; + parameter CLK_SEL_28 = "FALSE"; + parameter CLK_SEL_29 = "FALSE"; + parameter CLK_SEL_30 = "FALSE"; + parameter CLK_SEL_31 = "FALSE"; + parameter integer DATARATE_00 = 1800; + parameter integer DATARATE_01 = 1800; + parameter integer DATARATE_02 = 1800; + parameter integer DATARATE_03 = 1800; + parameter integer DATARATE_04 = 1800; + parameter integer DATARATE_05 = 1800; + parameter integer DATARATE_06 = 1800; + parameter integer DATARATE_07 = 1800; + parameter integer DATARATE_08 = 1800; + parameter integer DATARATE_09 = 1800; + parameter integer DATARATE_10 = 1800; + parameter integer DATARATE_11 = 1800; + parameter integer DATARATE_12 = 1800; + parameter integer DATARATE_13 = 1800; + parameter integer DATARATE_14 = 1800; + parameter integer DATARATE_15 = 1800; + parameter DA_LOCKOUT_0 = "FALSE"; + parameter DA_LOCKOUT_1 = "FALSE"; + parameter [0:0] IS_APB_0_PCLK_INVERTED = 1'b0; + parameter [0:0] IS_APB_0_PRESET_N_INVERTED = 1'b0; + parameter [0:0] IS_APB_1_PCLK_INVERTED = 1'b0; + parameter [0:0] IS_APB_1_PRESET_N_INVERTED = 1'b0; + parameter [0:0] IS_AXI_00_ACLK_INVERTED = 1'b0; + parameter [0:0] IS_AXI_00_ARESET_N_INVERTED = 1'b0; + parameter [0:0] IS_AXI_01_ACLK_INVERTED = 1'b0; + parameter [0:0] IS_AXI_01_ARESET_N_INVERTED = 1'b0; + parameter [0:0] IS_AXI_02_ACLK_INVERTED = 1'b0; + parameter [0:0] IS_AXI_02_ARESET_N_INVERTED = 1'b0; + parameter [0:0] IS_AXI_03_ACLK_INVERTED = 1'b0; + parameter [0:0] IS_AXI_03_ARESET_N_INVERTED = 1'b0; + parameter [0:0] IS_AXI_04_ACLK_INVERTED = 1'b0; + parameter [0:0] IS_AXI_04_ARESET_N_INVERTED = 1'b0; + parameter [0:0] IS_AXI_05_ACLK_INVERTED = 1'b0; + parameter [0:0] IS_AXI_05_ARESET_N_INVERTED = 1'b0; + parameter [0:0] IS_AXI_06_ACLK_INVERTED = 1'b0; + parameter [0:0] IS_AXI_06_ARESET_N_INVERTED = 1'b0; + parameter [0:0] IS_AXI_07_ACLK_INVERTED = 1'b0; + parameter [0:0] IS_AXI_07_ARESET_N_INVERTED = 1'b0; + parameter [0:0] IS_AXI_08_ACLK_INVERTED = 1'b0; + parameter [0:0] IS_AXI_08_ARESET_N_INVERTED = 1'b0; + parameter [0:0] IS_AXI_09_ACLK_INVERTED = 1'b0; + parameter [0:0] IS_AXI_09_ARESET_N_INVERTED = 1'b0; + parameter [0:0] IS_AXI_10_ACLK_INVERTED = 1'b0; + parameter [0:0] IS_AXI_10_ARESET_N_INVERTED = 1'b0; + parameter [0:0] IS_AXI_11_ACLK_INVERTED = 1'b0; + parameter [0:0] IS_AXI_11_ARESET_N_INVERTED = 1'b0; + parameter [0:0] IS_AXI_12_ACLK_INVERTED = 1'b0; + parameter [0:0] IS_AXI_12_ARESET_N_INVERTED = 1'b0; + parameter [0:0] IS_AXI_13_ACLK_INVERTED = 1'b0; + parameter [0:0] IS_AXI_13_ARESET_N_INVERTED = 1'b0; + parameter [0:0] IS_AXI_14_ACLK_INVERTED = 1'b0; + parameter [0:0] IS_AXI_14_ARESET_N_INVERTED = 1'b0; + parameter [0:0] IS_AXI_15_ACLK_INVERTED = 1'b0; + parameter [0:0] IS_AXI_15_ARESET_N_INVERTED = 1'b0; + parameter [0:0] IS_AXI_16_ACLK_INVERTED = 1'b0; + parameter [0:0] IS_AXI_16_ARESET_N_INVERTED = 1'b0; + parameter [0:0] IS_AXI_17_ACLK_INVERTED = 1'b0; + parameter [0:0] IS_AXI_17_ARESET_N_INVERTED = 1'b0; + parameter [0:0] IS_AXI_18_ACLK_INVERTED = 1'b0; + parameter [0:0] IS_AXI_18_ARESET_N_INVERTED = 1'b0; + parameter [0:0] IS_AXI_19_ACLK_INVERTED = 1'b0; + parameter [0:0] IS_AXI_19_ARESET_N_INVERTED = 1'b0; + parameter [0:0] IS_AXI_20_ACLK_INVERTED = 1'b0; + parameter [0:0] IS_AXI_20_ARESET_N_INVERTED = 1'b0; + parameter [0:0] IS_AXI_21_ACLK_INVERTED = 1'b0; + parameter [0:0] IS_AXI_21_ARESET_N_INVERTED = 1'b0; + parameter [0:0] IS_AXI_22_ACLK_INVERTED = 1'b0; + parameter [0:0] IS_AXI_22_ARESET_N_INVERTED = 1'b0; + parameter [0:0] IS_AXI_23_ACLK_INVERTED = 1'b0; + parameter [0:0] IS_AXI_23_ARESET_N_INVERTED = 1'b0; + parameter [0:0] IS_AXI_24_ACLK_INVERTED = 1'b0; + parameter [0:0] IS_AXI_24_ARESET_N_INVERTED = 1'b0; + parameter [0:0] IS_AXI_25_ACLK_INVERTED = 1'b0; + parameter [0:0] IS_AXI_25_ARESET_N_INVERTED = 1'b0; + parameter [0:0] IS_AXI_26_ACLK_INVERTED = 1'b0; + parameter [0:0] IS_AXI_26_ARESET_N_INVERTED = 1'b0; + parameter [0:0] IS_AXI_27_ACLK_INVERTED = 1'b0; + parameter [0:0] IS_AXI_27_ARESET_N_INVERTED = 1'b0; + parameter [0:0] IS_AXI_28_ACLK_INVERTED = 1'b0; + parameter [0:0] IS_AXI_28_ARESET_N_INVERTED = 1'b0; + parameter [0:0] IS_AXI_29_ACLK_INVERTED = 1'b0; + parameter [0:0] IS_AXI_29_ARESET_N_INVERTED = 1'b0; + parameter [0:0] IS_AXI_30_ACLK_INVERTED = 1'b0; + parameter [0:0] IS_AXI_30_ARESET_N_INVERTED = 1'b0; + parameter [0:0] IS_AXI_31_ACLK_INVERTED = 1'b0; + parameter [0:0] IS_AXI_31_ARESET_N_INVERTED = 1'b0; + parameter MC_ENABLE_00 = "FALSE"; + parameter MC_ENABLE_01 = "FALSE"; + parameter MC_ENABLE_02 = "FALSE"; + parameter MC_ENABLE_03 = "FALSE"; + parameter MC_ENABLE_04 = "FALSE"; + parameter MC_ENABLE_05 = "FALSE"; + parameter MC_ENABLE_06 = "FALSE"; + parameter MC_ENABLE_07 = "FALSE"; + parameter MC_ENABLE_08 = "FALSE"; + parameter MC_ENABLE_09 = "FALSE"; + parameter MC_ENABLE_10 = "FALSE"; + parameter MC_ENABLE_11 = "FALSE"; + parameter MC_ENABLE_12 = "FALSE"; + parameter MC_ENABLE_13 = "FALSE"; + parameter MC_ENABLE_14 = "FALSE"; + parameter MC_ENABLE_15 = "FALSE"; + parameter MC_ENABLE_APB_00 = "FALSE"; + parameter MC_ENABLE_APB_01 = "FALSE"; + parameter integer PAGEHIT_PERCENT_00 = 75; + parameter integer PAGEHIT_PERCENT_01 = 75; + parameter PHY_ENABLE_00 = "FALSE"; + parameter PHY_ENABLE_01 = "FALSE"; + parameter PHY_ENABLE_02 = "FALSE"; + parameter PHY_ENABLE_03 = "FALSE"; + parameter PHY_ENABLE_04 = "FALSE"; + parameter PHY_ENABLE_05 = "FALSE"; + parameter PHY_ENABLE_06 = "FALSE"; + parameter PHY_ENABLE_07 = "FALSE"; + parameter PHY_ENABLE_08 = "FALSE"; + parameter PHY_ENABLE_09 = "FALSE"; + parameter PHY_ENABLE_10 = "FALSE"; + parameter PHY_ENABLE_11 = "FALSE"; + parameter PHY_ENABLE_12 = "FALSE"; + parameter PHY_ENABLE_13 = "FALSE"; + parameter PHY_ENABLE_14 = "FALSE"; + parameter PHY_ENABLE_15 = "FALSE"; + parameter PHY_ENABLE_16 = "FALSE"; + parameter PHY_ENABLE_17 = "FALSE"; + parameter PHY_ENABLE_18 = "FALSE"; + parameter PHY_ENABLE_19 = "FALSE"; + parameter PHY_ENABLE_20 = "FALSE"; + parameter PHY_ENABLE_21 = "FALSE"; + parameter PHY_ENABLE_22 = "FALSE"; + parameter PHY_ENABLE_23 = "FALSE"; + parameter PHY_ENABLE_24 = "FALSE"; + parameter PHY_ENABLE_25 = "FALSE"; + parameter PHY_ENABLE_26 = "FALSE"; + parameter PHY_ENABLE_27 = "FALSE"; + parameter PHY_ENABLE_28 = "FALSE"; + parameter PHY_ENABLE_29 = "FALSE"; + parameter PHY_ENABLE_30 = "FALSE"; + parameter PHY_ENABLE_31 = "FALSE"; + parameter PHY_ENABLE_APB_00 = "FALSE"; + parameter PHY_ENABLE_APB_01 = "FALSE"; + parameter PHY_PCLK_INVERT_01 = "FALSE"; + parameter PHY_PCLK_INVERT_02 = "FALSE"; + parameter integer READ_PERCENT_00 = 50; + parameter integer READ_PERCENT_01 = 50; + parameter integer READ_PERCENT_02 = 50; + parameter integer READ_PERCENT_03 = 50; + parameter integer READ_PERCENT_04 = 50; + parameter integer READ_PERCENT_05 = 50; + parameter integer READ_PERCENT_06 = 50; + parameter integer READ_PERCENT_07 = 50; + parameter integer READ_PERCENT_08 = 50; + parameter integer READ_PERCENT_09 = 50; + parameter integer READ_PERCENT_10 = 50; + parameter integer READ_PERCENT_11 = 50; + parameter integer READ_PERCENT_12 = 50; + parameter integer READ_PERCENT_13 = 50; + parameter integer READ_PERCENT_14 = 50; + parameter integer READ_PERCENT_15 = 50; + parameter integer READ_PERCENT_16 = 50; + parameter integer READ_PERCENT_17 = 50; + parameter integer READ_PERCENT_18 = 50; + parameter integer READ_PERCENT_19 = 50; + parameter integer READ_PERCENT_20 = 50; + parameter integer READ_PERCENT_21 = 50; + parameter integer READ_PERCENT_22 = 50; + parameter integer READ_PERCENT_23 = 50; + parameter integer READ_PERCENT_24 = 50; + parameter integer READ_PERCENT_25 = 50; + parameter integer READ_PERCENT_26 = 50; + parameter integer READ_PERCENT_27 = 50; + parameter integer READ_PERCENT_28 = 50; + parameter integer READ_PERCENT_29 = 50; + parameter integer READ_PERCENT_30 = 50; + parameter integer READ_PERCENT_31 = 50; + parameter SIM_DEVICE = "ULTRASCALE_PLUS"; + parameter SWITCH_ENABLE_00 = "FALSE"; + parameter SWITCH_ENABLE_01 = "FALSE"; + parameter integer WRITE_PERCENT_00 = 50; + parameter integer WRITE_PERCENT_01 = 50; + parameter integer WRITE_PERCENT_02 = 50; + parameter integer WRITE_PERCENT_03 = 50; + parameter integer WRITE_PERCENT_04 = 50; + parameter integer WRITE_PERCENT_05 = 50; + parameter integer WRITE_PERCENT_06 = 50; + parameter integer WRITE_PERCENT_07 = 50; + parameter integer WRITE_PERCENT_08 = 50; + parameter integer WRITE_PERCENT_09 = 50; + parameter integer WRITE_PERCENT_10 = 50; + parameter integer WRITE_PERCENT_11 = 50; + parameter integer WRITE_PERCENT_12 = 50; + parameter integer WRITE_PERCENT_13 = 50; + parameter integer WRITE_PERCENT_14 = 50; + parameter integer WRITE_PERCENT_15 = 50; + parameter integer WRITE_PERCENT_16 = 50; + parameter integer WRITE_PERCENT_17 = 50; + parameter integer WRITE_PERCENT_18 = 50; + parameter integer WRITE_PERCENT_19 = 50; + parameter integer WRITE_PERCENT_20 = 50; + parameter integer WRITE_PERCENT_21 = 50; + parameter integer WRITE_PERCENT_22 = 50; + parameter integer WRITE_PERCENT_23 = 50; + parameter integer WRITE_PERCENT_24 = 50; + parameter integer WRITE_PERCENT_25 = 50; + parameter integer WRITE_PERCENT_26 = 50; + parameter integer WRITE_PERCENT_27 = 50; + parameter integer WRITE_PERCENT_28 = 50; + parameter integer WRITE_PERCENT_29 = 50; + parameter integer WRITE_PERCENT_30 = 50; + parameter integer WRITE_PERCENT_31 = 50; + output [31:0] APB_0_PRDATA; + output APB_0_PREADY; + output APB_0_PSLVERR; + output [31:0] APB_1_PRDATA; + output APB_1_PREADY; + output APB_1_PSLVERR; + output AXI_00_ARREADY; + output AXI_00_AWREADY; + output [5:0] AXI_00_BID; + output [1:0] AXI_00_BRESP; + output AXI_00_BVALID; + output [1:0] AXI_00_DFI_AW_AERR_N; + output AXI_00_DFI_CLK_BUF; + output [7:0] AXI_00_DFI_DBI_BYTE_DISABLE; + output [20:0] AXI_00_DFI_DW_RDDATA_DBI; + output [7:0] AXI_00_DFI_DW_RDDATA_DERR; + output [1:0] AXI_00_DFI_DW_RDDATA_VALID; + output AXI_00_DFI_INIT_COMPLETE; + output AXI_00_DFI_PHYUPD_REQ; + output AXI_00_DFI_PHY_LP_STATE; + output AXI_00_DFI_RST_N_BUF; + output [5:0] AXI_00_MC_STATUS; + output [7:0] AXI_00_PHY_STATUS; + output [255:0] AXI_00_RDATA; + output [31:0] AXI_00_RDATA_PARITY; + output [5:0] AXI_00_RID; + output AXI_00_RLAST; + output [1:0] AXI_00_RRESP; + output AXI_00_RVALID; + output AXI_00_WREADY; + output AXI_01_ARREADY; + output AXI_01_AWREADY; + output [5:0] AXI_01_BID; + output [1:0] AXI_01_BRESP; + output AXI_01_BVALID; + output [1:0] AXI_01_DFI_AW_AERR_N; + output AXI_01_DFI_CLK_BUF; + output [7:0] AXI_01_DFI_DBI_BYTE_DISABLE; + output [20:0] AXI_01_DFI_DW_RDDATA_DBI; + output [7:0] AXI_01_DFI_DW_RDDATA_DERR; + output [1:0] AXI_01_DFI_DW_RDDATA_VALID; + output AXI_01_DFI_INIT_COMPLETE; + output AXI_01_DFI_PHYUPD_REQ; + output AXI_01_DFI_PHY_LP_STATE; + output AXI_01_DFI_RST_N_BUF; + output [255:0] AXI_01_RDATA; + output [31:0] AXI_01_RDATA_PARITY; + output [5:0] AXI_01_RID; + output AXI_01_RLAST; + output [1:0] AXI_01_RRESP; + output AXI_01_RVALID; + output AXI_01_WREADY; + output AXI_02_ARREADY; + output AXI_02_AWREADY; + output [5:0] AXI_02_BID; + output [1:0] AXI_02_BRESP; + output AXI_02_BVALID; + output [1:0] AXI_02_DFI_AW_AERR_N; + output AXI_02_DFI_CLK_BUF; + output [7:0] AXI_02_DFI_DBI_BYTE_DISABLE; + output [20:0] AXI_02_DFI_DW_RDDATA_DBI; + output [7:0] AXI_02_DFI_DW_RDDATA_DERR; + output [1:0] AXI_02_DFI_DW_RDDATA_VALID; + output AXI_02_DFI_INIT_COMPLETE; + output AXI_02_DFI_PHYUPD_REQ; + output AXI_02_DFI_PHY_LP_STATE; + output AXI_02_DFI_RST_N_BUF; + output [5:0] AXI_02_MC_STATUS; + output [7:0] AXI_02_PHY_STATUS; + output [255:0] AXI_02_RDATA; + output [31:0] AXI_02_RDATA_PARITY; + output [5:0] AXI_02_RID; + output AXI_02_RLAST; + output [1:0] AXI_02_RRESP; + output AXI_02_RVALID; + output AXI_02_WREADY; + output AXI_03_ARREADY; + output AXI_03_AWREADY; + output [5:0] AXI_03_BID; + output [1:0] AXI_03_BRESP; + output AXI_03_BVALID; + output [1:0] AXI_03_DFI_AW_AERR_N; + output AXI_03_DFI_CLK_BUF; + output [7:0] AXI_03_DFI_DBI_BYTE_DISABLE; + output [20:0] AXI_03_DFI_DW_RDDATA_DBI; + output [7:0] AXI_03_DFI_DW_RDDATA_DERR; + output [1:0] AXI_03_DFI_DW_RDDATA_VALID; + output AXI_03_DFI_INIT_COMPLETE; + output AXI_03_DFI_PHYUPD_REQ; + output AXI_03_DFI_PHY_LP_STATE; + output AXI_03_DFI_RST_N_BUF; + output [255:0] AXI_03_RDATA; + output [31:0] AXI_03_RDATA_PARITY; + output [5:0] AXI_03_RID; + output AXI_03_RLAST; + output [1:0] AXI_03_RRESP; + output AXI_03_RVALID; + output AXI_03_WREADY; + output AXI_04_ARREADY; + output AXI_04_AWREADY; + output [5:0] AXI_04_BID; + output [1:0] AXI_04_BRESP; + output AXI_04_BVALID; + output [1:0] AXI_04_DFI_AW_AERR_N; + output AXI_04_DFI_CLK_BUF; + output [7:0] AXI_04_DFI_DBI_BYTE_DISABLE; + output [20:0] AXI_04_DFI_DW_RDDATA_DBI; + output [7:0] AXI_04_DFI_DW_RDDATA_DERR; + output [1:0] AXI_04_DFI_DW_RDDATA_VALID; + output AXI_04_DFI_INIT_COMPLETE; + output AXI_04_DFI_PHYUPD_REQ; + output AXI_04_DFI_PHY_LP_STATE; + output AXI_04_DFI_RST_N_BUF; + output [5:0] AXI_04_MC_STATUS; + output [7:0] AXI_04_PHY_STATUS; + output [255:0] AXI_04_RDATA; + output [31:0] AXI_04_RDATA_PARITY; + output [5:0] AXI_04_RID; + output AXI_04_RLAST; + output [1:0] AXI_04_RRESP; + output AXI_04_RVALID; + output AXI_04_WREADY; + output AXI_05_ARREADY; + output AXI_05_AWREADY; + output [5:0] AXI_05_BID; + output [1:0] AXI_05_BRESP; + output AXI_05_BVALID; + output [1:0] AXI_05_DFI_AW_AERR_N; + output AXI_05_DFI_CLK_BUF; + output [7:0] AXI_05_DFI_DBI_BYTE_DISABLE; + output [20:0] AXI_05_DFI_DW_RDDATA_DBI; + output [7:0] AXI_05_DFI_DW_RDDATA_DERR; + output [1:0] AXI_05_DFI_DW_RDDATA_VALID; + output AXI_05_DFI_INIT_COMPLETE; + output AXI_05_DFI_PHYUPD_REQ; + output AXI_05_DFI_PHY_LP_STATE; + output AXI_05_DFI_RST_N_BUF; + output [255:0] AXI_05_RDATA; + output [31:0] AXI_05_RDATA_PARITY; + output [5:0] AXI_05_RID; + output AXI_05_RLAST; + output [1:0] AXI_05_RRESP; + output AXI_05_RVALID; + output AXI_05_WREADY; + output AXI_06_ARREADY; + output AXI_06_AWREADY; + output [5:0] AXI_06_BID; + output [1:0] AXI_06_BRESP; + output AXI_06_BVALID; + output [1:0] AXI_06_DFI_AW_AERR_N; + output AXI_06_DFI_CLK_BUF; + output [7:0] AXI_06_DFI_DBI_BYTE_DISABLE; + output [20:0] AXI_06_DFI_DW_RDDATA_DBI; + output [7:0] AXI_06_DFI_DW_RDDATA_DERR; + output [1:0] AXI_06_DFI_DW_RDDATA_VALID; + output AXI_06_DFI_INIT_COMPLETE; + output AXI_06_DFI_PHYUPD_REQ; + output AXI_06_DFI_PHY_LP_STATE; + output AXI_06_DFI_RST_N_BUF; + output [5:0] AXI_06_MC_STATUS; + output [7:0] AXI_06_PHY_STATUS; + output [255:0] AXI_06_RDATA; + output [31:0] AXI_06_RDATA_PARITY; + output [5:0] AXI_06_RID; + output AXI_06_RLAST; + output [1:0] AXI_06_RRESP; + output AXI_06_RVALID; + output AXI_06_WREADY; + output AXI_07_ARREADY; + output AXI_07_AWREADY; + output [5:0] AXI_07_BID; + output [1:0] AXI_07_BRESP; + output AXI_07_BVALID; + output [1:0] AXI_07_DFI_AW_AERR_N; + output AXI_07_DFI_CLK_BUF; + output [7:0] AXI_07_DFI_DBI_BYTE_DISABLE; + output [20:0] AXI_07_DFI_DW_RDDATA_DBI; + output [7:0] AXI_07_DFI_DW_RDDATA_DERR; + output [1:0] AXI_07_DFI_DW_RDDATA_VALID; + output AXI_07_DFI_INIT_COMPLETE; + output AXI_07_DFI_PHYUPD_REQ; + output AXI_07_DFI_PHY_LP_STATE; + output AXI_07_DFI_RST_N_BUF; + output [255:0] AXI_07_RDATA; + output [31:0] AXI_07_RDATA_PARITY; + output [5:0] AXI_07_RID; + output AXI_07_RLAST; + output [1:0] AXI_07_RRESP; + output AXI_07_RVALID; + output AXI_07_WREADY; + output AXI_08_ARREADY; + output AXI_08_AWREADY; + output [5:0] AXI_08_BID; + output [1:0] AXI_08_BRESP; + output AXI_08_BVALID; + output [1:0] AXI_08_DFI_AW_AERR_N; + output AXI_08_DFI_CLK_BUF; + output [7:0] AXI_08_DFI_DBI_BYTE_DISABLE; + output [20:0] AXI_08_DFI_DW_RDDATA_DBI; + output [7:0] AXI_08_DFI_DW_RDDATA_DERR; + output [1:0] AXI_08_DFI_DW_RDDATA_VALID; + output AXI_08_DFI_INIT_COMPLETE; + output AXI_08_DFI_PHYUPD_REQ; + output AXI_08_DFI_PHY_LP_STATE; + output AXI_08_DFI_RST_N_BUF; + output [5:0] AXI_08_MC_STATUS; + output [7:0] AXI_08_PHY_STATUS; + output [255:0] AXI_08_RDATA; + output [31:0] AXI_08_RDATA_PARITY; + output [5:0] AXI_08_RID; + output AXI_08_RLAST; + output [1:0] AXI_08_RRESP; + output AXI_08_RVALID; + output AXI_08_WREADY; + output AXI_09_ARREADY; + output AXI_09_AWREADY; + output [5:0] AXI_09_BID; + output [1:0] AXI_09_BRESP; + output AXI_09_BVALID; + output [1:0] AXI_09_DFI_AW_AERR_N; + output AXI_09_DFI_CLK_BUF; + output [7:0] AXI_09_DFI_DBI_BYTE_DISABLE; + output [20:0] AXI_09_DFI_DW_RDDATA_DBI; + output [7:0] AXI_09_DFI_DW_RDDATA_DERR; + output [1:0] AXI_09_DFI_DW_RDDATA_VALID; + output AXI_09_DFI_INIT_COMPLETE; + output AXI_09_DFI_PHYUPD_REQ; + output AXI_09_DFI_PHY_LP_STATE; + output AXI_09_DFI_RST_N_BUF; + output [255:0] AXI_09_RDATA; + output [31:0] AXI_09_RDATA_PARITY; + output [5:0] AXI_09_RID; + output AXI_09_RLAST; + output [1:0] AXI_09_RRESP; + output AXI_09_RVALID; + output AXI_09_WREADY; + output AXI_10_ARREADY; + output AXI_10_AWREADY; + output [5:0] AXI_10_BID; + output [1:0] AXI_10_BRESP; + output AXI_10_BVALID; + output [1:0] AXI_10_DFI_AW_AERR_N; + output AXI_10_DFI_CLK_BUF; + output [7:0] AXI_10_DFI_DBI_BYTE_DISABLE; + output [20:0] AXI_10_DFI_DW_RDDATA_DBI; + output [7:0] AXI_10_DFI_DW_RDDATA_DERR; + output [1:0] AXI_10_DFI_DW_RDDATA_VALID; + output AXI_10_DFI_INIT_COMPLETE; + output AXI_10_DFI_PHYUPD_REQ; + output AXI_10_DFI_PHY_LP_STATE; + output AXI_10_DFI_RST_N_BUF; + output [5:0] AXI_10_MC_STATUS; + output [7:0] AXI_10_PHY_STATUS; + output [255:0] AXI_10_RDATA; + output [31:0] AXI_10_RDATA_PARITY; + output [5:0] AXI_10_RID; + output AXI_10_RLAST; + output [1:0] AXI_10_RRESP; + output AXI_10_RVALID; + output AXI_10_WREADY; + output AXI_11_ARREADY; + output AXI_11_AWREADY; + output [5:0] AXI_11_BID; + output [1:0] AXI_11_BRESP; + output AXI_11_BVALID; + output [1:0] AXI_11_DFI_AW_AERR_N; + output AXI_11_DFI_CLK_BUF; + output [7:0] AXI_11_DFI_DBI_BYTE_DISABLE; + output [20:0] AXI_11_DFI_DW_RDDATA_DBI; + output [7:0] AXI_11_DFI_DW_RDDATA_DERR; + output [1:0] AXI_11_DFI_DW_RDDATA_VALID; + output AXI_11_DFI_INIT_COMPLETE; + output AXI_11_DFI_PHYUPD_REQ; + output AXI_11_DFI_PHY_LP_STATE; + output AXI_11_DFI_RST_N_BUF; + output [255:0] AXI_11_RDATA; + output [31:0] AXI_11_RDATA_PARITY; + output [5:0] AXI_11_RID; + output AXI_11_RLAST; + output [1:0] AXI_11_RRESP; + output AXI_11_RVALID; + output AXI_11_WREADY; + output AXI_12_ARREADY; + output AXI_12_AWREADY; + output [5:0] AXI_12_BID; + output [1:0] AXI_12_BRESP; + output AXI_12_BVALID; + output [1:0] AXI_12_DFI_AW_AERR_N; + output AXI_12_DFI_CLK_BUF; + output [7:0] AXI_12_DFI_DBI_BYTE_DISABLE; + output [20:0] AXI_12_DFI_DW_RDDATA_DBI; + output [7:0] AXI_12_DFI_DW_RDDATA_DERR; + output [1:0] AXI_12_DFI_DW_RDDATA_VALID; + output AXI_12_DFI_INIT_COMPLETE; + output AXI_12_DFI_PHYUPD_REQ; + output AXI_12_DFI_PHY_LP_STATE; + output AXI_12_DFI_RST_N_BUF; + output [5:0] AXI_12_MC_STATUS; + output [7:0] AXI_12_PHY_STATUS; + output [255:0] AXI_12_RDATA; + output [31:0] AXI_12_RDATA_PARITY; + output [5:0] AXI_12_RID; + output AXI_12_RLAST; + output [1:0] AXI_12_RRESP; + output AXI_12_RVALID; + output AXI_12_WREADY; + output AXI_13_ARREADY; + output AXI_13_AWREADY; + output [5:0] AXI_13_BID; + output [1:0] AXI_13_BRESP; + output AXI_13_BVALID; + output [1:0] AXI_13_DFI_AW_AERR_N; + output AXI_13_DFI_CLK_BUF; + output [7:0] AXI_13_DFI_DBI_BYTE_DISABLE; + output [20:0] AXI_13_DFI_DW_RDDATA_DBI; + output [7:0] AXI_13_DFI_DW_RDDATA_DERR; + output [1:0] AXI_13_DFI_DW_RDDATA_VALID; + output AXI_13_DFI_INIT_COMPLETE; + output AXI_13_DFI_PHYUPD_REQ; + output AXI_13_DFI_PHY_LP_STATE; + output AXI_13_DFI_RST_N_BUF; + output [255:0] AXI_13_RDATA; + output [31:0] AXI_13_RDATA_PARITY; + output [5:0] AXI_13_RID; + output AXI_13_RLAST; + output [1:0] AXI_13_RRESP; + output AXI_13_RVALID; + output AXI_13_WREADY; + output AXI_14_ARREADY; + output AXI_14_AWREADY; + output [5:0] AXI_14_BID; + output [1:0] AXI_14_BRESP; + output AXI_14_BVALID; + output [1:0] AXI_14_DFI_AW_AERR_N; + output AXI_14_DFI_CLK_BUF; + output [7:0] AXI_14_DFI_DBI_BYTE_DISABLE; + output [20:0] AXI_14_DFI_DW_RDDATA_DBI; + output [7:0] AXI_14_DFI_DW_RDDATA_DERR; + output [1:0] AXI_14_DFI_DW_RDDATA_VALID; + output AXI_14_DFI_INIT_COMPLETE; + output AXI_14_DFI_PHYUPD_REQ; + output AXI_14_DFI_PHY_LP_STATE; + output AXI_14_DFI_RST_N_BUF; + output [5:0] AXI_14_MC_STATUS; + output [7:0] AXI_14_PHY_STATUS; + output [255:0] AXI_14_RDATA; + output [31:0] AXI_14_RDATA_PARITY; + output [5:0] AXI_14_RID; + output AXI_14_RLAST; + output [1:0] AXI_14_RRESP; + output AXI_14_RVALID; + output AXI_14_WREADY; + output AXI_15_ARREADY; + output AXI_15_AWREADY; + output [5:0] AXI_15_BID; + output [1:0] AXI_15_BRESP; + output AXI_15_BVALID; + output [1:0] AXI_15_DFI_AW_AERR_N; + output AXI_15_DFI_CLK_BUF; + output [7:0] AXI_15_DFI_DBI_BYTE_DISABLE; + output [20:0] AXI_15_DFI_DW_RDDATA_DBI; + output [7:0] AXI_15_DFI_DW_RDDATA_DERR; + output [1:0] AXI_15_DFI_DW_RDDATA_VALID; + output AXI_15_DFI_INIT_COMPLETE; + output AXI_15_DFI_PHYUPD_REQ; + output AXI_15_DFI_PHY_LP_STATE; + output AXI_15_DFI_RST_N_BUF; + output [255:0] AXI_15_RDATA; + output [31:0] AXI_15_RDATA_PARITY; + output [5:0] AXI_15_RID; + output AXI_15_RLAST; + output [1:0] AXI_15_RRESP; + output AXI_15_RVALID; + output AXI_15_WREADY; + output AXI_16_ARREADY; + output AXI_16_AWREADY; + output [5:0] AXI_16_BID; + output [1:0] AXI_16_BRESP; + output AXI_16_BVALID; + output [1:0] AXI_16_DFI_AW_AERR_N; + output AXI_16_DFI_CLK_BUF; + output [7:0] AXI_16_DFI_DBI_BYTE_DISABLE; + output [20:0] AXI_16_DFI_DW_RDDATA_DBI; + output [7:0] AXI_16_DFI_DW_RDDATA_DERR; + output [1:0] AXI_16_DFI_DW_RDDATA_VALID; + output AXI_16_DFI_INIT_COMPLETE; + output AXI_16_DFI_PHYUPD_REQ; + output AXI_16_DFI_PHY_LP_STATE; + output AXI_16_DFI_RST_N_BUF; + output [5:0] AXI_16_MC_STATUS; + output [7:0] AXI_16_PHY_STATUS; + output [255:0] AXI_16_RDATA; + output [31:0] AXI_16_RDATA_PARITY; + output [5:0] AXI_16_RID; + output AXI_16_RLAST; + output [1:0] AXI_16_RRESP; + output AXI_16_RVALID; + output AXI_16_WREADY; + output AXI_17_ARREADY; + output AXI_17_AWREADY; + output [5:0] AXI_17_BID; + output [1:0] AXI_17_BRESP; + output AXI_17_BVALID; + output [1:0] AXI_17_DFI_AW_AERR_N; + output AXI_17_DFI_CLK_BUF; + output [7:0] AXI_17_DFI_DBI_BYTE_DISABLE; + output [20:0] AXI_17_DFI_DW_RDDATA_DBI; + output [7:0] AXI_17_DFI_DW_RDDATA_DERR; + output [1:0] AXI_17_DFI_DW_RDDATA_VALID; + output AXI_17_DFI_INIT_COMPLETE; + output AXI_17_DFI_PHYUPD_REQ; + output AXI_17_DFI_PHY_LP_STATE; + output AXI_17_DFI_RST_N_BUF; + output [255:0] AXI_17_RDATA; + output [31:0] AXI_17_RDATA_PARITY; + output [5:0] AXI_17_RID; + output AXI_17_RLAST; + output [1:0] AXI_17_RRESP; + output AXI_17_RVALID; + output AXI_17_WREADY; + output AXI_18_ARREADY; + output AXI_18_AWREADY; + output [5:0] AXI_18_BID; + output [1:0] AXI_18_BRESP; + output AXI_18_BVALID; + output [1:0] AXI_18_DFI_AW_AERR_N; + output AXI_18_DFI_CLK_BUF; + output [7:0] AXI_18_DFI_DBI_BYTE_DISABLE; + output [20:0] AXI_18_DFI_DW_RDDATA_DBI; + output [7:0] AXI_18_DFI_DW_RDDATA_DERR; + output [1:0] AXI_18_DFI_DW_RDDATA_VALID; + output AXI_18_DFI_INIT_COMPLETE; + output AXI_18_DFI_PHYUPD_REQ; + output AXI_18_DFI_PHY_LP_STATE; + output AXI_18_DFI_RST_N_BUF; + output [5:0] AXI_18_MC_STATUS; + output [7:0] AXI_18_PHY_STATUS; + output [255:0] AXI_18_RDATA; + output [31:0] AXI_18_RDATA_PARITY; + output [5:0] AXI_18_RID; + output AXI_18_RLAST; + output [1:0] AXI_18_RRESP; + output AXI_18_RVALID; + output AXI_18_WREADY; + output AXI_19_ARREADY; + output AXI_19_AWREADY; + output [5:0] AXI_19_BID; + output [1:0] AXI_19_BRESP; + output AXI_19_BVALID; + output [1:0] AXI_19_DFI_AW_AERR_N; + output AXI_19_DFI_CLK_BUF; + output [7:0] AXI_19_DFI_DBI_BYTE_DISABLE; + output [20:0] AXI_19_DFI_DW_RDDATA_DBI; + output [7:0] AXI_19_DFI_DW_RDDATA_DERR; + output [1:0] AXI_19_DFI_DW_RDDATA_VALID; + output AXI_19_DFI_INIT_COMPLETE; + output AXI_19_DFI_PHYUPD_REQ; + output AXI_19_DFI_PHY_LP_STATE; + output AXI_19_DFI_RST_N_BUF; + output [255:0] AXI_19_RDATA; + output [31:0] AXI_19_RDATA_PARITY; + output [5:0] AXI_19_RID; + output AXI_19_RLAST; + output [1:0] AXI_19_RRESP; + output AXI_19_RVALID; + output AXI_19_WREADY; + output AXI_20_ARREADY; + output AXI_20_AWREADY; + output [5:0] AXI_20_BID; + output [1:0] AXI_20_BRESP; + output AXI_20_BVALID; + output [1:0] AXI_20_DFI_AW_AERR_N; + output AXI_20_DFI_CLK_BUF; + output [7:0] AXI_20_DFI_DBI_BYTE_DISABLE; + output [20:0] AXI_20_DFI_DW_RDDATA_DBI; + output [7:0] AXI_20_DFI_DW_RDDATA_DERR; + output [1:0] AXI_20_DFI_DW_RDDATA_VALID; + output AXI_20_DFI_INIT_COMPLETE; + output AXI_20_DFI_PHYUPD_REQ; + output AXI_20_DFI_PHY_LP_STATE; + output AXI_20_DFI_RST_N_BUF; + output [5:0] AXI_20_MC_STATUS; + output [7:0] AXI_20_PHY_STATUS; + output [255:0] AXI_20_RDATA; + output [31:0] AXI_20_RDATA_PARITY; + output [5:0] AXI_20_RID; + output AXI_20_RLAST; + output [1:0] AXI_20_RRESP; + output AXI_20_RVALID; + output AXI_20_WREADY; + output AXI_21_ARREADY; + output AXI_21_AWREADY; + output [5:0] AXI_21_BID; + output [1:0] AXI_21_BRESP; + output AXI_21_BVALID; + output [1:0] AXI_21_DFI_AW_AERR_N; + output AXI_21_DFI_CLK_BUF; + output [7:0] AXI_21_DFI_DBI_BYTE_DISABLE; + output [20:0] AXI_21_DFI_DW_RDDATA_DBI; + output [7:0] AXI_21_DFI_DW_RDDATA_DERR; + output [1:0] AXI_21_DFI_DW_RDDATA_VALID; + output AXI_21_DFI_INIT_COMPLETE; + output AXI_21_DFI_PHYUPD_REQ; + output AXI_21_DFI_PHY_LP_STATE; + output AXI_21_DFI_RST_N_BUF; + output [255:0] AXI_21_RDATA; + output [31:0] AXI_21_RDATA_PARITY; + output [5:0] AXI_21_RID; + output AXI_21_RLAST; + output [1:0] AXI_21_RRESP; + output AXI_21_RVALID; + output AXI_21_WREADY; + output AXI_22_ARREADY; + output AXI_22_AWREADY; + output [5:0] AXI_22_BID; + output [1:0] AXI_22_BRESP; + output AXI_22_BVALID; + output [1:0] AXI_22_DFI_AW_AERR_N; + output AXI_22_DFI_CLK_BUF; + output [7:0] AXI_22_DFI_DBI_BYTE_DISABLE; + output [20:0] AXI_22_DFI_DW_RDDATA_DBI; + output [7:0] AXI_22_DFI_DW_RDDATA_DERR; + output [1:0] AXI_22_DFI_DW_RDDATA_VALID; + output AXI_22_DFI_INIT_COMPLETE; + output AXI_22_DFI_PHYUPD_REQ; + output AXI_22_DFI_PHY_LP_STATE; + output AXI_22_DFI_RST_N_BUF; + output [5:0] AXI_22_MC_STATUS; + output [7:0] AXI_22_PHY_STATUS; + output [255:0] AXI_22_RDATA; + output [31:0] AXI_22_RDATA_PARITY; + output [5:0] AXI_22_RID; + output AXI_22_RLAST; + output [1:0] AXI_22_RRESP; + output AXI_22_RVALID; + output AXI_22_WREADY; + output AXI_23_ARREADY; + output AXI_23_AWREADY; + output [5:0] AXI_23_BID; + output [1:0] AXI_23_BRESP; + output AXI_23_BVALID; + output [1:0] AXI_23_DFI_AW_AERR_N; + output AXI_23_DFI_CLK_BUF; + output [7:0] AXI_23_DFI_DBI_BYTE_DISABLE; + output [20:0] AXI_23_DFI_DW_RDDATA_DBI; + output [7:0] AXI_23_DFI_DW_RDDATA_DERR; + output [1:0] AXI_23_DFI_DW_RDDATA_VALID; + output AXI_23_DFI_INIT_COMPLETE; + output AXI_23_DFI_PHYUPD_REQ; + output AXI_23_DFI_PHY_LP_STATE; + output AXI_23_DFI_RST_N_BUF; + output [255:0] AXI_23_RDATA; + output [31:0] AXI_23_RDATA_PARITY; + output [5:0] AXI_23_RID; + output AXI_23_RLAST; + output [1:0] AXI_23_RRESP; + output AXI_23_RVALID; + output AXI_23_WREADY; + output AXI_24_ARREADY; + output AXI_24_AWREADY; + output [5:0] AXI_24_BID; + output [1:0] AXI_24_BRESP; + output AXI_24_BVALID; + output [1:0] AXI_24_DFI_AW_AERR_N; + output AXI_24_DFI_CLK_BUF; + output [7:0] AXI_24_DFI_DBI_BYTE_DISABLE; + output [20:0] AXI_24_DFI_DW_RDDATA_DBI; + output [7:0] AXI_24_DFI_DW_RDDATA_DERR; + output [1:0] AXI_24_DFI_DW_RDDATA_VALID; + output AXI_24_DFI_INIT_COMPLETE; + output AXI_24_DFI_PHYUPD_REQ; + output AXI_24_DFI_PHY_LP_STATE; + output AXI_24_DFI_RST_N_BUF; + output [5:0] AXI_24_MC_STATUS; + output [7:0] AXI_24_PHY_STATUS; + output [255:0] AXI_24_RDATA; + output [31:0] AXI_24_RDATA_PARITY; + output [5:0] AXI_24_RID; + output AXI_24_RLAST; + output [1:0] AXI_24_RRESP; + output AXI_24_RVALID; + output AXI_24_WREADY; + output AXI_25_ARREADY; + output AXI_25_AWREADY; + output [5:0] AXI_25_BID; + output [1:0] AXI_25_BRESP; + output AXI_25_BVALID; + output [1:0] AXI_25_DFI_AW_AERR_N; + output AXI_25_DFI_CLK_BUF; + output [7:0] AXI_25_DFI_DBI_BYTE_DISABLE; + output [20:0] AXI_25_DFI_DW_RDDATA_DBI; + output [7:0] AXI_25_DFI_DW_RDDATA_DERR; + output [1:0] AXI_25_DFI_DW_RDDATA_VALID; + output AXI_25_DFI_INIT_COMPLETE; + output AXI_25_DFI_PHYUPD_REQ; + output AXI_25_DFI_PHY_LP_STATE; + output AXI_25_DFI_RST_N_BUF; + output [255:0] AXI_25_RDATA; + output [31:0] AXI_25_RDATA_PARITY; + output [5:0] AXI_25_RID; + output AXI_25_RLAST; + output [1:0] AXI_25_RRESP; + output AXI_25_RVALID; + output AXI_25_WREADY; + output AXI_26_ARREADY; + output AXI_26_AWREADY; + output [5:0] AXI_26_BID; + output [1:0] AXI_26_BRESP; + output AXI_26_BVALID; + output [1:0] AXI_26_DFI_AW_AERR_N; + output AXI_26_DFI_CLK_BUF; + output [7:0] AXI_26_DFI_DBI_BYTE_DISABLE; + output [20:0] AXI_26_DFI_DW_RDDATA_DBI; + output [7:0] AXI_26_DFI_DW_RDDATA_DERR; + output [1:0] AXI_26_DFI_DW_RDDATA_VALID; + output AXI_26_DFI_INIT_COMPLETE; + output AXI_26_DFI_PHYUPD_REQ; + output AXI_26_DFI_PHY_LP_STATE; + output AXI_26_DFI_RST_N_BUF; + output [5:0] AXI_26_MC_STATUS; + output [7:0] AXI_26_PHY_STATUS; + output [255:0] AXI_26_RDATA; + output [31:0] AXI_26_RDATA_PARITY; + output [5:0] AXI_26_RID; + output AXI_26_RLAST; + output [1:0] AXI_26_RRESP; + output AXI_26_RVALID; + output AXI_26_WREADY; + output AXI_27_ARREADY; + output AXI_27_AWREADY; + output [5:0] AXI_27_BID; + output [1:0] AXI_27_BRESP; + output AXI_27_BVALID; + output [1:0] AXI_27_DFI_AW_AERR_N; + output AXI_27_DFI_CLK_BUF; + output [7:0] AXI_27_DFI_DBI_BYTE_DISABLE; + output [20:0] AXI_27_DFI_DW_RDDATA_DBI; + output [7:0] AXI_27_DFI_DW_RDDATA_DERR; + output [1:0] AXI_27_DFI_DW_RDDATA_VALID; + output AXI_27_DFI_INIT_COMPLETE; + output AXI_27_DFI_PHYUPD_REQ; + output AXI_27_DFI_PHY_LP_STATE; + output AXI_27_DFI_RST_N_BUF; + output [255:0] AXI_27_RDATA; + output [31:0] AXI_27_RDATA_PARITY; + output [5:0] AXI_27_RID; + output AXI_27_RLAST; + output [1:0] AXI_27_RRESP; + output AXI_27_RVALID; + output AXI_27_WREADY; + output AXI_28_ARREADY; + output AXI_28_AWREADY; + output [5:0] AXI_28_BID; + output [1:0] AXI_28_BRESP; + output AXI_28_BVALID; + output [1:0] AXI_28_DFI_AW_AERR_N; + output AXI_28_DFI_CLK_BUF; + output [7:0] AXI_28_DFI_DBI_BYTE_DISABLE; + output [20:0] AXI_28_DFI_DW_RDDATA_DBI; + output [7:0] AXI_28_DFI_DW_RDDATA_DERR; + output [1:0] AXI_28_DFI_DW_RDDATA_VALID; + output AXI_28_DFI_INIT_COMPLETE; + output AXI_28_DFI_PHYUPD_REQ; + output AXI_28_DFI_PHY_LP_STATE; + output AXI_28_DFI_RST_N_BUF; + output [5:0] AXI_28_MC_STATUS; + output [7:0] AXI_28_PHY_STATUS; + output [255:0] AXI_28_RDATA; + output [31:0] AXI_28_RDATA_PARITY; + output [5:0] AXI_28_RID; + output AXI_28_RLAST; + output [1:0] AXI_28_RRESP; + output AXI_28_RVALID; + output AXI_28_WREADY; + output AXI_29_ARREADY; + output AXI_29_AWREADY; + output [5:0] AXI_29_BID; + output [1:0] AXI_29_BRESP; + output AXI_29_BVALID; + output [1:0] AXI_29_DFI_AW_AERR_N; + output AXI_29_DFI_CLK_BUF; + output [7:0] AXI_29_DFI_DBI_BYTE_DISABLE; + output [20:0] AXI_29_DFI_DW_RDDATA_DBI; + output [7:0] AXI_29_DFI_DW_RDDATA_DERR; + output [1:0] AXI_29_DFI_DW_RDDATA_VALID; + output AXI_29_DFI_INIT_COMPLETE; + output AXI_29_DFI_PHYUPD_REQ; + output AXI_29_DFI_PHY_LP_STATE; + output AXI_29_DFI_RST_N_BUF; + output [255:0] AXI_29_RDATA; + output [31:0] AXI_29_RDATA_PARITY; + output [5:0] AXI_29_RID; + output AXI_29_RLAST; + output [1:0] AXI_29_RRESP; + output AXI_29_RVALID; + output AXI_29_WREADY; + output AXI_30_ARREADY; + output AXI_30_AWREADY; + output [5:0] AXI_30_BID; + output [1:0] AXI_30_BRESP; + output AXI_30_BVALID; + output [1:0] AXI_30_DFI_AW_AERR_N; + output AXI_30_DFI_CLK_BUF; + output [7:0] AXI_30_DFI_DBI_BYTE_DISABLE; + output [20:0] AXI_30_DFI_DW_RDDATA_DBI; + output [7:0] AXI_30_DFI_DW_RDDATA_DERR; + output [1:0] AXI_30_DFI_DW_RDDATA_VALID; + output AXI_30_DFI_INIT_COMPLETE; + output AXI_30_DFI_PHYUPD_REQ; + output AXI_30_DFI_PHY_LP_STATE; + output AXI_30_DFI_RST_N_BUF; + output [5:0] AXI_30_MC_STATUS; + output [7:0] AXI_30_PHY_STATUS; + output [255:0] AXI_30_RDATA; + output [31:0] AXI_30_RDATA_PARITY; + output [5:0] AXI_30_RID; + output AXI_30_RLAST; + output [1:0] AXI_30_RRESP; + output AXI_30_RVALID; + output AXI_30_WREADY; + output AXI_31_ARREADY; + output AXI_31_AWREADY; + output [5:0] AXI_31_BID; + output [1:0] AXI_31_BRESP; + output AXI_31_BVALID; + output [1:0] AXI_31_DFI_AW_AERR_N; + output AXI_31_DFI_CLK_BUF; + output [7:0] AXI_31_DFI_DBI_BYTE_DISABLE; + output [20:0] AXI_31_DFI_DW_RDDATA_DBI; + output [7:0] AXI_31_DFI_DW_RDDATA_DERR; + output [1:0] AXI_31_DFI_DW_RDDATA_VALID; + output AXI_31_DFI_INIT_COMPLETE; + output AXI_31_DFI_PHYUPD_REQ; + output AXI_31_DFI_PHY_LP_STATE; + output AXI_31_DFI_RST_N_BUF; + output [255:0] AXI_31_RDATA; + output [31:0] AXI_31_RDATA_PARITY; + output [5:0] AXI_31_RID; + output AXI_31_RLAST; + output [1:0] AXI_31_RRESP; + output AXI_31_RVALID; + output AXI_31_WREADY; + output DRAM_0_STAT_CATTRIP; + output [2:0] DRAM_0_STAT_TEMP; + output DRAM_1_STAT_CATTRIP; + output [2:0] DRAM_1_STAT_TEMP; + input [21:0] APB_0_PADDR; + (* invertible_pin = "IS_APB_0_PCLK_INVERTED" *) + input APB_0_PCLK; + input APB_0_PENABLE; + (* invertible_pin = "IS_APB_0_PRESET_N_INVERTED" *) + input APB_0_PRESET_N; + input APB_0_PSEL; + input [31:0] APB_0_PWDATA; + input APB_0_PWRITE; + input [21:0] APB_1_PADDR; + (* invertible_pin = "IS_APB_1_PCLK_INVERTED" *) + input APB_1_PCLK; + input APB_1_PENABLE; + (* invertible_pin = "IS_APB_1_PRESET_N_INVERTED" *) + input APB_1_PRESET_N; + input APB_1_PSEL; + input [31:0] APB_1_PWDATA; + input APB_1_PWRITE; + (* invertible_pin = "IS_AXI_00_ACLK_INVERTED" *) + input AXI_00_ACLK; + input [36:0] AXI_00_ARADDR; + input [1:0] AXI_00_ARBURST; + (* invertible_pin = "IS_AXI_00_ARESET_N_INVERTED" *) + input AXI_00_ARESET_N; + input [5:0] AXI_00_ARID; + input [3:0] AXI_00_ARLEN; + input [2:0] AXI_00_ARSIZE; + input AXI_00_ARVALID; + input [36:0] AXI_00_AWADDR; + input [1:0] AXI_00_AWBURST; + input [5:0] AXI_00_AWID; + input [3:0] AXI_00_AWLEN; + input [2:0] AXI_00_AWSIZE; + input AXI_00_AWVALID; + input AXI_00_BREADY; + input AXI_00_DFI_LP_PWR_X_REQ; + input AXI_00_RREADY; + input [255:0] AXI_00_WDATA; + input [31:0] AXI_00_WDATA_PARITY; + input AXI_00_WLAST; + input [31:0] AXI_00_WSTRB; + input AXI_00_WVALID; + (* invertible_pin = "IS_AXI_01_ACLK_INVERTED" *) + input AXI_01_ACLK; + input [36:0] AXI_01_ARADDR; + input [1:0] AXI_01_ARBURST; + (* invertible_pin = "IS_AXI_01_ARESET_N_INVERTED" *) + input AXI_01_ARESET_N; + input [5:0] AXI_01_ARID; + input [3:0] AXI_01_ARLEN; + input [2:0] AXI_01_ARSIZE; + input AXI_01_ARVALID; + input [36:0] AXI_01_AWADDR; + input [1:0] AXI_01_AWBURST; + input [5:0] AXI_01_AWID; + input [3:0] AXI_01_AWLEN; + input [2:0] AXI_01_AWSIZE; + input AXI_01_AWVALID; + input AXI_01_BREADY; + input AXI_01_DFI_LP_PWR_X_REQ; + input AXI_01_RREADY; + input [255:0] AXI_01_WDATA; + input [31:0] AXI_01_WDATA_PARITY; + input AXI_01_WLAST; + input [31:0] AXI_01_WSTRB; + input AXI_01_WVALID; + (* invertible_pin = "IS_AXI_02_ACLK_INVERTED" *) + input AXI_02_ACLK; + input [36:0] AXI_02_ARADDR; + input [1:0] AXI_02_ARBURST; + (* invertible_pin = "IS_AXI_02_ARESET_N_INVERTED" *) + input AXI_02_ARESET_N; + input [5:0] AXI_02_ARID; + input [3:0] AXI_02_ARLEN; + input [2:0] AXI_02_ARSIZE; + input AXI_02_ARVALID; + input [36:0] AXI_02_AWADDR; + input [1:0] AXI_02_AWBURST; + input [5:0] AXI_02_AWID; + input [3:0] AXI_02_AWLEN; + input [2:0] AXI_02_AWSIZE; + input AXI_02_AWVALID; + input AXI_02_BREADY; + input AXI_02_DFI_LP_PWR_X_REQ; + input AXI_02_RREADY; + input [255:0] AXI_02_WDATA; + input [31:0] AXI_02_WDATA_PARITY; + input AXI_02_WLAST; + input [31:0] AXI_02_WSTRB; + input AXI_02_WVALID; + (* invertible_pin = "IS_AXI_03_ACLK_INVERTED" *) + input AXI_03_ACLK; + input [36:0] AXI_03_ARADDR; + input [1:0] AXI_03_ARBURST; + (* invertible_pin = "IS_AXI_03_ARESET_N_INVERTED" *) + input AXI_03_ARESET_N; + input [5:0] AXI_03_ARID; + input [3:0] AXI_03_ARLEN; + input [2:0] AXI_03_ARSIZE; + input AXI_03_ARVALID; + input [36:0] AXI_03_AWADDR; + input [1:0] AXI_03_AWBURST; + input [5:0] AXI_03_AWID; + input [3:0] AXI_03_AWLEN; + input [2:0] AXI_03_AWSIZE; + input AXI_03_AWVALID; + input AXI_03_BREADY; + input AXI_03_DFI_LP_PWR_X_REQ; + input AXI_03_RREADY; + input [255:0] AXI_03_WDATA; + input [31:0] AXI_03_WDATA_PARITY; + input AXI_03_WLAST; + input [31:0] AXI_03_WSTRB; + input AXI_03_WVALID; + (* invertible_pin = "IS_AXI_04_ACLK_INVERTED" *) + input AXI_04_ACLK; + input [36:0] AXI_04_ARADDR; + input [1:0] AXI_04_ARBURST; + (* invertible_pin = "IS_AXI_04_ARESET_N_INVERTED" *) + input AXI_04_ARESET_N; + input [5:0] AXI_04_ARID; + input [3:0] AXI_04_ARLEN; + input [2:0] AXI_04_ARSIZE; + input AXI_04_ARVALID; + input [36:0] AXI_04_AWADDR; + input [1:0] AXI_04_AWBURST; + input [5:0] AXI_04_AWID; + input [3:0] AXI_04_AWLEN; + input [2:0] AXI_04_AWSIZE; + input AXI_04_AWVALID; + input AXI_04_BREADY; + input AXI_04_DFI_LP_PWR_X_REQ; + input AXI_04_RREADY; + input [255:0] AXI_04_WDATA; + input [31:0] AXI_04_WDATA_PARITY; + input AXI_04_WLAST; + input [31:0] AXI_04_WSTRB; + input AXI_04_WVALID; + (* invertible_pin = "IS_AXI_05_ACLK_INVERTED" *) + input AXI_05_ACLK; + input [36:0] AXI_05_ARADDR; + input [1:0] AXI_05_ARBURST; + (* invertible_pin = "IS_AXI_05_ARESET_N_INVERTED" *) + input AXI_05_ARESET_N; + input [5:0] AXI_05_ARID; + input [3:0] AXI_05_ARLEN; + input [2:0] AXI_05_ARSIZE; + input AXI_05_ARVALID; + input [36:0] AXI_05_AWADDR; + input [1:0] AXI_05_AWBURST; + input [5:0] AXI_05_AWID; + input [3:0] AXI_05_AWLEN; + input [2:0] AXI_05_AWSIZE; + input AXI_05_AWVALID; + input AXI_05_BREADY; + input AXI_05_DFI_LP_PWR_X_REQ; + input AXI_05_RREADY; + input [255:0] AXI_05_WDATA; + input [31:0] AXI_05_WDATA_PARITY; + input AXI_05_WLAST; + input [31:0] AXI_05_WSTRB; + input AXI_05_WVALID; + (* invertible_pin = "IS_AXI_06_ACLK_INVERTED" *) + input AXI_06_ACLK; + input [36:0] AXI_06_ARADDR; + input [1:0] AXI_06_ARBURST; + (* invertible_pin = "IS_AXI_06_ARESET_N_INVERTED" *) + input AXI_06_ARESET_N; + input [5:0] AXI_06_ARID; + input [3:0] AXI_06_ARLEN; + input [2:0] AXI_06_ARSIZE; + input AXI_06_ARVALID; + input [36:0] AXI_06_AWADDR; + input [1:0] AXI_06_AWBURST; + input [5:0] AXI_06_AWID; + input [3:0] AXI_06_AWLEN; + input [2:0] AXI_06_AWSIZE; + input AXI_06_AWVALID; + input AXI_06_BREADY; + input AXI_06_DFI_LP_PWR_X_REQ; + input AXI_06_RREADY; + input [255:0] AXI_06_WDATA; + input [31:0] AXI_06_WDATA_PARITY; + input AXI_06_WLAST; + input [31:0] AXI_06_WSTRB; + input AXI_06_WVALID; + (* invertible_pin = "IS_AXI_07_ACLK_INVERTED" *) + input AXI_07_ACLK; + input [36:0] AXI_07_ARADDR; + input [1:0] AXI_07_ARBURST; + (* invertible_pin = "IS_AXI_07_ARESET_N_INVERTED" *) + input AXI_07_ARESET_N; + input [5:0] AXI_07_ARID; + input [3:0] AXI_07_ARLEN; + input [2:0] AXI_07_ARSIZE; + input AXI_07_ARVALID; + input [36:0] AXI_07_AWADDR; + input [1:0] AXI_07_AWBURST; + input [5:0] AXI_07_AWID; + input [3:0] AXI_07_AWLEN; + input [2:0] AXI_07_AWSIZE; + input AXI_07_AWVALID; + input AXI_07_BREADY; + input AXI_07_DFI_LP_PWR_X_REQ; + input AXI_07_RREADY; + input [255:0] AXI_07_WDATA; + input [31:0] AXI_07_WDATA_PARITY; + input AXI_07_WLAST; + input [31:0] AXI_07_WSTRB; + input AXI_07_WVALID; + (* invertible_pin = "IS_AXI_08_ACLK_INVERTED" *) + input AXI_08_ACLK; + input [36:0] AXI_08_ARADDR; + input [1:0] AXI_08_ARBURST; + (* invertible_pin = "IS_AXI_08_ARESET_N_INVERTED" *) + input AXI_08_ARESET_N; + input [5:0] AXI_08_ARID; + input [3:0] AXI_08_ARLEN; + input [2:0] AXI_08_ARSIZE; + input AXI_08_ARVALID; + input [36:0] AXI_08_AWADDR; + input [1:0] AXI_08_AWBURST; + input [5:0] AXI_08_AWID; + input [3:0] AXI_08_AWLEN; + input [2:0] AXI_08_AWSIZE; + input AXI_08_AWVALID; + input AXI_08_BREADY; + input AXI_08_DFI_LP_PWR_X_REQ; + input AXI_08_RREADY; + input [255:0] AXI_08_WDATA; + input [31:0] AXI_08_WDATA_PARITY; + input AXI_08_WLAST; + input [31:0] AXI_08_WSTRB; + input AXI_08_WVALID; + (* invertible_pin = "IS_AXI_09_ACLK_INVERTED" *) + input AXI_09_ACLK; + input [36:0] AXI_09_ARADDR; + input [1:0] AXI_09_ARBURST; + (* invertible_pin = "IS_AXI_09_ARESET_N_INVERTED" *) + input AXI_09_ARESET_N; + input [5:0] AXI_09_ARID; + input [3:0] AXI_09_ARLEN; + input [2:0] AXI_09_ARSIZE; + input AXI_09_ARVALID; + input [36:0] AXI_09_AWADDR; + input [1:0] AXI_09_AWBURST; + input [5:0] AXI_09_AWID; + input [3:0] AXI_09_AWLEN; + input [2:0] AXI_09_AWSIZE; + input AXI_09_AWVALID; + input AXI_09_BREADY; + input AXI_09_DFI_LP_PWR_X_REQ; + input AXI_09_RREADY; + input [255:0] AXI_09_WDATA; + input [31:0] AXI_09_WDATA_PARITY; + input AXI_09_WLAST; + input [31:0] AXI_09_WSTRB; + input AXI_09_WVALID; + (* invertible_pin = "IS_AXI_10_ACLK_INVERTED" *) + input AXI_10_ACLK; + input [36:0] AXI_10_ARADDR; + input [1:0] AXI_10_ARBURST; + (* invertible_pin = "IS_AXI_10_ARESET_N_INVERTED" *) + input AXI_10_ARESET_N; + input [5:0] AXI_10_ARID; + input [3:0] AXI_10_ARLEN; + input [2:0] AXI_10_ARSIZE; + input AXI_10_ARVALID; + input [36:0] AXI_10_AWADDR; + input [1:0] AXI_10_AWBURST; + input [5:0] AXI_10_AWID; + input [3:0] AXI_10_AWLEN; + input [2:0] AXI_10_AWSIZE; + input AXI_10_AWVALID; + input AXI_10_BREADY; + input AXI_10_DFI_LP_PWR_X_REQ; + input AXI_10_RREADY; + input [255:0] AXI_10_WDATA; + input [31:0] AXI_10_WDATA_PARITY; + input AXI_10_WLAST; + input [31:0] AXI_10_WSTRB; + input AXI_10_WVALID; + (* invertible_pin = "IS_AXI_11_ACLK_INVERTED" *) + input AXI_11_ACLK; + input [36:0] AXI_11_ARADDR; + input [1:0] AXI_11_ARBURST; + (* invertible_pin = "IS_AXI_11_ARESET_N_INVERTED" *) + input AXI_11_ARESET_N; + input [5:0] AXI_11_ARID; + input [3:0] AXI_11_ARLEN; + input [2:0] AXI_11_ARSIZE; + input AXI_11_ARVALID; + input [36:0] AXI_11_AWADDR; + input [1:0] AXI_11_AWBURST; + input [5:0] AXI_11_AWID; + input [3:0] AXI_11_AWLEN; + input [2:0] AXI_11_AWSIZE; + input AXI_11_AWVALID; + input AXI_11_BREADY; + input AXI_11_DFI_LP_PWR_X_REQ; + input AXI_11_RREADY; + input [255:0] AXI_11_WDATA; + input [31:0] AXI_11_WDATA_PARITY; + input AXI_11_WLAST; + input [31:0] AXI_11_WSTRB; + input AXI_11_WVALID; + (* invertible_pin = "IS_AXI_12_ACLK_INVERTED" *) + input AXI_12_ACLK; + input [36:0] AXI_12_ARADDR; + input [1:0] AXI_12_ARBURST; + (* invertible_pin = "IS_AXI_12_ARESET_N_INVERTED" *) + input AXI_12_ARESET_N; + input [5:0] AXI_12_ARID; + input [3:0] AXI_12_ARLEN; + input [2:0] AXI_12_ARSIZE; + input AXI_12_ARVALID; + input [36:0] AXI_12_AWADDR; + input [1:0] AXI_12_AWBURST; + input [5:0] AXI_12_AWID; + input [3:0] AXI_12_AWLEN; + input [2:0] AXI_12_AWSIZE; + input AXI_12_AWVALID; + input AXI_12_BREADY; + input AXI_12_DFI_LP_PWR_X_REQ; + input AXI_12_RREADY; + input [255:0] AXI_12_WDATA; + input [31:0] AXI_12_WDATA_PARITY; + input AXI_12_WLAST; + input [31:0] AXI_12_WSTRB; + input AXI_12_WVALID; + (* invertible_pin = "IS_AXI_13_ACLK_INVERTED" *) + input AXI_13_ACLK; + input [36:0] AXI_13_ARADDR; + input [1:0] AXI_13_ARBURST; + (* invertible_pin = "IS_AXI_13_ARESET_N_INVERTED" *) + input AXI_13_ARESET_N; + input [5:0] AXI_13_ARID; + input [3:0] AXI_13_ARLEN; + input [2:0] AXI_13_ARSIZE; + input AXI_13_ARVALID; + input [36:0] AXI_13_AWADDR; + input [1:0] AXI_13_AWBURST; + input [5:0] AXI_13_AWID; + input [3:0] AXI_13_AWLEN; + input [2:0] AXI_13_AWSIZE; + input AXI_13_AWVALID; + input AXI_13_BREADY; + input AXI_13_DFI_LP_PWR_X_REQ; + input AXI_13_RREADY; + input [255:0] AXI_13_WDATA; + input [31:0] AXI_13_WDATA_PARITY; + input AXI_13_WLAST; + input [31:0] AXI_13_WSTRB; + input AXI_13_WVALID; + (* invertible_pin = "IS_AXI_14_ACLK_INVERTED" *) + input AXI_14_ACLK; + input [36:0] AXI_14_ARADDR; + input [1:0] AXI_14_ARBURST; + (* invertible_pin = "IS_AXI_14_ARESET_N_INVERTED" *) + input AXI_14_ARESET_N; + input [5:0] AXI_14_ARID; + input [3:0] AXI_14_ARLEN; + input [2:0] AXI_14_ARSIZE; + input AXI_14_ARVALID; + input [36:0] AXI_14_AWADDR; + input [1:0] AXI_14_AWBURST; + input [5:0] AXI_14_AWID; + input [3:0] AXI_14_AWLEN; + input [2:0] AXI_14_AWSIZE; + input AXI_14_AWVALID; + input AXI_14_BREADY; + input AXI_14_DFI_LP_PWR_X_REQ; + input AXI_14_RREADY; + input [255:0] AXI_14_WDATA; + input [31:0] AXI_14_WDATA_PARITY; + input AXI_14_WLAST; + input [31:0] AXI_14_WSTRB; + input AXI_14_WVALID; + (* invertible_pin = "IS_AXI_15_ACLK_INVERTED" *) + input AXI_15_ACLK; + input [36:0] AXI_15_ARADDR; + input [1:0] AXI_15_ARBURST; + (* invertible_pin = "IS_AXI_15_ARESET_N_INVERTED" *) + input AXI_15_ARESET_N; + input [5:0] AXI_15_ARID; + input [3:0] AXI_15_ARLEN; + input [2:0] AXI_15_ARSIZE; + input AXI_15_ARVALID; + input [36:0] AXI_15_AWADDR; + input [1:0] AXI_15_AWBURST; + input [5:0] AXI_15_AWID; + input [3:0] AXI_15_AWLEN; + input [2:0] AXI_15_AWSIZE; + input AXI_15_AWVALID; + input AXI_15_BREADY; + input AXI_15_DFI_LP_PWR_X_REQ; + input AXI_15_RREADY; + input [255:0] AXI_15_WDATA; + input [31:0] AXI_15_WDATA_PARITY; + input AXI_15_WLAST; + input [31:0] AXI_15_WSTRB; + input AXI_15_WVALID; + (* invertible_pin = "IS_AXI_16_ACLK_INVERTED" *) + input AXI_16_ACLK; + input [36:0] AXI_16_ARADDR; + input [1:0] AXI_16_ARBURST; + (* invertible_pin = "IS_AXI_16_ARESET_N_INVERTED" *) + input AXI_16_ARESET_N; + input [5:0] AXI_16_ARID; + input [3:0] AXI_16_ARLEN; + input [2:0] AXI_16_ARSIZE; + input AXI_16_ARVALID; + input [36:0] AXI_16_AWADDR; + input [1:0] AXI_16_AWBURST; + input [5:0] AXI_16_AWID; + input [3:0] AXI_16_AWLEN; + input [2:0] AXI_16_AWSIZE; + input AXI_16_AWVALID; + input AXI_16_BREADY; + input AXI_16_DFI_LP_PWR_X_REQ; + input AXI_16_RREADY; + input [255:0] AXI_16_WDATA; + input [31:0] AXI_16_WDATA_PARITY; + input AXI_16_WLAST; + input [31:0] AXI_16_WSTRB; + input AXI_16_WVALID; + (* invertible_pin = "IS_AXI_17_ACLK_INVERTED" *) + input AXI_17_ACLK; + input [36:0] AXI_17_ARADDR; + input [1:0] AXI_17_ARBURST; + (* invertible_pin = "IS_AXI_17_ARESET_N_INVERTED" *) + input AXI_17_ARESET_N; + input [5:0] AXI_17_ARID; + input [3:0] AXI_17_ARLEN; + input [2:0] AXI_17_ARSIZE; + input AXI_17_ARVALID; + input [36:0] AXI_17_AWADDR; + input [1:0] AXI_17_AWBURST; + input [5:0] AXI_17_AWID; + input [3:0] AXI_17_AWLEN; + input [2:0] AXI_17_AWSIZE; + input AXI_17_AWVALID; + input AXI_17_BREADY; + input AXI_17_DFI_LP_PWR_X_REQ; + input AXI_17_RREADY; + input [255:0] AXI_17_WDATA; + input [31:0] AXI_17_WDATA_PARITY; + input AXI_17_WLAST; + input [31:0] AXI_17_WSTRB; + input AXI_17_WVALID; + (* invertible_pin = "IS_AXI_18_ACLK_INVERTED" *) + input AXI_18_ACLK; + input [36:0] AXI_18_ARADDR; + input [1:0] AXI_18_ARBURST; + (* invertible_pin = "IS_AXI_18_ARESET_N_INVERTED" *) + input AXI_18_ARESET_N; + input [5:0] AXI_18_ARID; + input [3:0] AXI_18_ARLEN; + input [2:0] AXI_18_ARSIZE; + input AXI_18_ARVALID; + input [36:0] AXI_18_AWADDR; + input [1:0] AXI_18_AWBURST; + input [5:0] AXI_18_AWID; + input [3:0] AXI_18_AWLEN; + input [2:0] AXI_18_AWSIZE; + input AXI_18_AWVALID; + input AXI_18_BREADY; + input AXI_18_DFI_LP_PWR_X_REQ; + input AXI_18_RREADY; + input [255:0] AXI_18_WDATA; + input [31:0] AXI_18_WDATA_PARITY; + input AXI_18_WLAST; + input [31:0] AXI_18_WSTRB; + input AXI_18_WVALID; + (* invertible_pin = "IS_AXI_19_ACLK_INVERTED" *) + input AXI_19_ACLK; + input [36:0] AXI_19_ARADDR; + input [1:0] AXI_19_ARBURST; + (* invertible_pin = "IS_AXI_19_ARESET_N_INVERTED" *) + input AXI_19_ARESET_N; + input [5:0] AXI_19_ARID; + input [3:0] AXI_19_ARLEN; + input [2:0] AXI_19_ARSIZE; + input AXI_19_ARVALID; + input [36:0] AXI_19_AWADDR; + input [1:0] AXI_19_AWBURST; + input [5:0] AXI_19_AWID; + input [3:0] AXI_19_AWLEN; + input [2:0] AXI_19_AWSIZE; + input AXI_19_AWVALID; + input AXI_19_BREADY; + input AXI_19_DFI_LP_PWR_X_REQ; + input AXI_19_RREADY; + input [255:0] AXI_19_WDATA; + input [31:0] AXI_19_WDATA_PARITY; + input AXI_19_WLAST; + input [31:0] AXI_19_WSTRB; + input AXI_19_WVALID; + (* invertible_pin = "IS_AXI_20_ACLK_INVERTED" *) + input AXI_20_ACLK; + input [36:0] AXI_20_ARADDR; + input [1:0] AXI_20_ARBURST; + (* invertible_pin = "IS_AXI_20_ARESET_N_INVERTED" *) + input AXI_20_ARESET_N; + input [5:0] AXI_20_ARID; + input [3:0] AXI_20_ARLEN; + input [2:0] AXI_20_ARSIZE; + input AXI_20_ARVALID; + input [36:0] AXI_20_AWADDR; + input [1:0] AXI_20_AWBURST; + input [5:0] AXI_20_AWID; + input [3:0] AXI_20_AWLEN; + input [2:0] AXI_20_AWSIZE; + input AXI_20_AWVALID; + input AXI_20_BREADY; + input AXI_20_DFI_LP_PWR_X_REQ; + input AXI_20_RREADY; + input [255:0] AXI_20_WDATA; + input [31:0] AXI_20_WDATA_PARITY; + input AXI_20_WLAST; + input [31:0] AXI_20_WSTRB; + input AXI_20_WVALID; + (* invertible_pin = "IS_AXI_21_ACLK_INVERTED" *) + input AXI_21_ACLK; + input [36:0] AXI_21_ARADDR; + input [1:0] AXI_21_ARBURST; + (* invertible_pin = "IS_AXI_21_ARESET_N_INVERTED" *) + input AXI_21_ARESET_N; + input [5:0] AXI_21_ARID; + input [3:0] AXI_21_ARLEN; + input [2:0] AXI_21_ARSIZE; + input AXI_21_ARVALID; + input [36:0] AXI_21_AWADDR; + input [1:0] AXI_21_AWBURST; + input [5:0] AXI_21_AWID; + input [3:0] AXI_21_AWLEN; + input [2:0] AXI_21_AWSIZE; + input AXI_21_AWVALID; + input AXI_21_BREADY; + input AXI_21_DFI_LP_PWR_X_REQ; + input AXI_21_RREADY; + input [255:0] AXI_21_WDATA; + input [31:0] AXI_21_WDATA_PARITY; + input AXI_21_WLAST; + input [31:0] AXI_21_WSTRB; + input AXI_21_WVALID; + (* invertible_pin = "IS_AXI_22_ACLK_INVERTED" *) + input AXI_22_ACLK; + input [36:0] AXI_22_ARADDR; + input [1:0] AXI_22_ARBURST; + (* invertible_pin = "IS_AXI_22_ARESET_N_INVERTED" *) + input AXI_22_ARESET_N; + input [5:0] AXI_22_ARID; + input [3:0] AXI_22_ARLEN; + input [2:0] AXI_22_ARSIZE; + input AXI_22_ARVALID; + input [36:0] AXI_22_AWADDR; + input [1:0] AXI_22_AWBURST; + input [5:0] AXI_22_AWID; + input [3:0] AXI_22_AWLEN; + input [2:0] AXI_22_AWSIZE; + input AXI_22_AWVALID; + input AXI_22_BREADY; + input AXI_22_DFI_LP_PWR_X_REQ; + input AXI_22_RREADY; + input [255:0] AXI_22_WDATA; + input [31:0] AXI_22_WDATA_PARITY; + input AXI_22_WLAST; + input [31:0] AXI_22_WSTRB; + input AXI_22_WVALID; + (* invertible_pin = "IS_AXI_23_ACLK_INVERTED" *) + input AXI_23_ACLK; + input [36:0] AXI_23_ARADDR; + input [1:0] AXI_23_ARBURST; + (* invertible_pin = "IS_AXI_23_ARESET_N_INVERTED" *) + input AXI_23_ARESET_N; + input [5:0] AXI_23_ARID; + input [3:0] AXI_23_ARLEN; + input [2:0] AXI_23_ARSIZE; + input AXI_23_ARVALID; + input [36:0] AXI_23_AWADDR; + input [1:0] AXI_23_AWBURST; + input [5:0] AXI_23_AWID; + input [3:0] AXI_23_AWLEN; + input [2:0] AXI_23_AWSIZE; + input AXI_23_AWVALID; + input AXI_23_BREADY; + input AXI_23_DFI_LP_PWR_X_REQ; + input AXI_23_RREADY; + input [255:0] AXI_23_WDATA; + input [31:0] AXI_23_WDATA_PARITY; + input AXI_23_WLAST; + input [31:0] AXI_23_WSTRB; + input AXI_23_WVALID; + (* invertible_pin = "IS_AXI_24_ACLK_INVERTED" *) + input AXI_24_ACLK; + input [36:0] AXI_24_ARADDR; + input [1:0] AXI_24_ARBURST; + (* invertible_pin = "IS_AXI_24_ARESET_N_INVERTED" *) + input AXI_24_ARESET_N; + input [5:0] AXI_24_ARID; + input [3:0] AXI_24_ARLEN; + input [2:0] AXI_24_ARSIZE; + input AXI_24_ARVALID; + input [36:0] AXI_24_AWADDR; + input [1:0] AXI_24_AWBURST; + input [5:0] AXI_24_AWID; + input [3:0] AXI_24_AWLEN; + input [2:0] AXI_24_AWSIZE; + input AXI_24_AWVALID; + input AXI_24_BREADY; + input AXI_24_DFI_LP_PWR_X_REQ; + input AXI_24_RREADY; + input [255:0] AXI_24_WDATA; + input [31:0] AXI_24_WDATA_PARITY; + input AXI_24_WLAST; + input [31:0] AXI_24_WSTRB; + input AXI_24_WVALID; + (* invertible_pin = "IS_AXI_25_ACLK_INVERTED" *) + input AXI_25_ACLK; + input [36:0] AXI_25_ARADDR; + input [1:0] AXI_25_ARBURST; + (* invertible_pin = "IS_AXI_25_ARESET_N_INVERTED" *) + input AXI_25_ARESET_N; + input [5:0] AXI_25_ARID; + input [3:0] AXI_25_ARLEN; + input [2:0] AXI_25_ARSIZE; + input AXI_25_ARVALID; + input [36:0] AXI_25_AWADDR; + input [1:0] AXI_25_AWBURST; + input [5:0] AXI_25_AWID; + input [3:0] AXI_25_AWLEN; + input [2:0] AXI_25_AWSIZE; + input AXI_25_AWVALID; + input AXI_25_BREADY; + input AXI_25_DFI_LP_PWR_X_REQ; + input AXI_25_RREADY; + input [255:0] AXI_25_WDATA; + input [31:0] AXI_25_WDATA_PARITY; + input AXI_25_WLAST; + input [31:0] AXI_25_WSTRB; + input AXI_25_WVALID; + (* invertible_pin = "IS_AXI_26_ACLK_INVERTED" *) + input AXI_26_ACLK; + input [36:0] AXI_26_ARADDR; + input [1:0] AXI_26_ARBURST; + (* invertible_pin = "IS_AXI_26_ARESET_N_INVERTED" *) + input AXI_26_ARESET_N; + input [5:0] AXI_26_ARID; + input [3:0] AXI_26_ARLEN; + input [2:0] AXI_26_ARSIZE; + input AXI_26_ARVALID; + input [36:0] AXI_26_AWADDR; + input [1:0] AXI_26_AWBURST; + input [5:0] AXI_26_AWID; + input [3:0] AXI_26_AWLEN; + input [2:0] AXI_26_AWSIZE; + input AXI_26_AWVALID; + input AXI_26_BREADY; + input AXI_26_DFI_LP_PWR_X_REQ; + input AXI_26_RREADY; + input [255:0] AXI_26_WDATA; + input [31:0] AXI_26_WDATA_PARITY; + input AXI_26_WLAST; + input [31:0] AXI_26_WSTRB; + input AXI_26_WVALID; + (* invertible_pin = "IS_AXI_27_ACLK_INVERTED" *) + input AXI_27_ACLK; + input [36:0] AXI_27_ARADDR; + input [1:0] AXI_27_ARBURST; + (* invertible_pin = "IS_AXI_27_ARESET_N_INVERTED" *) + input AXI_27_ARESET_N; + input [5:0] AXI_27_ARID; + input [3:0] AXI_27_ARLEN; + input [2:0] AXI_27_ARSIZE; + input AXI_27_ARVALID; + input [36:0] AXI_27_AWADDR; + input [1:0] AXI_27_AWBURST; + input [5:0] AXI_27_AWID; + input [3:0] AXI_27_AWLEN; + input [2:0] AXI_27_AWSIZE; + input AXI_27_AWVALID; + input AXI_27_BREADY; + input AXI_27_DFI_LP_PWR_X_REQ; + input AXI_27_RREADY; + input [255:0] AXI_27_WDATA; + input [31:0] AXI_27_WDATA_PARITY; + input AXI_27_WLAST; + input [31:0] AXI_27_WSTRB; + input AXI_27_WVALID; + (* invertible_pin = "IS_AXI_28_ACLK_INVERTED" *) + input AXI_28_ACLK; + input [36:0] AXI_28_ARADDR; + input [1:0] AXI_28_ARBURST; + (* invertible_pin = "IS_AXI_28_ARESET_N_INVERTED" *) + input AXI_28_ARESET_N; + input [5:0] AXI_28_ARID; + input [3:0] AXI_28_ARLEN; + input [2:0] AXI_28_ARSIZE; + input AXI_28_ARVALID; + input [36:0] AXI_28_AWADDR; + input [1:0] AXI_28_AWBURST; + input [5:0] AXI_28_AWID; + input [3:0] AXI_28_AWLEN; + input [2:0] AXI_28_AWSIZE; + input AXI_28_AWVALID; + input AXI_28_BREADY; + input AXI_28_DFI_LP_PWR_X_REQ; + input AXI_28_RREADY; + input [255:0] AXI_28_WDATA; + input [31:0] AXI_28_WDATA_PARITY; + input AXI_28_WLAST; + input [31:0] AXI_28_WSTRB; + input AXI_28_WVALID; + (* invertible_pin = "IS_AXI_29_ACLK_INVERTED" *) + input AXI_29_ACLK; + input [36:0] AXI_29_ARADDR; + input [1:0] AXI_29_ARBURST; + (* invertible_pin = "IS_AXI_29_ARESET_N_INVERTED" *) + input AXI_29_ARESET_N; + input [5:0] AXI_29_ARID; + input [3:0] AXI_29_ARLEN; + input [2:0] AXI_29_ARSIZE; + input AXI_29_ARVALID; + input [36:0] AXI_29_AWADDR; + input [1:0] AXI_29_AWBURST; + input [5:0] AXI_29_AWID; + input [3:0] AXI_29_AWLEN; + input [2:0] AXI_29_AWSIZE; + input AXI_29_AWVALID; + input AXI_29_BREADY; + input AXI_29_DFI_LP_PWR_X_REQ; + input AXI_29_RREADY; + input [255:0] AXI_29_WDATA; + input [31:0] AXI_29_WDATA_PARITY; + input AXI_29_WLAST; + input [31:0] AXI_29_WSTRB; + input AXI_29_WVALID; + (* invertible_pin = "IS_AXI_30_ACLK_INVERTED" *) + input AXI_30_ACLK; + input [36:0] AXI_30_ARADDR; + input [1:0] AXI_30_ARBURST; + (* invertible_pin = "IS_AXI_30_ARESET_N_INVERTED" *) + input AXI_30_ARESET_N; + input [5:0] AXI_30_ARID; + input [3:0] AXI_30_ARLEN; + input [2:0] AXI_30_ARSIZE; + input AXI_30_ARVALID; + input [36:0] AXI_30_AWADDR; + input [1:0] AXI_30_AWBURST; + input [5:0] AXI_30_AWID; + input [3:0] AXI_30_AWLEN; + input [2:0] AXI_30_AWSIZE; + input AXI_30_AWVALID; + input AXI_30_BREADY; + input AXI_30_DFI_LP_PWR_X_REQ; + input AXI_30_RREADY; + input [255:0] AXI_30_WDATA; + input [31:0] AXI_30_WDATA_PARITY; + input AXI_30_WLAST; + input [31:0] AXI_30_WSTRB; + input AXI_30_WVALID; + (* invertible_pin = "IS_AXI_31_ACLK_INVERTED" *) + input AXI_31_ACLK; + input [36:0] AXI_31_ARADDR; + input [1:0] AXI_31_ARBURST; + (* invertible_pin = "IS_AXI_31_ARESET_N_INVERTED" *) + input AXI_31_ARESET_N; + input [5:0] AXI_31_ARID; + input [3:0] AXI_31_ARLEN; + input [2:0] AXI_31_ARSIZE; + input AXI_31_ARVALID; + input [36:0] AXI_31_AWADDR; + input [1:0] AXI_31_AWBURST; + input [5:0] AXI_31_AWID; + input [3:0] AXI_31_AWLEN; + input [2:0] AXI_31_AWSIZE; + input AXI_31_AWVALID; + input AXI_31_BREADY; + input AXI_31_DFI_LP_PWR_X_REQ; + input AXI_31_RREADY; + input [255:0] AXI_31_WDATA; + input [31:0] AXI_31_WDATA_PARITY; + input AXI_31_WLAST; + input [31:0] AXI_31_WSTRB; + input AXI_31_WVALID; + input BSCAN_DRCK_0; + input BSCAN_DRCK_1; + input BSCAN_TCK_0; + input BSCAN_TCK_1; + input HBM_REF_CLK_0; + input HBM_REF_CLK_1; + input MBIST_EN_00; + input MBIST_EN_01; + input MBIST_EN_02; + input MBIST_EN_03; + input MBIST_EN_04; + input MBIST_EN_05; + input MBIST_EN_06; + input MBIST_EN_07; + input MBIST_EN_08; + input MBIST_EN_09; + input MBIST_EN_10; + input MBIST_EN_11; + input MBIST_EN_12; + input MBIST_EN_13; + input MBIST_EN_14; + input MBIST_EN_15; +endmodule + module PPC405_ADV (...); parameter in_delay=100; parameter out_delay=100; @@ -25658,269 +31011,6 @@ module PPC440 (...); input [28:31] TIEC440PVR; endmodule -module MCB (...); - parameter integer ARB_NUM_TIME_SLOTS = 12; - parameter [17:0] ARB_TIME_SLOT_0 = 18'b111111111111111111; - parameter [17:0] ARB_TIME_SLOT_1 = 18'b111111111111111111; - parameter [17:0] ARB_TIME_SLOT_10 = 18'b111111111111111111; - parameter [17:0] ARB_TIME_SLOT_11 = 18'b111111111111111111; - parameter [17:0] ARB_TIME_SLOT_2 = 18'b111111111111111111; - parameter [17:0] ARB_TIME_SLOT_3 = 18'b111111111111111111; - parameter [17:0] ARB_TIME_SLOT_4 = 18'b111111111111111111; - parameter [17:0] ARB_TIME_SLOT_5 = 18'b111111111111111111; - parameter [17:0] ARB_TIME_SLOT_6 = 18'b111111111111111111; - parameter [17:0] ARB_TIME_SLOT_7 = 18'b111111111111111111; - parameter [17:0] ARB_TIME_SLOT_8 = 18'b111111111111111111; - parameter [17:0] ARB_TIME_SLOT_9 = 18'b111111111111111111; - parameter [2:0] CAL_BA = 3'h0; - parameter CAL_BYPASS = "YES"; - parameter [11:0] CAL_CA = 12'h000; - parameter CAL_CALIBRATION_MODE = "NOCALIBRATION"; - parameter integer CAL_CLK_DIV = 1; - parameter CAL_DELAY = "QUARTER"; - parameter [14:0] CAL_RA = 15'h0000; - parameter MEM_ADDR_ORDER = "BANK_ROW_COLUMN"; - parameter integer MEM_BA_SIZE = 3; - parameter integer MEM_BURST_LEN = 8; - parameter integer MEM_CAS_LATENCY = 4; - parameter integer MEM_CA_SIZE = 11; - parameter MEM_DDR1_2_ODS = "FULL"; - parameter MEM_DDR2_3_HIGH_TEMP_SR = "NORMAL"; - parameter MEM_DDR2_3_PA_SR = "FULL"; - parameter integer MEM_DDR2_ADD_LATENCY = 0; - parameter MEM_DDR2_DIFF_DQS_EN = "YES"; - parameter MEM_DDR2_RTT = "50OHMS"; - parameter integer MEM_DDR2_WRT_RECOVERY = 4; - parameter MEM_DDR3_ADD_LATENCY = "OFF"; - parameter MEM_DDR3_AUTO_SR = "ENABLED"; - parameter integer MEM_DDR3_CAS_LATENCY = 7; - parameter integer MEM_DDR3_CAS_WR_LATENCY = 5; - parameter MEM_DDR3_DYN_WRT_ODT = "OFF"; - parameter MEM_DDR3_ODS = "DIV7"; - parameter MEM_DDR3_RTT = "DIV2"; - parameter integer MEM_DDR3_WRT_RECOVERY = 7; - parameter MEM_MDDR_ODS = "FULL"; - parameter MEM_MOBILE_PA_SR = "FULL"; - parameter integer MEM_MOBILE_TC_SR = 0; - parameter integer MEM_RAS_VAL = 0; - parameter integer MEM_RA_SIZE = 13; - parameter integer MEM_RCD_VAL = 1; - parameter integer MEM_REFI_VAL = 0; - parameter integer MEM_RFC_VAL = 0; - parameter integer MEM_RP_VAL = 0; - parameter integer MEM_RTP_VAL = 0; - parameter MEM_TYPE = "DDR3"; - parameter integer MEM_WIDTH = 4; - parameter integer MEM_WR_VAL = 0; - parameter integer MEM_WTR_VAL = 3; - parameter PORT_CONFIG = "B32_B32_B32_B32"; - output CAS; - output CKE; - output DQIOWEN0; - output DQSIOWEN90N; - output DQSIOWEN90P; - output IOIDRPADD; - output IOIDRPBROADCAST; - output IOIDRPCLK; - output IOIDRPCS; - output IOIDRPSDO; - output IOIDRPTRAIN; - output IOIDRPUPDATE; - output LDMN; - output LDMP; - output ODT; - output P0CMDEMPTY; - output P0CMDFULL; - output P0RDEMPTY; - output P0RDERROR; - output P0RDFULL; - output P0RDOVERFLOW; - output P0WREMPTY; - output P0WRERROR; - output P0WRFULL; - output P0WRUNDERRUN; - output P1CMDEMPTY; - output P1CMDFULL; - output P1RDEMPTY; - output P1RDERROR; - output P1RDFULL; - output P1RDOVERFLOW; - output P1WREMPTY; - output P1WRERROR; - output P1WRFULL; - output P1WRUNDERRUN; - output P2CMDEMPTY; - output P2CMDFULL; - output P2EMPTY; - output P2ERROR; - output P2FULL; - output P2RDOVERFLOW; - output P2WRUNDERRUN; - output P3CMDEMPTY; - output P3CMDFULL; - output P3EMPTY; - output P3ERROR; - output P3FULL; - output P3RDOVERFLOW; - output P3WRUNDERRUN; - output P4CMDEMPTY; - output P4CMDFULL; - output P4EMPTY; - output P4ERROR; - output P4FULL; - output P4RDOVERFLOW; - output P4WRUNDERRUN; - output P5CMDEMPTY; - output P5CMDFULL; - output P5EMPTY; - output P5ERROR; - output P5FULL; - output P5RDOVERFLOW; - output P5WRUNDERRUN; - output RAS; - output RST; - output SELFREFRESHMODE; - output UDMN; - output UDMP; - output UOCALSTART; - output UOCMDREADYIN; - output UODATAVALID; - output UODONECAL; - output UOREFRSHFLAG; - output UOSDO; - output WE; - output [14:0] ADDR; - output [15:0] DQON; - output [15:0] DQOP; - output [2:0] BA; - output [31:0] P0RDDATA; - output [31:0] P1RDDATA; - output [31:0] P2RDDATA; - output [31:0] P3RDDATA; - output [31:0] P4RDDATA; - output [31:0] P5RDDATA; - output [31:0] STATUS; - output [4:0] IOIDRPADDR; - output [6:0] P0RDCOUNT; - output [6:0] P0WRCOUNT; - output [6:0] P1RDCOUNT; - output [6:0] P1WRCOUNT; - output [6:0] P2COUNT; - output [6:0] P3COUNT; - output [6:0] P4COUNT; - output [6:0] P5COUNT; - output [7:0] UODATA; - input DQSIOIN; - input DQSIOIP; - input IOIDRPSDI; - input P0ARBEN; - input P0CMDCLK; - input P0CMDEN; - input P0RDCLK; - input P0RDEN; - input P0WRCLK; - input P0WREN; - input P1ARBEN; - input P1CMDCLK; - input P1CMDEN; - input P1RDCLK; - input P1RDEN; - input P1WRCLK; - input P1WREN; - input P2ARBEN; - input P2CLK; - input P2CMDCLK; - input P2CMDEN; - input P2EN; - input P3ARBEN; - input P3CLK; - input P3CMDCLK; - input P3CMDEN; - input P3EN; - input P4ARBEN; - input P4CLK; - input P4CMDCLK; - input P4CMDEN; - input P4EN; - input P5ARBEN; - input P5CLK; - input P5CMDCLK; - input P5CMDEN; - input P5EN; - input PLLLOCK; - input RECAL; - input SELFREFRESHENTER; - input SYSRST; - input UDQSIOIN; - input UDQSIOIP; - input UIADD; - input UIBROADCAST; - input UICLK; - input UICMD; - input UICMDEN; - input UICMDIN; - input UICS; - input UIDONECAL; - input UIDQLOWERDEC; - input UIDQLOWERINC; - input UIDQUPPERDEC; - input UIDQUPPERINC; - input UIDRPUPDATE; - input UILDQSDEC; - input UILDQSINC; - input UIREAD; - input UISDI; - input UIUDQSDEC; - input UIUDQSINC; - input [11:0] P0CMDCA; - input [11:0] P1CMDCA; - input [11:0] P2CMDCA; - input [11:0] P3CMDCA; - input [11:0] P4CMDCA; - input [11:0] P5CMDCA; - input [14:0] P0CMDRA; - input [14:0] P1CMDRA; - input [14:0] P2CMDRA; - input [14:0] P3CMDRA; - input [14:0] P4CMDRA; - input [14:0] P5CMDRA; - input [15:0] DQI; - input [1:0] PLLCE; - input [1:0] PLLCLK; - input [2:0] P0CMDBA; - input [2:0] P0CMDINSTR; - input [2:0] P1CMDBA; - input [2:0] P1CMDINSTR; - input [2:0] P2CMDBA; - input [2:0] P2CMDINSTR; - input [2:0] P3CMDBA; - input [2:0] P3CMDINSTR; - input [2:0] P4CMDBA; - input [2:0] P4CMDINSTR; - input [2:0] P5CMDBA; - input [2:0] P5CMDINSTR; - input [31:0] P0WRDATA; - input [31:0] P1WRDATA; - input [31:0] P2WRDATA; - input [31:0] P3WRDATA; - input [31:0] P4WRDATA; - input [31:0] P5WRDATA; - input [3:0] P0RWRMASK; - input [3:0] P1RWRMASK; - input [3:0] P2WRMASK; - input [3:0] P3WRMASK; - input [3:0] P4WRMASK; - input [3:0] P5WRMASK; - input [3:0] UIDQCOUNT; - input [4:0] UIADDR; - input [5:0] P0CMDBL; - input [5:0] P1CMDBL; - input [5:0] P2CMDBL; - input [5:0] P3CMDBL; - input [5:0] P4CMDBL; - input [5:0] P5CMDBL; -endmodule - (* keep *) module PS7 (...); output DMA0DAVALID; @@ -28054,3 +33144,297 @@ module ILKNE4 (...); input TX_SOPIN3; endmodule +(* keep *) +module VCU (...); + parameter integer CORECLKREQ = 667; + parameter integer DECHORRESOLUTION = 3840; + parameter DECODERCHROMAFORMAT = "4_2_2"; + parameter DECODERCODING = "H.265"; + parameter integer DECODERCOLORDEPTH = 10; + parameter integer DECODERNUMCORES = 2; + parameter integer DECVERTRESOLUTION = 2160; + parameter ENABLEDECODER = "TRUE"; + parameter ENABLEENCODER = "TRUE"; + parameter integer ENCHORRESOLUTION = 3840; + parameter ENCODERCHROMAFORMAT = "4_2_2"; + parameter ENCODERCODING = "H.265"; + parameter integer ENCODERCOLORDEPTH = 10; + parameter integer ENCODERNUMCORES = 4; + parameter integer ENCVERTRESOLUTION = 2160; + output VCUPLARREADYAXILITEAPB; + output VCUPLAWREADYAXILITEAPB; + output [1:0] VCUPLBRESPAXILITEAPB; + output VCUPLBVALIDAXILITEAPB; + output VCUPLCORESTATUSCLKPLL; + output [43:0] VCUPLDECARADDR0; + output [43:0] VCUPLDECARADDR1; + output [1:0] VCUPLDECARBURST0; + output [1:0] VCUPLDECARBURST1; + output [3:0] VCUPLDECARCACHE0; + output [3:0] VCUPLDECARCACHE1; + output [3:0] VCUPLDECARID0; + output [3:0] VCUPLDECARID1; + output [7:0] VCUPLDECARLEN0; + output [7:0] VCUPLDECARLEN1; + output VCUPLDECARPROT0; + output VCUPLDECARPROT1; + output [3:0] VCUPLDECARQOS0; + output [3:0] VCUPLDECARQOS1; + output [2:0] VCUPLDECARSIZE0; + output [2:0] VCUPLDECARSIZE1; + output VCUPLDECARVALID0; + output VCUPLDECARVALID1; + output [43:0] VCUPLDECAWADDR0; + output [43:0] VCUPLDECAWADDR1; + output [1:0] VCUPLDECAWBURST0; + output [1:0] VCUPLDECAWBURST1; + output [3:0] VCUPLDECAWCACHE0; + output [3:0] VCUPLDECAWCACHE1; + output [3:0] VCUPLDECAWID0; + output [3:0] VCUPLDECAWID1; + output [7:0] VCUPLDECAWLEN0; + output [7:0] VCUPLDECAWLEN1; + output VCUPLDECAWPROT0; + output VCUPLDECAWPROT1; + output [3:0] VCUPLDECAWQOS0; + output [3:0] VCUPLDECAWQOS1; + output [2:0] VCUPLDECAWSIZE0; + output [2:0] VCUPLDECAWSIZE1; + output VCUPLDECAWVALID0; + output VCUPLDECAWVALID1; + output VCUPLDECBREADY0; + output VCUPLDECBREADY1; + output VCUPLDECRREADY0; + output VCUPLDECRREADY1; + output [127:0] VCUPLDECWDATA0; + output [127:0] VCUPLDECWDATA1; + output VCUPLDECWLAST0; + output VCUPLDECWLAST1; + output VCUPLDECWVALID0; + output VCUPLDECWVALID1; + output [16:0] VCUPLENCALL2CADDR; + output VCUPLENCALL2CRVALID; + output [319:0] VCUPLENCALL2CWDATA; + output VCUPLENCALL2CWVALID; + output [43:0] VCUPLENCARADDR0; + output [43:0] VCUPLENCARADDR1; + output [1:0] VCUPLENCARBURST0; + output [1:0] VCUPLENCARBURST1; + output [3:0] VCUPLENCARCACHE0; + output [3:0] VCUPLENCARCACHE1; + output [3:0] VCUPLENCARID0; + output [3:0] VCUPLENCARID1; + output [7:0] VCUPLENCARLEN0; + output [7:0] VCUPLENCARLEN1; + output VCUPLENCARPROT0; + output VCUPLENCARPROT1; + output [3:0] VCUPLENCARQOS0; + output [3:0] VCUPLENCARQOS1; + output [2:0] VCUPLENCARSIZE0; + output [2:0] VCUPLENCARSIZE1; + output VCUPLENCARVALID0; + output VCUPLENCARVALID1; + output [43:0] VCUPLENCAWADDR0; + output [43:0] VCUPLENCAWADDR1; + output [1:0] VCUPLENCAWBURST0; + output [1:0] VCUPLENCAWBURST1; + output [3:0] VCUPLENCAWCACHE0; + output [3:0] VCUPLENCAWCACHE1; + output [3:0] VCUPLENCAWID0; + output [3:0] VCUPLENCAWID1; + output [7:0] VCUPLENCAWLEN0; + output [7:0] VCUPLENCAWLEN1; + output VCUPLENCAWPROT0; + output VCUPLENCAWPROT1; + output [3:0] VCUPLENCAWQOS0; + output [3:0] VCUPLENCAWQOS1; + output [2:0] VCUPLENCAWSIZE0; + output [2:0] VCUPLENCAWSIZE1; + output VCUPLENCAWVALID0; + output VCUPLENCAWVALID1; + output VCUPLENCBREADY0; + output VCUPLENCBREADY1; + output VCUPLENCRREADY0; + output VCUPLENCRREADY1; + output [127:0] VCUPLENCWDATA0; + output [127:0] VCUPLENCWDATA1; + output VCUPLENCWLAST0; + output VCUPLENCWLAST1; + output VCUPLENCWVALID0; + output VCUPLENCWVALID1; + output [43:0] VCUPLMCUMAXIICDCARADDR; + output [1:0] VCUPLMCUMAXIICDCARBURST; + output [3:0] VCUPLMCUMAXIICDCARCACHE; + output [2:0] VCUPLMCUMAXIICDCARID; + output [7:0] VCUPLMCUMAXIICDCARLEN; + output VCUPLMCUMAXIICDCARLOCK; + output [2:0] VCUPLMCUMAXIICDCARPROT; + output [3:0] VCUPLMCUMAXIICDCARQOS; + output [2:0] VCUPLMCUMAXIICDCARSIZE; + output VCUPLMCUMAXIICDCARVALID; + output [43:0] VCUPLMCUMAXIICDCAWADDR; + output [1:0] VCUPLMCUMAXIICDCAWBURST; + output [3:0] VCUPLMCUMAXIICDCAWCACHE; + output [2:0] VCUPLMCUMAXIICDCAWID; + output [7:0] VCUPLMCUMAXIICDCAWLEN; + output VCUPLMCUMAXIICDCAWLOCK; + output [2:0] VCUPLMCUMAXIICDCAWPROT; + output [3:0] VCUPLMCUMAXIICDCAWQOS; + output [2:0] VCUPLMCUMAXIICDCAWSIZE; + output VCUPLMCUMAXIICDCAWVALID; + output VCUPLMCUMAXIICDCBREADY; + output VCUPLMCUMAXIICDCRREADY; + output [31:0] VCUPLMCUMAXIICDCWDATA; + output VCUPLMCUMAXIICDCWLAST; + output [3:0] VCUPLMCUMAXIICDCWSTRB; + output VCUPLMCUMAXIICDCWVALID; + output VCUPLMCUSTATUSCLKPLL; + output VCUPLPINTREQ; + output VCUPLPLLSTATUSPLLLOCK; + output VCUPLPWRSUPPLYSTATUSVCCAUX; + output VCUPLPWRSUPPLYSTATUSVCUINT; + output [31:0] VCUPLRDATAAXILITEAPB; + output [1:0] VCUPLRRESPAXILITEAPB; + output VCUPLRVALIDAXILITEAPB; + output VCUPLWREADYAXILITEAPB; + input INITPLVCUGASKETCLAMPCONTROLLVLSHVCCINTD; + input [19:0] PLVCUARADDRAXILITEAPB; + input [2:0] PLVCUARPROTAXILITEAPB; + input PLVCUARVALIDAXILITEAPB; + input [19:0] PLVCUAWADDRAXILITEAPB; + input [2:0] PLVCUAWPROTAXILITEAPB; + input PLVCUAWVALIDAXILITEAPB; + input PLVCUAXIDECCLK; + input PLVCUAXIENCCLK; + input PLVCUAXILITECLK; + input PLVCUAXIMCUCLK; + input PLVCUBREADYAXILITEAPB; + input PLVCUCORECLK; + input PLVCUDECARREADY0; + input PLVCUDECARREADY1; + input PLVCUDECAWREADY0; + input PLVCUDECAWREADY1; + input [3:0] PLVCUDECBID0; + input [3:0] PLVCUDECBID1; + input [1:0] PLVCUDECBRESP0; + input [1:0] PLVCUDECBRESP1; + input PLVCUDECBVALID0; + input PLVCUDECBVALID1; + input [127:0] PLVCUDECRDATA0; + input [127:0] PLVCUDECRDATA1; + input [3:0] PLVCUDECRID0; + input [3:0] PLVCUDECRID1; + input PLVCUDECRLAST0; + input PLVCUDECRLAST1; + input [1:0] PLVCUDECRRESP0; + input [1:0] PLVCUDECRRESP1; + input PLVCUDECRVALID0; + input PLVCUDECRVALID1; + input PLVCUDECWREADY0; + input PLVCUDECWREADY1; + input [319:0] PLVCUENCALL2CRDATA; + input PLVCUENCALL2CRREADY; + input PLVCUENCARREADY0; + input PLVCUENCARREADY1; + input PLVCUENCAWREADY0; + input PLVCUENCAWREADY1; + input [3:0] PLVCUENCBID0; + input [3:0] PLVCUENCBID1; + input [1:0] PLVCUENCBRESP0; + input [1:0] PLVCUENCBRESP1; + input PLVCUENCBVALID0; + input PLVCUENCBVALID1; + input PLVCUENCL2CCLK; + input [127:0] PLVCUENCRDATA0; + input [127:0] PLVCUENCRDATA1; + input [3:0] PLVCUENCRID0; + input [3:0] PLVCUENCRID1; + input PLVCUENCRLAST0; + input PLVCUENCRLAST1; + input [1:0] PLVCUENCRRESP0; + input [1:0] PLVCUENCRRESP1; + input PLVCUENCRVALID0; + input PLVCUENCRVALID1; + input PLVCUENCWREADY0; + input PLVCUENCWREADY1; + input PLVCUMCUCLK; + input PLVCUMCUMAXIICDCARREADY; + input PLVCUMCUMAXIICDCAWREADY; + input [2:0] PLVCUMCUMAXIICDCBID; + input [1:0] PLVCUMCUMAXIICDCBRESP; + input PLVCUMCUMAXIICDCBVALID; + input [31:0] PLVCUMCUMAXIICDCRDATA; + input [2:0] PLVCUMCUMAXIICDCRID; + input PLVCUMCUMAXIICDCRLAST; + input [1:0] PLVCUMCUMAXIICDCRRESP; + input PLVCUMCUMAXIICDCRVALID; + input PLVCUMCUMAXIICDCWREADY; + input PLVCUPLLREFCLKPL; + input PLVCURAWRSTN; + input PLVCURREADYAXILITEAPB; + input [31:0] PLVCUWDATAAXILITEAPB; + input [3:0] PLVCUWSTRBAXILITEAPB; + input PLVCUWVALIDAXILITEAPB; +endmodule + +module FE (...); + parameter MODE = "TURBO_DECODE"; + parameter real PHYSICAL_UTILIZATION = 100.00; + parameter SIM_DEVICE = "ULTRASCALE_PLUS"; + parameter STANDARD = "LTE"; + parameter real THROUGHPUT_UTILIZATION = 100.00; + output [399:0] DEBUG_DOUT; + output DEBUG_PHASE; + output INTERRUPT; + output [511:0] M_AXIS_DOUT_TDATA; + output M_AXIS_DOUT_TLAST; + output M_AXIS_DOUT_TVALID; + output [31:0] M_AXIS_STATUS_TDATA; + output M_AXIS_STATUS_TVALID; + output [15:0] SPARE_OUT; + output S_AXIS_CTRL_TREADY; + output S_AXIS_DIN_TREADY; + output S_AXIS_DIN_WORDS_TREADY; + output S_AXIS_DOUT_WORDS_TREADY; + output S_AXI_ARREADY; + output S_AXI_AWREADY; + output S_AXI_BVALID; + output [31:0] S_AXI_RDATA; + output S_AXI_RVALID; + output S_AXI_WREADY; + input CORE_CLK; + input DEBUG_CLK_EN; + input DEBUG_EN; + input [3:0] DEBUG_SEL_IN; + input M_AXIS_DOUT_ACLK; + input M_AXIS_DOUT_TREADY; + input M_AXIS_STATUS_ACLK; + input M_AXIS_STATUS_TREADY; + input RESET_N; + input [15:0] SPARE_IN; + input S_AXIS_CTRL_ACLK; + input [31:0] S_AXIS_CTRL_TDATA; + input S_AXIS_CTRL_TVALID; + input S_AXIS_DIN_ACLK; + input [511:0] S_AXIS_DIN_TDATA; + input S_AXIS_DIN_TLAST; + input S_AXIS_DIN_TVALID; + input S_AXIS_DIN_WORDS_ACLK; + input [31:0] S_AXIS_DIN_WORDS_TDATA; + input S_AXIS_DIN_WORDS_TLAST; + input S_AXIS_DIN_WORDS_TVALID; + input S_AXIS_DOUT_WORDS_ACLK; + input [31:0] S_AXIS_DOUT_WORDS_TDATA; + input S_AXIS_DOUT_WORDS_TLAST; + input S_AXIS_DOUT_WORDS_TVALID; + input S_AXI_ACLK; + input [17:0] S_AXI_ARADDR; + input S_AXI_ARVALID; + input [17:0] S_AXI_AWADDR; + input S_AXI_AWVALID; + input S_AXI_BREADY; + input S_AXI_RREADY; + input [31:0] S_AXI_WDATA; + input S_AXI_WVALID; +endmodule + diff --git a/techlibs/xilinx/xilinx_dffopt.cc b/techlibs/xilinx/xilinx_dffopt.cc index 365f505fb..598f1b216 100644 --- a/techlibs/xilinx/xilinx_dffopt.cc +++ b/techlibs/xilinx/xilinx_dffopt.cc @@ -209,7 +209,7 @@ lut_sigin_done: continue; LutData lut_d = it_D->second.first; Cell *cell_d = it_D->second.second; - if (cell->getParam(ID(IS_D_INVERTED)).as_bool()) { + if (cell->hasParam(ID(IS_D_INVERTED)) && cell->getParam(ID(IS_D_INVERTED)).as_bool()) { // Flip all bits in the LUT. for (int i = 0; i < GetSize(lut_d.first); i++) lut_d.first.bits[i] = (lut_d.first.bits[i] == State::S1) ? State::S0 : State::S1; @@ -249,7 +249,7 @@ lut_sigin_done: if (has_s) { SigBit sig_S = sigmap(cell->getPort(ID::S)); LutData lut_s = LutData(Const(2, 2), {sig_S}); - bool inv_s = cell->getParam(ID(IS_S_INVERTED)).as_bool(); + bool inv_s = cell->hasParam(ID(IS_S_INVERTED)) && cell->getParam(ID(IS_S_INVERTED)).as_bool(); auto it_S = bit_to_lut.find(sig_S); if (it_S != bit_to_lut.end()) lut_s = it_S->second.first; @@ -271,7 +271,7 @@ lut_sigin_done: if (has_r) { SigBit sig_R = sigmap(cell->getPort(ID::R)); LutData lut_r = LutData(Const(2, 2), {sig_R}); - bool inv_r = cell->getParam(ID(IS_R_INVERTED)).as_bool(); + bool inv_r = cell->hasParam(ID(IS_R_INVERTED)) && cell->getParam(ID(IS_R_INVERTED)).as_bool(); auto it_R = bit_to_lut.find(sig_R); if (it_R != bit_to_lut.end()) lut_r = it_R->second.first; diff --git a/tests/arch/xilinx/mux.ys b/tests/arch/xilinx/mux.ys index 1b2788448..c2a23de6d 100644 --- a/tests/arch/xilinx/mux.ys +++ b/tests/arch/xilinx/mux.ys @@ -40,10 +40,11 @@ proc equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx -noiopad # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd mux16 # Constrain all select calls below inside the top module +select -assert-max 2 t:LUT3 select -assert-max 2 t:LUT4 select -assert-min 4 t:LUT6 select -assert-max 7 t:LUT6 select -assert-max 2 t:MUXF7 dump -select -assert-none t:LUT6 t:LUT4 t:MUXF7 %% t:* %D +select -assert-none t:LUT6 t:LUT4 t:LUT3 t:MUXF7 %% t:* %D diff --git a/tests/arch/xilinx/xilinx_dffopt.ys b/tests/arch/xilinx/xilinx_dffopt.ys index 2c729832e..c09699411 100644 --- a/tests/arch/xilinx/xilinx_dffopt.ys +++ b/tests/arch/xilinx/xilinx_dffopt.ys @@ -223,3 +223,49 @@ select -assert-count 1 t:LUT2 select -assert-none t:FDRSE t:LUT4 t:LUT2 %% t:* %D design -reset + + +read_verilog << EOT + +// FDSE_1, mergeable CE and S, but CE only not worth it. + +module t0 (...); +input wire clk; +input wire [7:0] i; +output wire [7:0] o; + +wire [7:0] tmp ; + +LUT2 #(.INIT(4'h6)) lut0 (.I0(i[0]), .I1(i[1]), .O(tmp[0])); +LUT2 #(.INIT(4'h6)) lut1 (.I0(i[1]), .I1(i[2]), .O(tmp[1])); + +FDSE_1 ff (.D(tmp[0]), .CE(i[7]), .S(tmp[1]), .Q(o[0])); + +endmodule + +EOT + +read_verilog -lib +/xilinx/cells_sim.v +design -save t0 + +equiv_opt -blacklist xilinx_dffopt_blacklist.txt -assert -map +/xilinx/cells_sim.v xilinx_dffopt +design -load postopt +clean + +cd t0 +select -assert-count 1 t:FDSE_1 +select -assert-count 1 t:LUT5 +select -assert-none t:FDSE_1 t:LUT5 %% t:* %D + +design -load t0 + +equiv_opt -blacklist xilinx_dffopt_blacklist.txt -assert -map +/xilinx/cells_sim.v xilinx_dffopt -lut4 +design -load postopt +clean + +cd t0 +select -assert-count 1 t:FDSE_1 +select -assert-count 2 t:LUT2 +select -assert-none t:FDSE_1 t:LUT2 %% t:* %D + +design -reset diff --git a/tests/opt/opt_share_bug2538.ys b/tests/opt/opt_share_bug2538.ys new file mode 100644 index 000000000..7261c6695 --- /dev/null +++ b/tests/opt/opt_share_bug2538.ys @@ -0,0 +1,20 @@ +read_verilog <<EOT + +module top(...); + +input [3:0] A; +input S; +output [1:0] Y; + +wire [3:0] A1 = A + 1; +wire [3:0] A2 = A + 2; +assign Y = S ? A1[3:2] : A2[3:2]; + +endmodule + +EOT + +proc +alumacc +equiv_opt -assert opt_share + diff --git a/tests/simple/const_branch_finish.v b/tests/simple/const_branch_finish.v index 8166688e6..f585be87a 100644 --- a/tests/simple/const_branch_finish.v +++ b/tests/simple/const_branch_finish.v @@ -21,9 +21,6 @@ module top; end end generate - begin : unconditional_block - initial `CONSTANT_CHECK - end if (WIDTH == 32) begin : conditional_block initial `CONSTANT_CHECK end diff --git a/tests/simple/const_fold_func.v b/tests/simple/const_fold_func.v new file mode 100644 index 000000000..ee2f12e06 --- /dev/null +++ b/tests/simple/const_fold_func.v @@ -0,0 +1,61 @@ +module top( + input wire [3:0] inp, + output wire [3:0] out1, out2, out3, out4, out5, + output reg [3:0] out6 +); + function automatic [3:0] flip; + input [3:0] inp; + flip = ~inp; + endfunction + + function automatic [3:0] help; + input [3:0] inp; + help = flip(inp); + endfunction + + // while loops are const-eval-only + function automatic [3:0] loop; + input [3:0] inp; + reg [3:0] val; + begin + val = inp; + loop = 1; + while (val != inp) begin + loop = loop * 2; + val = val + 1; + end + end + endfunction + + // not const-eval-only, despite calling a const-eval-only function + function automatic [3:0] help_mul; + input [3:0] inp; + help_mul = inp * loop(2); + endfunction + + // can be elaborated so long as exp is a constant + function automatic [3:0] pow_flip_a; + input [3:0] base, exp; + begin + pow_flip_a = 1; + if (exp > 0) + pow_flip_a = base * pow_flip_a(flip(base), exp - 1); + end + endfunction + + function automatic [3:0] pow_flip_b; + input [3:0] base, exp; + begin + out6[exp] = base & 1; + pow_flip_b = 1; + if (exp > 0) + pow_flip_b = base * pow_flip_b(flip(base), exp - 1); + end + endfunction + + assign out1 = flip(flip(inp)); + assign out2 = help(flip(inp)); + assign out3 = help_mul(inp); + assign out4 = pow_flip_a(flip(inp), 3); + assign out5 = pow_flip_b(2, 2); +endmodule diff --git a/tests/simple/const_func_shadow.v b/tests/simple/const_func_shadow.v new file mode 100644 index 000000000..ca63606d9 --- /dev/null +++ b/tests/simple/const_func_shadow.v @@ -0,0 +1,33 @@ +module top(w, x, y, z); + function [11:0] func; + input reg [2:0] x; + input reg [2:0] y; + begin + x = x * (y + 1); + begin : foo + reg [2:0] y; + y = x + 1; + begin : bar + reg [2:0] x; + x = y + 1; + begin : blah + reg [2:0] y; + y = x + 1; + func[2:0] = y; + end + func[5:3] = x; + end + func[8:6] = y; + end + func[11:9] = x; + end + endfunction + output wire [func(2, 3) - 1:0] w; + output wire [func(1, 3) - 1:0] x; + output wire [func(3, 1) - 1:0] y; + output wire [func(5, 2) - 1:0] z; + assign w = 1'sb1; + assign x = 1'sb1; + assign y = 1'sb1; + assign z = 1'sb1; +endmodule diff --git a/tests/simple/func_block.v b/tests/simple/func_block.v new file mode 100644 index 000000000..be759d1a9 --- /dev/null +++ b/tests/simple/func_block.v @@ -0,0 +1,33 @@ +`default_nettype none + +module top(inp, out1, out2, out3); + input wire [31:0] inp; + + function automatic [31:0] func1; + input [31:0] inp; + reg [31:0] idx; + for (idx = 0; idx < 32; idx = idx + 1) begin : blk + func1[idx] = (idx & 1'b1) ^ inp[idx]; + end + endfunction + + function automatic [31:0] func2; + input [31:0] inp; + reg [31:0] idx; + for (idx = 0; idx < 32; idx = idx + 1) begin : blk + func2[idx] = (idx & 1'b1) ^ inp[idx]; + end + endfunction + + function automatic [31:0] func3; + localparam A = 32 - 1; + parameter B = 1 - 0; + input [31:0] inp; + func3[A:B] = inp[A:B]; + endfunction + + output wire [31:0] out1, out2, out3; + assign out1 = func1(inp); + assign out2 = func2(inp); + assign out3 = func3(inp); +endmodule diff --git a/tests/simple/func_recurse.v b/tests/simple/func_recurse.v new file mode 100644 index 000000000..d61c8cc06 --- /dev/null +++ b/tests/simple/func_recurse.v @@ -0,0 +1,25 @@ +module top( + input wire [3:0] inp, + output wire [3:0] out1, out2 +); + function automatic [3:0] pow_a; + input [3:0] base, exp; + begin + pow_a = 1; + if (exp > 0) + pow_a = base * pow_a(base, exp - 1); + end + endfunction + + function automatic [3:0] pow_b; + input [3:0] base, exp; + begin + pow_b = 1; + if (exp > 0) + pow_b = base * pow_b(base, exp - 1); + end + endfunction + + assign out1 = pow_a(inp, 3); + assign out2 = pow_b(2, 2); +endmodule diff --git a/tests/simple/func_width_scope.v b/tests/simple/func_width_scope.v new file mode 100644 index 000000000..ce81e894e --- /dev/null +++ b/tests/simple/func_width_scope.v @@ -0,0 +1,41 @@ +module top(inp, out1, out2); + input wire signed inp; + + localparam WIDTH_A = 5; + function automatic [WIDTH_A-1:0] func1; + input reg [WIDTH_A-1:0] inp; + func1 = ~inp; + endfunction + wire [func1(0)-1:0] xc; + assign xc = 1'sb1; + wire [WIDTH_A-1:0] xn; + assign xn = func1(inp); + + generate + if (1) begin : blk + localparam WIDTH_A = 6; + function automatic [WIDTH_A-1:0] func2; + input reg [WIDTH_A-1:0] inp; + func2 = ~inp; + endfunction + wire [func2(0)-1:0] yc; + assign yc = 1'sb1; + wire [WIDTH_A-1:0] yn; + assign yn = func2(inp); + + localparam WIDTH_B = 7; + function automatic [WIDTH_B-1:0] func3; + input reg [WIDTH_B-1:0] inp; + func3 = ~inp; + endfunction + wire [func3(0)-1:0] zc; + assign zc = 1'sb1; + wire [WIDTH_B-1:0] zn; + assign zn = func3(inp); + end + endgenerate + + output wire [1023:0] out1, out2; + assign out1 = {xc, 1'b0, blk.yc, 1'b0, blk.zc}; + assign out2 = {xn, 1'b0, blk.yn, 1'b0, blk.zn}; +endmodule diff --git a/tests/simple/genblk_collide.v b/tests/simple/genblk_collide.v new file mode 100644 index 000000000..f42dd2cfc --- /dev/null +++ b/tests/simple/genblk_collide.v @@ -0,0 +1,27 @@ +`default_nettype none + +module top1; + generate + if (1) begin : foo + if (1) begin : bar + wire x; + end + assign bar.x = 1; + wire y; + end + endgenerate +endmodule + +module top2; + genvar i; + generate + if (1) begin : foo + wire x; + for (i = 0; i < 1; i = i + 1) begin : foo + if (1) begin : foo + assign x = 1; + end + end + end + endgenerate +endmodule diff --git a/tests/simple/genblk_dive.v b/tests/simple/genblk_dive.v new file mode 100644 index 000000000..98d0e1f4b --- /dev/null +++ b/tests/simple/genblk_dive.v @@ -0,0 +1,21 @@ +`default_nettype none +module top(output wire x); + generate + if (1) begin : Z + if (1) begin : A + wire x; + if (1) begin : B + wire x; + if (1) begin : C + wire x; + assign B.x = 0; + wire z = A.B.C.x; + end + assign A.x = A.B.C.x; + end + assign B.C.x = B.x; + end + end + endgenerate + assign x = Z.A.x; +endmodule diff --git a/tests/simple/genblk_order.v b/tests/simple/genblk_order.v new file mode 100644 index 000000000..7c3a7a756 --- /dev/null +++ b/tests/simple/genblk_order.v @@ -0,0 +1,18 @@ +`default_nettype none +module top( + output wire out1, + output wire out2 +); + generate + if (1) begin : outer + if (1) begin : foo + wire x = 0; + if (1) begin : foo + wire x = 1; + assign out1 = foo.x; + end + assign out2 = foo.x; + end + end + endgenerate +endmodule diff --git a/tests/simple/genblk_port_shadow.v b/tests/simple/genblk_port_shadow.v new file mode 100644 index 000000000..a04631a20 --- /dev/null +++ b/tests/simple/genblk_port_shadow.v @@ -0,0 +1,10 @@ +module top(x); + generate + if (1) begin : blk + wire x; + assign x = 0; + end + endgenerate + output wire x; + assign x = blk.x; +endmodule diff --git a/tests/simple/generate.v b/tests/simple/generate.v index 12327b36e..445c88ba8 100644 --- a/tests/simple/generate.v +++ b/tests/simple/generate.v @@ -167,7 +167,7 @@ module gen_test7; reg [2:0] out2; wire [2:0] out3; generate - begin : cond + if (1) begin : cond reg [2:0] sub_out1; reg [2:0] sub_out2; wire [2:0] sub_out3; @@ -215,9 +215,9 @@ module gen_test8; wire [1:0] x = 2'b11; generate - begin : A + if (1) begin : A wire [1:0] x; - begin : B + if (1) begin : B wire [1:0] x = 2'b00; `ASSERT(x == 0) `ASSERT(A.x == 2) @@ -228,7 +228,7 @@ module gen_test8; `ASSERT(gen_test8.A.C.x == 1) `ASSERT(gen_test8.A.B.x == 0) end - begin : C + if (1) begin : C wire [1:0] x = 2'b01; `ASSERT(x == 1) `ASSERT(A.x == 2) @@ -260,3 +260,66 @@ module gen_test8; `ASSERT(gen_test8.A.C.x == 1) `ASSERT(gen_test8.A.B.x == 0) endmodule + +// ------------------------------------------ + +module gen_test9; + +// `define VERIFY +`ifdef VERIFY + `define ASSERT(expr) assert property (expr); +`else + `define ASSERT(expr) +`endif + + wire [1:0] w = 2'b11; + generate + begin : A + wire [1:0] x; + begin : B + wire [1:0] y = 2'b00; + `ASSERT(w == 3) + `ASSERT(x == 2) + `ASSERT(y == 0) + `ASSERT(A.x == 2) + `ASSERT(A.C.z == 1) + `ASSERT(A.B.y == 0) + `ASSERT(gen_test9.w == 3) + `ASSERT(gen_test9.A.x == 2) + `ASSERT(gen_test9.A.C.z == 1) + `ASSERT(gen_test9.A.B.y == 0) + end + begin : C + wire [1:0] z = 2'b01; + `ASSERT(w == 3) + `ASSERT(x == 2) + `ASSERT(z == 1) + `ASSERT(A.x == 2) + `ASSERT(A.C.z == 1) + `ASSERT(A.B.y == 0) + `ASSERT(gen_test9.w == 3) + `ASSERT(gen_test9.A.x == 2) + `ASSERT(gen_test9.A.C.z == 1) + `ASSERT(gen_test9.A.B.y == 0) + end + assign x = B.y ^ 2'b11 ^ C.z; + `ASSERT(x == 2) + `ASSERT(A.x == 2) + `ASSERT(A.C.z == 1) + `ASSERT(A.B.y == 0) + `ASSERT(gen_test9.w == 3) + `ASSERT(gen_test9.A.x == 2) + `ASSERT(gen_test9.A.C.z == 1) + `ASSERT(gen_test9.A.B.y == 0) + end + endgenerate + + `ASSERT(w == 3) + `ASSERT(A.x == 2) + `ASSERT(A.C.z == 1) + `ASSERT(A.B.y == 0) + `ASSERT(gen_test9.w == 3) + `ASSERT(gen_test9.A.x == 2) + `ASSERT(gen_test9.A.C.z == 1) + `ASSERT(gen_test9.A.B.y == 0) +endmodule diff --git a/tests/simple/local_loop_var.sv b/tests/simple/local_loop_var.sv new file mode 100644 index 000000000..46b4e5c22 --- /dev/null +++ b/tests/simple/local_loop_var.sv @@ -0,0 +1,11 @@ +module top(out); + output integer out; + initial begin + integer i; + for (i = 0; i < 5; i = i + 1) + if (i == 0) + out = 1; + else + out += 2 ** i; + end +endmodule diff --git a/tests/simple/loop_var_shadow.v b/tests/simple/loop_var_shadow.v new file mode 100644 index 000000000..0222a4493 --- /dev/null +++ b/tests/simple/loop_var_shadow.v @@ -0,0 +1,15 @@ +module top(out); + genvar i; + generate + for (i = 0; i < 2; i = i + 1) begin : loop + localparam j = i + 1; + if (1) begin : blk + localparam i = j + 1; + wire [i:0] x; + assign x = 1'sb1; + end + end + endgenerate + output wire [63:0] out; + assign out = {loop[0].blk.x, loop[1].blk.x}; +endmodule diff --git a/tests/simple/macro_arg_spaces.sv b/tests/simple/macro_arg_spaces.sv new file mode 100644 index 000000000..75c4cd136 --- /dev/null +++ b/tests/simple/macro_arg_spaces.sv @@ -0,0 +1,28 @@ +module top( + input wire [31:0] i, + output wire [31:0] x, y, z +); + +`define BAR(a) a +`define FOO(a = function automatic [31:0] f) a + +`BAR(function automatic [31:0] a); + input [31:0] i; + a = i * 2; +endfunction + +`FOO(); + input [31:0] i; + f = i * 3; +endfunction + +`FOO(function automatic [31:0] b); + input [31:0] i; + b = i * 5; +endfunction + +assign x = a(i); +assign y = f(i); +assign z = b(i); + +endmodule diff --git a/tests/simple/macro_arg_surrounding_spaces.v b/tests/simple/macro_arg_surrounding_spaces.v new file mode 100644 index 000000000..3dbb5ea01 --- /dev/null +++ b/tests/simple/macro_arg_surrounding_spaces.v @@ -0,0 +1,20 @@ +module top( + IDENT_V_, + IDENT_W_, + IDENT_X_, + IDENT_Y_, + IDENT_Z_, + IDENT_A_, + IDENT_B_, + IDENT_C_ +); + `define MACRO(dummy, x) IDENT_``x``_ + output wire IDENT_V_; + output wire `MACRO(_,W); + output wire `MACRO(_, X); + output wire `MACRO(_,Y ); + output wire `MACRO(_, Z ); + output wire `MACRO(_, A); + output wire `MACRO(_,B ); + output wire `MACRO(_, C ); +endmodule diff --git a/tests/simple/named_genblk.v b/tests/simple/named_genblk.v new file mode 100644 index 000000000..b8300fc4d --- /dev/null +++ b/tests/simple/named_genblk.v @@ -0,0 +1,27 @@ +`default_nettype none +module top; + generate + if (1) begin + wire t; + begin : foo + wire x; + end + wire u; + end + begin : bar + wire x; + wire y; + begin : baz + wire x; + wire z; + end + end + endgenerate + assign genblk1.t = 1; + assign genblk1.foo.x = 1; + assign genblk1.u = 1; + assign bar.x = 1; + assign bar.y = 1; + assign bar.baz.x = 1; + assign bar.baz.z = 1; +endmodule diff --git a/tests/simple/nested_genblk_resolve.v b/tests/simple/nested_genblk_resolve.v new file mode 100644 index 000000000..da5593f8a --- /dev/null +++ b/tests/simple/nested_genblk_resolve.v @@ -0,0 +1,14 @@ +`default_nettype none +module top; + generate + if (1) begin + wire x; + genvar i; + for (i = 0; i < 1; i = i + 1) begin + if (1) begin + assign x = 1; + end + end + end + endgenerate +endmodule diff --git a/tests/simple/unnamed_block_decl.sv b/tests/simple/unnamed_block_decl.sv new file mode 100644 index 000000000..e81b457a8 --- /dev/null +++ b/tests/simple/unnamed_block_decl.sv @@ -0,0 +1,17 @@ +module top(z); + output integer z; + initial begin + integer x; + x = 1; + begin + integer y; + y = x + 1; + begin + integer z; + z = y + 1; + y = z + 1; + end + z = y + 1; + end + end +endmodule diff --git a/tests/svtypes/typedef_struct_port.sv b/tests/svtypes/typedef_struct_port.sv new file mode 100644 index 000000000..ecc03bee8 --- /dev/null +++ b/tests/svtypes/typedef_struct_port.sv @@ -0,0 +1,111 @@ +package p; + +typedef struct packed { + byte a; + byte b; +} p_t; + +typedef logic [31:0] l_t; + +endpackage + +module foo1( + input p::p_t p, + output p::p_t o +); + assign o = p; +endmodule + +module foo2(p, o); + input p::p_t p; + output p::p_t o; + assign o = p; +endmodule + +module foo3(input p::l_t p, input p::l_t o); + assign o = p; +endmodule + +module foo4(input logic [15:0] p, input logic [15:0] o); + assign o = p; +endmodule + +module test_parser(a,b,c,d,e,f,g,h,i); +input [7:0] a; // no explicit net declaration - net is unsigned +input [7:0] b; +input signed [7:0] c; +input signed [7:0] d; // no explicit net declaration - net is signed +output [7:0] e; // no explicit net declaration - net is unsigned +output [7:0] f; +output signed [7:0] g; +output signed [7:0] h; // no explicit net declaration - net is signed +output unsigned [7:0] i; +wire signed [7:0] b; // port b inherits signed attribute from net decl. +wire [7:0] c; // net c inherits signed attribute from port +logic signed [7:0] f;// port f inherits signed attribute from logic decl. +logic [7:0] g; // logic g inherits signed attribute from port + + assign a = 8'b10001111; + assign b = 8'b10001111; + assign c = 8'b10001111; + assign d = 8'b10001111; + assign e = 8'b10001111; + assign f = 8'b10001111; + assign g = 8'b10001111; + assign h = 8'b10001111; + assign i = 8'b10001111; + always_comb begin + assert($unsigned(143) == a); + assert($signed(-113) == b); + assert($signed(-113) == c); + assert($signed(-113) == d); + assert($unsigned(143) == e); + assert($unsigned(143) == f); + assert($signed(-113) == g); + assert($signed(-113) == h); + assert($unsigned(143) == i); + end +endmodule + +module top; + p::p_t ps; + assign ps.a = 8'hAA; + assign ps.b = 8'h55; + foo1 foo(.p(ps)); + + p::p_t body; + assign body.a = 8'hBB; + assign body.b = 8'h66; + foo2 foo_b(.p(body)); + + typedef p::l_t local_alias; + + local_alias l_s; + assign l_s = 32'hAAAAAAAA; + foo3 foo_l(.p(l_s)); + + typedef logic [15:0] sl_t; + + sl_t sl_s; + assign sl_s = 16'hBBBB; + foo4 foo_sl(.p(sl_s)); + + typedef sl_t local_alias_st; + + local_alias_st lsl_s; + assign lsl_s = 16'hCCCC; + foo4 foo_lsl(.p(lsl_s)); + + const logic j = 1'b1; + + always_comb begin + assert(8'hAA == ps.a); + assert(8'h55 == ps.b); + assert(8'hBB == body.a); + assert(8'h66 == body.b); + assert(32'hAAAAAAAA == l_s); + assert(16'hBBBB == sl_s); + assert(16'hCCCC == lsl_s); + assert(1'b1 == j); + end +endmodule diff --git a/tests/svtypes/typedef_struct_port.ys b/tests/svtypes/typedef_struct_port.ys new file mode 100644 index 000000000..5b75c3105 --- /dev/null +++ b/tests/svtypes/typedef_struct_port.ys @@ -0,0 +1,6 @@ +read_verilog -sv typedef_struct_port.sv +hierarchy; proc; opt +select -module top +sat -verify -seq 1 -tempinduct -prove-asserts -show-all +select -module test_parser +sat -verify -seq 1 -tempinduct -prove-asserts -show-all diff --git a/tests/various/.gitignore b/tests/various/.gitignore index 12d4e5048..2bb6c7179 100644 --- a/tests/various/.gitignore +++ b/tests/various/.gitignore @@ -4,3 +4,4 @@ /write_gzip.v.gz /run-test.mk /plugin.so +/plugin.so.dSYM diff --git a/tests/various/const_arg_loop.v b/tests/various/const_arg_loop.v index 3bfff4acd..358fb439a 100644 --- a/tests/various/const_arg_loop.v +++ b/tests/various/const_arg_loop.v @@ -14,6 +14,11 @@ module top; end endfunction + function automatic [31:0] pass_through; + input [31:0] inp; + pass_through = inp; + endfunction + function automatic [31:0] operation2; input [4:0] var; input integer num; @@ -39,6 +44,18 @@ module top; end endfunction + function automatic [16:0] operation4; + input [15:0] a; + input b; + operation4 = {a, b}; + endfunction + + function automatic integer operation5; + input x; + integer x; + operation5 = x; + endfunction + wire [31:0] a; assign a = 2; @@ -47,18 +64,30 @@ module top; wire [31:0] x1; assign x1 = operation1(A, a); + wire [31:0] x1b; + assign x1b = operation1(pass_through(A), a); + wire [31:0] x2; assign x2 = operation2(A, a); wire [31:0] x3; assign x3 = operation3(A, a); + wire [16:0] x4; + assign x4 = operation4(a[15:0], 0); + + wire [31:0] x5; + assign x5 = operation5(64); + // `define VERIFY `ifdef VERIFY assert property (a == 2); assert property (A == 3); assert property (x1 == 16); + assert property (x1b == 16); assert property (x2 == 4); assert property (x3 == 16); + assert property (x4 == a << 1); + assert property (x5 == 64); `endif endmodule diff --git a/tests/various/fib.v b/tests/various/fib.v new file mode 100644 index 000000000..986749626 --- /dev/null +++ b/tests/various/fib.v @@ -0,0 +1,65 @@ +module gate( + off, fib0, fib1, fib2, fib3, fib4, fib5, fib6, fib7, fib8, fib9 +); + input wire signed [31:0] off; + + function automatic integer fib( + input integer k + ); + if (k == 0) + fib = 0; + else if (k == 1) + fib = 1; + else + fib = fib(k - 1) + fib(k - 2); + endfunction + + function automatic integer fib_wrap( + input integer k, + output integer o + ); + o = off + fib(k); + endfunction + + output integer fib0; + output integer fib1; + output integer fib2; + output integer fib3; + output integer fib4; + output integer fib5; + output integer fib6; + output integer fib7; + output integer fib8; + output integer fib9; + + initial begin : blk + integer unused; + unused = fib_wrap(0, fib0); + unused = fib_wrap(1, fib1); + unused = fib_wrap(2, fib2); + unused = fib_wrap(3, fib3); + unused = fib_wrap(4, fib4); + unused = fib_wrap(5, fib5); + unused = fib_wrap(6, fib6); + unused = fib_wrap(7, fib7); + unused = fib_wrap(8, fib8); + unused = fib_wrap(9, fib9); + end +endmodule + +module gold( + off, fib0, fib1, fib2, fib3, fib4, fib5, fib6, fib7, fib8, fib9 +); + input wire signed [31:0] off; + + output integer fib0 = off + 0; + output integer fib1 = off + 1; + output integer fib2 = off + 1; + output integer fib3 = off + 2; + output integer fib4 = off + 3; + output integer fib5 = off + 5; + output integer fib6 = off + 8; + output integer fib7 = off + 13; + output integer fib8 = off + 21; + output integer fib9 = off + 34; +endmodule diff --git a/tests/various/fib.ys b/tests/various/fib.ys new file mode 100644 index 000000000..946e0738a --- /dev/null +++ b/tests/various/fib.ys @@ -0,0 +1,6 @@ +read_verilog fib.v +hierarchy +proc +equiv_make gold gate equiv +equiv_simple +equiv_status -assert diff --git a/tests/various/func_port_implied_dir.sv b/tests/various/func_port_implied_dir.sv new file mode 100644 index 000000000..0424f1b46 --- /dev/null +++ b/tests/various/func_port_implied_dir.sv @@ -0,0 +1,23 @@ +module gate(w, x, y, z); + function automatic integer bar( + integer a + ); + bar = 2 ** a; + endfunction + output integer w = bar(4); + + function automatic integer foo( + input integer a, /* implicitly input */ integer b, + output integer c, /* implicitly output */ integer d + ); + c = 42; + d = 51; + foo = a + b + 1; + endfunction + output integer x, y, z; + initial x = foo(1, 2, y, z); +endmodule + +module gold(w, x, y, z); + output integer w = 16, x = 4, y = 42, z = 51; +endmodule diff --git a/tests/various/func_port_implied_dir.ys b/tests/various/func_port_implied_dir.ys new file mode 100644 index 000000000..b5c22a05b --- /dev/null +++ b/tests/various/func_port_implied_dir.ys @@ -0,0 +1,6 @@ +read_verilog -sv func_port_implied_dir.sv +hierarchy +proc +equiv_make gold gate equiv +equiv_simple +equiv_status -assert diff --git a/tests/various/gen_if_null.v b/tests/various/gen_if_null.v index a12ac6288..992bc68b3 100644 --- a/tests/various/gen_if_null.v +++ b/tests/various/gen_if_null.v @@ -1,13 +1,17 @@ -module test(x, y, z); +`default_nettype none +module test; localparam OFF = 0; generate if (OFF) ; - else input x; - if (!OFF) input y; + else wire x; + if (!OFF) wire y; else ; if (OFF) ; else ; if (OFF) ; - input z; + wire z; endgenerate + assign genblk1.x = 0; + assign genblk2.y = 0; + assign z = 0; endmodule diff --git a/tests/various/gen_if_null.ys b/tests/various/gen_if_null.ys index 31dfc444b..0733e3a94 100644 --- a/tests/various/gen_if_null.ys +++ b/tests/various/gen_if_null.ys @@ -1,4 +1,4 @@ read_verilog gen_if_null.v -select -assert-count 1 test/x -select -assert-count 1 test/y +select -assert-count 1 test/genblk1.x +select -assert-count 1 test/genblk2.y select -assert-count 1 test/z diff --git a/tests/various/memory_word_as_index.data b/tests/various/memory_word_as_index.data new file mode 100644 index 000000000..d525c18ee --- /dev/null +++ b/tests/various/memory_word_as_index.data @@ -0,0 +1,4 @@ +00 04 08 0c +10 14 18 1c +20 24 28 2c +30 34 38 3c diff --git a/tests/various/memory_word_as_index.v b/tests/various/memory_word_as_index.v new file mode 100644 index 000000000..a99ea9566 --- /dev/null +++ b/tests/various/memory_word_as_index.v @@ -0,0 +1,21 @@ +`define DATA 64'h492e5c4d7747e032 + +`define GATE(n, expr) \ +module gate``n(sel, out); \ + input wire [3:0] sel; \ + output wire out; \ + reg [63:0] bits; \ + reg [5:0] ptrs[15:0]; \ + initial bits = `DATA; \ + initial $readmemh("memory_word_as_index.data", ptrs); \ + assign out = expr; \ +endmodule + +`GATE(1, bits[ptrs[sel]]) +`GATE(2, bits[ptrs[sel][5:0]]) +`GATE(3, bits[ptrs[sel]+:1]) + +module gold(sel, out); + input wire [3:0] sel; + output wire out = `DATA >> (sel * 4); +endmodule diff --git a/tests/various/memory_word_as_index.ys b/tests/various/memory_word_as_index.ys new file mode 100644 index 000000000..9a2dea40e --- /dev/null +++ b/tests/various/memory_word_as_index.ys @@ -0,0 +1,23 @@ +read_verilog memory_word_as_index.v + +hierarchy +proc +memory +flatten +opt -full + +equiv_make gold gate1 equiv +equiv_simple +equiv_status -assert + +delete equiv + +equiv_make gold gate2 equiv +equiv_simple +equiv_status -assert + +delete equiv + +equiv_make gold gate3 equiv +equiv_simple +equiv_status -assert diff --git a/tests/various/port_sign_extend.v b/tests/various/port_sign_extend.v new file mode 100644 index 000000000..813ceb503 --- /dev/null +++ b/tests/various/port_sign_extend.v @@ -0,0 +1,95 @@ +module GeneratorSigned1(out); + output wire signed out; + assign out = 1; +endmodule + +module GeneratorUnsigned1(out); + output wire out; + assign out = 1; +endmodule + +module GeneratorSigned2(out); + output wire signed [1:0] out; + assign out = 2; +endmodule + +module GeneratorUnsigned2(out); + output wire [1:0] out; + assign out = 2; +endmodule + +module PassThrough(a, b); + input wire [3:0] a; + output wire [3:0] b; + assign b = a; +endmodule + +module act(o1, o2, o3, o4, o5, o6, o7, o8, o9, yay1, nay1, yay2, nay2); + output wire [3:0] o1, o2, o3, o4, o5, o6, o7, o8, o9; + + // unsigned constant + PassThrough pt1(1'b1, o1); + + // unsigned wire + wire tmp2; + assign tmp2 = 1'sb1; + PassThrough pt2(tmp2, o2); + + // signed constant + PassThrough pt3(1'sb1, o3); + + // signed wire + wire signed tmp4; + assign tmp4 = 1'sb1; + PassThrough pt4(tmp4, o4); + + // signed expressions + wire signed [1:0] tmp5a = 2'b11; + wire signed [1:0] tmp5b = 2'b01; + PassThrough pt5(tmp5a ^ tmp5b, o5); + + wire signed [2:0] tmp6a = 3'b100; + wire signed [2:0] tmp6b = 3'b001; + PassThrough pt6(tmp6a ? tmp6a : tmp6b, o6); + + wire signed [2:0] tmp7 = 3'b011; + PassThrough pt7(~tmp7, o7); + + reg signed [2:0] tmp8 [0:0]; + initial tmp8[0] = 3'b101; + PassThrough pt8(tmp8[0], o8); + + wire signed [2:0] tmp9a = 3'b100; + wire signed [1:0] tmp9b = 2'b11; + PassThrough pt9(0 ? tmp9a : tmp9b, o9); + + output wire [2:0] yay1, nay1; + GeneratorSigned1 os1(yay1); + GeneratorUnsigned1 ou1(nay1); + + output wire [2:0] yay2, nay2; + GeneratorSigned2 os2(yay2); + GeneratorUnsigned2 ou2(nay2); +endmodule + +module ref(o1, o2, o3, o4, o5, o6, o7, o8, o9, yay1, nay1, yay2, nay2); + output wire [3:0] o1, o2, o3, o4, o5, o6, o7, o8, o9; + + assign o1 = 4'b0001; + assign o2 = 4'b0001; + assign o3 = 4'b1111; + assign o4 = 4'b1111; + assign o5 = 4'b1110; + assign o6 = 4'b1100; + assign o7 = 4'b1100; + assign o8 = 4'b1101; + assign o9 = 4'b1111; + + output wire [2:0] yay1, nay1; + assign yay1 = 3'b111; + assign nay1 = 3'b001; + + output wire [2:0] yay2, nay2; + assign yay2 = 3'b110; + assign nay2 = 3'b010; +endmodule diff --git a/tests/various/port_sign_extend.ys b/tests/various/port_sign_extend.ys new file mode 100644 index 000000000..6d1adf7f3 --- /dev/null +++ b/tests/various/port_sign_extend.ys @@ -0,0 +1,29 @@ +read_verilog -nomem2reg port_sign_extend.v +hierarchy +flatten +proc +memory +equiv_make ref act equiv +equiv_simple +equiv_status -assert + +delete + +read_verilog -nomem2reg port_sign_extend.v +flatten +proc +memory +equiv_make ref act equiv +equiv_simple +equiv_status -assert + +delete + +read_verilog -nomem2reg port_sign_extend.v +hierarchy +proc +memory +equiv_make ref act equiv +prep -flatten -top equiv +equiv_induct +equiv_status -assert diff --git a/tests/various/rand_const.sv b/tests/various/rand_const.sv new file mode 100644 index 000000000..be00812c0 --- /dev/null +++ b/tests/various/rand_const.sv @@ -0,0 +1,8 @@ +module top; + rand const reg rx; + const reg ry; + rand reg rz; + rand const integer ix; + const integer iy; + rand integer iz; +endmodule diff --git a/tests/various/rand_const.ys b/tests/various/rand_const.ys new file mode 100644 index 000000000..74e43c7cc --- /dev/null +++ b/tests/various/rand_const.ys @@ -0,0 +1 @@ +read_verilog -sv rand_const.sv diff --git a/tests/verilog/atom_type_signedness.ys b/tests/verilog/atom_type_signedness.ys new file mode 100644 index 000000000..22bbe6efc --- /dev/null +++ b/tests/verilog/atom_type_signedness.ys @@ -0,0 +1,19 @@ +read_verilog -dump_ast1 -dump_ast2 -sv <<EOT +module dut(); + +enum integer { uInteger = -10 } a; +enum int { uInt = -11 } b; +enum shortint { uShortInt = -12 } c; +enum byte { uByte = -13 } d; + +always_comb begin + assert(-10 == uInteger); + assert(-11 == uInt); + assert(-12 == uShortInt); + assert(-13 == uByte); +end +endmodule +EOT +hierarchy; proc; opt +select -module dut +sat -verify -seq 1 -tempinduct -prove-asserts -show-all diff --git a/tests/verilog/block_labels.ys b/tests/verilog/block_labels.ys new file mode 100644 index 000000000..e76bcf771 --- /dev/null +++ b/tests/verilog/block_labels.ys @@ -0,0 +1,26 @@ +read_verilog <<EOT +module foo; + + genvar a = 0; + for (a = 0; a < 10; a++) begin : a + end : a +endmodule +EOT +read_verilog <<EOT +module foo2; + + genvar a = 0; + for (a = 0; a < 10; a++) begin : a + end +endmodule +EOT + +logger -expect error "Begin label \(a\) and end label \(b\) don't match\." 1 +read_verilog <<EOT +module foo3; + + genvar a = 0; + for (a = 0; a < 10; a++) begin : a + end : b +endmodule +EOT diff --git a/tests/verilog/bug2493.ys b/tests/verilog/bug2493.ys new file mode 100644 index 000000000..380d2a823 --- /dev/null +++ b/tests/verilog/bug2493.ys @@ -0,0 +1,12 @@ +logger -expect error "Failed to detect width for identifier \\genblk1\.y!" 1 +read_verilog <<EOT +module top1; + wire x; + generate + if (1) begin + mod y(); + assign x = y; + end + endgenerate +endmodule +EOT diff --git a/tests/verilog/bug656.v b/tests/verilog/bug656.v new file mode 100644 index 000000000..068d045fd --- /dev/null +++ b/tests/verilog/bug656.v @@ -0,0 +1,21 @@ +module top #( + parameter WIDTH = 6 +) ( + input [WIDTH-1:0] a_i, + input [WIDTH-1:0] b_i, + output [WIDTH-1:0] z_o +); + genvar g; + generate + for (g = 0; g < WIDTH; g = g + 1) begin + if (g > 2) begin + wire tmp; + assign tmp = a_i[g] || b_i[g]; + assign z_o[g] = tmp; + end + else begin + assign z_o[g] = a_i[g] && b_i[g]; + end + end + endgenerate +endmodule diff --git a/tests/verilog/bug656.ys b/tests/verilog/bug656.ys new file mode 100644 index 000000000..7f367341a --- /dev/null +++ b/tests/verilog/bug656.ys @@ -0,0 +1,13 @@ +read_verilog bug656.v + +select -assert-count 1 top/a_i +select -assert-count 1 top/b_i +select -assert-count 1 top/z_o + +select -assert-none top/genblk1[0].genblk1.tmp +select -assert-none top/genblk1[1].genblk1.tmp +select -assert-none top/genblk1[2].genblk1.tmp + +select -assert-count 1 top/genblk1[3].genblk1.tmp +select -assert-count 1 top/genblk1[4].genblk1.tmp +select -assert-count 1 top/genblk1[5].genblk1.tmp diff --git a/tests/verilog/genblk_case.v b/tests/verilog/genblk_case.v new file mode 100644 index 000000000..081fb09d3 --- /dev/null +++ b/tests/verilog/genblk_case.v @@ -0,0 +1,26 @@ +module top; + parameter YES = 1; + generate + if (YES) wire y; + else wire n; + + if (!YES) wire n; + else wire y; + + case (YES) + 1: wire y; + 0: wire n; + endcase + + case (!YES) + 0: wire y; + 1: wire n; + endcase + + if (YES) wire y; + else wire n; + + if (!YES) wire n; + else wire y; + endgenerate +endmodule diff --git a/tests/verilog/genblk_case.ys b/tests/verilog/genblk_case.ys new file mode 100644 index 000000000..3c1bb51f9 --- /dev/null +++ b/tests/verilog/genblk_case.ys @@ -0,0 +1,15 @@ +read_verilog genblk_case.v + +select -assert-count 0 top/genblk1.n +select -assert-count 0 top/genblk2.n +select -assert-count 0 top/genblk3.n +select -assert-count 0 top/genblk4.n +select -assert-count 0 top/genblk5.n +select -assert-count 0 top/genblk6.n + +select -assert-count 1 top/genblk1.y +select -assert-count 1 top/genblk2.y +select -assert-count 1 top/genblk3.y +select -assert-count 1 top/genblk4.y +select -assert-count 1 top/genblk5.y +select -assert-count 1 top/genblk6.y diff --git a/tests/verilog/genblk_port_decl.ys b/tests/verilog/genblk_port_decl.ys new file mode 100644 index 000000000..589d3d2e1 --- /dev/null +++ b/tests/verilog/genblk_port_decl.ys @@ -0,0 +1,12 @@ +logger -expect error "Cannot declare module port `\\x' within a generate block\." 1 +read_verilog <<EOT +module top(x); + generate + if (1) begin : blk + output wire x; + assign x = 1; + end + endgenerate + output wire x; +endmodule +EOT diff --git a/tests/verilog/hidden_decl.ys b/tests/verilog/hidden_decl.ys new file mode 100644 index 000000000..aed7847dc --- /dev/null +++ b/tests/verilog/hidden_decl.ys @@ -0,0 +1,11 @@ +logger -expect error "Identifier `\\y' is implicitly declared and `default_nettype is set to none" 1 +read_verilog <<EOT +`default_nettype none +module top1; + wire x; + generate + if (1) wire y; + endgenerate + assign x = y; +endmodule +EOT diff --git a/tests/verilog/unnamed_block.ys b/tests/verilog/unnamed_block.ys new file mode 100644 index 000000000..0f209a089 --- /dev/null +++ b/tests/verilog/unnamed_block.ys @@ -0,0 +1,28 @@ +read_verilog <<EOT +module top; + initial begin : blk + integer x; + end +endmodule +EOT + +delete + +read_verilog -sv <<EOT +module top; + initial begin + integer x; + end +endmodule +EOT + +delete + +logger -expect error "Local declaration in unnamed block is only supported in SystemVerilog mode!" 1 +read_verilog <<EOT +module top; + initial begin + integer x; + end +endmodule +EOT diff --git a/tests/verilog/unnamed_genblk.sv b/tests/verilog/unnamed_genblk.sv new file mode 100644 index 000000000..41828b1b0 --- /dev/null +++ b/tests/verilog/unnamed_genblk.sv @@ -0,0 +1,39 @@ +// This test is taken directly from Section 27.6 of IEEE 1800-2017 + +module top; + parameter genblk2 = 0; + genvar i; + + // The following generate block is implicitly named genblk1 + + if (genblk2) logic a; // top.genblk1.a + else logic b; // top.genblk1.b + + // The following generate block is implicitly named genblk02 + // as genblk2 is already a declared identifier + + if (genblk2) logic a; // top.genblk02.a + else logic b; // top.genblk02.b + + // The following generate block would have been named genblk3 + // but is explicitly named g1 + + for (i = 0; i < 1; i = i + 1) begin : g1 // block name + // The following generate block is implicitly named genblk1 + // as the first nested scope inside g1 + if (1) logic a; // top.g1[0].genblk1.a + end + + // The following generate block is implicitly named genblk4 since + // it belongs to the fourth generate construct in scope "top". + // The previous generate block would have been + // named genblk3 if it had not been explicitly named g1 + + for (i = 0; i < 1; i = i + 1) + // The following generate block is implicitly named genblk1 + // as the first nested generate block in genblk4 + if (1) logic a; // top.genblk4[0].genblk1.a + + // The following generate block is implicitly named genblk5 + if (1) logic a; // top.genblk5.a +endmodule diff --git a/tests/verilog/unnamed_genblk.ys b/tests/verilog/unnamed_genblk.ys new file mode 100644 index 000000000..2b9aa9d69 --- /dev/null +++ b/tests/verilog/unnamed_genblk.ys @@ -0,0 +1,8 @@ +read_verilog -sv unnamed_genblk.sv +select -assert-count 0 top/genblk1.a +select -assert-count 1 top/genblk02.b +select -assert-count 0 top/genblk1.a +select -assert-count 1 top/genblk02.b +select -assert-count 1 top/g1[0].genblk1.a +select -assert-count 1 top/genblk4[0].genblk1.a +select -assert-count 1 top/genblk5.a diff --git a/tests/verilog/wire_and_var.sv b/tests/verilog/wire_and_var.sv new file mode 100644 index 000000000..79c7c04c6 --- /dev/null +++ b/tests/verilog/wire_and_var.sv @@ -0,0 +1,33 @@ +`define TEST(kwd) \ + kwd kwd``_1; \ + kwd kwd``_2; \ + initial kwd``_1 = 1; \ + assign kwd``_2 = 1; + +`define TEST_VAR(kwd) \ + var kwd var_``kwd``_1; \ + var kwd var_``kwd``_2; \ + initial var_``kwd``_1 = 1; \ + assign var_``kwd``_2 = 1; + +`define TEST_WIRE(kwd) \ + wire kwd wire_``kwd``_1; \ + wire kwd wire_``kwd``_2; \ + initial wire_``kwd``_1 = 1; \ + assign wire_``kwd``_2 = 1; + +module top; + +`TEST(wire) // wire assigned in a block +`TEST(reg) // reg assigned in a continuous assignment +`TEST(logic) +`TEST(integer) + +`TEST_VAR(reg) // reg assigned in a continuous assignment +`TEST_VAR(logic) +`TEST_VAR(integer) + +`TEST_WIRE(logic) // wire assigned in a block +`TEST_WIRE(integer) // wire assigned in a block + +endmodule diff --git a/tests/verilog/wire_and_var.ys b/tests/verilog/wire_and_var.ys new file mode 100644 index 000000000..9359a9d55 --- /dev/null +++ b/tests/verilog/wire_and_var.ys @@ -0,0 +1,9 @@ +logger -expect warning "wire '\\wire_1' is assigned in a block" 1 +logger -expect warning "reg '\\reg_2' is assigned in a continuous assignment" 1 + +logger -expect warning "reg '\\var_reg_2' is assigned in a continuous assignment" 1 + +logger -expect warning "wire '\\wire_logic_1' is assigned in a block" 1 +logger -expect warning "wire '\\wire_integer_1' is assigned in a block" 1 + +read_verilog -sv wire_and_var.sv |