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-rw-r--r--Makefile6
-rw-r--r--frontends/ast/genrtlil.cc2
-rw-r--r--frontends/ast/simplify.cc28
-rw-r--r--frontends/ilang/ilang_parser.y6
-rw-r--r--frontends/verilog/verilog_frontend.cc2
-rw-r--r--frontends/verilog/verilog_frontend.h2
-rw-r--r--frontends/verilog/verilog_parser.y68
-rw-r--r--kernel/constids.inc3
-rw-r--r--techlibs/ecp5/synth_ecp5.cc13
-rw-r--r--techlibs/ice40/synth_ice40.cc24
-rw-r--r--techlibs/xilinx/synth_xilinx.cc8
-rw-r--r--tests/various/primitives.ys16
-rw-r--r--tests/various/specify.ys6
13 files changed, 119 insertions, 65 deletions
diff --git a/Makefile b/Makefile
index 47de420b8..838d29788 100644
--- a/Makefile
+++ b/Makefile
@@ -136,7 +136,7 @@ bumpversion:
# is just a symlink to your actual ABC working directory, as 'make mrproper'
# will remove the 'abc' directory and you do not want to accidentally
# delete your work on ABC..
-ABCREV = d14acd8
+ABCREV = fd2c9b1
ABCPULL = 1
ABCURL ?= https://github.com/YosysHQ/abc
ABCMKARGS = CC="$(CXX)" CXX="$(CXX)" ABC_USE_LIBSTDCXX=1
@@ -281,13 +281,13 @@ yosys.html: misc/yosys.html
else ifeq ($(CONFIG),wasi)
ifeq ($(WASI_SDK),)
-CXX = clang++
+CXX = clang
LD = clang++
AR = llvm-ar
RANLIB = llvm-ranlib
WASIFLAGS := -target wasm32-wasi --sysroot $(WASI_SYSROOT) $(WASIFLAGS)
else
-CXX = $(WASI_SDK)/bin/clang++
+CXX = $(WASI_SDK)/bin/clang
LD = $(WASI_SDK)/bin/clang++
AR = $(WASI_SDK)/bin/ar
RANLIB = $(WASI_SDK)/bin/ranlib
diff --git a/frontends/ast/genrtlil.cc b/frontends/ast/genrtlil.cc
index 5894c7b3c..996762715 100644
--- a/frontends/ast/genrtlil.cc
+++ b/frontends/ast/genrtlil.cc
@@ -171,7 +171,7 @@ struct AST_INTERNAL::LookaheadRewriter
for (auto c : node->id2ast->children)
wire->children.push_back(c->clone());
wire->str = stringf("$lookahead%s$%d", node->str.c_str(), autoidx++);
- wire->attributes["\\nosync"] = AstNode::mkconst_int(1, false);
+ wire->attributes[ID::nosync] = AstNode::mkconst_int(1, false);
wire->is_logic = true;
while (wire->simplify(true, false, false, 1, -1, false, false)) { }
current_ast_mod->children.push_back(wire);
diff --git a/frontends/ast/simplify.cc b/frontends/ast/simplify.cc
index 837c14ad7..252219094 100644
--- a/frontends/ast/simplify.cc
+++ b/frontends/ast/simplify.cc
@@ -920,11 +920,11 @@ bool AstNode::simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage,
range_swapped = templ->range_swapped;
range_left = templ->range_left;
range_right = templ->range_right;
- attributes["\\wiretype"] = mkconst_str(resolved_type->str);
+ attributes[ID::wiretype] = mkconst_str(resolved_type->str);
//check if enum
- if (templ->attributes.count("\\enum_type")){
+ if (templ->attributes.count(ID::enum_type)){
//get reference to enum node:
- std::string enum_type = templ->attributes["\\enum_type"]->str.c_str();
+ const std::string &enum_type = templ->attributes[ID::enum_type]->str;
// log("enum_type=%s (count=%lu)\n", enum_type.c_str(), current_scope.count(enum_type));
// log("current scope:\n");
// for (auto &it : current_scope)
@@ -972,7 +972,7 @@ bool AstNode::simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage,
RTLIL::Const val = enum_item->children[0]->bitsAsConst(width, is_signed);
enum_item_str.append(val.as_string());
//set attribute for available val to enum item name mappings
- attributes[enum_item_str.c_str()] = mkconst_str(enum_item->str);
+ attributes[enum_item_str] = mkconst_str(enum_item->str);
}
}
@@ -1021,7 +1021,7 @@ bool AstNode::simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage,
range_swapped = templ->range_swapped;
range_left = templ->range_left;
range_right = templ->range_right;
- attributes["\\wiretype"] = mkconst_str(resolved_type->str);
+ attributes[ID::wiretype] = mkconst_str(resolved_type->str);
for (auto template_child : templ->children)
children.push_back(template_child->clone());
did_something = true;
@@ -1739,8 +1739,10 @@ bool AstNode::simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage,
AstNode *node = children_list[1];
if (op_type != AST_POS)
- for (size_t i = 2; i < children_list.size(); i++)
+ for (size_t i = 2; i < children_list.size(); i++) {
node = new AstNode(op_type, node, children_list[i]);
+ node->location = location;
+ }
if (invert_results)
node = new AstNode(AST_BIT_NOT, node);
@@ -1810,14 +1812,14 @@ bool AstNode::simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage,
AstNode *wire_mask = new AstNode(AST_WIRE, new AstNode(AST_RANGE, mkconst_int(source_width-1, true), mkconst_int(0, true)));
wire_mask->str = stringf("$bitselwrite$mask$%s:%d$%d", filename.c_str(), location.first_line, autoidx++);
- wire_mask->attributes["\\nosync"] = AstNode::mkconst_int(1, false);
+ wire_mask->attributes[ID::nosync] = AstNode::mkconst_int(1, false);
wire_mask->is_logic = true;
while (wire_mask->simplify(true, false, false, 1, -1, false, false)) { }
current_ast_mod->children.push_back(wire_mask);
AstNode *wire_data = new AstNode(AST_WIRE, new AstNode(AST_RANGE, mkconst_int(source_width-1, true), mkconst_int(0, true)));
wire_data->str = stringf("$bitselwrite$data$%s:%d$%d", filename.c_str(), location.first_line, autoidx++);
- wire_data->attributes["\\nosync"] = AstNode::mkconst_int(1, false);
+ wire_data->attributes[ID::nosync] = AstNode::mkconst_int(1, false);
wire_data->is_logic = true;
while (wire_data->simplify(true, false, false, 1, -1, false, false)) { }
current_ast_mod->children.push_back(wire_data);
@@ -2637,7 +2639,7 @@ skip_dynamic_range_lvalue_expansion:;
bool recommend_const_eval = false;
bool require_const_eval = in_param ? false : has_const_only_constructs(recommend_const_eval);
- if ((in_param || recommend_const_eval || require_const_eval) && !decl->attributes.count("\\via_celltype"))
+ if ((in_param || recommend_const_eval || require_const_eval) && !decl->attributes.count(ID::via_celltype))
{
bool all_args_const = true;
for (auto child : children) {
@@ -2696,9 +2698,9 @@ skip_dynamic_range_lvalue_expansion:;
goto replace_fcall_with_id;
}
- if (decl->attributes.count("\\via_celltype"))
+ if (decl->attributes.count(ID::via_celltype))
{
- std::string celltype = decl->attributes.at("\\via_celltype")->asAttrConst().decode_string();
+ std::string celltype = decl->attributes.at(ID::via_celltype)->asAttrConst().decode_string();
std::string outport = str;
if (celltype.find(' ') != std::string::npos) {
@@ -2792,7 +2794,7 @@ skip_dynamic_range_lvalue_expansion:;
wire->is_reg = true;
wire->attributes[ID::nosync] = AstNode::mkconst_int(1, false);
if (child->type == AST_ENUM_ITEM)
- wire->attributes["\\enum_base_type"] = child->attributes["\\enum_base_type"];
+ wire->attributes[ID::enum_base_type] = child->attributes[ID::enum_base_type];
wire_cache[child->str] = wire;
@@ -4092,7 +4094,7 @@ void AstNode::allocateDefaultEnumValues()
int last_enum_int = -1;
for (auto node : children) {
log_assert(node->type==AST_ENUM_ITEM);
- node->attributes["\\enum_base_type"] = mkconst_str(str);
+ node->attributes[ID::enum_base_type] = mkconst_str(str);
for (size_t i = 0; i < node->children.size(); i++) {
switch (node->children[i]->type) {
case AST_NONE:
diff --git a/frontends/ilang/ilang_parser.y b/frontends/ilang/ilang_parser.y
index 8e21fb176..118f13de9 100644
--- a/frontends/ilang/ilang_parser.y
+++ b/frontends/ilang/ilang_parser.y
@@ -107,16 +107,16 @@ module:
delete_current_module = false;
if (current_design->has($2)) {
RTLIL::Module *existing_mod = current_design->module($2);
- if (!flag_overwrite && (flag_lib || (attrbuf.count("\\blackbox") && attrbuf.at("\\blackbox").as_bool()))) {
+ if (!flag_overwrite && (flag_lib || (attrbuf.count(ID::blackbox) && attrbuf.at(ID::blackbox).as_bool()))) {
log("Ignoring blackbox re-definition of module %s.\n", $2);
delete_current_module = true;
- } else if (!flag_nooverwrite && !flag_overwrite && !existing_mod->get_bool_attribute("\\blackbox")) {
+ } else if (!flag_nooverwrite && !flag_overwrite && !existing_mod->get_bool_attribute(ID::blackbox)) {
rtlil_frontend_ilang_yyerror(stringf("ilang error: redefinition of module %s.", $2).c_str());
} else if (flag_nooverwrite) {
log("Ignoring re-definition of module %s.\n", $2);
delete_current_module = true;
} else {
- log("Replacing existing%s module %s.\n", existing_mod->get_bool_attribute("\\blackbox") ? " blackbox" : "", $2);
+ log("Replacing existing%s module %s.\n", existing_mod->get_bool_attribute(ID::blackbox) ? " blackbox" : "", $2);
current_design->remove(existing_mod);
}
}
diff --git a/frontends/verilog/verilog_frontend.cc b/frontends/verilog/verilog_frontend.cc
index 6879e0943..26abe49b5 100644
--- a/frontends/verilog/verilog_frontend.cc
+++ b/frontends/verilog/verilog_frontend.cc
@@ -48,7 +48,7 @@ static void error_on_dpi_function(AST::AstNode *node)
error_on_dpi_function(child);
}
-static void add_package_types(std::map<std::string, AST::AstNode *> &user_types, std::vector<AST::AstNode *> &package_list)
+static void add_package_types(dict<std::string, AST::AstNode *> &user_types, std::vector<AST::AstNode *> &package_list)
{
// prime the parser's user type lookup table with the package qualified names
// of typedefed names in the packages seen so far.
diff --git a/frontends/verilog/verilog_frontend.h b/frontends/verilog/verilog_frontend.h
index 444cc7297..aa7881038 100644
--- a/frontends/verilog/verilog_frontend.h
+++ b/frontends/verilog/verilog_frontend.h
@@ -50,7 +50,7 @@ namespace VERILOG_FRONTEND
extern std::vector<UserTypeMap *> user_type_stack;
// names of package typedef'ed types
- extern std::map<std::string, AST::AstNode*> pkg_user_types;
+ extern dict<std::string, AST::AstNode*> pkg_user_types;
// state of `default_nettype
extern bool default_nettype_wire;
diff --git a/frontends/verilog/verilog_parser.y b/frontends/verilog/verilog_parser.y
index 3738f8f3d..4a531c09f 100644
--- a/frontends/verilog/verilog_parser.y
+++ b/frontends/verilog/verilog_parser.y
@@ -50,12 +50,12 @@ using namespace VERILOG_FRONTEND;
YOSYS_NAMESPACE_BEGIN
namespace VERILOG_FRONTEND {
int port_counter;
- std::map<std::string, int> port_stubs;
- std::map<std::string, AstNode*> *attr_list, default_attr_list;
- std::stack<std::map<std::string, AstNode*> *> attr_list_stack;
- std::map<std::string, AstNode*> *albuf;
+ dict<std::string, int> port_stubs;
+ dict<IdString, AstNode*> *attr_list, default_attr_list;
+ std::stack<dict<IdString, AstNode*> *> attr_list_stack;
+ dict<IdString, AstNode*> *albuf;
std::vector<UserTypeMap*> user_type_stack;
- std::map<std::string, AstNode*> pkg_user_types;
+ dict<std::string, AstNode*> pkg_user_types;
std::vector<AstNode*> ast_stack;
struct AstNode *astbuf1, *astbuf2, *astbuf3;
struct AstNode *current_function_or_task;
@@ -87,7 +87,7 @@ YOSYS_NAMESPACE_END
int frontend_verilog_yylex(YYSTYPE *yylval_param, YYLTYPE *yyloc_param);
-static void append_attr(AstNode *ast, std::map<std::string, AstNode*> *al)
+static void append_attr(AstNode *ast, dict<IdString, AstNode*> *al)
{
for (auto &it : *al) {
if (ast->attributes.count(it.first) > 0)
@@ -97,7 +97,7 @@ static void append_attr(AstNode *ast, std::map<std::string, AstNode*> *al)
delete al;
}
-static void append_attr_clone(AstNode *ast, std::map<std::string, AstNode*> *al)
+static void append_attr_clone(AstNode *ast, dict<IdString, AstNode*> *al)
{
for (auto &it : *al) {
if (ast->attributes.count(it.first) > 0)
@@ -106,7 +106,7 @@ static void append_attr_clone(AstNode *ast, std::map<std::string, AstNode*> *al)
}
}
-static void free_attr(std::map<std::string, AstNode*> *al)
+static void free_attr(dict<IdString, AstNode*> *al)
{
for (auto &it : *al)
delete it.second;
@@ -192,7 +192,7 @@ static void addRange(AstNode *parent, int msb = 31, int lsb = 0, bool isSigned =
%union {
std::string *string;
struct YOSYS_NAMESPACE_PREFIX AST::AstNode *ast;
- std::map<std::string, YOSYS_NAMESPACE_PREFIX AST::AstNode*> *al;
+ YOSYS_NAMESPACE_PREFIX dict<YOSYS_NAMESPACE_PREFIX RTLIL::IdString, YOSYS_NAMESPACE_PREFIX AST::AstNode*> *al;
struct specify_target *specify_target_ptr;
struct specify_triple *specify_triple_ptr;
struct specify_rise_fall *specify_rise_fall_ptr;
@@ -289,7 +289,7 @@ attr:
{
if (attr_list != nullptr)
attr_list_stack.push(attr_list);
- attr_list = new std::map<std::string, AstNode*>;
+ attr_list = new dict<IdString, AstNode*>;
for (auto &it : default_attr_list)
(*attr_list)[it.first] = it.second->clone();
} attr_opt {
@@ -311,7 +311,7 @@ defattr:
DEFATTR_BEGIN {
if (attr_list != nullptr)
attr_list_stack.push(attr_list);
- attr_list = new std::map<std::string, AstNode*>;
+ attr_list = new dict<IdString, AstNode*>;
for (auto &it : default_attr_list)
delete it.second;
default_attr_list.clear();
@@ -885,6 +885,7 @@ specify_item:
cell->str = stringf("$specify$%d", autoidx++);
cell->children.push_back(new AstNode(AST_CELLTYPE));
cell->children.back()->str = target->dat ? "$specify3" : "$specify2";
+ SET_AST_NODE_LOC(cell, en_expr ? @1 : @2, @10);
char oper_polarity = 0;
char oper_type = oper->at(0);
@@ -973,6 +974,7 @@ specify_item:
cell->str = stringf("$specify$%d", autoidx++);
cell->children.push_back(new AstNode(AST_CELLTYPE));
cell->children.back()->str = "$specrule";
+ SET_AST_NODE_LOC(cell, @1, @14);
cell->children.push_back(new AstNode(AST_PARASET, AstNode::mkconst_str(*$1)));
cell->children.back()->str = "\\TYPE";
@@ -1099,8 +1101,8 @@ specify_rise_fall:
$$->fall = *$4;
delete $2;
delete $4;
- delete $6;
- log_file_warning(current_filename, get_line_num(), "Path delay expressions beyond rise/fall not currently supported. Ignoring.\n");
+ delete $6;
+ log_file_warning(current_filename, get_line_num(), "Path delay expressions beyond rise/fall not currently supported. Ignoring.\n");
} |
'(' specify_triple ',' specify_triple ',' specify_triple ',' specify_triple ',' specify_triple ',' specify_triple ')' {
$$ = new specify_rise_fall;
@@ -1108,11 +1110,11 @@ specify_rise_fall:
$$->fall = *$4;
delete $2;
delete $4;
- delete $6;
- delete $8;
- delete $10;
- delete $12;
- log_file_warning(current_filename, get_line_num(), "Path delay expressions beyond rise/fall not currently supported. Ignoring.\n");
+ delete $6;
+ delete $8;
+ delete $10;
+ delete $12;
+ log_file_warning(current_filename, get_line_num(), "Path delay expressions beyond rise/fall not currently supported. Ignoring.\n");
} |
'(' specify_triple ',' specify_triple ',' specify_triple ',' specify_triple ',' specify_triple ',' specify_triple ',' specify_triple ',' specify_triple ',' specify_triple ',' specify_triple ',' specify_triple ',' specify_triple ')' {
$$ = new specify_rise_fall;
@@ -1120,17 +1122,17 @@ specify_rise_fall:
$$->fall = *$4;
delete $2;
delete $4;
- delete $6;
- delete $8;
- delete $10;
- delete $12;
- delete $14;
- delete $16;
- delete $18;
- delete $20;
- delete $22;
- delete $24;
- log_file_warning(current_filename, get_line_num(), "Path delay expressions beyond rise/fall not currently supported. Ignoring.\n");
+ delete $6;
+ delete $8;
+ delete $10;
+ delete $12;
+ delete $14;
+ delete $16;
+ delete $18;
+ delete $20;
+ delete $22;
+ delete $24;
+ log_file_warning(current_filename, get_line_num(), "Path delay expressions beyond rise/fall not currently supported. Ignoring.\n");
}
specify_triple:
@@ -1388,7 +1390,7 @@ enum_type: TOK_ENUM {
delete astbuf1;
astbuf1 = tnode;
tnode->type = AST_WIRE;
- tnode->attributes["\\enum_type"] = AstNode::mkconst_str(astbuf2->str);
+ tnode->attributes[ID::enum_type] = AstNode::mkconst_str(astbuf2->str);
// drop constant but keep any range
delete tnode->children[0];
tnode->children.erase(tnode->children.begin()); }
@@ -1747,7 +1749,9 @@ single_prim:
/* no name */ {
astbuf2 = astbuf1->clone();
ast_stack.back()->children.push_back(astbuf2);
- } '(' cell_port_list ')';
+ } '(' cell_port_list ')' {
+ SET_AST_NODE_LOC(astbuf2, @1, @$);
+ }
cell_parameter_list_opt:
'#' '(' cell_parameter_list ')' | /* empty */;
@@ -2341,7 +2345,7 @@ unique_case_attr:
case_attr:
attr unique_case_attr {
- if ($2) (*$1)["\\parallel_case"] = AstNode::mkconst_int(1, false);
+ if ($2) (*$1)[ID::parallel_case] = AstNode::mkconst_int(1, false);
$$ = $1;
};
diff --git a/kernel/constids.inc b/kernel/constids.inc
index 27b652e24..aa75a9c09 100644
--- a/kernel/constids.inc
+++ b/kernel/constids.inc
@@ -74,6 +74,8 @@ X(EN)
X(EN_DST)
X(EN_POLARITY)
X(EN_SRC)
+X(enum_base_type)
+X(enum_type)
X(equiv_merged)
X(equiv_region)
X(extract_order)
@@ -196,6 +198,7 @@ X(U)
X(unique)
X(unused_bits)
X(V)
+X(via_celltype)
X(wand)
X(whitebox)
X(WIDTH)
diff --git a/techlibs/ecp5/synth_ecp5.cc b/techlibs/ecp5/synth_ecp5.cc
index ab740ea0d..b9b236a0c 100644
--- a/techlibs/ecp5/synth_ecp5.cc
+++ b/techlibs/ecp5/synth_ecp5.cc
@@ -30,6 +30,11 @@ struct SynthEcp5Pass : public ScriptPass
{
SynthEcp5Pass() : ScriptPass("synth_ecp5", "synthesis for ECP5 FPGAs") { }
+ void on_register() YS_OVERRIDE
+ {
+ RTLIL::constpad["synth_ecp5.abc9.W"] = "300";
+ }
+
void help() YS_OVERRIDE
{
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
@@ -324,6 +329,14 @@ struct SynthEcp5Pass : public ScriptPass
if (abc9) {
run("read_verilog -icells -lib -specify +/abc9_model.v +/ecp5/abc9_model.v");
+ std::string abc9_opts;
+ if (nowidelut)
+ abc9_opts += " -maxlut 4";
+ std::string k = "synth_ecp5.abc9.W";
+ if (active_design && active_design->scratchpad.count(k))
+ abc9_opts += stringf(" -W %s", active_design->scratchpad_get_string(k).c_str());
+ else
+ abc9_opts += stringf(" -W %s", RTLIL::constpad.at(k).c_str());
if (nowidelut)
run("abc9 -maxlut 4 -W 200");
else
diff --git a/techlibs/ice40/synth_ice40.cc b/techlibs/ice40/synth_ice40.cc
index 9724b7dd5..2b211572d 100644
--- a/techlibs/ice40/synth_ice40.cc
+++ b/techlibs/ice40/synth_ice40.cc
@@ -29,6 +29,13 @@ struct SynthIce40Pass : public ScriptPass
{
SynthIce40Pass() : ScriptPass("synth_ice40", "synthesis for iCE40 FPGAs") { }
+ void on_register() YS_OVERRIDE
+ {
+ RTLIL::constpad["synth_ice40.abc9.hx.W"] = "250";
+ RTLIL::constpad["synth_ice40.abc9.lp.W"] = "400";
+ RTLIL::constpad["synth_ice40.abc9.u.W"] = "750";
+ }
+
void help() YS_OVERRIDE
{
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
@@ -373,14 +380,15 @@ struct SynthIce40Pass : public ScriptPass
if (!noabc) {
if (abc9) {
run("read_verilog " + define + " -icells -lib -specify +/abc9_model.v +/ice40/abc9_model.v");
- int wire_delay;
- if (device_opt == "lp")
- wire_delay = 400;
- else if (device_opt == "u")
- wire_delay = 750;
- else
- wire_delay = 250;
- run(stringf("abc9 -W %d", wire_delay));
+ std::string abc9_opts;
+ std::string k = "synth_ice40.abc9.W";
+ if (active_design && active_design->scratchpad.count(k))
+ abc9_opts += stringf(" -W %s", active_design->scratchpad_get_string(k).c_str());
+ else {
+ k = stringf("synth_ice40.abc9.%s.W", device_opt.c_str());
+ abc9_opts += stringf(" -W %s", RTLIL::constpad.at(k).c_str());
+ }
+ run("abc9 " + abc9_opts);
}
else
run("abc -dress -lut 4", "(skip if -noabc)");
diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc
index 1c190d37e..229ffcb3d 100644
--- a/techlibs/xilinx/synth_xilinx.cc
+++ b/techlibs/xilinx/synth_xilinx.cc
@@ -619,11 +619,13 @@ struct SynthXilinxPass : public ScriptPass
run("techmap " + techmap_args);
run("read_verilog -icells -lib -specify +/abc9_model.v +/xilinx/abc9_model.v");
std::string abc9_opts;
- auto k = stringf("synth_xilinx.abc9.%s.W", family.c_str());
- if (active_design->scratchpad.count(k))
+ std::string k = "synth_xilinx.abc9.W";
+ if (active_design && active_design->scratchpad.count(k))
abc9_opts += stringf(" -W %s", active_design->scratchpad_get_string(k).c_str());
- else
+ else {
+ k = stringf("synth_xilinx.abc9.%s.W", family.c_str());
abc9_opts += stringf(" -W %s", RTLIL::constpad.at(k, RTLIL::constpad.at("synth_xilinx.abc9.xc7.W")).c_str());
+ }
if (nowidelut)
abc9_opts += stringf(" -maxlut %d", lut_size);
if (dff_mode)
diff --git a/tests/various/primitives.ys b/tests/various/primitives.ys
new file mode 100644
index 000000000..9307ca50f
--- /dev/null
+++ b/tests/various/primitives.ys
@@ -0,0 +1,16 @@
+read_verilog <<EOT
+module top(input a, b, output [5:0] y);
+and (y[0], a, b);
+nand (y[1], a, b);
+or (y[2], a, b);
+nor (y[3], a, b);
+xor (y[4], a, b);
+xnor (y[5], a, b);
+endmodule
+EOT
+select -assert-count 1 t:$and a:src=<<EOT:2.4-2.17 %i
+select -assert-count 1 t:$and a:src=<<EOT:3.5-3.18 %i
+select -assert-count 1 t:$or a:src=<<EOT:4.3-4.16 %i
+select -assert-count 1 t:$or a:src=<<EOT:5.4-5.17 %i
+select -assert-count 1 t:$xor a:src=<<EOT:6.4-6.17 %i
+select -assert-count 1 t:$xor a:src=<<EOT:7.5-7.18 %i
diff --git a/tests/various/specify.ys b/tests/various/specify.ys
index 9d55b8eb5..d7260d524 100644
--- a/tests/various/specify.ys
+++ b/tests/various/specify.ys
@@ -4,10 +4,16 @@ cd test
select t:$specify2 -assert-count 0
select t:$specify3 -assert-count 1
select t:$specrule -assert-count 2
+select t:$specify3 a:src=specify.v:10.3-10.49 %i -assert-count 1
+select t:$specrule a:src=specify.v:11.3-11.36 %i -assert-count 1
+select t:$specrule a:src=specify.v:12.3-12.35 %i -assert-count 1
cd test2
select t:$specify2 -assert-count 2
select t:$specify3 -assert-count 0
select t:$specrule -assert-count 0
+select t:$specify2 a:src=specify.v:26.3-26.20 %i -assert-count 1
+ # ^^ Note use of macro
+select t:$specify2 a:src=specify.v:28.3-28.18 %i -assert-count 1
cd
write_verilog specify.out
design -stash gold
generated by cgit v1.2.3 (git 2.25.1) at 2025-04-06 11:16:05 +0000