diff options
| -rw-r--r-- | examples/igloo2/.gitignore | 2 | ||||
| -rw-r--r-- | examples/igloo2/example.v | 22 | ||||
| -rw-r--r-- | examples/igloo2/example.ys | 2 | ||||
| -rw-r--r-- | examples/igloo2/libero.sh | 4 | ||||
| -rw-r--r-- | examples/igloo2/libero.tcl | 14 | ||||
| -rw-r--r-- | frontends/verilog/verilog_lexer.l | 2 |
6 files changed, 45 insertions, 1 deletions
diff --git a/examples/igloo2/.gitignore b/examples/igloo2/.gitignore new file mode 100644 index 000000000..ae86e69cc --- /dev/null +++ b/examples/igloo2/.gitignore @@ -0,0 +1,2 @@ +/example.edn +/work diff --git a/examples/igloo2/example.v b/examples/igloo2/example.v new file mode 100644 index 000000000..3eb7007c5 --- /dev/null +++ b/examples/igloo2/example.v @@ -0,0 +1,22 @@ +module top ( + input clk, + output LED1, + output LED2, + output LED3, + output LED4, + output LED5 +); + + localparam BITS = 5; + localparam LOG2DELAY = 22; + + reg [BITS+LOG2DELAY-1:0] counter = 0; + reg [BITS-1:0] outcnt; + + always @(posedge clk) begin + counter <= counter + 1; + outcnt <= counter >> LOG2DELAY; + end + + assign {LED1, LED2, LED3, LED4, LED5} = outcnt ^ (outcnt >> 1); +endmodule diff --git a/examples/igloo2/example.ys b/examples/igloo2/example.ys new file mode 100644 index 000000000..75a305d86 --- /dev/null +++ b/examples/igloo2/example.ys @@ -0,0 +1,2 @@ +read_verilog example.v +synth_sf2 -top top -edif example.edn diff --git a/examples/igloo2/libero.sh b/examples/igloo2/libero.sh new file mode 100644 index 000000000..582f6ccb9 --- /dev/null +++ b/examples/igloo2/libero.sh @@ -0,0 +1,4 @@ +#!/bin/bash +set -ex +rm -rf work +LM_LICENSE_FILE=1702@`hostname` /opt/microsemi/Libero_SoC_v11.9/Libero/bin/libero SCRIPT:libero.tcl diff --git a/examples/igloo2/libero.tcl b/examples/igloo2/libero.tcl new file mode 100644 index 000000000..cc1ab2403 --- /dev/null +++ b/examples/igloo2/libero.tcl @@ -0,0 +1,14 @@ +# Run with "libero SCRIPT:libero.tcl" + +new_project \ + -name top \ + -location work \ + -family IGLOO2 \ + -die PA4MGL500 \ + -package tq144 \ + -speed -1 \ + -hdl VERILOG + +import_files -edif {example.edn} +run_tool –name {COMPILE} +run_tool –name {PLACEROUTEN} diff --git a/frontends/verilog/verilog_lexer.l b/frontends/verilog/verilog_lexer.l index f9118e142..1b1873e24 100644 --- a/frontends/verilog/verilog_lexer.l +++ b/frontends/verilog/verilog_lexer.l @@ -274,7 +274,7 @@ YOSYS_NAMESPACE_END yystr[j++] = yystr[i++]; } yystr[j] = 0; - frontend_verilog_yylval.string = new std::string(yystr); + frontend_verilog_yylval.string = new std::string(yystr, j); free(yystr); return TOK_STRING; } |