int a = aig_map.at(sig[i]);

if (verbose_map)

if (wire->port_input) {

log_assert((a & 1) == 0);

}

if (wire->port_output) {

int o = ordered_outputs.at(sig[i]);

}

if (init_inputs.count(sig[i])) {

int a = init_inputs.at(sig[i]);

log_assert((a & 1) == 0);

}

if (ordered_latches.count(sig[i])) {

int l = ordered_latches.at(sig[i]);

if (zinit_mode && (aig_latchinit.at(l) == 1))

else

}

}

}

if (input_bits.count(b)) {

int a = aig_map.at(b);

log_assert((a & 1) == 0);

}

if (output_bits.count(b)) {

int o = ordered_outputs.at(b);

continue;

}

}

ff->attributes[ID::abc9_mergeability] = mergeability[i];

}

if (!map_filename.empty()) {

std::ifstream mf(map_filename);

log_assert(wire->port_input);

log_debug("Renaming input %s", log_id(wire));

if (index == 0) {

// Cope with the fact that a CI might be identical

// to a PI (necessary due to ABC); in those cases

// simply connect the latter to the former

if (!existing)

module->rename(wire, escaped_s);

else {

}

log_debug(" -> %s\n", log_id(escaped_s));

}

module->rename(wire, indexed_name);

else {

module->connect(wire, existing);

wire->port_input = false;

}

log_debug(" -> %s\n", log_id(indexed_name));

}

}

else if (type == "output") {

log_assert(static_cast<unsigned>(variable + co_count) < outputs.size());

log_assert(wire->port_output);

log_debug("Renaming output %s", log_id(wire));

if (index == 0) {

// Cope with the fact that a CO might be identical

// to a PO (necessary due to ABC); in those cases

// simply connect the latter to the former

module->rename(wire, escaped_s);

else {

wire->port_output = false;

existing->port_output = true;

}

log_debug(" -> %s\n", log_id(escaped_s));

}

module->rename(wire, indexed_name);

else {

wire->port_output = false;

existing->port_output = true;

}

log_debug(" -> %s\n", log_id(indexed_name));

}

}

else if (type == "box") {

RTLIL::Cell* cell = module->cell(stringf("$box%d", variable));

for (auto &wp : wideports_cache) {

auto name = wp.first;

RTLIL::Wire *wire = module->wire(name);

if (wire)

// Do not make ports with a mix of input/output into

// wide ports

bool port_input = false, port_output = false;

RTLIL::IdString other_name = name.str() + stringf("[%d]", i);

RTLIL::Wire *other_wire = module->wire(other_name);

if (other_wire) {

}

}

wire->port_input = port_input;

wire->port_output = port_output;

RTLIL::Wire *other_wire = module->wire(other_name);

if (other_wire) {

other_wire->port_input = false;

other_wire->port_output = false;

if (wire->port_input)

else

}

}

}

// helper function for creating RTLIL code for unary operations

static RTLIL::SigSpec uniop2rtlil(AstNode *that, IdString type, int result_width, const RTLIL::SigSpec &arg, bool gen_attributes = true)

{

RTLIL::Cell *cell = current_module->addCell(name, type);

RTLIL::Wire *wire = current_module->addWire(cell->name.str() + "_Y", result_width);

if (gen_attributes)

for (auto &attr : that->attributes) {

return;

}

RTLIL::Cell *cell = current_module->addCell(name, ID($pos));

RTLIL::Wire *wire = current_module->addWire(cell->name.str() + "_Y", width);

if (that != NULL)

for (auto &attr : that->attributes) {

// helper function for creating RTLIL code for binary operations

static RTLIL::SigSpec binop2rtlil(AstNode *that, IdString type, int result_width, const RTLIL::SigSpec &left, const RTLIL::SigSpec &right)

{

RTLIL::Cell *cell = current_module->addCell(name, type);

RTLIL::Wire *wire = current_module->addWire(cell->name.str() + "_Y", result_width);

for (auto &attr : that->attributes) {

if (attr.second->type != AST_CONSTANT)

sstr << "$ternary$" << that->filename << ":" << that->location.first_line << "$" << (autoidx++);

RTLIL::Cell *cell = current_module->addCell(sstr.str(), ID($mux));

RTLIL::Wire *wire = current_module->addWire(cell->name.str() + "_Y", left.size());

for (auto &attr : that->attributes) {

if (attr.second->type != AST_CONSTANT)

sstr << "$memrd$" << str << "$" << filename << ":" << location.first_line << "$" << (autoidx++);

RTLIL::Cell *cell = current_module->addCell(sstr.str(), ID($memrd));

RTLIL::Wire *wire = current_module->addWire(cell->name.str() + "_DATA", current_module->memories[str]->width);

int mem_width, mem_size, addr_bits;

is_signed = id2ast->is_signed;

AstNode *node = children_list[1];

if (op_type != AST_POS)

node = new AstNode(op_type, node, children_list[i]);

if (invert_results)

node = new AstNode(AST_BIT_NOT, node);

cell->str = stringf("$specify$%d", autoidx++);

cell->children.push_back(new AstNode(AST_CELLTYPE));

cell->children.back()->str = target->dat ? "$specify3" : "$specify2";

char oper_polarity = 0;

char oper_type = oper->at(0);

cell->str = stringf("$specify$%d", autoidx++);

cell->children.push_back(new AstNode(AST_CELLTYPE));

cell->children.back()->str = "$specrule";

cell->children.push_back(new AstNode(AST_PARASET, AstNode::mkconst_str(*$1)));

cell->children.back()->str = "\\TYPE";

$$->fall = *$4;

delete $2;

delete $4;

} |

'(' specify_triple ',' specify_triple ',' specify_triple ',' specify_triple ',' specify_triple ',' specify_triple ')' {

$$ = new specify_rise_fall;

$$->fall = *$4;

delete $2;

delete $4;

} |

'(' specify_triple ',' specify_triple ',' specify_triple ',' specify_triple ',' specify_triple ',' specify_triple ',' specify_triple ',' specify_triple ',' specify_triple ',' specify_triple ',' specify_triple ',' specify_triple ')' {

$$ = new specify_rise_fall;

$$->fall = *$4;

delete $2;

delete $4;

}

specify_triple:

/* no name */ {

astbuf2 = astbuf1->clone();

ast_stack.back()->children.push_back(astbuf2);

cell_parameter_list_opt:

'#' '(' cell_parameter_list ')' | /* empty */;

if (check_expected_logs)

log_check_expected();

#ifdef EMSCRIPTEN

log_files = backup_log_files;

throw 0;

}

if (item.second.current_count != item.second.expected_count) {

log_warn_regexes.clear();

item.second.pattern.c_str(), item.second.current_count, item.second.expected_count);

}

}

_exit(0);

#else

_Exit(0);

} else {

display_error_log_msg = false;

log_warn_regexes.clear();

std::regex_constants::egrep)

#endif

# include <sys/time.h>

# include <sys/resource.h>

#endif

#if defined(_MSC_VER)

#define S__LINE__sub1(x) S__LINE__sub2(x)

#define S__LINE__ S__LINE__sub1(__LINE__)

struct log_cmd_error_exception { };

extern std::vector<FILE*> log_files;

RTLIL::SigSpec sig_a = assign_map(cell->getPort(ID::A));

RTLIL::SigSpec sig_b = assign_map(cell->getPort(ID::B));

RTLIL::SigSpec sig_y = cell->getPort(ID::Y);

bool sub = cell->type == ID($sub);

int i;

module->connect(sig_y[i], a);

else if (sub && b == State::S1 && a == State::S1)

module->connect(sig_y[i], State::S0);

module->connect(sig_y[i], b);

else

break;

}

if (i > 0) {

cover_list("opt.opt_expr.fine", "$add", "$sub", cell->type.str());

cell->setPort(ID::Y, sig_y.extract_end(i));

cell->fixup_parameters();

did_something = true;

RTLIL::SigSpec sig_x = cell->getPort(ID::X);

RTLIL::SigSpec sig_y = cell->getPort(ID::Y);

RTLIL::SigSpec sig_co = cell->getPort(ID::CO);

if (sig_bi != State::S0 && sig_bi != State::S1)

goto skip_fine_alu;

bool bi = sig_bi == State::S1;

bool ci = sig_ci == State::S1;

int i;

module->connect(sig_y[i], a);

module->connect(sig_x[i], ci ? module->Not(NEW_ID, a).as_bit() : a);

module->connect(sig_co[i], ci ? State::S1 : State::S0);

}

module->connect(sig_y[i], bi ? module->Not(NEW_ID, b).as_bit() : b);

module->connect(sig_x[i], (bi ^ ci) ? module->Not(NEW_ID, b).as_bit() : b);

module->connect(sig_co[i], ci ? State::S1 : State::S0);

}

if (i > 0) {

cover("opt.opt_expr.fine.$alu");

cell->setPort(ID::X, sig_x.extract_end(i));

cell->setPort(ID::Y, sig_y.extract_end(i));

cell->setPort(ID::CO, sig_co.extract_end(i));

if (mapped_mod == NULL)

log_error("ABC output file does not contain a module `%s$abc'.\n", log_id(module));

dict<IdString,std::vector<IdString>> box_ports;

wire->attributes.erase(ID::abc9_scc);

RTLIL::Wire *remap_wire = module->wire(remap_name(port));

log_assert(GetSize(signal) >= GetSize(remap_wire));

RTLIL::SigSig conn;

{

SynthEcp5Pass() : ScriptPass("synth_ecp5", "synthesis for ECP5 FPGAs") { }

void help() YS_OVERRIDE

{

// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|

if (abc9) {

run("read_verilog -icells -lib -specify +/abc9_model.v +/ecp5/abc9_model.v");

if (nowidelut)

run("abc9 -maxlut 4 -W 200");

else

{

SynthIce40Pass() : ScriptPass("synth_ice40", "synthesis for iCE40 FPGAs") { }

void help() YS_OVERRIDE

{

// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|

if (!noabc) {

if (abc9) {

run("read_verilog " + define + " -icells -lib -specify +/abc9_model.v +/ice40/abc9_model.v");

}

else

run("abc -dress -lut 4", "(skip if -noabc)");

run("techmap " + techmap_args);

run("read_verilog -icells -lib -specify +/abc9_model.v +/xilinx/abc9_model.v");

std::string abc9_opts;

abc9_opts += stringf(" -W %s", active_design->scratchpad_get_string(k).c_str());

abc9_opts += stringf(" -W %s", RTLIL::constpad.at(k, RTLIL::constpad.at("synth_xilinx.abc9.xc7.W")).c_str());

if (nowidelut)

abc9_opts += stringf(" -maxlut %d", lut_size);

if (dff_mode)

sat -verify -prove-asserts -show-ports -seq 16 miter

" -l ${aig}.log

done

select t:$specify2 -assert-count 0

select t:$specify3 -assert-count 1

select t:$specrule -assert-count 2

cd test2

select t:$specify2 -assert-count 2

select t:$specify3 -assert-count 0

select t:$specrule -assert-count 0

cd

write_verilog specify.out

design -stash gold