diff options
| -rw-r--r-- | kernel/rtlil.cc | 1 | ||||
| -rw-r--r-- | passes/hierarchy/hierarchy.cc | 4 |
2 files changed, 1 insertions, 4 deletions
diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc index 40ad8ca13..365bfd9f8 100644 --- a/kernel/rtlil.cc +++ b/kernel/rtlil.cc @@ -2050,6 +2050,7 @@ RTLIL::Memory::Memory() hashidx_ = hashidx_count; width = 1; + start_offset = 0; size = 0; } diff --git a/passes/hierarchy/hierarchy.cc b/passes/hierarchy/hierarchy.cc index 337af7fd7..f1c4a1d3b 100644 --- a/passes/hierarchy/hierarchy.cc +++ b/passes/hierarchy/hierarchy.cc @@ -175,16 +175,12 @@ bool expand_module(RTLIL::Design *design, RTLIL::Module *module, bool flag_check { filename = dir + "/" + RTLIL::unescape_id(cell->type) + ".v"; if (check_file_exists(filename)) { - std::vector<std::string> args; - args.push_back(filename); Frontend::frontend_call(design, NULL, filename, "verilog"); goto loaded_module; } filename = dir + "/" + RTLIL::unescape_id(cell->type) + ".il"; if (check_file_exists(filename)) { - std::vector<std::string> args; - args.push_back(filename); Frontend::frontend_call(design, NULL, filename, "ilang"); goto loaded_module; } |