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-rw-r--r--Makefile2
-rw-r--r--techlibs/fabulous/cells_map.v7
-rw-r--r--techlibs/fabulous/prims.v32
-rw-r--r--techlibs/gowin/cells_sim.v244
4 files changed, 283 insertions, 2 deletions
diff --git a/Makefile b/Makefile
index c38495fe2..9592a6a5b 100644
--- a/Makefile
+++ b/Makefile
@@ -141,7 +141,7 @@ LDLIBS += -lrt
endif
endif
-YOSYS_VER := 0.27+22
+YOSYS_VER := 0.27+33
# Note: We arrange for .gitcommit to contain the (short) commit hash in
# tarballs generated with git-archive(1) using .gitattributes. The git repo
diff --git a/techlibs/fabulous/cells_map.v b/techlibs/fabulous/cells_map.v
index eadd18b6f..e33e641a8 100644
--- a/techlibs/fabulous/cells_map.v
+++ b/techlibs/fabulous/cells_map.v
@@ -16,10 +16,15 @@ module \$lut (A, Y);
end else
if (WIDTH == 3) begin
LUT3 #(.INIT(LUT)) _TECHMAP_REPLACE_ (.O(Y), .I0(A[0]), .I1(A[1]), .I2(A[2]));
-
end else
if (WIDTH == 4) begin
LUT4 #(.INIT(LUT)) _TECHMAP_REPLACE_ (.O(Y), .I0(A[0]), .I1(A[1]), .I2(A[2]), .I3(A[3]));
+ end else
+ if (WIDTH == 5) begin
+ LUT5 #(.INIT(LUT)) _TECHMAP_REPLACE_ (.O(Y), .I0(A[0]), .I1(A[1]), .I2(A[2]), .I3(A[3]), .I4(A[4]));
+ end else
+ if (WIDTH == 6) begin
+ LUT6 #(.INIT(LUT)) _TECHMAP_REPLACE_ (.O(Y), .I0(A[0]), .I1(A[1]), .I2(A[2]), .I3(A[3]), .I4(A[4]), .I5(A[5]));
end else begin
wire _TECHMAP_FAIL_ = 1;
end
diff --git a/techlibs/fabulous/prims.v b/techlibs/fabulous/prims.v
index fe3e8536a..21dc5223d 100644
--- a/techlibs/fabulous/prims.v
+++ b/techlibs/fabulous/prims.v
@@ -38,6 +38,38 @@ module LUT4_HA(output O, Co, input I0, I1, I2, I3, Ci);
assign Co = (Ci & I1) | (Ci & I2) | (I1 & I2);
endmodule
+module LUT5(output O, input I0, I1, I2, I3, I4);
+ parameter [31:0] INIT = 0;
+ wire [15: 0] s4 = I4 ? INIT[31:16] : INIT[15: 0];
+ wire [ 7: 0] s3 = I3 ? s4[15: 8] : s4[ 7: 0];
+ wire [ 3: 0] s2 = I2 ? s3[ 7: 4] : s3[ 3: 0];
+ wire [ 1: 0] s1 = I1 ? s2[ 3: 2] : s2[ 1: 0];
+ assign O = I0 ? s1[1] : s1[0];
+endmodule
+
+module LUT6(output O, input I0, I1, I2, I3, I4, I5);
+ parameter [63:0] INIT = 0;
+ wire [31: 0] s5 = I5 ? INIT[63:32] : INIT[31: 0];
+ wire [15: 0] s4 = I4 ? s5[31:16] : s5[15: 0];
+ wire [ 7: 0] s3 = I3 ? s4[15: 8] : s4[ 7: 0];
+ wire [ 3: 0] s2 = I2 ? s3[ 7: 4] : s3[ 3: 0];
+ wire [ 1: 0] s1 = I1 ? s2[ 3: 2] : s2[ 1: 0];
+ assign O = I0 ? s1[1] : s1[0];
+endmodule
+
+module LUT55_FCY (output O, Co, input I0, I1, I2, I3, I4, Ci);
+ parameter [63:0] INIT = 0;
+
+ wire comb1, comb2;
+
+ LUT5 #(.INIT(INIT[31: 0])) l5_1 (.I0(I0), .I1(I1), .I2(I2), .I3(I3), .I4(I4), .O(comb1));
+ LUT5 #(.INIT(INIT[63:32])) l5_2 (.I0(I0), .I1(I1), .I2(I2), .I3(I3), .I4(I4), .O(comb2));
+
+ assign O = comb1 ^ Ci;
+ assign Co = comb1 ? Ci : comb2;
+endmodule
+
+
module LUTFF(input CLK, D, output reg O);
initial O = 1'b0;
always @ (posedge CLK) begin
diff --git a/techlibs/gowin/cells_sim.v b/techlibs/gowin/cells_sim.v
index 535fd05ed..86bd677e2 100644
--- a/techlibs/gowin/cells_sim.v
+++ b/techlibs/gowin/cells_sim.v
@@ -598,6 +598,250 @@ module TLVDS_OBUF (I, O, OB);
assign OB = ~I;
endmodule
+module OSER4(D3, D2, D1, D0, TX1, TX0, FCLK, PCLK, RESET, Q1, Q0);
+ output Q1;
+ output Q0;
+
+ input D3;
+ input D2;
+ input D1;
+ input D0;
+ input TX1;
+ input TX0;
+ input FCLK;
+ input PCLK;
+ input RESET;
+
+ parameter GSREN = "false";
+ parameter LSREN = "true";
+ parameter TXCLK_POL = 0;
+ parameter HWL = "false";
+endmodule
+
+module OSER8(D7, D6, D5, D4, D3, D2, D1, D0, TX3, TX2, TX1, TX0, FCLK, PCLK, RESET, Q1, Q0);
+ output Q1;
+ output Q0;
+
+ input D7;
+ input D6;
+ input D5;
+ input D4;
+ input D3;
+ input D2;
+ input D1;
+ input D0;
+ input TX3;
+ input TX2;
+ input TX1;
+ input TX0;
+ input FCLK;
+ input PCLK;
+ input RESET;
+
+ parameter GSREN = "false";
+ parameter LSREN = "true";
+ parameter TXCLK_POL = 0;
+ parameter HWL = "false";
+endmodule
+
+module OSER10(D9, D8, D7, D6, D5, D4, D3, D2, D1, D0, FCLK, PCLK, RESET, Q);
+ output Q;
+
+ input D9;
+ input D8;
+ input D7;
+ input D6;
+ input D5;
+ input D4;
+ input D3;
+ input D2;
+ input D1;
+ input D0;
+ input FCLK;
+ input PCLK;
+ input RESET;
+
+ parameter GSREN = "false";
+ parameter LSREN = "true";
+endmodule
+
+module OVIDEO(D6, D5, D4, D3, D2, D1, D0, FCLK, PCLK, RESET, Q);
+ output Q;
+
+ input D6;
+ input D5;
+ input D4;
+ input D3;
+ input D2;
+ input D1;
+ input D0;
+ input FCLK;
+ input PCLK;
+ input RESET;
+
+ parameter GSREN = "false";
+ parameter LSREN = "true";
+endmodule
+
+module OSER16(D15, D14, D13, D12, D11, D10,
+D9, D8, D7, D6, D5, D4, D3, D2, D1, D0, FCLK, PCLK,
+RESET, Q);
+ output Q;
+
+ input D15;
+ input D14;
+ input D13;
+ input D12;
+ input D11;
+ input D10;
+ input D9;
+ input D8;
+ input D7;
+ input D6;
+ input D5;
+ input D4;
+ input D3;
+ input D2;
+ input D1;
+ input D0;
+ input FCLK;
+ input PCLK;
+ input RESET;
+
+ parameter GSREN = "false";
+ parameter LSREN = "true";
+endmodule
+
+module IDES4(Q3, Q2, Q1, Q0, FCLK, PCLK,
+RESET, CALIB, D);
+ input D;
+ input FCLK;
+ input PCLK;
+ input RESET;
+ input CALIB;
+
+ output Q3;
+ output Q2;
+ output Q1;
+ output Q0;
+
+ parameter GSREN = "false";
+ parameter LSREN = "true";
+endmodule
+
+module IDES8(Q7, Q6, Q5, Q4, Q3, Q2, Q1, Q0, FCLK, PCLK,
+RESET, CALIB, D);
+ input D;
+ input FCLK;
+ input PCLK;
+ input RESET;
+ input CALIB;
+
+ output Q7;
+ output Q6;
+ output Q5;
+ output Q4;
+ output Q3;
+ output Q2;
+ output Q1;
+ output Q0;
+
+ parameter GSREN = "false";
+ parameter LSREN = "true";
+endmodule
+
+module IDES10(Q9, Q8, Q7, Q6, Q5, Q4, Q3, Q2, Q1, Q0, FCLK, PCLK,
+RESET, CALIB, D);
+ input D;
+ input FCLK;
+ input PCLK;
+ input RESET;
+ input CALIB;
+
+ output Q9;
+ output Q8;
+ output Q7;
+ output Q6;
+ output Q5;
+ output Q4;
+ output Q3;
+ output Q2;
+ output Q1;
+ output Q0;
+
+ parameter GSREN = "false";
+ parameter LSREN = "true";
+endmodule
+
+module IVIDEO(Q6, Q5, Q4, Q3, Q2, Q1, Q0, FCLK, PCLK,
+RESET, CALIB, D);
+ input D;
+ input FCLK;
+ input PCLK;
+ input RESET;
+ input CALIB;
+
+ output Q6;
+ output Q5;
+ output Q4;
+ output Q3;
+ output Q2;
+ output Q1;
+ output Q0;
+
+ parameter GSREN = "false";
+ parameter LSREN = "true";
+endmodule
+
+module IDES16(Q15, Q14, Q13, Q12, Q11, Q10,
+Q9, Q8, Q7, Q6, Q5, Q4, Q3, Q2, Q1, Q0, FCLK, PCLK,
+RESET, CALIB, D);
+ input D;
+ input FCLK;
+ input PCLK;
+ input RESET;
+ input CALIB;
+
+ output Q15;
+ output Q14;
+ output Q13;
+ output Q12;
+ output Q11;
+ output Q10;
+ output Q9;
+ output Q8;
+ output Q7;
+ output Q6;
+ output Q5;
+ output Q4;
+ output Q3;
+ output Q2;
+ output Q1;
+ output Q0;
+
+ parameter GSREN = "false";
+ parameter LSREN = "true";
+endmodule
+
+module IDDR(D, CLK, Q0, Q1);
+ input D;
+ input CLK;
+ output Q0;
+ output Q1;
+ parameter Q0_INIT = 1'b0;
+ parameter Q1_INIT = 1'b0;
+endmodule
+
+module IDDRC(D, CLK, CLEAR, Q0, Q1);
+ input D;
+ input CLK;
+ input CLEAR;
+ output Q0;
+ output Q1;
+ parameter Q0_INIT = 1'b0;
+ parameter Q1_INIT = 1'b0;
+endmodule
+
(* blackbox *)
module ODDR(D0, D1, TX, CLK, Q0, Q1);
input D0;
generated by cgit v1.2.3 (git 2.25.1) at 2024-05-29 07:53:20 +0000