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-rw-r--r--Makefile2
-rw-r--r--backends/aiger/aiger.cc112
-rw-r--r--backends/smt2/smt2.cc275
-rw-r--r--backends/smt2/smtbmc.py8
-rw-r--r--backends/smt2/smtio.py2
-rw-r--r--frontends/ast/ast.cc2
-rw-r--r--frontends/ast/ast.h2
-rw-r--r--frontends/ast/genrtlil.cc7
-rw-r--r--frontends/ast/simplify.cc4
-rw-r--r--frontends/verilog/verilog_lexer.l3
-rw-r--r--frontends/verilog/verilog_parser.y26
-rw-r--r--kernel/celltypes.h2
-rw-r--r--kernel/rtlil.cc18
-rw-r--r--kernel/rtlil.h2
-rw-r--r--manual/CHAPTER_CellLib.tex2
-rw-r--r--passes/hierarchy/hierarchy.cc2
-rw-r--r--passes/opt/opt_clean.cc2
-rw-r--r--passes/tests/test_cell.cc2
-rw-r--r--techlibs/common/simlib.v16
-rw-r--r--techlibs/greenpak4/cells_sim.v7
20 files changed, 410 insertions, 86 deletions
diff --git a/Makefile b/Makefile
index a6779334e..e779cf20d 100644
--- a/Makefile
+++ b/Makefile
@@ -478,7 +478,7 @@ ifeq ($(ENABLE_LIBYOSYS),1)
endif
uninstall:
- $(INSTALL_SUDO) rm -vf $(addprefix $(DESTDIR)$(BINDIR),$(notdir $(TARGETS)))
+ $(INSTALL_SUDO) rm -vf $(addprefix $(DESTDIR)$(BINDIR)/,$(notdir $(TARGETS)))
$(INSTALL_SUDO) rm -rvf $(DESTDIR)$(DATDIR)
ifeq ($(ENABLE_LIBYOSYS),1)
$(INSTALL_SUDO) rm -vf $(DESTDIR)$(LIBDIR)/libyosys.so
diff --git a/backends/aiger/aiger.cc b/backends/aiger/aiger.cc
index ab1fba6f1..02871a6fd 100644
--- a/backends/aiger/aiger.cc
+++ b/backends/aiger/aiger.cc
@@ -46,11 +46,13 @@ struct AigerWriter
dict<SigBit, SigBit> not_map, ff_map;
dict<SigBit, pair<SigBit, SigBit>> and_map;
vector<pair<SigBit, SigBit>> asserts, assumes;
+ vector<pair<SigBit, SigBit>> liveness, fairness;
pool<SigBit> initstate_bits;
vector<pair<int, int>> aig_gates;
vector<int> aig_latchin, aig_latchinit, aig_outputs;
- int aig_m = 0, aig_i = 0, aig_l = 0, aig_o = 0, aig_a = 0, aig_b = 0, aig_c = 0;
+ int aig_m = 0, aig_i = 0, aig_l = 0, aig_o = 0, aig_a = 0;
+ int aig_b = 0, aig_c = 0, aig_j = 0, aig_f = 0;
dict<SigBit, int> aig_map;
dict<SigBit, int> ordered_outputs;
@@ -163,6 +165,22 @@ struct AigerWriter
continue;
}
+ if (cell->type == "$live")
+ {
+ SigBit A = sigmap(cell->getPort("\\A").as_bit());
+ SigBit EN = sigmap(cell->getPort("\\EN").as_bit());
+ liveness.push_back(make_pair(A, EN));
+ continue;
+ }
+
+ if (cell->type == "$fair")
+ {
+ SigBit A = sigmap(cell->getPort("\\A").as_bit());
+ SigBit EN = sigmap(cell->getPort("\\EN").as_bit());
+ fairness.push_back(make_pair(A, EN));
+ continue;
+ }
+
if (cell->type == "$anyconst")
{
for (auto bit : sigmap(cell->getPort("\\Y")))
@@ -198,6 +216,12 @@ struct AigerWriter
}
}
+ int fair_live_inputs_cnt = GetSize(liveness);
+ int fair_live_inputs_m = aig_m;
+
+ aig_m += fair_live_inputs_cnt;
+ aig_i += fair_live_inputs_cnt;
+
for (auto it : ff_map) {
aig_m++, aig_l++;
aig_map[it.first] = 2*aig_m;
@@ -214,6 +238,16 @@ struct AigerWriter
aig_latchinit.push_back(0);
}
+ int fair_live_latches_cnt = GetSize(fairness) + 2*GetSize(liveness);
+ int fair_live_latches_m = aig_m;
+ int fair_live_latches_l = aig_l;
+
+ aig_m += fair_live_latches_cnt;
+ aig_l += fair_live_latches_cnt;
+
+ for (int i = 0; i < fair_live_latches_cnt; i++)
+ aig_latchinit.push_back(0);
+
if (zinit_mode)
{
for (auto it : ff_map)
@@ -263,23 +297,67 @@ struct AigerWriter
int bit_en = bit2aig(it.second);
aig_outputs.push_back(mkgate(bit_a^1, bit_en)^1);
}
+
+ for (auto it : liveness)
+ {
+ int input_m = ++fair_live_inputs_m;
+ int latch_m1 = ++fair_live_latches_m;
+ int latch_m2 = ++fair_live_latches_m;
+
+ log_assert(GetSize(aig_latchin) == fair_live_latches_l);
+ fair_live_latches_l += 2;
+
+ int bit_a = bit2aig(it.first);
+ int bit_en = bit2aig(it.second);
+ int bit_s = 2*input_m;
+ int bit_q1 = 2*latch_m1;
+ int bit_q2 = 2*latch_m2;
+
+ int bit_d1 = mkgate(mkgate(bit_s, bit_en)^1, bit_q1^1)^1;
+ int bit_d2 = mkgate(mkgate(bit_d1, bit_a)^1, bit_q2^1)^1;
+
+ aig_j++;
+ aig_latchin.push_back(bit_d1);
+ aig_latchin.push_back(bit_d2);
+ aig_outputs.push_back(mkgate(bit_q1, bit_q2^1));
+ }
+
+ for (auto it : fairness)
+ {
+ int latch_m = ++fair_live_latches_m;
+
+ log_assert(GetSize(aig_latchin) == fair_live_latches_l);
+ fair_live_latches_l += 1;
+
+ int bit_a = bit2aig(it.first);
+ int bit_en = bit2aig(it.second);
+ int bit_q = 2*latch_m;
+
+ aig_f++;
+ aig_latchin.push_back(mkgate(mkgate(bit_q^1, bit_en^1)^1, bit_a^1));
+ aig_outputs.push_back(bit_q^1);
+ }
}
void write_aiger(std::ostream &f, bool ascii_mode, bool miter_mode, bool symbols_mode)
{
+ int aig_obc = aig_o + aig_b + aig_c;
+ int aig_obcj = aig_obc + aig_j;
+ int aig_obcjf = aig_obcj + aig_f;
+
log_assert(aig_m == aig_i + aig_l + aig_a);
log_assert(aig_l == GetSize(aig_latchin));
log_assert(aig_l == GetSize(aig_latchinit));
- log_assert((aig_o + aig_b + aig_c) == GetSize(aig_outputs));
+ log_assert(aig_obcjf == GetSize(aig_outputs));
if (miter_mode) {
- if (aig_b || aig_c)
- log_error("Running AIGER back-end in -miter mode, but design contains $assert and/or $assume cells!\n");
+ if (aig_b || aig_c || aig_j || aig_f)
+ log_error("Running AIGER back-end in -miter mode, but design contains $assert, $assume, $live and/or $fair cells!\n");
f << stringf("%s %d %d %d 0 %d %d\n", ascii_mode ? "aag" : "aig", aig_m, aig_i, aig_l, aig_a, aig_o);
} else {
f << stringf("%s %d %d %d %d %d", ascii_mode ? "aag" : "aig", aig_m, aig_i, aig_l, aig_o, aig_a);
- if (aig_b || aig_c)
- f << stringf(" %d %d", aig_b, aig_c);
+ if (aig_b || aig_c || aig_j || aig_f)
+ f << stringf(" %d %d %d %d", aig_b, aig_c, aig_j, aig_f);
f << stringf("\n");
}
@@ -297,7 +375,16 @@ struct AigerWriter
f << stringf("%d %d %d\n", 2*(aig_i+i)+2, aig_latchin.at(i), 2*(aig_i+i)+2);
}
- for (int i = 0; i < aig_o + aig_b + aig_c; i++)
+ for (int i = 0; i < aig_obc; i++)
+ f << stringf("%d\n", aig_outputs.at(i));
+
+ for (int i = aig_obc; i < aig_obcj; i++)
+ f << stringf("1\n");
+
+ for (int i = aig_obc; i < aig_obcj; i++)
+ f << stringf("%d\n", aig_outputs.at(i));
+
+ for (int i = aig_obcj; i < aig_obcjf; i++)
f << stringf("%d\n", aig_outputs.at(i));
for (int i = 0; i < aig_a; i++)
@@ -314,7 +401,16 @@ struct AigerWriter
f << stringf("%d %d\n", aig_latchin.at(i), 2*(aig_i+i)+2);
}
- for (int i = 0; i < aig_o + aig_b + aig_c; i++)
+ for (int i = 0; i < aig_obc; i++)
+ f << stringf("%d\n", aig_outputs.at(i));
+
+ for (int i = aig_obc; i < aig_obcj; i++)
+ f << stringf("1\n");
+
+ for (int i = aig_obc; i < aig_obcj; i++)
+ f << stringf("%d\n", aig_outputs.at(i));
+
+ for (int i = aig_obcj; i < aig_obcjf; i++)
f << stringf("%d\n", aig_outputs.at(i));
for (int i = 0; i < aig_a; i++) {
diff --git a/backends/smt2/smt2.cc b/backends/smt2/smt2.cc
index 932f5cd68..6c2100f05 100644
--- a/backends/smt2/smt2.cc
+++ b/backends/smt2/smt2.cc
@@ -32,8 +32,9 @@ struct Smt2Worker
CellTypes ct;
SigMap sigmap;
RTLIL::Module *module;
- bool bvmode, memmode, wiresmode, verbose;
- int idcounter;
+ bool bvmode, memmode, wiresmode, verbose, statebv;
+ dict<IdString, int> &mod_stbv_width;
+ int idcounter, statebv_width;
std::vector<std::string> decls, trans, hier;
std::map<RTLIL::SigBit, RTLIL::Cell*> bit_driver;
@@ -63,12 +64,39 @@ struct Smt2Worker
return get_id(obj->name);
}
- Smt2Worker(RTLIL::Module *module, bool bvmode, bool memmode, bool wiresmode, bool verbose) :
- ct(module->design), sigmap(module), module(module), bvmode(bvmode), memmode(memmode),
- wiresmode(wiresmode), verbose(verbose), idcounter(0)
+ void makebits(std::string name, int width = 0, std::string comment = std::string())
{
- decls.push_back(stringf("(declare-sort |%s_s| 0)\n", get_id(module)));
- decls.push_back(stringf("(declare-fun |%s_is| (|%s_s|) Bool)\n", get_id(module), get_id(module)));
+ std::string decl_str;
+
+ if (statebv)
+ {
+ if (width == 0) {
+ decl_str = stringf("(define-fun |%s| ((state |%s_s|)) Bool (= ((_ extract %d %d) state) #b1))", name.c_str(), get_id(module), statebv_width, statebv_width);
+ statebv_width += 1;
+ } else {
+ decl_str = stringf("(define-fun |%s| ((state |%s_s|)) (_ BitVec %d) ((_ extract %d %d) state))", name.c_str(), get_id(module), width, statebv_width+width-1, statebv_width);
+ statebv_width += width;
+ }
+ }
+ else
+ {
+ if (width == 0) {
+ decl_str = stringf("(declare-fun |%s| (|%s_s|) Bool)\n", name.c_str(), get_id(module));
+ } else {
+ decl_str = stringf("(declare-fun |%s| (|%s_s|) (_ BitVec %d))", name.c_str(), get_id(module), width);
+ }
+ }
+
+ if (!comment.empty())
+ decl_str += " ; " + comment;
+ decls.push_back(decl_str + "\n");
+ }
+
+ Smt2Worker(RTLIL::Module *module, bool bvmode, bool memmode, bool wiresmode, bool verbose, bool statebv, dict<IdString, int> &mod_stbv_width) :
+ ct(module->design), sigmap(module), module(module), bvmode(bvmode), memmode(memmode), wiresmode(wiresmode),
+ verbose(verbose), statebv(statebv), mod_stbv_width(mod_stbv_width), idcounter(0), statebv_width(0)
+ {
+ makebits(stringf("%s_is", get_id(module)));
for (auto cell : module->cells())
for (auto &conn : cell->connections()) {
@@ -162,8 +190,7 @@ struct Smt2Worker
if (fcache.count(bit) == 0) {
if (verbose) log("%*s-> external bool: %s\n", 2+2*GetSize(recursive_cells), "",
log_signal(bit));
- decls.push_back(stringf("(declare-fun |%s#%d| (|%s_s|) Bool) ; %s\n",
- get_id(module), idcounter, get_id(module), log_signal(bit)));
+ makebits(stringf("%s#%d", get_id(module), idcounter), 0, log_signal(bit));
register_bool(bit, idcounter++);
}
@@ -237,8 +264,7 @@ struct Smt2Worker
log_signal(sig.extract(i, j)));
for (auto bit : sig.extract(i, j))
log_assert(bit_driver.count(bit) == 0);
- decls.push_back(stringf("(declare-fun |%s#%d| (|%s_s|) (_ BitVec %d)) ; %s\n",
- get_id(module), idcounter, get_id(module), j, log_signal(sig.extract(i, j))));
+ makebits(stringf("%s#%d", get_id(module), idcounter), j, log_signal(sig.extract(i, j)));
subexpr.push_back(stringf("(|%s#%d| %s)", get_id(module), idcounter, state_name));
register_bv(sig.extract(i, j), idcounter++);
}
@@ -382,8 +408,7 @@ struct Smt2Worker
if (cell->type.in("$_FF_", "$_DFF_P_", "$_DFF_N_"))
{
registers.insert(cell);
- decls.push_back(stringf("(declare-fun |%s#%d| (|%s_s|) Bool) ; %s\n",
- get_id(module), idcounter, get_id(module), log_signal(cell->getPort("\\Q"))));
+ makebits(stringf("%s#%d", get_id(module), idcounter), 0, log_signal(cell->getPort("\\Q")));
register_bool(cell->getPort("\\Q"), idcounter++);
recursive_cells.erase(cell);
return;
@@ -410,8 +435,7 @@ struct Smt2Worker
if (cell->type.in("$ff", "$dff"))
{
registers.insert(cell);
- decls.push_back(stringf("(declare-fun |%s#%d| (|%s_s|) (_ BitVec %d)) ; %s\n",
- get_id(module), idcounter, get_id(module), GetSize(cell->getPort("\\Q")), log_signal(cell->getPort("\\Q"))));
+ makebits(stringf("%s#%d", get_id(module), idcounter), GetSize(cell->getPort("\\Q")), log_signal(cell->getPort("\\Q")));
register_bv(cell->getPort("\\Q"), idcounter++);
recursive_cells.erase(cell);
return;
@@ -422,8 +446,7 @@ struct Smt2Worker
registers.insert(cell);
decls.push_back(stringf("; yosys-smt2-%s %s#%d %s\n", cell->type.c_str() + 1, get_id(module), idcounter,
cell->attributes.count("\\src") ? cell->attributes.at("\\src").decode_string().c_str() : get_id(cell)));
- decls.push_back(stringf("(declare-fun |%s#%d| (|%s_s|) (_ BitVec %d)) ; %s\n",
- get_id(module), idcounter, get_id(module), GetSize(cell->getPort("\\Y")), log_signal(cell->getPort("\\Y"))));
+ makebits(stringf("%s#%d", get_id(module), idcounter), GetSize(cell->getPort("\\Y")), log_signal(cell->getPort("\\Y")));
register_bv(cell->getPort("\\Y"), idcounter++);
recursive_cells.erase(cell);
return;
@@ -513,30 +536,80 @@ struct Smt2Worker
int abits = cell->getParam("\\ABITS").as_int();
int width = cell->getParam("\\WIDTH").as_int();
int rd_ports = cell->getParam("\\RD_PORTS").as_int();
+ int wr_ports = cell->getParam("\\WR_PORTS").as_int();
+
+ decls.push_back(stringf("; yosys-smt2-memory %s %d %d %d %d\n", get_id(cell), abits, width, rd_ports, wr_ports));
+
+ if (statebv)
+ {
+ int mem_size = cell->getParam("\\SIZE").as_int();
+ int mem_offset = cell->getParam("\\OFFSET").as_int();
+
+ makebits(stringf("%s#%d#0", get_id(module), arrayid), width*mem_size, get_id(cell));
+
+ decls.push_back(stringf("(define-fun |%s_m %s| ((state |%s_s|)) (_ BitVec %d) (|%s#%d#0| state))\n",
+ get_id(module), get_id(cell), get_id(module), width*mem_size, get_id(module), arrayid));
+
+ for (int i = 0; i < rd_ports; i++)
+ {
+ SigSpec addr_sig = cell->getPort("\\RD_ADDR").extract(abits*i, abits);
+ SigSpec data_sig = cell->getPort("\\RD_DATA").extract(width*i, width);
+ std::string addr = get_bv(addr_sig);
+
+ if (cell->getParam("\\RD_CLK_ENABLE").extract(i).as_bool())
+ log_error("Read port %d (%s) of memory %s.%s is clocked. This is not supported by \"write_smt2\"! "
+ "Call \"memory\" with -nordff to avoid this error.\n", i, log_signal(data_sig), log_id(cell), log_id(module));
+
+ decls.push_back(stringf("(define-fun |%s_m:%d %s| ((state |%s_s|)) (_ BitVec %d) %s) ; %s\n",
+ get_id(module), i, get_id(cell), get_id(module), abits, addr.c_str(), log_signal(addr_sig)));
+
+ std::string read_expr = "#b";
+ for (int k = 0; k < width; k++)
+ read_expr += "0";
- decls.push_back(stringf("(declare-fun |%s#%d#0| (|%s_s|) (Array (_ BitVec %d) (_ BitVec %d))) ; %s\n",
- get_id(module), arrayid, get_id(module), abits, width, get_id(cell)));
+ for (int k = 0; k < mem_size; k++)
+ read_expr = stringf("(ite (= (|%s_m:%d %s| state) #b%s) ((_ extract %d %d) (|%s#%d#0| state))\n %s)",
+ get_id(module), i, get_id(cell), Const(k+mem_offset, abits).as_string().c_str(),
+ width*(k+1)-1, width*k, get_id(module), arrayid, read_expr.c_str());
- decls.push_back(stringf("; yosys-smt2-memory %s %d %d %d\n", get_id(cell), abits, width, rd_ports));
- decls.push_back(stringf("(define-fun |%s_m %s| ((state |%s_s|)) (Array (_ BitVec %d) (_ BitVec %d)) (|%s#%d#0| state))\n",
- get_id(module), get_id(cell), get_id(module), abits, width, get_id(module), arrayid));
+ decls.push_back(stringf("(define-fun |%s#%d| ((state |%s_s|)) (_ BitVec %d)\n %s) ; %s\n",
+ get_id(module), idcounter, get_id(module), width, read_expr.c_str(), log_signal(data_sig)));
- for (int i = 0; i < rd_ports; i++)
+ decls.push_back(stringf("(define-fun |%s_m:%dD %s| ((state |%s_s|)) (_ BitVec %d) (|%s#%d| state))\n",
+ get_id(module), i, get_id(cell), get_id(module), width, get_id(module), idcounter));
+
+ register_bv(data_sig, idcounter++);
+ }
+ }
+ else
{
- SigSpec addr_sig = cell->getPort("\\RD_ADDR").extract(abits*i, abits);
- SigSpec data_sig = cell->getPort("\\RD_DATA").extract(width*i, width);
- std::string addr = get_bv(addr_sig);
+ decls.push_back(stringf("(declare-fun |%s#%d#0| (|%s_s|) (Array (_ BitVec %d) (_ BitVec %d))) ; %s\n",
+ get_id(module), arrayid, get_id(module), abits, width, get_id(cell)));
+
+ decls.push_back(stringf("(define-fun |%s_m %s| ((state |%s_s|)) (Array (_ BitVec %d) (_ BitVec %d)) (|%s#%d#0| state))\n",
+ get_id(module), get_id(cell), get_id(module), abits, width, get_id(module), arrayid));
+
+ for (int i = 0; i < rd_ports; i++)
+ {
+ SigSpec addr_sig = cell->getPort("\\RD_ADDR").extract(abits*i, abits);
+ SigSpec data_sig = cell->getPort("\\RD_DATA").extract(width*i, width);
+ std::string addr = get_bv(addr_sig);
- if (cell->getParam("\\RD_CLK_ENABLE").extract(i).as_bool())
- log_error("Read port %d (%s) of memory %s.%s is clocked. This is not supported by \"write_smt2\"! "
- "Call \"memory\" with -nordff to avoid this error.\n", i, log_signal(data_sig), log_id(cell), log_id(module));
+ if (cell->getParam("\\RD_CLK_ENABLE").extract(i).as_bool())
+ log_error("Read port %d (%s) of memory %s.%s is clocked. This is not supported by \"write_smt2\"! "
+ "Call \"memory\" with -nordff to avoid this error.\n", i, log_signal(data_sig), log_id(cell), log_id(module));
- decls.push_back(stringf("(define-fun |%s_m:%d %s| ((state |%s_s|)) (_ BitVec %d) %s) ; %s\n",
- get_id(module), i, get_id(cell), get_id(module), abits, addr.c_str(), log_signal(addr_sig)));
+ decls.push_back(stringf("(define-fun |%s_m:%d %s| ((state |%s_s|)) (_ BitVec %d) %s) ; %s\n",
+ get_id(module), i, get_id(cell), get_id(module), abits, addr.c_str(), log_signal(addr_sig)));
- decls.push_back(stringf("(define-fun |%s#%d| ((state |%s_s|)) (_ BitVec %d) (select (|%s#%d#0| state) %s)) ; %s\n",
- get_id(module), idcounter, get_id(module), width, get_id(module), arrayid, addr.c_str(), log_signal(data_sig)));
- register_bv(data_sig, idcounter++);
+ decls.push_back(stringf("(define-fun |%s#%d| ((state |%s_s|)) (_ BitVec %d) (select (|%s#%d#0| state) (|%s_m:%d %s| state))) ; %s\n",
+ get_id(module), idcounter, get_id(module), width, get_id(module), arrayid, get_id(module), i, get_id(cell), log_signal(data_sig)));
+
+ decls.push_back(stringf("(define-fun |%s_m:%dD %s| ((state |%s_s|)) (_ BitVec %d) (|%s#%d| state))\n",
+ get_id(module), i, get_id(cell), get_id(module), width, get_id(module), idcounter));
+
+ register_bv(data_sig, idcounter++);
+ }
}
registers.insert(cell);
@@ -559,26 +632,26 @@ struct Smt2Worker
if (w->port_output && !w->port_input) {
if (GetSize(w) > 1) {
if (bvmode) {
- decls.push_back(stringf("(declare-fun |%s#%d| (|%s_s|) (_ BitVec %d)) ; %s\n",
- get_id(module), idcounter, get_id(module), GetSize(w), log_signal(sig)));
+ makebits(stringf("%s#%d", get_id(module), idcounter), GetSize(w), log_signal(sig));
register_bv(sig, idcounter++);
} else {
for (int i = 0; i < GetSize(w); i++) {
- decls.push_back(stringf("(declare-fun |%s#%d| (|%s_s|) Bool) ; %s\n",
- get_id(module), idcounter, get_id(module), log_signal(sig[i])));
+ makebits(stringf("%s#%d", get_id(module), idcounter), 0, log_signal(sig[i]));
register_bool(sig[i], idcounter++);
}
}
} else {
- decls.push_back(stringf("(declare-fun |%s#%d| (|%s_s|) Bool) ; %s\n",
- get_id(module), idcounter, get_id(module), log_signal(sig)));
+ makebits(stringf("%s#%d", get_id(module), idcounter), 0, log_signal(sig));
register_bool(sig, idcounter++);
}
}
}
- decls.push_back(stringf("(declare-fun |%s_h %s| (|%s_s|) |%s_s|)\n",
- get_id(module), get_id(cell->name), get_id(module), get_id(cell->type)));
+ if (statebv)
+ makebits(stringf("%s_h %s", get_id(module), get_id(cell->name)), mod_stbv_width.at(cell->type));
+ else
+ decls.push_back(stringf("(declare-fun |%s_h %s| (|%s_s|) |%s_s|)\n",
+ get_id(module), get_id(cell->name), get_id(module), get_id(cell->type)));
hiercells.insert(cell);
hiercells_queue.insert(cell);
@@ -719,21 +792,82 @@ struct Smt2Worker
int abits = cell->getParam("\\ABITS").as_int();
int width = cell->getParam("\\WIDTH").as_int();
+ int rd_ports = cell->getParam("\\RD_PORTS").as_int();
int wr_ports = cell->getParam("\\WR_PORTS").as_int();
- for (int i = 0; i < wr_ports; i++)
+ if (statebv)
{
- std::string addr = get_bv(cell->getPort("\\WR_ADDR").extract(abits*i, abits));
- std::string data = get_bv(cell->getPort("\\WR_DATA").extract(width*i, width));
- std::string mask = get_bv(cell->getPort("\\WR_EN").extract(width*i, width));
-
- data = stringf("(bvor (bvand %s %s) (bvand (select (|%s#%d#%d| state) %s) (bvnot %s)))",
- data.c_str(), mask.c_str(), get_id(module), arrayid, i, addr.c_str(), mask.c_str());
+ int mem_size = cell->getParam("\\SIZE").as_int();
+ int mem_offset = cell->getParam("\\OFFSET").as_int();
+
+ for (int i = 0; i < wr_ports; i++)
+ {
+ SigSpec addr_sig = cell->getPort("\\WR_ADDR").extract(abits*i, abits);
+ SigSpec data_sig = cell->getPort("\\WR_DATA").extract(width*i, width);
+ SigSpec mask_sig = cell->getPort("\\WR_EN").extract(width*i, width);
+
+ std::string addr = get_bv(addr_sig);
+ std::string data = get_bv(data_sig);
+ std::string mask = get_bv(mask_sig);
+
+ decls.push_back(stringf("(define-fun |%s_m:%d %s| ((state |%s_s|)) (_ BitVec %d) %s) ; %s\n",
+ get_id(module), rd_ports+i, get_id(cell), get_id(module), abits, addr.c_str(), log_signal(addr_sig)));
+ addr = stringf("(|%s_m:%d %s| state)", get_id(module), rd_ports+i, get_id(cell));
+
+ decls.push_back(stringf("(define-fun |%s_m:%dD %s| ((state |%s_s|)) (_ BitVec %d) %s) ; %s\n",
+ get_id(module), rd_ports+i, get_id(cell), get_id(module), width, data.c_str(), log_signal(data_sig)));
+ data = stringf("(|%s_m:%dD %s| state)", get_id(module), rd_ports+i, get_id(cell));
+
+ decls.push_back(stringf("(define-fun |%s_m:%dM %s| ((state |%s_s|)) (_ BitVec %d) %s) ; %s\n",
+ get_id(module), rd_ports+i, get_id(cell), get_id(module), width, mask.c_str(), log_signal(mask_sig)));
+ mask = stringf("(|%s_m:%dM %s| state)", get_id(module), rd_ports+i, get_id(cell));
+
+ std::string data_expr;
+
+ for (int k = mem_size-1; k >= 0; k--) {
+ std::string new_data = stringf("(bvor (bvand %s %s) (bvand ((_ extract %d %d) (|%s#%d#%d| state)) (bvnot %s)))",
+ data.c_str(), mask.c_str(), width*(k+1)-1, width*k, get_id(module), arrayid, i, mask.c_str());
+ data_expr += stringf("\n (ite (= %s #b%s) %s ((_ extract %d %d) (|%s#%d#%d| state)))",
+ addr.c_str(), Const(k+mem_offset, abits).as_string().c_str(), new_data.c_str(),
+ width*(k+1)-1, width*k, get_id(module), arrayid, i);
+ }
- decls.push_back(stringf("(define-fun |%s#%d#%d| ((state |%s_s|)) (Array (_ BitVec %d) (_ BitVec %d)) "
- "(store (|%s#%d#%d| state) %s %s)) ; %s\n",
- get_id(module), arrayid, i+1, get_id(module), abits, width,
- get_id(module), arrayid, i, addr.c_str(), data.c_str(), get_id(cell)));
+ decls.push_back(stringf("(define-fun |%s#%d#%d| ((state |%s_s|)) (_ BitVec %d) (concat%s)) ; %s\n",
+ get_id(module), arrayid, i+1, get_id(module), width*mem_size, data_expr.c_str(), get_id(cell)));
+ }
+ }
+ else
+ {
+ for (int i = 0; i < wr_ports; i++)
+ {
+ SigSpec addr_sig = cell->getPort("\\WR_ADDR").extract(abits*i, abits);
+ SigSpec data_sig = cell->getPort("\\WR_DATA").extract(width*i, width);
+ SigSpec mask_sig = cell->getPort("\\WR_EN").extract(width*i, width);
+
+ std::string addr = get_bv(addr_sig);
+ std::string data = get_bv(data_sig);
+ std::string mask = get_bv(mask_sig);
+
+ decls.push_back(stringf("(define-fun |%s_m:%d %s| ((state |%s_s|)) (_ BitVec %d) %s) ; %s\n",
+ get_id(module), rd_ports+i, get_id(cell), get_id(module), abits, addr.c_str(), log_signal(addr_sig)));
+ addr = stringf("(|%s_m:%d %s| state)", get_id(module), rd_ports+i, get_id(cell));
+
+ decls.push_back(stringf("(define-fun |%s_m:%dD %s| ((state |%s_s|)) (_ BitVec %d) %s) ; %s\n",
+ get_id(module), rd_ports+i, get_id(cell), get_id(module), width, data.c_str(), log_signal(data_sig)));
+ data = stringf("(|%s_m:%dD %s| state)", get_id(module), rd_ports+i, get_id(cell));
+
+ decls.push_back(stringf("(define-fun |%s_m:%dM %s| ((state |%s_s|)) (_ BitVec %d) %s) ; %s\n",
+ get_id(module), rd_ports+i, get_id(cell), get_id(module), width, mask.c_str(), log_signal(mask_sig)));
+ mask = stringf("(|%s_m:%dM %s| state)", get_id(module), rd_ports+i, get_id(cell));
+
+ data = stringf("(bvor (bvand %s %s) (bvand (select (|%s#%d#%d| state) %s) (bvnot %s)))",
+ data.c_str(), mask.c_str(), get_id(module), arrayid, i, addr.c_str(), mask.c_str());
+
+ decls.push_back(stringf("(define-fun |%s#%d#%d| ((state |%s_s|)) (Array (_ BitVec %d) (_ BitVec %d)) "
+ "(store (|%s#%d#%d| state) %s %s)) ; %s\n",
+ get_id(module), arrayid, i+1, get_id(module), abits, width,
+ get_id(module), arrayid, i, addr.c_str(), data.c_str(), get_id(cell)));
+ }
}
std::string expr_d = stringf("(|%s#%d#%d| state)", get_id(module), arrayid, wr_ports);
@@ -755,10 +889,14 @@ struct Smt2Worker
if (bit == State::S0 || bit == State::S1)
gen_init_constr = true;
- if (gen_init_constr) {
- init_list.push_back(stringf("(= (select (|%s#%d#0| state) #b%s) #b%s) ; %s[%d]",
- get_id(module), arrayid, Const(i, abits).as_string().c_str(),
- initword.as_string().c_str(), get_id(cell), i));
+ if (gen_init_constr)
+ {
+ if (statebv)
+ /* FIXME */;
+ else
+ init_list.push_back(stringf("(= (select (|%s#%d#0| state) #b%s) #b%s) ; %s[%d]",
+ get_id(module), arrayid, Const(i, abits).as_string().c_str(),
+ initword.as_string().c_str(), get_id(cell), i));
}
}
}
@@ -854,6 +992,12 @@ struct Smt2Worker
{
f << stringf("; yosys-smt2-module %s\n", get_id(module));
+ if (statebv) {
+ f << stringf("(define-sort |%s_s| () (_ BitVec %d))\n", get_id(module), statebv_width);
+ mod_stbv_width[module->name] = statebv_width;
+ } else
+ f << stringf("(declare-sort |%s_s| 0)\n", get_id(module));
+
for (auto it : decls)
f << it;
@@ -924,6 +1068,11 @@ struct Smt2Backend : public Backend {
log(" -verbose\n");
log(" this will print the recursive walk used to export the modules.\n");
log("\n");
+ log(" -stbv\n");
+ log(" Use a BitVec sort to represent a state instead of an uninterpreted\n");
+ log(" sort. As a side-effect this will prevent use of arrays to model\n");
+ log(" memories.\n");
+ log("\n");
log(" -nobv\n");
log(" disable support for BitVec (FixedSizeBitVectors theory). without this\n");
log(" option multi-bit wires are represented using the BitVec sort and\n");
@@ -997,7 +1146,7 @@ struct Smt2Backend : public Backend {
virtual void execute(std::ostream *&f, std::string filename, std::vector<std::string> args, RTLIL::Design *design)
{
std::ifstream template_f;
- bool bvmode = true, memmode = true, wiresmode = false, verbose = false;
+ bool bvmode = true, memmode = true, wiresmode = false, verbose = false, statebv = false;
log_header(design, "Executing SMT2 backend.\n");
@@ -1014,6 +1163,10 @@ struct Smt2Backend : public Backend {
log_warning("Options -bv and -mem are now the default. Support for -bv and -mem will be removed in the future.\n");
continue;
}
+ if (args[argidx] == "-stbv") {
+ statebv = true;
+ continue;
+ }
if (args[argidx] == "-nobv") {
bvmode = false;
memmode = false;
@@ -1055,6 +1208,9 @@ struct Smt2Backend : public Backend {
if (!memmode)
*f << stringf("; yosys-smt2-nomem\n");
+ if (statebv)
+ *f << stringf("; yosys-smt2-stbv\n");
+
std::vector<RTLIL::Module*> sorted_modules;
// extract module dependencies
@@ -1084,6 +1240,7 @@ struct Smt2Backend : public Backend {
module_deps.erase(sorted_modules.at(sorted_modules_idx++));
}
+ dict<IdString, int> mod_stbv_width;
Module *topmod = design->top_module();
std::string topmod_id;
@@ -1094,7 +1251,7 @@ struct Smt2Backend : public Backend {
log("Creating SMT-LIBv2 representation of module %s.\n", log_id(module));
- Smt2Worker worker(module, bvmode, memmode, wiresmode, verbose);
+ Smt2Worker worker(module, bvmode, memmode, wiresmode, verbose, statebv, mod_stbv_width);
worker.run();
worker.write(*f);
diff --git a/backends/smt2/smtbmc.py b/backends/smt2/smtbmc.py
index d8b47504c..39ac181dd 100644
--- a/backends/smt2/smtbmc.py
+++ b/backends/smt2/smtbmc.py
@@ -613,12 +613,12 @@ def write_vlogtb_trace(steps_start, steps_stop, index):
mems = sorted(smt.hiermems(topmod))
for mempath in mems:
- abits, width, ports = smt.mem_info(topmod, mempath)
+ abits, width, rports, wports = smt.mem_info(topmod, mempath)
mem = smt.mem_expr(topmod, "s%d" % steps_start, mempath)
addr_expr_list = list()
for i in range(steps_start, steps_stop):
- for j in range(ports):
+ for j in range(rports):
addr_expr_list.append(smt.mem_expr(topmod, "s%d" % i, mempath, j))
addr_list = set()
@@ -674,12 +674,12 @@ def write_constr_trace(steps_start, steps_stop, index):
mems = sorted(smt.hiermems(topmod))
for mempath in mems:
- abits, width, ports = smt.mem_info(topmod, mempath)
+ abits, width, rports, wports = smt.mem_info(topmod, mempath)
mem = smt.mem_expr(topmod, "s%d" % steps_start, mempath)
addr_expr_list = list()
for i in range(steps_start, steps_stop):
- for j in range(ports):
+ for j in range(rports):
addr_expr_list.append(smt.mem_expr(topmod, "s%d" % i, mempath, j))
addr_list = set((smt.bv2int(val) for val in smt.get_list(addr_expr_list)))
diff --git a/backends/smt2/smtio.py b/backends/smt2/smtio.py
index 93cadd104..797539b9f 100644
--- a/backends/smt2/smtio.py
+++ b/backends/smt2/smtio.py
@@ -328,7 +328,7 @@ class SmtIo:
self.modinfo[self.curmod].wsize[fields[2]] = int(fields[3])
if fields[1] == "yosys-smt2-memory":
- self.modinfo[self.curmod].memories[fields[2]] = (int(fields[3]), int(fields[4]), int(fields[5]))
+ self.modinfo[self.curmod].memories[fields[2]] = (int(fields[3]), int(fields[4]), int(fields[5]), int(fields[6]))
if fields[1] == "yosys-smt2-wire":
self.modinfo[self.curmod].wires.add(fields[2])
diff --git a/frontends/ast/ast.cc b/frontends/ast/ast.cc
index 06660102b..482acd364 100644
--- a/frontends/ast/ast.cc
+++ b/frontends/ast/ast.cc
@@ -84,6 +84,8 @@ std::string AST::type2str(AstNodeType type)
X(AST_PREFIX)
X(AST_ASSERT)
X(AST_ASSUME)
+ X(AST_LIVE)
+ X(AST_FAIR)
X(AST_COVER)
X(AST_FCALL)
X(AST_TO_BITS)
diff --git a/frontends/ast/ast.h b/frontends/ast/ast.h
index 0b9116d39..bddda9667 100644
--- a/frontends/ast/ast.h
+++ b/frontends/ast/ast.h
@@ -65,6 +65,8 @@ namespace AST
AST_PREFIX,
AST_ASSERT,
AST_ASSUME,
+ AST_LIVE,
+ AST_FAIR,
AST_COVER,
AST_FCALL,
diff --git a/frontends/ast/genrtlil.cc b/frontends/ast/genrtlil.cc
index bdac4de00..78e83e038 100644
--- a/frontends/ast/genrtlil.cc
+++ b/frontends/ast/genrtlil.cc
@@ -1336,10 +1336,15 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
// generate $assert cells
case AST_ASSERT:
case AST_ASSUME:
+ case AST_LIVE:
+ case AST_FAIR:
case AST_COVER:
{
- const char *celltype = "$assert";
+ const char *celltype = nullptr;
+ if (type == AST_ASSERT) celltype = "$assert";
if (type == AST_ASSUME) celltype = "$assume";
+ if (type == AST_LIVE) celltype = "$live";
+ if (type == AST_FAIR) celltype = "$fair";
if (type == AST_COVER) celltype = "$cover";
log_assert(children.size() == 2);
diff --git a/frontends/ast/simplify.cc b/frontends/ast/simplify.cc
index f7fcbc479..28c9945ab 100644
--- a/frontends/ast/simplify.cc
+++ b/frontends/ast/simplify.cc
@@ -1400,7 +1400,7 @@ bool AstNode::simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage,
}
skip_dynamic_range_lvalue_expansion:;
- if (stage > 1 && (type == AST_ASSERT || type == AST_ASSUME || type == AST_COVER) && current_block != NULL)
+ if (stage > 1 && (type == AST_ASSERT || type == AST_ASSUME || type == AST_LIVE || type == AST_FAIR || type == AST_COVER) && current_block != NULL)
{
std::stringstream sstr;
sstr << "$formal$" << filename << ":" << linenum << "$" << (autoidx++);
@@ -1462,7 +1462,7 @@ skip_dynamic_range_lvalue_expansion:;
goto apply_newNode;
}
- if (stage > 1 && (type == AST_ASSERT || type == AST_ASSUME || type == AST_COVER) && children.size() == 1)
+ if (stage > 1 && (type == AST_ASSERT || type == AST_ASSUME || type == AST_LIVE || type == AST_FAIR || type == AST_COVER) && children.size() == 1)
{
children.push_back(mkconst_int(1, false, 1));
did_something = true;
diff --git a/frontends/verilog/verilog_lexer.l b/frontends/verilog/verilog_lexer.l
index 091c1a029..885332b76 100644
--- a/frontends/verilog/verilog_lexer.l
+++ b/frontends/verilog/verilog_lexer.l
@@ -191,6 +191,9 @@ YOSYS_NAMESPACE_END
"logic" { SV_KEYWORD(TOK_REG); }
"bit" { SV_KEYWORD(TOK_REG); }
+"eventually" { if (formal_mode) return TOK_EVENTUALLY; SV_KEYWORD(TOK_EVENTUALLY); }
+"s_eventually" { if (formal_mode) return TOK_EVENTUALLY; SV_KEYWORD(TOK_EVENTUALLY); }
+
"input" { return TOK_INPUT; }
"output" { return TOK_OUTPUT; }
"inout" { return TOK_INOUT; }
diff --git a/frontends/verilog/verilog_parser.y b/frontends/verilog/verilog_parser.y
index 9b2498694..60b1ecffd 100644
--- a/frontends/verilog/verilog_parser.y
+++ b/frontends/verilog/verilog_parser.y
@@ -116,7 +116,7 @@ static void free_attr(std::map<std::string, AstNode*> *al)
%token TOK_SUPPLY0 TOK_SUPPLY1 TOK_TO_SIGNED TOK_TO_UNSIGNED
%token TOK_POS_INDEXED TOK_NEG_INDEXED TOK_ASSERT TOK_ASSUME
%token TOK_RESTRICT TOK_COVER TOK_PROPERTY TOK_ENUM TOK_TYPEDEF
-%token TOK_RAND TOK_CONST TOK_CHECKER TOK_ENDCHECKER
+%token TOK_RAND TOK_CONST TOK_CHECKER TOK_ENDCHECKER TOK_EVENTUALLY
%token TOK_INCREMENT TOK_DECREMENT TOK_UNIQUE TOK_PRIORITY
%type <ast> range range_or_multirange non_opt_range non_opt_multirange range_or_signed_int
@@ -1030,6 +1030,12 @@ assert:
TOK_ASSUME '(' expr ')' ';' {
ast_stack.back()->children.push_back(new AstNode(AST_ASSUME, $3));
} |
+ TOK_ASSERT '(' TOK_EVENTUALLY expr ')' ';' {
+ ast_stack.back()->children.push_back(new AstNode(assume_asserts_mode ? AST_FAIR : AST_LIVE, $4));
+ } |
+ TOK_ASSUME '(' TOK_EVENTUALLY expr ')' ';' {
+ ast_stack.back()->children.push_back(new AstNode(AST_FAIR, $4));
+ } |
TOK_COVER '(' expr ')' ';' {
ast_stack.back()->children.push_back(new AstNode(AST_COVER, $3));
} |
@@ -1044,6 +1050,12 @@ assert:
delete $3;
else
ast_stack.back()->children.push_back(new AstNode(AST_ASSUME, $3));
+ } |
+ TOK_RESTRICT '(' TOK_EVENTUALLY expr ')' ';' {
+ if (norestrict_mode)
+ delete $4;
+ else
+ ast_stack.back()->children.push_back(new AstNode(AST_FAIR, $4));
};
assert_property:
@@ -1053,6 +1065,12 @@ assert_property:
TOK_ASSUME TOK_PROPERTY '(' expr ')' ';' {
ast_stack.back()->children.push_back(new AstNode(AST_ASSUME, $4));
} |
+ TOK_ASSERT TOK_PROPERTY '(' TOK_EVENTUALLY expr ')' ';' {
+ ast_stack.back()->children.push_back(new AstNode(assume_asserts_mode ? AST_FAIR : AST_LIVE, $5));
+ } |
+ TOK_ASSUME TOK_PROPERTY '(' TOK_EVENTUALLY expr ')' ';' {
+ ast_stack.back()->children.push_back(new AstNode(AST_FAIR, $5));
+ } |
TOK_COVER TOK_PROPERTY '(' expr ')' ';' {
ast_stack.back()->children.push_back(new AstNode(AST_COVER, $4));
} |
@@ -1061,6 +1079,12 @@ assert_property:
delete $4;
else
ast_stack.back()->children.push_back(new AstNode(AST_ASSUME, $4));
+ } |
+ TOK_RESTRICT TOK_PROPERTY '(' TOK_EVENTUALLY expr ')' ';' {
+ if (norestrict_mode)
+ delete $5;
+ else
+ ast_stack.back()->children.push_back(new AstNode(AST_FAIR, $5));
};
simple_behavioral_stmt:
diff --git a/kernel/celltypes.h b/kernel/celltypes.h
index 8f31d0172..c43f685ac 100644
--- a/kernel/celltypes.h
+++ b/kernel/celltypes.h
@@ -116,6 +116,8 @@ struct CellTypes
setup_type("$assert", {A, EN}, pool<RTLIL::IdString>(), true);
setup_type("$assume", {A, EN}, pool<RTLIL::IdString>(), true);
+ setup_type("$live", {A, EN}, pool<RTLIL::IdString>(), true);
+ setup_type("$fair", {A, EN}, pool<RTLIL::IdString>(), true);
setup_type("$cover", {A, EN}, pool<RTLIL::IdString>(), true);
setup_type("$initstate", pool<RTLIL::IdString>(), {Y}, true);
setup_type("$anyconst", pool<RTLIL::IdString>(), {Y}, true);
diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc
index 978a7a537..6ce3f1376 100644
--- a/kernel/rtlil.cc
+++ b/kernel/rtlil.cc
@@ -1026,7 +1026,7 @@ namespace {
return;
}
- if (cell->type.in("$assert", "$assume", "$cover")) {
+ if (cell->type.in("$assert", "$assume", "$live", "$fair", "$cover")) {
port("\\A", 1);
port("\\EN", 1);
check_expected();
@@ -1819,6 +1819,22 @@ RTLIL::Cell* RTLIL::Module::addAssume(RTLIL::IdString name, RTLIL::SigSpec sig_a
return cell;
}
+RTLIL::Cell* RTLIL::Module::addLive(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_en)
+{
+ RTLIL::Cell *cell = addCell(name, "$live");
+ cell->setPort("\\A", sig_a);
+ cell->setPort("\\EN", sig_en);
+ return cell;
+}
+
+RTLIL::Cell* RTLIL::Module::addFair(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_en)
+{
+ RTLIL::Cell *cell = addCell(name, "$fair");
+ cell->setPort("\\A", sig_a);
+ cell->setPort("\\EN", sig_en);
+ return cell;
+}
+
RTLIL::Cell* RTLIL::Module::addCover(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_en)
{
RTLIL::Cell *cell = addCell(name, "$cover");
diff --git a/kernel/rtlil.h b/kernel/rtlil.h
index 7a6f5717d..ab8771256 100644
--- a/kernel/rtlil.h
+++ b/kernel/rtlil.h
@@ -1007,6 +1007,8 @@ public:
RTLIL::Cell* addTribuf (RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_en, RTLIL::SigSpec sig_y);
RTLIL::Cell* addAssert (RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_en);
RTLIL::Cell* addAssume (RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_en);
+ RTLIL::Cell* addLive (RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_en);
+ RTLIL::Cell* addFair (RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_en);
RTLIL::Cell* addCover (RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_en);
RTLIL::Cell* addEquiv (RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y);
diff --git a/manual/CHAPTER_CellLib.tex b/manual/CHAPTER_CellLib.tex
index 7686f5963..b2ba1fd88 100644
--- a/manual/CHAPTER_CellLib.tex
+++ b/manual/CHAPTER_CellLib.tex
@@ -421,7 +421,7 @@ pass. The combinatorial logic cells can be mapped to physical cells from a Liber
using the {\tt abc} pass.
\begin{fixme}
-Add information about {\tt \$assert}, {\tt \$assume}, {\tt \$cover}, {\tt \$equiv}, {\tt \$initstate}, {\tt \$anyconst}, and {\tt \$anyseq} cells.
+Add information about {\tt \$assert}, {\tt \$assume}, {\tt \$live}, {\tt \$fair}, {\tt \$cover}, {\tt \$equiv}, {\tt \$initstate}, {\tt \$anyconst}, and {\tt \$anyseq} cells.
\end{fixme}
\begin{fixme}
diff --git a/passes/hierarchy/hierarchy.cc b/passes/hierarchy/hierarchy.cc
index 3534cbcdb..d71e9c574 100644
--- a/passes/hierarchy/hierarchy.cc
+++ b/passes/hierarchy/hierarchy.cc
@@ -313,7 +313,7 @@ bool set_keep_assert(std::map<RTLIL::Module*, bool> &cache, RTLIL::Module *mod)
if (cache.count(mod) == 0)
for (auto c : mod->cells()) {
RTLIL::Module *m = mod->design->module(c->type);
- if ((m != nullptr && set_keep_assert(cache, m)) || c->type.in("$assert", "$assume", "$cover"))
+ if ((m != nullptr && set_keep_assert(cache, m)) || c->type.in("$assert", "$assume", "$live", "$fair", "$cover"))
return cache[mod] = true;
}
return cache[mod];
diff --git a/passes/opt/opt_clean.cc b/passes/opt/opt_clean.cc
index 65944caec..c426c4bf2 100644
--- a/passes/opt/opt_clean.cc
+++ b/passes/opt/opt_clean.cc
@@ -64,7 +64,7 @@ struct keep_cache_t
bool query(Cell *cell)
{
- if (cell->type.in("$memwr", "$meminit", "$assert", "$assume", "$cover"))
+ if (cell->type.in("$memwr", "$meminit", "$assert", "$assume", "$live", "$fair", "$cover"))
return true;
if (cell->has_keep_attr())
diff --git a/passes/tests/test_cell.cc b/passes/tests/test_cell.cc
index 049c20533..47b6bdf23 100644
--- a/passes/tests/test_cell.cc
+++ b/passes/tests/test_cell.cc
@@ -852,8 +852,6 @@ struct TestCellPass : public Pass {
// cell_types["$slice"] = "A";
// cell_types["$concat"] = "A";
- // cell_types["$assert"] = "A";
- // cell_types["$assume"] = "A";
cell_types["$lut"] = "*";
cell_types["$sop"] = "*";
diff --git a/techlibs/common/simlib.v b/techlibs/common/simlib.v
index d0abd3b34..276503fe8 100644
--- a/techlibs/common/simlib.v
+++ b/techlibs/common/simlib.v
@@ -1305,6 +1305,22 @@ endmodule
// --------------------------------------------------------
+module \$live (A, EN);
+
+input A, EN;
+
+endmodule
+
+// --------------------------------------------------------
+
+module \$fair (A, EN);
+
+input A, EN;
+
+endmodule
+
+// --------------------------------------------------------
+
module \$cover (A, EN);
input A, EN;
diff --git a/techlibs/greenpak4/cells_sim.v b/techlibs/greenpak4/cells_sim.v
index dd21bdd50..57f27b44e 100644
--- a/techlibs/greenpak4/cells_sim.v
+++ b/techlibs/greenpak4/cells_sim.v
@@ -53,7 +53,7 @@ module GP_CLKBUF(input wire IN, output wire OUT);
assign OUT = IN;
endmodule
-module GP_COUNT8(input CLK, input wire RST, output reg OUT);
+module GP_COUNT8(input CLK, input wire RST, output reg OUT, output reg[7:0] POUT);
parameter RESET_MODE = "RISING";
@@ -67,6 +67,7 @@ module GP_COUNT8(input CLK, input wire RST, output reg OUT);
//Combinatorially output whenever we wrap low
always @(*) begin
OUT <= (count == 8'h0);
+ OUT <= count;
end
//POR or SYSRST reset value is COUNT_TO. Datasheet is unclear but conversations w/ Silego confirm.
@@ -103,7 +104,7 @@ module GP_COUNT14(input CLK, input wire RST, output reg OUT);
endmodule
module GP_COUNT8_ADV(input CLK, input RST, output reg OUT,
- input UP, input KEEP);
+ input UP, input KEEP, output reg[7:0] POUT);
parameter RESET_MODE = "RISING";
parameter RESET_VALUE = "ZERO";
@@ -116,7 +117,7 @@ module GP_COUNT8_ADV(input CLK, input RST, output reg OUT,
endmodule
module GP_COUNT14_ADV(input CLK, input RST, output reg OUT,
- input UP, input KEEP);
+ input UP, input KEEP, output reg[7:0] POUT);
parameter RESET_MODE = "RISING";
parameter RESET_VALUE = "ZERO";
generated by cgit v1.2.3 (git 2.25.1) at 2025-04-07 05:05:08 +0000