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-rw-r--r--backends/smt2/smt2.cc2
-rw-r--r--manual/command-reference-manual.tex2
-rw-r--r--passes/sat/miter.cc116
-rw-r--r--passes/techmap/iopadmap.cc24
-rw-r--r--techlibs/ice40/cells_sim.v4
-rw-r--r--techlibs/ice40/synth_ice40.cc1
-rw-r--r--techlibs/xilinx/cells_xtra.py2
-rw-r--r--techlibs/xilinx/cells_xtra.v1
-rw-r--r--tests/various/ice40_mince_abc9.ys17
9 files changed, 98 insertions, 71 deletions
diff --git a/backends/smt2/smt2.cc b/backends/smt2/smt2.cc
index ea252b6b9..628765831 100644
--- a/backends/smt2/smt2.cc
+++ b/backends/smt2/smt2.cc
@@ -1394,7 +1394,7 @@ struct Smt2Backend : public Backend {
log("\n");
log("For this proof we create the following template (test.tpl).\n");
log("\n");
- log(" ; we need QF_UFBV for this poof\n");
+ log(" ; we need QF_UFBV for this proof\n");
log(" (set-logic QF_UFBV)\n");
log("\n");
log(" ; insert the auto-generated code here\n");
diff --git a/manual/command-reference-manual.tex b/manual/command-reference-manual.tex
index bed6326e2..4925defe3 100644
--- a/manual/command-reference-manual.tex
+++ b/manual/command-reference-manual.tex
@@ -5350,7 +5350,7 @@ never transition from a non-zero value to a zero value.
For this proof we create the following template (test.tpl).
- ; we need QF_UFBV for this poof
+ ; we need QF_UFBV for this proof
(set-logic QF_UFBV)
; insert the auto-generated code here
diff --git a/passes/sat/miter.cc b/passes/sat/miter.cc
index 49ef40061..742433935 100644
--- a/passes/sat/miter.cc
+++ b/passes/sat/miter.cc
@@ -66,50 +66,48 @@ void create_miter_equiv(struct Pass *that, std::vector<std::string> args, RTLIL:
RTLIL::IdString gate_name = RTLIL::escape_id(args[argidx++]);
RTLIL::IdString miter_name = RTLIL::escape_id(args[argidx++]);
- if (design->modules_.count(gold_name) == 0)
+ if (design->module(gold_name) == nullptr)
log_cmd_error("Can't find gold module %s!\n", gold_name.c_str());
- if (design->modules_.count(gate_name) == 0)
+ if (design->module(gate_name) == nullptr)
log_cmd_error("Can't find gate module %s!\n", gate_name.c_str());
- if (design->modules_.count(miter_name) != 0)
+ if (design->module(miter_name) != nullptr)
log_cmd_error("There is already a module %s!\n", miter_name.c_str());
- RTLIL::Module *gold_module = design->modules_.at(gold_name);
- RTLIL::Module *gate_module = design->modules_.at(gate_name);
+ RTLIL::Module *gold_module = design->module(gold_name);
+ RTLIL::Module *gate_module = design->module(gate_name);
- for (auto &it : gold_module->wires_) {
- RTLIL::Wire *w1 = it.second, *w2;
- if (w1->port_id == 0)
+ for (auto gold_wire : gold_module->wires()) {
+ if (gold_wire->port_id == 0)
continue;
- if (gate_module->wires_.count(it.second->name) == 0)
+ RTLIL::Wire *gate_wire = gate_module->wire(gold_wire->name);
+ if (gate_wire == nullptr)
goto match_gold_port_error;
- w2 = gate_module->wires_.at(it.second->name);
- if (w1->port_input != w2->port_input)
+ if (gold_wire->port_input != gate_wire->port_input)
goto match_gold_port_error;
- if (w1->port_output != w2->port_output)
+ if (gold_wire->port_output != gate_wire->port_output)
goto match_gold_port_error;
- if (w1->width != w2->width)
+ if (gold_wire->width != gate_wire->width)
goto match_gold_port_error;
continue;
match_gold_port_error:
- log_cmd_error("No matching port in gate module was found for %s!\n", it.second->name.c_str());
+ log_cmd_error("No matching port in gate module was found for %s!\n", gold_wire->name.c_str());
}
- for (auto &it : gate_module->wires_) {
- RTLIL::Wire *w1 = it.second, *w2;
- if (w1->port_id == 0)
+ for (auto gate_wire : gate_module->wires()) {
+ if (gate_wire->port_id == 0)
continue;
- if (gold_module->wires_.count(it.second->name) == 0)
+ RTLIL::Wire *gold_wire = gold_module->wire(gate_wire->name);
+ if (gold_wire == nullptr)
goto match_gate_port_error;
- w2 = gold_module->wires_.at(it.second->name);
- if (w1->port_input != w2->port_input)
+ if (gate_wire->port_input != gold_wire->port_input)
goto match_gate_port_error;
- if (w1->port_output != w2->port_output)
+ if (gate_wire->port_output != gold_wire->port_output)
goto match_gate_port_error;
- if (w1->width != w2->width)
+ if (gate_wire->width != gold_wire->width)
goto match_gate_port_error;
continue;
match_gate_port_error:
- log_cmd_error("No matching port in gold module was found for %s!\n", it.second->name.c_str());
+ log_cmd_error("No matching port in gold module was found for %s!\n", gate_wire->name.c_str());
}
log("Creating miter cell \"%s\" with gold cell \"%s\" and gate cell \"%s\".\n", RTLIL::id2cstr(miter_name), RTLIL::id2cstr(gold_name), RTLIL::id2cstr(gate_name));
@@ -123,73 +121,71 @@ void create_miter_equiv(struct Pass *that, std::vector<std::string> args, RTLIL:
RTLIL::SigSpec all_conditions;
- for (auto &it : gold_module->wires_)
+ for (auto gold_wire : gold_module->wires())
{
- RTLIL::Wire *w1 = it.second;
-
- if (w1->port_input)
+ if (gold_wire->port_input)
{
- RTLIL::Wire *w2 = miter_module->addWire("\\in_" + RTLIL::unescape_id(w1->name), w1->width);
- w2->port_input = true;
+ RTLIL::Wire *w = miter_module->addWire("\\in_" + RTLIL::unescape_id(gold_wire->name), gold_wire->width);
+ w->port_input = true;
- gold_cell->setPort(w1->name, w2);
- gate_cell->setPort(w1->name, w2);
+ gold_cell->setPort(gold_wire->name, w);
+ gate_cell->setPort(gold_wire->name, w);
}
- if (w1->port_output)
+ if (gold_wire->port_output)
{
- RTLIL::Wire *w2_gold = miter_module->addWire("\\gold_" + RTLIL::unescape_id(w1->name), w1->width);
- w2_gold->port_output = flag_make_outputs;
+ RTLIL::Wire *w_gold = miter_module->addWire("\\gold_" + RTLIL::unescape_id(gold_wire->name), gold_wire->width);
+ w_gold->port_output = flag_make_outputs;
- RTLIL::Wire *w2_gate = miter_module->addWire("\\gate_" + RTLIL::unescape_id(w1->name), w1->width);
- w2_gate->port_output = flag_make_outputs;
+ RTLIL::Wire *w_gate = miter_module->addWire("\\gate_" + RTLIL::unescape_id(gold_wire->name), gold_wire->width);
+ w_gate->port_output = flag_make_outputs;
- gold_cell->setPort(w1->name, w2_gold);
- gate_cell->setPort(w1->name, w2_gate);
+ gold_cell->setPort(gold_wire->name, w_gold);
+ gate_cell->setPort(gold_wire->name, w_gate);
RTLIL::SigSpec this_condition;
if (flag_ignore_gold_x)
{
- RTLIL::SigSpec gold_x = miter_module->addWire(NEW_ID, w2_gold->width);
- for (int i = 0; i < w2_gold->width; i++) {
+ RTLIL::SigSpec gold_x = miter_module->addWire(NEW_ID, w_gold->width);
+ for (int i = 0; i < w_gold->width; i++) {
RTLIL::Cell *eqx_cell = miter_module->addCell(NEW_ID, "$eqx");
eqx_cell->parameters["\\A_WIDTH"] = 1;
eqx_cell->parameters["\\B_WIDTH"] = 1;
eqx_cell->parameters["\\Y_WIDTH"] = 1;
eqx_cell->parameters["\\A_SIGNED"] = 0;
eqx_cell->parameters["\\B_SIGNED"] = 0;
- eqx_cell->setPort("\\A", RTLIL::SigSpec(w2_gold, i));
+ eqx_cell->setPort("\\A", RTLIL::SigSpec(w_gold, i));
eqx_cell->setPort("\\B", RTLIL::State::Sx);
eqx_cell->setPort("\\Y", gold_x.extract(i, 1));
}
- RTLIL::SigSpec gold_masked = miter_module->addWire(NEW_ID, w2_gold->width);
- RTLIL::SigSpec gate_masked = miter_module->addWire(NEW_ID, w2_gate->width);
+ RTLIL::SigSpec gold_masked = miter_module->addWire(NEW_ID, w_gold->width);
+ RTLIL::SigSpec gate_masked = miter_module->addWire(NEW_ID, w_gate->width);
RTLIL::Cell *or_gold_cell = miter_module->addCell(NEW_ID, "$or");
- or_gold_cell->parameters["\\A_WIDTH"] = w2_gold->width;
- or_gold_cell->parameters["\\B_WIDTH"] = w2_gold->width;
- or_gold_cell->parameters["\\Y_WIDTH"] = w2_gold->width;
+ or_gold_cell->parameters["\\A_WIDTH"] = w_gold->width;
+ or_gold_cell->parameters["\\B_WIDTH"] = w_gold->width;
+ or_gold_cell->parameters["\\Y_WIDTH"] = w_gold->width;
or_gold_cell->parameters["\\A_SIGNED"] = 0;
or_gold_cell->parameters["\\B_SIGNED"] = 0;
- or_gold_cell->setPort("\\A", w2_gold);
+ or_gold_cell->setPort("\\A", w_gold);
or_gold_cell->setPort("\\B", gold_x);
or_gold_cell->setPort("\\Y", gold_masked);
RTLIL::Cell *or_gate_cell = miter_module->addCell(NEW_ID, "$or");
- or_gate_cell->parameters["\\A_WIDTH"] = w2_gate->width;
- or_gate_cell->parameters["\\B_WIDTH"] = w2_gate->width;
- or_gate_cell->parameters["\\Y_WIDTH"] = w2_gate->width;
+ or_gate_cell->parameters["\\A_WIDTH"] = w_gate->width;
+ or_gate_cell->parameters["\\B_WIDTH"] = w_gate->width;
+ or_gate_cell->parameters["\\Y_WIDTH"] = w_gate->width;
or_gate_cell->parameters["\\A_SIGNED"] = 0;
or_gate_cell->parameters["\\B_SIGNED"] = 0;
- or_gate_cell->setPort("\\A", w2_gate);
+ or_gate_cell->setPort("\\A", w_gate);
or_gate_cell->setPort("\\B", gold_x);
or_gate_cell->setPort("\\Y", gate_masked);
RTLIL::Cell *eq_cell = miter_module->addCell(NEW_ID, "$eqx");
- eq_cell->parameters["\\A_WIDTH"] = w2_gold->width;
- eq_cell->parameters["\\B_WIDTH"] = w2_gate->width;
+ eq_cell->parameters["\\A_WIDTH"] = w_gold->width;
+ eq_cell->parameters["\\B_WIDTH"] = w_gate->width;
eq_cell->parameters["\\Y_WIDTH"] = 1;
eq_cell->parameters["\\A_SIGNED"] = 0;
eq_cell->parameters["\\B_SIGNED"] = 0;
@@ -201,20 +197,20 @@ void create_miter_equiv(struct Pass *that, std::vector<std::string> args, RTLIL:
else
{
RTLIL::Cell *eq_cell = miter_module->addCell(NEW_ID, "$eqx");
- eq_cell->parameters["\\A_WIDTH"] = w2_gold->width;
- eq_cell->parameters["\\B_WIDTH"] = w2_gate->width;
+ eq_cell->parameters["\\A_WIDTH"] = w_gold->width;
+ eq_cell->parameters["\\B_WIDTH"] = w_gate->width;
eq_cell->parameters["\\Y_WIDTH"] = 1;
eq_cell->parameters["\\A_SIGNED"] = 0;
eq_cell->parameters["\\B_SIGNED"] = 0;
- eq_cell->setPort("\\A", w2_gold);
- eq_cell->setPort("\\B", w2_gate);
+ eq_cell->setPort("\\A", w_gold);
+ eq_cell->setPort("\\B", w_gate);
eq_cell->setPort("\\Y", miter_module->addWire(NEW_ID));
this_condition = eq_cell->getPort("\\Y");
}
if (flag_make_outcmp)
{
- RTLIL::Wire *w_cmp = miter_module->addWire("\\cmp_" + RTLIL::unescape_id(w1->name));
+ RTLIL::Wire *w_cmp = miter_module->addWire("\\cmp_" + RTLIL::unescape_id(gold_wire->name));
w_cmp->port_output = true;
miter_module->connect(RTLIL::SigSig(w_cmp, this_condition));
}
@@ -285,9 +281,9 @@ void create_miter_assert(struct Pass *that, std::vector<std::string> args, RTLIL
IdString module_name = RTLIL::escape_id(args[argidx++]);
IdString miter_name = argidx < args.size() ? RTLIL::escape_id(args[argidx++]) : "";
- if (design->modules_.count(module_name) == 0)
+ if (design->module(module_name) == nullptr)
log_cmd_error("Can't find module %s!\n", module_name.c_str());
- if (!miter_name.empty() && design->modules_.count(miter_name) != 0)
+ if (!miter_name.empty() && design->module(miter_name) != nullptr)
log_cmd_error("There is already a module %s!\n", miter_name.c_str());
Module *module = design->module(module_name);
diff --git a/passes/techmap/iopadmap.cc b/passes/techmap/iopadmap.cc
index f63012d1a..8b1862237 100644
--- a/passes/techmap/iopadmap.cc
+++ b/passes/techmap/iopadmap.cc
@@ -308,7 +308,9 @@ struct IopadmapPass : public Pass {
{
log("Mapping port %s.%s[%d] using %s.\n", log_id(module), log_id(wire), i, tinoutpad_celltype.c_str());
- Cell *cell = module->addCell(NEW_ID, RTLIL::escape_id(tinoutpad_celltype));
+ Cell *cell = module->addCell(
+ module->uniquify(stringf("$iopadmap$%s.%s[%d]", log_id(module), log_id(wire), i)),
+ RTLIL::escape_id(tinoutpad_celltype));
cell->setPort(RTLIL::escape_id(tinoutpad_portname_oe), en_sig);
cell->attributes[ID::keep] = RTLIL::Const(1);
@@ -328,7 +330,9 @@ struct IopadmapPass : public Pass {
} else {
log("Mapping port %s.%s[%d] using %s.\n", log_id(module), log_id(wire), i, toutpad_celltype.c_str());
- Cell *cell = module->addCell(NEW_ID, RTLIL::escape_id(toutpad_celltype));
+ Cell *cell = module->addCell(
+ module->uniquify(stringf("$iopadmap$%s.%s[%d]", log_id(module), log_id(wire), i)),
+ RTLIL::escape_id(toutpad_celltype));
cell->setPort(RTLIL::escape_id(toutpad_portname_oe), en_sig);
cell->setPort(RTLIL::escape_id(toutpad_portname_i), data_sig);
@@ -406,7 +410,9 @@ struct IopadmapPass : public Pass {
SigBit wire_bit(wire, i);
- RTLIL::Cell *cell = module->addCell(NEW_ID, RTLIL::escape_id(celltype));
+ RTLIL::Cell *cell = module->addCell(
+ module->uniquify(stringf("$iopadmap$%s.%s", log_id(module->name), log_id(wire->name))),
+ RTLIL::escape_id(celltype));
cell->setPort(RTLIL::escape_id(portname_int), wire_bit);
if (!portname_pad.empty())
@@ -420,12 +426,16 @@ struct IopadmapPass : public Pass {
}
else
{
- RTLIL::Cell *cell = module->addCell(NEW_ID, RTLIL::escape_id(celltype));
+ RTLIL::Cell *cell = module->addCell(
+ module->uniquify(stringf("$iopadmap$%s.%s", log_id(module->name), log_id(wire->name))),
+ RTLIL::escape_id(celltype));
cell->setPort(RTLIL::escape_id(portname_int), RTLIL::SigSpec(wire));
if (!portname_pad.empty()) {
RTLIL::Wire *new_wire = NULL;
- new_wire = module->addWire(NEW_ID, wire);
+ new_wire = module->addWire(
+ module->uniquify(stringf("$iopadmap$%s", log_id(wire))),
+ wire);
module->swap_names(new_wire, wire);
wire->attributes.clear();
cell->setPort(RTLIL::escape_id(portname_pad), RTLIL::SigSpec(new_wire));
@@ -446,7 +456,9 @@ struct IopadmapPass : public Pass {
for (auto &it : rewrite_bits) {
RTLIL::Wire *wire = it.first;
- RTLIL::Wire *new_wire = module->addWire(NEW_ID, wire);
+ RTLIL::Wire *new_wire = module->addWire(
+ module->uniquify(stringf("$iopadmap$%s", log_id(wire))),
+ wire);
module->swap_names(new_wire, wire);
wire->attributes.clear();
for (int i = 0; i < wire->width; i++)
diff --git a/techlibs/ice40/cells_sim.v b/techlibs/ice40/cells_sim.v
index aa1d7aa86..6a0e3031e 100644
--- a/techlibs/ice40/cells_sim.v
+++ b/techlibs/ice40/cells_sim.v
@@ -2382,9 +2382,9 @@ module SB_SPRAM256KA (
// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L13167
//$setup(negedge STANDBY, posedge CLOCK, 1715);
// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L13206
- $setup(WREN, posedge CLK, 289);
+ $setup(WREN, posedge CLOCK, 289);
// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L13207-L13222
- (posedge RCLK => (DATAOUT : 16'bx)) = 1821;
+ (posedge CLOCK => (DATAOUT : 16'bx)) = 1821;
// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L13223-L13238
(posedge SLEEP => (DATAOUT : 16'b0)) = 1099;
endspecify
diff --git a/techlibs/ice40/synth_ice40.cc b/techlibs/ice40/synth_ice40.cc
index 80bd05a84..b8aedaadf 100644
--- a/techlibs/ice40/synth_ice40.cc
+++ b/techlibs/ice40/synth_ice40.cc
@@ -345,6 +345,7 @@ struct SynthIce40Pass : public ScriptPass
if (min_ce_use >= 0) {
run("opt_merge");
run(stringf("dff2dffe -unmap-mince %d", min_ce_use));
+ run("simplemap t:$dff");
}
run("techmap -D NO_LUT -D NO_ADDER -map +/ice40/cells_map.v");
run("opt_expr -mux_undef");
diff --git a/techlibs/xilinx/cells_xtra.py b/techlibs/xilinx/cells_xtra.py
index 749b1e0a7..f086291ab 100644
--- a/techlibs/xilinx/cells_xtra.py
+++ b/techlibs/xilinx/cells_xtra.py
@@ -302,7 +302,7 @@ CELLS = [
Cell('IOBUF_DCIEN', port_attrs={'IO': ['iopad_external_pin']}),
Cell('IOBUF_INTERMDISABLE', port_attrs={'IO': ['iopad_external_pin']}),
Cell('IOBUFE3', port_attrs={'IO': ['iopad_external_pin']}),
- Cell('IOBUFDS', port_attrs={'IO': ['iopad_external_pin']}),
+ Cell('IOBUFDS', port_attrs={'IO': ['iopad_external_pin'], 'IOB': ['iopad_external_pin']}),
Cell('IOBUFDS_DCIEN', port_attrs={'IO': ['iopad_external_pin'], 'IOB': ['iopad_external_pin']}),
Cell('IOBUFDS_INTERMDISABLE', port_attrs={'IO': ['iopad_external_pin'], 'IOB': ['iopad_external_pin']}),
Cell('IOBUFDS_DIFF_OUT', port_attrs={'IO': ['iopad_external_pin'], 'IOB': ['iopad_external_pin']}),
diff --git a/techlibs/xilinx/cells_xtra.v b/techlibs/xilinx/cells_xtra.v
index ac4ad4e36..3021f6b5a 100644
--- a/techlibs/xilinx/cells_xtra.v
+++ b/techlibs/xilinx/cells_xtra.v
@@ -7072,6 +7072,7 @@ module IOBUFDS (...);
output O;
(* iopad_external_pin *)
inout IO;
+ (* iopad_external_pin *)
inout IOB;
input I;
input T;
diff --git a/tests/various/ice40_mince_abc9.ys b/tests/various/ice40_mince_abc9.ys
new file mode 100644
index 000000000..408e16f05
--- /dev/null
+++ b/tests/various/ice40_mince_abc9.ys
@@ -0,0 +1,17 @@
+read_verilog <<EOT
+
+module top(input clk, ce, input [2:0] a, b, output reg [2:0] q);
+
+ reg [2:0] aa, bb;
+
+ always @(posedge clk) begin
+ if (ce) begin
+ aa <= a;
+ end
+ bb <= b;
+ q <= aa + bb;
+ end
+endmodule
+EOT
+
+synth_ice40 -abc9 -dffe_min_ce_use 4
generated by cgit v1.2.3 (git 2.25.1) at 2025-04-15 21:52:16 +0000