diff options
| -rw-r--r-- | Makefile | 20 | ||||
| -rw-r--r-- | README.md | 9 | ||||
| -rw-r--r-- | frontends/ast/ast.cc | 4 | ||||
| -rw-r--r-- | techlibs/ecp5/Makefile.inc | 9 | ||||
| -rw-r--r-- | techlibs/gowin/Makefile.inc | 3 |
5 files changed, 32 insertions, 13 deletions
@@ -622,10 +622,10 @@ include $(YOSYS_SRC)/techlibs/*/Makefile.inc else -include frontends/verilog/Makefile.inc -include frontends/ilang/Makefile.inc -include frontends/ast/Makefile.inc -include frontends/blif/Makefile.inc +include $(YOSYS_SRC)/frontends/verilog/Makefile.inc +include $(YOSYS_SRC)/frontends/ilang/Makefile.inc +include $(YOSYS_SRC)/frontends/ast/Makefile.inc +include $(YOSYS_SRC)/frontends/blif/Makefile.inc OBJS += passes/hierarchy/hierarchy.o OBJS += passes/cmds/select.o @@ -635,14 +635,14 @@ OBJS += passes/cmds/cover.o OBJS += passes/cmds/design.o OBJS += passes/cmds/plugin.o -include passes/proc/Makefile.inc -include passes/opt/Makefile.inc -include passes/techmap/Makefile.inc +include $(YOSYS_SRC)/passes/proc/Makefile.inc +include $(YOSYS_SRC)/passes/opt/Makefile.inc +include $(YOSYS_SRC)/passes/techmap/Makefile.inc -include backends/verilog/Makefile.inc -include backends/ilang/Makefile.inc +include $(YOSYS_SRC)/backends/verilog/Makefile.inc +include $(YOSYS_SRC)/backends/ilang/Makefile.inc -include techlibs/common/Makefile.inc +include $(YOSYS_SRC)/techlibs/common/Makefile.inc endif @@ -118,6 +118,13 @@ Tests are located in the tests subdirectory and can be executed using the test t $ make test +To use a separate (out-of-tree) build directory, provide a path to the Makefile. + + $ mkdir build; cd build + $ make -f ../Makefile + +Out-of-tree builds require a clean source tree. + Getting Started =============== @@ -388,7 +395,7 @@ Verilog Attributes and non-standard features - The cell attribute ``wildcard_port_conns`` represents wildcard port connections (SystemVerilog ``.*``). These are resolved to concrete - connections to matching wires in ``hierarchy``. + connections to matching wires in ``hierarchy``. - In addition to the ``(* ... *)`` attribute syntax, Yosys supports the non-standard ``{* ... *}`` attribute syntax to set default attributes diff --git a/frontends/ast/ast.cc b/frontends/ast/ast.cc index 733556621..6a9af3f57 100644 --- a/frontends/ast/ast.cc +++ b/frontends/ast/ast.cc @@ -946,6 +946,7 @@ RTLIL::Const AstNode::realAsConst(int width) // create a new AstModule from an AST_MODULE AST node static AstModule* process_module(AstNode *ast, bool defer, AstNode *original_ast = NULL, bool quiet = false) { + log_assert(current_scope.empty()); log_assert(ast->type == AST_MODULE || ast->type == AST_INTERFACE); if (defer) @@ -1117,6 +1118,7 @@ static AstModule* process_module(AstNode *ast, bool defer, AstNode *original_ast } ignoreThisSignalsInInitial = RTLIL::SigSpec(); + current_scope.clear(); } else { for (auto &attr : ast->attributes) { @@ -1229,11 +1231,13 @@ void AST::process(RTLIL::Design *design, AstNode *ast, bool dump_ast1, bool dump // process enum/other declarations (*it)->simplify(true, false, false, 1, -1, false, false); design->verilog_packages.push_back((*it)->clone()); + current_scope.clear(); } else { // must be global definition (*it)->simplify(false, false, false, 1, -1, false, false); //process enum/other declarations design->verilog_globals.push_back((*it)->clone()); + current_scope.clear(); } } } diff --git a/techlibs/ecp5/Makefile.inc b/techlibs/ecp5/Makefile.inc index e4ee4991f..217151e96 100644 --- a/techlibs/ecp5/Makefile.inc +++ b/techlibs/ecp5/Makefile.inc @@ -2,6 +2,15 @@ OBJS += techlibs/ecp5/synth_ecp5.o techlibs/ecp5/ecp5_ffinit.o \ techlibs/ecp5/ecp5_gsr.o +GENFILES += techlibs/ecp5/bram_init_1_2_4.vh +GENFILES += techlibs/ecp5/bram_init_9_18_36.vh +GENFILES += techlibs/ecp5/bram_conn_1.vh +GENFILES += techlibs/ecp5/bram_conn_2.vh +GENFILES += techlibs/ecp5/bram_conn_4.vh +GENFILES += techlibs/ecp5/bram_conn_9.vh +GENFILES += techlibs/ecp5/bram_conn_18.vh +GENFILES += techlibs/ecp5/bram_conn_36.vh + $(eval $(call add_share_file,share/ecp5,techlibs/ecp5/cells_ff.vh)) $(eval $(call add_share_file,share/ecp5,techlibs/ecp5/cells_io.vh)) $(eval $(call add_share_file,share/ecp5,techlibs/ecp5/cells_map.v)) diff --git a/techlibs/gowin/Makefile.inc b/techlibs/gowin/Makefile.inc index fe5d9d6e6..0756e3bcf 100644 --- a/techlibs/gowin/Makefile.inc +++ b/techlibs/gowin/Makefile.inc @@ -2,6 +2,7 @@ OBJS += techlibs/gowin/synth_gowin.o OBJS += techlibs/gowin/determine_init.o +GENFILES += techlibs/gowin/bram_init_16.vh $(eval $(call add_share_file,share/gowin,techlibs/gowin/cells_map.v)) $(eval $(call add_share_file,share/gowin,techlibs/gowin/cells_sim.v)) @@ -11,8 +12,6 @@ $(eval $(call add_share_file,share/gowin,techlibs/gowin/brams.txt)) $(eval $(call add_share_file,share/gowin,techlibs/gowin/lutrams_map.v)) $(eval $(call add_share_file,share/gowin,techlibs/gowin/lutrams.txt)) - - $(eval $(call add_share_file,share/gowin,techlibs/gowin/brams_init3.vh)) EXTRA_OBJS += techlibs/gowin/brams_init.mk |