diff options
| -rw-r--r-- | Makefile | 2 | ||||
| -rw-r--r-- | backends/rtlil/rtlil_backend.cc | 4 | ||||
| -rw-r--r-- | backends/verilog/verilog_backend.cc | 3 | ||||
| -rw-r--r-- | kernel/rtlil.h | 2 |
4 files changed, 6 insertions, 5 deletions
@@ -129,7 +129,7 @@ LDFLAGS += -rdynamic LDLIBS += -lrt endif -YOSYS_VER := 0.12+13 +YOSYS_VER := 0.12+18 GIT_REV := $(shell git -C $(YOSYS_SRC) rev-parse --short HEAD 2> /dev/null || echo UNKNOWN) OBJS = kernel/version_$(GIT_REV).o diff --git a/backends/rtlil/rtlil_backend.cc b/backends/rtlil/rtlil_backend.cc index 68521d52d..1b11de5ec 100644 --- a/backends/rtlil/rtlil_backend.cc +++ b/backends/rtlil/rtlil_backend.cc @@ -358,8 +358,8 @@ void RTLIL_BACKEND::dump_module(std::ostream &f, std::string indent, RTLIL::Modu bool first_conn_line = true; for (auto it = module->connections().begin(); it != module->connections().end(); ++it) { - bool show_conn = !only_selected; - if (only_selected) { + bool show_conn = !only_selected || design->selected_whole_module(module->name); + if (!show_conn) { RTLIL::SigSpec sigs = it->first; sigs.append(it->second); for (auto &c : sigs.chunks()) { diff --git a/backends/verilog/verilog_backend.cc b/backends/verilog/verilog_backend.cc index 47ef1c479..13c78c526 100644 --- a/backends/verilog/verilog_backend.cc +++ b/backends/verilog/verilog_backend.cc @@ -358,7 +358,8 @@ void dump_sigchunk(std::ostream &f, const RTLIL::SigChunk &chunk, bool no_decima void dump_sigspec(std::ostream &f, const RTLIL::SigSpec &sig) { if (GetSize(sig) == 0) { - f << "\"\""; + // See IEEE 1364-2005 Clause 5.1.14. + f << "{0{1'b0}}"; return; } if (sig.is_chunk()) { diff --git a/kernel/rtlil.h b/kernel/rtlil.h index 073110f16..a562d253c 100644 --- a/kernel/rtlil.h +++ b/kernel/rtlil.h @@ -970,7 +970,7 @@ public: #ifndef NDEBUG void check(Module *mod = nullptr) const; #else - void check(Module *mod = nullptr) const { } + void check(Module *mod = nullptr) const { (void)mod; } #endif }; |