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-rw-r--r--backends/aiger/xaiger.cc59
-rw-r--r--techlibs/ecp5/cells_sim.v12
-rw-r--r--techlibs/ecp5/synth_ecp5.cc2
-rw-r--r--tests/arch/ecp5/bug1598.ys16
-rw-r--r--tests/arch/ecp5/mux.ys6
-rw-r--r--tests/arch/ice40/bug1598.ys16
-rw-r--r--tests/arch/xilinx/bug1598.ys16
7 files changed, 93 insertions, 34 deletions
diff --git a/backends/aiger/xaiger.cc b/backends/aiger/xaiger.cc
index 3599e19e3..445103771 100644
--- a/backends/aiger/xaiger.cc
+++ b/backends/aiger/xaiger.cc
@@ -599,25 +599,46 @@ struct XAigerWriter
RTLIL::Module *holes_module = module->design->addModule("$__holes__");
log_assert(holes_module);
+ dict<IdString, Cell*> cell_cache;
+
int port_id = 1;
int box_count = 0;
for (auto cell : box_list) {
- RTLIL::Module* box_module = module->design->module(cell->type);
+ RTLIL::Module* orig_box_module = module->design->module(cell->type);
+ log_assert(orig_box_module);
+ IdString derived_name = orig_box_module->derive(module->design, cell->parameters);
+ RTLIL::Module* box_module = module->design->module(derived_name);
+ if (box_module->has_processes())
+ log_error("ABC9 box '%s' contains processes!\n", box_module->name.c_str());
+
int box_inputs = 0, box_outputs = 0;
- Cell *holes_cell = nullptr;
- if (box_module->get_bool_attribute("\\whitebox")) {
+ auto r = cell_cache.insert(std::make_pair(derived_name, nullptr));
+ Cell *holes_cell = r.first->second;
+ if (r.second && box_module->get_bool_attribute("\\whitebox")) {
holes_cell = holes_module->addCell(cell->name, cell->type);
holes_cell->parameters = cell->parameters;
+ r.first->second = holes_cell;
+
+ // Since Module::derive() will create a new module, there
+ // is a chance that the ports will be alphabetically ordered
+ // again, which is a problem when carry-chains are involved.
+ // Inherit the port ordering from the original module here...
+ // (and set the port_id below, when iterating through those)
+ log_assert(GetSize(box_module->ports) == GetSize(orig_box_module->ports));
+ box_module->ports = orig_box_module->ports;
}
// NB: Assume box_module->ports are sorted alphabetically
// (as RTLIL::Module::fixup_ports() would do)
+ int box_port_id = 1;
for (const auto &port_name : box_module->ports) {
RTLIL::Wire *w = box_module->wire(port_name);
log_assert(w);
+ if (r.second)
+ w->port_id = box_port_id++;
RTLIL::Wire *holes_wire;
- RTLIL::SigSpec port_wire;
- if (w->port_input) {
+ RTLIL::SigSpec port_sig;
+ if (w->port_input)
for (int i = 0; i < GetSize(w); i++) {
box_inputs++;
holes_wire = holes_module->wire(stringf("\\i%d", box_inputs));
@@ -628,28 +649,29 @@ struct XAigerWriter
holes_module->ports.push_back(holes_wire->name);
}
if (holes_cell)
- port_wire.append(holes_wire);
+ port_sig.append(holes_wire);
}
- if (!port_wire.empty())
- holes_cell->setPort(w->name, port_wire);
- }
if (w->port_output) {
box_outputs += GetSize(w);
for (int i = 0; i < GetSize(w); i++) {
if (GetSize(w) == 1)
- holes_wire = holes_module->addWire(stringf("%s.%s", cell->name.c_str(), w->name.c_str()));
+ holes_wire = holes_module->addWire(stringf("%s.%s", cell->name.c_str(), log_id(w->name)));
else
- holes_wire = holes_module->addWire(stringf("%s.%s[%d]", cell->name.c_str(), w->name.c_str(), i));
+ holes_wire = holes_module->addWire(stringf("%s.%s[%d]", cell->name.c_str(), log_id(w->name), i));
holes_wire->port_output = true;
holes_wire->port_id = port_id++;
holes_module->ports.push_back(holes_wire->name);
if (holes_cell)
- port_wire.append(holes_wire);
+ port_sig.append(holes_wire);
else
holes_module->connect(holes_wire, State::S0);
}
- if (!port_wire.empty())
- holes_cell->setPort(w->name, port_wire);
+ }
+ if (!port_sig.empty()) {
+ if (r.second)
+ holes_cell->setPort(w->name, port_sig);
+ else
+ holes_module->connect(holes_cell->getPort(w->name), port_sig);
}
}
@@ -679,14 +701,11 @@ struct XAigerWriter
RTLIL::Selection& sel = holes_module->design->selection_stack.back();
sel.select(holes_module);
- // TODO: Should not need to opt_merge if we only instantiate
- // each box type once...
- Pass::call(holes_module->design, "opt_merge -share_all");
-
Pass::call(holes_module->design, "flatten -wb");
- // TODO: Should techmap/aigmap/check all lib_whitebox-es just once,
- // instead of per write_xaiger call
+ // Cannot techmap/aigmap/check all lib_whitebox-es outside of write_xaiger
+ // since boxes may contain parameters in which case `flatten` would have
+ // created a new $paramod ...
Pass::call(holes_module->design, "techmap");
Pass::call(holes_module->design, "aigmap");
for (auto cell : holes_module->cells())
diff --git a/techlibs/ecp5/cells_sim.v b/techlibs/ecp5/cells_sim.v
index f467218cc..0d3ec4e5b 100644
--- a/techlibs/ecp5/cells_sim.v
+++ b/techlibs/ecp5/cells_sim.v
@@ -1,5 +1,6 @@
// ---------------------------------------
+(* lib_whitebox *)
module LUT4(input A, B, C, D, output Z);
parameter [15:0] INIT = 16'h0000;
wire [7:0] s3 = D ? INIT[15:8] : INIT[7:0];
@@ -31,13 +32,8 @@ module CCU2C(
// First half
wire LUT4_0, LUT2_0;
-`ifdef _ABC
- assign LUT4_0 = INIT0[{D0, C0, B0, A0}];
- assign LUT2_0 = INIT0[{2'b00, B0, A0}];
-`else
LUT4 #(.INIT(INIT0)) lut4_0(.A(A0), .B(B0), .C(C0), .D(D0), .Z(LUT4_0));
LUT2 #(.INIT(INIT0[3:0])) lut2_0(.A(A0), .B(B0), .Z(LUT2_0));
-`endif
wire gated_cin_0 = (INJECT1_0 == "YES") ? 1'b0 : CIN;
assign S0 = LUT4_0 ^ gated_cin_0;
@@ -46,13 +42,8 @@ module CCU2C(
// Second half
wire LUT4_1, LUT2_1;
-`ifdef _ABC
- assign LUT4_1 = INIT1[{D1, C1, B1, A1}];
- assign LUT2_1 = INIT1[{2'b00, B1, A1}];
-`else
LUT4 #(.INIT(INIT1)) lut4_1(.A(A1), .B(B1), .C(C1), .D(D1), .Z(LUT4_1));
LUT2 #(.INIT(INIT1[3:0])) lut2_1(.A(A1), .B(B1), .Z(LUT2_1));
-`endif
wire gated_cin_1 = (INJECT1_1 == "YES") ? 1'b0 : cout_0;
assign S1 = LUT4_1 ^ gated_cin_1;
@@ -209,6 +200,7 @@ endmodule
// ---------------------------------------
+(* lib_whitebox *)
module LUT2(input A, B, output Z);
parameter [3:0] INIT = 4'h0;
wire [1:0] s1 = B ? INIT[ 3:2] : INIT[1:0];
diff --git a/techlibs/ecp5/synth_ecp5.cc b/techlibs/ecp5/synth_ecp5.cc
index b71bb2395..a0ea6d1f9 100644
--- a/techlibs/ecp5/synth_ecp5.cc
+++ b/techlibs/ecp5/synth_ecp5.cc
@@ -230,7 +230,7 @@ struct SynthEcp5Pass : public ScriptPass
{
if (check_label("begin"))
{
- run("read_verilog -D_ABC -lib +/ecp5/cells_sim.v +/ecp5/cells_bb.v");
+ run("read_verilog -lib +/ecp5/cells_sim.v +/ecp5/cells_bb.v");
run(stringf("hierarchy -check %s", help_mode ? "-top <top>" : top_opt.c_str()));
}
diff --git a/tests/arch/ecp5/bug1598.ys b/tests/arch/ecp5/bug1598.ys
new file mode 100644
index 000000000..1d1682fcd
--- /dev/null
+++ b/tests/arch/ecp5/bug1598.ys
@@ -0,0 +1,16 @@
+read_verilog <<EOT
+module led_blink (
+ input clk,
+ output ledc
+ );
+
+ reg [6:0] led_counter = 0;
+ always @( posedge clk ) begin
+ led_counter <= led_counter + 1;
+ end
+ assign ledc = !led_counter[ 6:3 ];
+
+endmodule
+EOT
+proc
+equiv_opt -assert -map +/ecp5/cells_sim.v synth_ecp5 -abc9
diff --git a/tests/arch/ecp5/mux.ys b/tests/arch/ecp5/mux.ys
index 92463aa32..22866832d 100644
--- a/tests/arch/ecp5/mux.ys
+++ b/tests/arch/ecp5/mux.ys
@@ -39,8 +39,8 @@ proc
equiv_opt -assert -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd mux16 # Constrain all select calls below inside the top module
-select -assert-count 8 t:L6MUX21
-select -assert-count 26 t:LUT4
-select -assert-count 12 t:PFUMX
+select -assert-count 12 t:L6MUX21
+select -assert-count 34 t:LUT4
+select -assert-count 17 t:PFUMX
select -assert-none t:LUT4 t:L6MUX21 t:PFUMX %% t:* %D
diff --git a/tests/arch/ice40/bug1598.ys b/tests/arch/ice40/bug1598.ys
new file mode 100644
index 000000000..8438cb979
--- /dev/null
+++ b/tests/arch/ice40/bug1598.ys
@@ -0,0 +1,16 @@
+read_verilog <<EOT
+module led_blink (
+ input clk,
+ output ledc
+ );
+
+ reg [6:0] led_counter = 0;
+ always @( posedge clk ) begin
+ led_counter <= led_counter + 1;
+ end
+ assign ledc = !led_counter[ 6:3 ];
+
+endmodule
+EOT
+proc
+equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 -abc9
diff --git a/tests/arch/xilinx/bug1598.ys b/tests/arch/xilinx/bug1598.ys
new file mode 100644
index 000000000..1175380b1
--- /dev/null
+++ b/tests/arch/xilinx/bug1598.ys
@@ -0,0 +1,16 @@
+read_verilog <<EOT
+module led_blink (
+ input clk,
+ output ledc
+ );
+
+ reg [6:0] led_counter = 0;
+ always @( posedge clk ) begin
+ led_counter <= led_counter + 1;
+ end
+ assign ledc = !led_counter[ 6:3 ];
+
+endmodule
+EOT
+proc
+equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx -abc9
generated by cgit v1.2.3 (git 2.25.1) at 2025-04-06 16:19:25 +0000