diff options
| -rw-r--r-- | Makefile | 2 | ||||
| -rw-r--r-- | frontends/verific/verific.cc | 2 | ||||
| -rw-r--r-- | passes/memory/memory_share.cc | 14 | ||||
| -rw-r--r-- | passes/opt/opt_dff.cc | 2 |
4 files changed, 18 insertions, 2 deletions
@@ -129,7 +129,7 @@ LDFLAGS += -rdynamic LDLIBS += -lrt endif -YOSYS_VER := 0.16+31 +YOSYS_VER := 0.16+34 GIT_REV := $(shell git -C $(YOSYS_SRC) rev-parse --short HEAD 2> /dev/null || echo UNKNOWN) OBJS = kernel/version_$(GIT_REV).o diff --git a/frontends/verific/verific.cc b/frontends/verific/verific.cc index 44196a310..284d5db31 100644 --- a/frontends/verific/verific.cc +++ b/frontends/verific/verific.cc @@ -2548,10 +2548,12 @@ struct VerificPass : public Pass { RuntimeFlags::SetVar("veri_extract_dualport_rams", 0); RuntimeFlags::SetVar("veri_extract_multiport_rams", 1); + RuntimeFlags::SetVar("veri_allow_any_ram_in_loop", 1); #ifdef VERIFIC_VHDL_SUPPORT RuntimeFlags::SetVar("vhdl_extract_dualport_rams", 0); RuntimeFlags::SetVar("vhdl_extract_multiport_rams", 1); + RuntimeFlags::SetVar("vhdl_allow_any_ram_in_loop", 1); RuntimeFlags::SetVar("vhdl_support_variable_slice", 1); RuntimeFlags::SetVar("vhdl_ignore_assertion_statements", 0); diff --git a/passes/memory/memory_share.cc b/passes/memory/memory_share.cc index ceea725d8..1ddc13f90 100644 --- a/passes/memory/memory_share.cc +++ b/passes/memory/memory_share.cc @@ -82,6 +82,11 @@ struct MemoryShareWorker log("Consolidating read ports of memory %s.%s by address:\n", log_id(module), log_id(mem.memid)); bool changed = false; + int abits = 0; + for (auto &port: mem.rd_ports) { + if (GetSize(port.addr) > abits) + abits = GetSize(port.addr); + } for (int i = 0; i < GetSize(mem.rd_ports); i++) { auto &port1 = mem.rd_ports[i]; @@ -114,6 +119,8 @@ struct MemoryShareWorker int wide_log2 = std::max(port1.wide_log2, port2.wide_log2); SigSpec addr1 = sigmap_xmux(port1.addr); SigSpec addr2 = sigmap_xmux(port2.addr); + addr1.extend_u0(abits); + addr2.extend_u0(abits); if (GetSize(addr1) <= wide_log2) continue; if (GetSize(addr2) <= wide_log2) @@ -192,6 +199,11 @@ struct MemoryShareWorker log("Consolidating write ports of memory %s.%s by address:\n", log_id(module), log_id(mem.memid)); bool changed = false; + int abits = 0; + for (auto &port: mem.wr_ports) { + if (GetSize(port.addr) > abits) + abits = GetSize(port.addr); + } for (int i = 0; i < GetSize(mem.wr_ports); i++) { auto &port1 = mem.wr_ports[i]; @@ -216,6 +228,8 @@ struct MemoryShareWorker int wide_log2 = std::max(port1.wide_log2, port2.wide_log2); SigSpec addr1 = sigmap_xmux(port1.addr); SigSpec addr2 = sigmap_xmux(port2.addr); + addr1.extend_u0(abits); + addr2.extend_u0(abits); if (GetSize(addr1) <= wide_log2) continue; if (GetSize(addr2) <= wide_log2) diff --git a/passes/opt/opt_dff.cc b/passes/opt/opt_dff.cc index 73d674c8d..0ad4acec2 100644 --- a/passes/opt/opt_dff.cc +++ b/passes/opt/opt_dff.cc @@ -554,7 +554,7 @@ struct OptDffWorker // The D input path is effectively useless, so remove it (this will be a const-input D latch, SR latch, or a const driver). log("Handling D = Q on %s (%s) from module %s (removing D path).\n", log_id(cell), log_id(cell->type), log_id(module)); - ff.has_clk = ff.has_ce = false; + ff.has_gclk = ff.has_clk = ff.has_ce = false; changed = true; } } |