diff options
| -rw-r--r-- | backends/cxxrtl/cxxrtl_backend.cc | 44 | ||||
| -rw-r--r-- | techlibs/ice40/cells_sim.v | 14 |
2 files changed, 30 insertions, 28 deletions
diff --git a/backends/cxxrtl/cxxrtl_backend.cc b/backends/cxxrtl/cxxrtl_backend.cc index dada9ae64..72190d99a 100644 --- a/backends/cxxrtl/cxxrtl_backend.cc +++ b/backends/cxxrtl/cxxrtl_backend.cc @@ -1134,31 +1134,33 @@ struct CxxrtlWorker { f << indent << "if(" << valid_index_temp << ".valid) {\n"; inc_indent(); if (writable_memories[memory]) { - std::string addr_temp = fresh_temporary(); - f << indent << "const value<" << cell->getPort(ID::ADDR).size() << "> &" << addr_temp << " = "; - dump_sigspec_rhs(cell->getPort(ID::ADDR)); - f << ";\n"; std::string lhs_temp = fresh_temporary(); f << indent << "value<" << memory->width << "> " << lhs_temp << " = " << mangle(memory) << "[" << valid_index_temp << ".index];\n"; std::vector<const RTLIL::Cell*> memwr_cells(transparent_for[cell].begin(), transparent_for[cell].end()); - std::sort(memwr_cells.begin(), memwr_cells.end(), - [](const RTLIL::Cell *a, const RTLIL::Cell *b) { - return a->getParam(ID::PRIORITY).as_int() < b->getParam(ID::PRIORITY).as_int(); - }); - for (auto memwr_cell : memwr_cells) { - f << indent << "if (" << addr_temp << " == "; - dump_sigspec_rhs(memwr_cell->getPort(ID::ADDR)); - f << ") {\n"; - inc_indent(); - f << indent << lhs_temp << " = " << lhs_temp; - f << ".update("; - dump_sigspec_rhs(memwr_cell->getPort(ID::DATA)); - f << ", "; - dump_sigspec_rhs(memwr_cell->getPort(ID::EN)); - f << ");\n"; - dec_indent(); - f << indent << "}\n"; + if (!memwr_cells.empty()) { + std::string addr_temp = fresh_temporary(); + f << indent << "const value<" << cell->getPort(ID::ADDR).size() << "> &" << addr_temp << " = "; + dump_sigspec_rhs(cell->getPort(ID::ADDR)); + f << ";\n"; + std::sort(memwr_cells.begin(), memwr_cells.end(), + [](const RTLIL::Cell *a, const RTLIL::Cell *b) { + return a->getParam(ID::PRIORITY).as_int() < b->getParam(ID::PRIORITY).as_int(); + }); + for (auto memwr_cell : memwr_cells) { + f << indent << "if (" << addr_temp << " == "; + dump_sigspec_rhs(memwr_cell->getPort(ID::ADDR)); + f << ") {\n"; + inc_indent(); + f << indent << lhs_temp << " = " << lhs_temp; + f << ".update("; + dump_sigspec_rhs(memwr_cell->getPort(ID::DATA)); + f << ", "; + dump_sigspec_rhs(memwr_cell->getPort(ID::EN)); + f << ");\n"; + dec_indent(); + f << indent << "}\n"; + } } f << indent; dump_sigspec_lhs(cell->getPort(ID::DATA)); diff --git a/techlibs/ice40/cells_sim.v b/techlibs/ice40/cells_sim.v index ad572c877..7ee809262 100644 --- a/techlibs/ice40/cells_sim.v +++ b/techlibs/ice40/cells_sim.v @@ -2508,7 +2508,7 @@ module SB_SPRAM256KA ( always @(negedge POWEROFF) begin for (i = 0; i <= 16383; i = i+1) - mem[i] = 'bx; + mem[i] = 16'bx; end always @(posedge CLOCK, posedge off) begin @@ -2516,17 +2516,17 @@ module SB_SPRAM256KA ( DATAOUT <= 0; end else if (STANDBY) begin - DATAOUT <= 'bx; + DATAOUT <= 16'bx; end else if (CHIPSELECT) begin if (!WREN) begin DATAOUT <= mem[ADDRESS]; end else begin - if (MASKWREN[0]) mem[ADDRESS][ 3: 0] = DATAIN[ 3: 0]; - if (MASKWREN[1]) mem[ADDRESS][ 7: 4] = DATAIN[ 7: 4]; - if (MASKWREN[2]) mem[ADDRESS][11: 8] = DATAIN[11: 8]; - if (MASKWREN[3]) mem[ADDRESS][15:12] = DATAIN[15:12]; - DATAOUT <= 'bx; + if (MASKWREN[0]) mem[ADDRESS][ 3: 0] <= DATAIN[ 3: 0]; + if (MASKWREN[1]) mem[ADDRESS][ 7: 4] <= DATAIN[ 7: 4]; + if (MASKWREN[2]) mem[ADDRESS][11: 8] <= DATAIN[11: 8]; + if (MASKWREN[3]) mem[ADDRESS][15:12] <= DATAIN[15:12]; + DATAOUT <= 16'bx; end end end |