aboutsummaryrefslogtreecommitdiffstats
diff options
context:
space:
mode:
Diffstat
-rw-r--r--.github/workflows/test-linux.yml9
-rw-r--r--.github/workflows/test-macos.yml29
-rw-r--r--passes/sat/sim.cc27
3 files changed, 27 insertions, 38 deletions
diff --git a/.github/workflows/test-linux.yml b/.github/workflows/test-linux.yml
index 9aa952e45..e27ea37d2 100644
--- a/.github/workflows/test-linux.yml
+++ b/.github/workflows/test-linux.yml
@@ -11,9 +11,7 @@ jobs:
- { id: ubuntu-20.04, name: focal }
compiler:
- 'clang-12'
- - 'clang-11'
- 'gcc-11'
- - 'gcc-10'
cpp_std:
- 'c++11'
- 'c++14'
@@ -21,6 +19,12 @@ jobs:
- 'c++20'
include:
# Limit the older compilers to C++11 mode
+ - os: { id: ubuntu-20.04, name: focal }
+ compiler: 'clang-11'
+ cpp_std: 'c++11'
+ - os: { id: ubuntu-20.04, name: focal }
+ compiler: 'gcc-10'
+ cpp_std: 'c++11'
- os: { id: ubuntu-18.04, name: bionic }
compiler: 'clang-3.9'
cpp_std: 'c++11'
@@ -120,6 +124,7 @@ jobs:
make -j${{ env.procs }} CCXXSTD=${{ matrix.cpp_std }} CC=$CC CXX=$CC LD=$CC
- name: Run tests
+ if: (matrix.cpp_std == 'c++11') && (matrix.compiler == 'gcc-11')
shell: bash
run: |
make -j${{ env.procs }} test CXXSTD=${{ matrix.cpp_std }} CC=$CC CXX=$CC LD=$CC
diff --git a/.github/workflows/test-macos.yml b/.github/workflows/test-macos.yml
index 09ab382bf..b14ce8633 100644
--- a/.github/workflows/test-macos.yml
+++ b/.github/workflows/test-macos.yml
@@ -67,6 +67,7 @@ jobs:
make -j${{ env.procs }} CXXSTD=${{ matrix.cpp_std }} CC=cc CXX=cc LD=cc
- name: Run tests
+ if: matrix.cpp_std == 'c++11'
shell: bash
run: |
make -j${{ env.procs }} test CXXSTD=${{ matrix.cpp_std }} CC=cc CXX=cc LD=cc
@@ -119,36 +120,8 @@ jobs:
- name: Checkout Yosys
uses: actions/checkout@v2
- - name: Get iverilog
- shell: bash
- run: |
- git clone https://github.com/steveicarus/iverilog.git
-
- - name: Cache iverilog
- id: cache-iverilog-homebrew
- uses: actions/cache@v2
- with:
- path: .local/
- key: ${{ matrix.os.id }}-homebrew-${{ hashFiles('iverilog/.git/refs/heads/master') }}
-
- - name: Build iverilog
- if: steps.cache-iverilog.outputs.cache-hit != 'true'
- shell: bash
- run: |
- mkdir -p $GITHUB_WORKSPACE/.local
- cd iverilog
- autoconf
- CC=gcc CXX=g++ ./configure --prefix=$GITHUB_WORKSPACE/.local
- make -j${{ env.procs }}
- make install
-
- name: Build yosys
shell: bash
run: |
make config-gcc
make -j${{ env.procs }} CXXSTD=${{ matrix.cpp_std }} CC=$CC CXX=$CC LD=$CC
-
- - name: Run tests
- shell: bash
- run: |
- make -j${{ env.procs }} test CXXSTD=${{ matrix.cpp_std }} CC=$CC CXX=$CC LD=$CC
diff --git a/passes/sat/sim.cc b/passes/sat/sim.cc
index b37bf25cd..5b69dd3bf 100644
--- a/passes/sat/sim.cc
+++ b/passes/sat/sim.cc
@@ -77,6 +77,7 @@ struct OutputWriter
struct SimShared
{
bool debug = false;
+ bool verbose = true;
bool hide_internal = true;
bool writeback = false;
bool zinit = false;
@@ -182,7 +183,7 @@ struct SimInstance
if ((shared->fst) && !(shared->hide_internal && wire->name[0] == '$')) {
fstHandle id = shared->fst->getHandle(scope + "." + RTLIL::unescape_id(wire->name));
if (id==0 && wire->name.isPublic())
- log_warning("Unable to found wire %s in input file.\n", (scope + "." + RTLIL::unescape_id(wire->name)).c_str());
+ log_warning("Unable to find wire %s in input file.\n", (scope + "." + RTLIL::unescape_id(wire->name)).c_str());
fst_handles[wire] = id;
}
@@ -765,7 +766,7 @@ struct SimInstance
IdString name = qsig.as_wire()->name;
fstHandle id = shared->fst->getHandle(scope + "." + RTLIL::unescape_id(name));
if (id==0 && name.isPublic())
- log_warning("Unable to found wire %s in input file.\n", (scope + "." + RTLIL::unescape_id(name)).c_str());
+ log_warning("Unable to find wire %s in input file.\n", (scope + "." + RTLIL::unescape_id(name)).c_str());
if (id!=0) {
Const fst_val = Const::from_string(shared->fst->valueOf(id));
set_state(qsig, fst_val);
@@ -920,7 +921,7 @@ struct SimWorker : SimShared
if (debug)
log("\n===== 0 =====\n");
- else
+ else if (verbose)
log("Simulating cycle 0.\n");
set_inports(reset, State::S1);
@@ -937,7 +938,7 @@ struct SimWorker : SimShared
{
if (debug)
log("\n===== %d =====\n", 10*cycle + 5);
- else
+ else if (verbose)
log("Simulating cycle %d.\n", (cycle*2)+1);
set_inports(clock, State::S0);
set_inports(clockn, State::S1);
@@ -947,7 +948,7 @@ struct SimWorker : SimShared
if (debug)
log("\n===== %d =====\n", 10*cycle + 10);
- else
+ else if (verbose)
log("Simulating cycle %d.\n", (cycle*2)+2);
set_inports(clock, State::S1);
@@ -1064,7 +1065,8 @@ struct SimWorker : SimShared
try {
fst->reconstructAllAtTimes(fst_clock, startCount, stopCount, [&](uint64_t time) {
- log("Co-simulating %s %d [%lu%s].\n", (all_samples ? "sample" : "cycle"), cycle, (unsigned long)time, fst->getTimescaleString());
+ if (verbose)
+ log("Co-simulating %s %d [%lu%s].\n", (all_samples ? "sample" : "cycle"), cycle, (unsigned long)time, fst->getTimescaleString());
bool did_something = false;
for(auto &item : inputs) {
std::string v = fst->valueOf(item.second);
@@ -1173,7 +1175,8 @@ struct SimWorker : SimShared
state = 3;
break;
default:
- log("Simulating cycle %d.\n", cycle);
+ if (verbose)
+ log("Simulating cycle %d.\n", cycle);
top->setState(inputs, line);
if (cycle) {
set_inports(clock, State::S1);
@@ -1254,7 +1257,8 @@ struct SimWorker : SimShared
curr_cycle = -1; // force detect change
if (curr_cycle != prev_cycle) {
- log("Simulating cycle %d.\n", cycle);
+ if (verbose)
+ log("Simulating cycle %d.\n", cycle);
set_inports(clock, State::S1);
set_inports(clockn, State::S0);
update();
@@ -1632,6 +1636,9 @@ struct SimPass : public Pass {
log(" -sim-gate\n");
log(" co-simulation, x in FST can match any value in simulation\n");
log("\n");
+ log(" -q\n");
+ log(" disable per-cycle/sample log message\n");
+ log("\n");
log(" -d\n");
log(" enable debug output\n");
log("\n");
@@ -1704,6 +1711,10 @@ struct SimPass : public Pass {
worker.hide_internal = false;
continue;
}
+ if (args[argidx] == "-q") {
+ worker.verbose = false;
+ continue;
+ }
if (args[argidx] == "-d") {
worker.debug = true;
continue;
generated by cgit v1.2.3 (git 2.25.1) at 2025-04-07 08:06:57 +0000