diff options
| -rw-r--r-- | frontends/ast/simplify.cc | 2 | ||||
| -rw-r--r-- | tests/sat/sizebits.sv (renamed from tests/simple/functions01.sv) | 0 | ||||
| -rw-r--r-- | tests/sat/sizebits.ys | 2 |
3 files changed, 3 insertions, 1 deletions
diff --git a/frontends/ast/simplify.cc b/frontends/ast/simplify.cc index 678951850..cd2120b8c 100644 --- a/frontends/ast/simplify.cc +++ b/frontends/ast/simplify.cc @@ -1870,7 +1870,7 @@ skip_dynamic_range_lvalue_expansion:; goto apply_newNode; } - if (VERILOG_FRONTEND::sv_mode && (str == "\\$size" || str == "\\$bits")) + if (str == "\\$size" || str == "\\$bits") { if (str == "\\$bits" && children.size() != 1) log_error("System function %s got %d arguments, expected 1 at %s:%d.\n", diff --git a/tests/simple/functions01.sv b/tests/sat/sizebits.sv index d7ce2326e..d7ce2326e 100644 --- a/tests/simple/functions01.sv +++ b/tests/sat/sizebits.sv diff --git a/tests/sat/sizebits.ys b/tests/sat/sizebits.ys new file mode 100644 index 000000000..689227a41 --- /dev/null +++ b/tests/sat/sizebits.ys @@ -0,0 +1,2 @@ +read_verilog -sv sizebits.sv +prep; sat -verify -prove-asserts |