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-rw-r--r--Makefile2
-rw-r--r--frontends/verilog/verilog_parser.y10
-rw-r--r--kernel/register.cc12
-rw-r--r--kernel/register.h1
-rw-r--r--passes/cmds/add.cc37
-rw-r--r--passes/techmap/abc9.cc14
-rw-r--r--passes/techmap/deminout.cc3
-rw-r--r--techlibs/ecp5/brams_map.v2
-rw-r--r--tests/rpc/frontend.py3
-rw-r--r--tests/simple/partsel.v4
-rw-r--r--tests/various/deminout_unused.ys14
11 files changed, 65 insertions, 37 deletions
diff --git a/Makefile b/Makefile
index e9dfd9df0..864be3c2e 100644
--- a/Makefile
+++ b/Makefile
@@ -128,7 +128,7 @@ bumpversion:
# is just a symlink to your actual ABC working directory, as 'make mrproper'
# will remove the 'abc' directory and you do not want to accidentally
# delete your work on ABC..
-ABCREV = 71f2b40
+ABCREV = ed90ce2
ABCPULL = 1
ABCURL ?= https://github.com/berkeley-abc/abc
ABCMKARGS = CC="$(CXX)" CXX="$(CXX)" ABC_USE_LIBSTDCXX=1
diff --git a/frontends/verilog/verilog_parser.y b/frontends/verilog/verilog_parser.y
index be8b39e9f..91982e2a3 100644
--- a/frontends/verilog/verilog_parser.y
+++ b/frontends/verilog/verilog_parser.y
@@ -593,13 +593,15 @@ non_opt_range:
} |
'[' expr TOK_POS_INDEXED expr ']' {
$$ = new AstNode(AST_RANGE);
- $$->children.push_back(new AstNode(AST_SUB, new AstNode(AST_ADD, $2->clone(), $4), AstNode::mkconst_int(1, true)));
- $$->children.push_back(new AstNode(AST_ADD, $2, AstNode::mkconst_int(0, true)));
+ AstNode *expr = new AstNode(AST_CONCAT, $2);
+ $$->children.push_back(new AstNode(AST_SUB, new AstNode(AST_ADD, expr->clone(), $4), AstNode::mkconst_int(1, true)));
+ $$->children.push_back(new AstNode(AST_ADD, expr, AstNode::mkconst_int(0, true)));
} |
'[' expr TOK_NEG_INDEXED expr ']' {
$$ = new AstNode(AST_RANGE);
- $$->children.push_back(new AstNode(AST_ADD, $2, AstNode::mkconst_int(0, true)));
- $$->children.push_back(new AstNode(AST_SUB, new AstNode(AST_ADD, $2->clone(), AstNode::mkconst_int(1, true)), $4));
+ AstNode *expr = new AstNode(AST_CONCAT, $2);
+ $$->children.push_back(new AstNode(AST_ADD, expr, AstNode::mkconst_int(0, true)));
+ $$->children.push_back(new AstNode(AST_SUB, new AstNode(AST_ADD, expr->clone(), AstNode::mkconst_int(1, true)), $4));
} |
'[' expr ']' {
$$ = new AstNode(AST_RANGE);
diff --git a/kernel/register.cc b/kernel/register.cc
index e59d59654..af8c1b8e8 100644
--- a/kernel/register.cc
+++ b/kernel/register.cc
@@ -400,6 +400,18 @@ void ScriptPass::run(std::string command, std::string info)
}
}
+void ScriptPass::run_nocheck(std::string command, std::string info)
+{
+ if (active_design == nullptr) {
+ if (info.empty())
+ log(" %s\n", command.c_str());
+ else
+ log(" %s %s\n", command.c_str(), info.c_str());
+ } else {
+ Pass::call(active_design, command);
+ }
+}
+
void ScriptPass::run_script(RTLIL::Design *design, std::string run_from, std::string run_to)
{
help_mode = false;
diff --git a/kernel/register.h b/kernel/register.h
index 4622845b6..3d89386b7 100644
--- a/kernel/register.h
+++ b/kernel/register.h
@@ -84,6 +84,7 @@ struct ScriptPass : Pass
bool check_label(std::string label, std::string info = std::string());
void run(std::string command, std::string info = std::string());
+ void run_nocheck(std::string command, std::string info = std::string());
void run_script(RTLIL::Design *design, std::string run_from = std::string(), std::string run_to = std::string());
void help_script();
};
diff --git a/passes/cmds/add.cc b/passes/cmds/add.cc
index dd05ac81f..62c253bed 100644
--- a/passes/cmds/add.cc
+++ b/passes/cmds/add.cc
@@ -24,24 +24,23 @@ PRIVATE_NAMESPACE_BEGIN
static void add_wire(RTLIL::Design *design, RTLIL::Module *module, std::string name, int width, bool flag_input, bool flag_output, bool flag_global)
{
- RTLIL::Wire *wire = NULL;
+ RTLIL::Wire *wire = nullptr;
name = RTLIL::escape_id(name);
if (module->count_id(name) != 0)
{
- if (module->wires_.count(name) > 0)
- wire = module->wires_.at(name);
+ wire = module->wire(name);
- if (wire != NULL && wire->width != width)
- wire = NULL;
+ if (wire != nullptr && wire->width != width)
+ wire = nullptr;
- if (wire != NULL && wire->port_input != flag_input)
- wire = NULL;
+ if (wire != nullptr && wire->port_input != flag_input)
+ wire = nullptr;
- if (wire != NULL && wire->port_output != flag_output)
- wire = NULL;
+ if (wire != nullptr && wire->port_output != flag_output)
+ wire = nullptr;
- if (wire == NULL)
+ if (wire == nullptr)
log_cmd_error("Found incompatible object with same name in module %s!\n", module->name.c_str());
log("Module %s already has such an object.\n", module->name.c_str());
@@ -53,7 +52,6 @@ static void add_wire(RTLIL::Design *design, RTLIL::Module *module, std::string n
wire->port_output = flag_output;
if (flag_input || flag_output) {
- wire->port_id = module->wires_.size();
module->fixup_ports();
}
@@ -63,21 +61,20 @@ static void add_wire(RTLIL::Design *design, RTLIL::Module *module, std::string n
if (!flag_global)
return;
- for (auto &it : module->cells_)
+ for (auto cell : module->cells())
{
- if (design->modules_.count(it.second->type) == 0)
+ RTLIL::Module *mod = design->module(cell->type);
+ if (mod == nullptr)
continue;
-
- RTLIL::Module *mod = design->modules_.at(it.second->type);
if (!design->selected_whole_module(mod->name))
continue;
if (mod->get_blackbox_attribute())
continue;
- if (it.second->hasPort(name))
+ if (cell->hasPort(name))
continue;
- it.second->setPort(name, wire);
- log("Added connection %s to cell %s.%s (%s).\n", name.c_str(), module->name.c_str(), it.first.c_str(), it.second->type.c_str());
+ cell->setPort(name, wire);
+ log("Added connection %s to cell %s.%s (%s).\n", name.c_str(), module->name.c_str(), cell->name.c_str(), cell->type.c_str());
}
}
@@ -155,9 +152,9 @@ struct AddPass : public Pass {
extra_args(args, argidx, design);
- for (auto &mod : design->modules_)
+ for (auto module : design->modules())
{
- RTLIL::Module *module = mod.second;
+ log_assert(module != nullptr);
if (!design->selected_whole_module(module->name))
continue;
if (module->get_bool_attribute("\\blackbox"))
diff --git a/passes/techmap/abc9.cc b/passes/techmap/abc9.cc
index 5e650230d..212e0692d 100644
--- a/passes/techmap/abc9.cc
+++ b/passes/techmap/abc9.cc
@@ -332,9 +332,9 @@ struct Abc9Pass : public ScriptPass
tempdir_name = make_temp_dir(tempdir_name);
if (!lut_mode)
- run(stringf("abc9_ops -write_lut %s/input.lut", tempdir_name.c_str()));
- run(stringf("abc9_ops -write_box %s/input.box", tempdir_name.c_str()));
- run(stringf("write_xaiger -map %s/input.sym %s/input.xaig", tempdir_name.c_str(), tempdir_name.c_str()));
+ run_nocheck(stringf("abc9_ops -write_lut %s/input.lut", tempdir_name.c_str()));
+ run_nocheck(stringf("abc9_ops -write_box %s/input.box", tempdir_name.c_str()));
+ run_nocheck(stringf("write_xaiger -map %s/input.sym %s/input.xaig", tempdir_name.c_str(), tempdir_name.c_str()));
int num_outputs = active_design->scratchpad_get_int("write_xaiger.num_outputs");
@@ -350,9 +350,9 @@ struct Abc9Pass : public ScriptPass
if (!lut_mode)
abc9_exe_cmd += stringf(" -lut %s/input.lut", tempdir_name.c_str());
abc9_exe_cmd += stringf(" -box %s/input.box", tempdir_name.c_str());
- run(abc9_exe_cmd);
- run(stringf("read_aiger -xaiger -wideports -module_name %s$abc9 -map %s/input.sym %s/output.aig", log_id(mod), tempdir_name.c_str(), tempdir_name.c_str()));
- run("abc9_ops -reintegrate");
+ run_nocheck(abc9_exe_cmd);
+ run_nocheck(stringf("read_aiger -xaiger -wideports -module_name %s$abc9 -map %s/input.sym %s/output.aig", log_id(mod), tempdir_name.c_str(), tempdir_name.c_str()));
+ run_nocheck("abc9_ops -reintegrate");
}
else
log("Don't call ABC as there is nothing to map.\n");
@@ -361,7 +361,7 @@ struct Abc9Pass : public ScriptPass
log("Removing temp directory.\n");
remove_directory(tempdir_name);
}
-
+ mod->check();
active_design->selection().selected_modules.clear();
log_pop();
}
diff --git a/passes/techmap/deminout.cc b/passes/techmap/deminout.cc
index b976b401b..35d43b106 100644
--- a/passes/techmap/deminout.cc
+++ b/passes/techmap/deminout.cc
@@ -121,8 +121,7 @@ struct DeminoutPass : public Pass {
goto tribuf_bit;
} else {
tribuf_bit:
- if (bits_used.count(bit))
- new_input = true;
+ new_input = true;
}
}
diff --git a/techlibs/ecp5/brams_map.v b/techlibs/ecp5/brams_map.v
index 310aedaf2..edda17c02 100644
--- a/techlibs/ecp5/brams_map.v
+++ b/techlibs/ecp5/brams_map.v
@@ -137,8 +137,6 @@ module \$__ECP5_PDPW16KD (CLK2, CLK3, A1ADDR, A1DATA, A1EN, B1ADDR, B1DATA, B1EN
localparam CLKWMUX = CLKPOL2 ? "CLKA" : "INV";
localparam CLKRMUX = CLKPOL3 ? "CLKB" : "INV";
- localparam WRITEMODE_A = TRANSP2 ? "WRITETHROUGH" : "READBEFOREWRITE";
-
PDPW16KD #(
`include "bram_init_9_18_36.vh"
.DATA_WIDTH_W(36),
diff --git a/tests/rpc/frontend.py b/tests/rpc/frontend.py
index eace07bf9..8cbec5682 100644
--- a/tests/rpc/frontend.py
+++ b/tests/rpc/frontend.py
@@ -83,10 +83,11 @@ def main():
if args.mode == "unix-socket":
sock = socket.socket(socket.AF_UNIX, socket.SOCK_STREAM)
+ sock.settimeout(30)
sock.bind(args.path)
try:
- ys_proc = subprocess.Popen(["../../yosys", "-ql", "unix.log", "-p", "connect_rpc -path {}; read_verilog design.v; hierarchy -top top; flatten; select -assert-count 1 t:$neg".format(args.path)])
sock.listen(1)
+ ys_proc = subprocess.Popen(["../../yosys", "-ql", "unix.log", "-p", "connect_rpc -path {}; read_verilog design.v; hierarchy -top top; flatten; select -assert-count 1 t:$neg".format(args.path)])
conn, addr = sock.accept()
file = conn.makefile("rw")
while True:
diff --git a/tests/simple/partsel.v b/tests/simple/partsel.v
index 7461358ad..83493fcb0 100644
--- a/tests/simple/partsel.v
+++ b/tests/simple/partsel.v
@@ -60,3 +60,7 @@ always @(posedge clk) begin
end
endmodule
+
+module partsel_test003(input [2:0] a, b, input [31:0] din, output [3:0] dout);
+assign dout = din[a*b +: 2];
+endmodule
diff --git a/tests/various/deminout_unused.ys b/tests/various/deminout_unused.ys
new file mode 100644
index 000000000..5ed00509d
--- /dev/null
+++ b/tests/various/deminout_unused.ys
@@ -0,0 +1,14 @@
+read_verilog <<EOT
+module top(input clk, inout [7:0] x);
+
+reg [3:0] ctr;
+always @(posedge clk) ctr <= ctr + 1'b1;
+
+assign x[7:4] = ctr;
+endmodule
+EOT
+proc
+tribuf
+deminout
+select -assert-count 1 i:x o:x %i
+
generated by cgit v1.2.3 (git 2.25.1) at 2025-04-23 21:31:10 +0000