diff options
| -rw-r--r-- | Makefile | 2 | ||||
| -rw-r--r-- | frontends/verilog/preproc.cc | 10 | ||||
| -rw-r--r-- | kernel/driver.cc | 3 | ||||
| -rw-r--r-- | kernel/mem.cc | 3 | ||||
| -rw-r--r-- | passes/cmds/bugpoint.cc | 2 | ||||
| -rw-r--r-- | tests/verilog/doubleslash.ys | 19 |
6 files changed, 36 insertions, 3 deletions
@@ -129,7 +129,7 @@ LDFLAGS += -rdynamic LDLIBS += -lrt endif -YOSYS_VER := 0.12+26 +YOSYS_VER := 0.12+30 GIT_REV := $(shell git -C $(YOSYS_SRC) rev-parse --short HEAD 2> /dev/null || echo UNKNOWN) OBJS = kernel/version_$(GIT_REV).o diff --git a/frontends/verilog/preproc.cc b/frontends/verilog/preproc.cc index 17f567587..883531e78 100644 --- a/frontends/verilog/preproc.cc +++ b/frontends/verilog/preproc.cc @@ -142,6 +142,16 @@ static std::string next_token(bool pass_newline = false) return_char(ch); } } + else if (ch == '\\') + { + while ((ch = next_char()) != 0) { + if (ch < 33 || ch > 126) { + return_char(ch); + break; + } + token += ch; + } + } else if (ch == '/') { if ((ch = next_char()) != 0) { diff --git a/kernel/driver.cc b/kernel/driver.cc index 7690c2ed2..f8f940e89 100644 --- a/kernel/driver.cc +++ b/kernel/driver.cc @@ -370,6 +370,7 @@ int main(int argc, char **argv) exit(0); case 'S': passes_commands.push_back("synth"); + run_shell = false; break; case 'g': log_force_debug++; @@ -382,9 +383,11 @@ int main(int argc, char **argv) break; case 'H': passes_commands.push_back("help"); + run_shell = false; break; case 'h': passes_commands.push_back(stringf("help %s", optarg)); + run_shell = false; break; case 'b': backend_command = optarg; diff --git a/kernel/mem.cc b/kernel/mem.cc index 746f667ea..96168ff76 100644 --- a/kernel/mem.cc +++ b/kernel/mem.cc @@ -985,7 +985,8 @@ Cell *Mem::extract_rdff(int idx, FfInitVals *initvals) { c = ff.emit(); } - log("Extracted %s FF from read port %d of %s.%s: %s\n", trans_use_addr ? "addr" : "data", + if (c) + log("Extracted %s FF from read port %d of %s.%s: %s\n", trans_use_addr ? "addr" : "data", idx, log_id(module), log_id(memid), log_id(c)); port.en = State::S1; diff --git a/passes/cmds/bugpoint.cc b/passes/cmds/bugpoint.cc index 16ac5b6a7..7b621504d 100644 --- a/passes/cmds/bugpoint.cc +++ b/passes/cmds/bugpoint.cc @@ -377,7 +377,7 @@ struct BugpointPass : public Pass { if (wire->get_bool_attribute(ID::bugpoint_keep)) continue; - if (wire->name.begins_with("$delete_wire")) + if (wire->name.begins_with("$delete_wire") || wire->name.begins_with("$auto$bugpoint")) continue; if (index++ == seed) diff --git a/tests/verilog/doubleslash.ys b/tests/verilog/doubleslash.ys new file mode 100644 index 000000000..8a51f12c2 --- /dev/null +++ b/tests/verilog/doubleslash.ys @@ -0,0 +1,19 @@ +read_verilog -sv <<EOT +module doubleslash + (input logic a, + input logic b, + output logic z); + + logic \a//b ; + + assign \a//b = a & b; + assign z = ~\a//b ; + +endmodule : doubleslash +EOT + +hierarchy +proc +opt -full + +write_verilog doubleslash.v |