diff options
| -rw-r--r-- | frontends/verilog/verilog_parser.y | 10 | ||||
| -rw-r--r-- | passes/cmds/add.cc | 37 | ||||
| -rw-r--r-- | passes/techmap/deminout.cc | 3 | ||||
| -rw-r--r-- | tests/simple/partsel.v | 4 | ||||
| -rw-r--r-- | tests/various/deminout_unused.ys | 14 |
5 files changed, 42 insertions, 26 deletions
diff --git a/frontends/verilog/verilog_parser.y b/frontends/verilog/verilog_parser.y index be8b39e9f..91982e2a3 100644 --- a/frontends/verilog/verilog_parser.y +++ b/frontends/verilog/verilog_parser.y @@ -593,13 +593,15 @@ non_opt_range: } | '[' expr TOK_POS_INDEXED expr ']' { $$ = new AstNode(AST_RANGE); - $$->children.push_back(new AstNode(AST_SUB, new AstNode(AST_ADD, $2->clone(), $4), AstNode::mkconst_int(1, true))); - $$->children.push_back(new AstNode(AST_ADD, $2, AstNode::mkconst_int(0, true))); + AstNode *expr = new AstNode(AST_CONCAT, $2); + $$->children.push_back(new AstNode(AST_SUB, new AstNode(AST_ADD, expr->clone(), $4), AstNode::mkconst_int(1, true))); + $$->children.push_back(new AstNode(AST_ADD, expr, AstNode::mkconst_int(0, true))); } | '[' expr TOK_NEG_INDEXED expr ']' { $$ = new AstNode(AST_RANGE); - $$->children.push_back(new AstNode(AST_ADD, $2, AstNode::mkconst_int(0, true))); - $$->children.push_back(new AstNode(AST_SUB, new AstNode(AST_ADD, $2->clone(), AstNode::mkconst_int(1, true)), $4)); + AstNode *expr = new AstNode(AST_CONCAT, $2); + $$->children.push_back(new AstNode(AST_ADD, expr, AstNode::mkconst_int(0, true))); + $$->children.push_back(new AstNode(AST_SUB, new AstNode(AST_ADD, expr->clone(), AstNode::mkconst_int(1, true)), $4)); } | '[' expr ']' { $$ = new AstNode(AST_RANGE); diff --git a/passes/cmds/add.cc b/passes/cmds/add.cc index dd05ac81f..62c253bed 100644 --- a/passes/cmds/add.cc +++ b/passes/cmds/add.cc @@ -24,24 +24,23 @@ PRIVATE_NAMESPACE_BEGIN static void add_wire(RTLIL::Design *design, RTLIL::Module *module, std::string name, int width, bool flag_input, bool flag_output, bool flag_global) { - RTLIL::Wire *wire = NULL; + RTLIL::Wire *wire = nullptr; name = RTLIL::escape_id(name); if (module->count_id(name) != 0) { - if (module->wires_.count(name) > 0) - wire = module->wires_.at(name); + wire = module->wire(name); - if (wire != NULL && wire->width != width) - wire = NULL; + if (wire != nullptr && wire->width != width) + wire = nullptr; - if (wire != NULL && wire->port_input != flag_input) - wire = NULL; + if (wire != nullptr && wire->port_input != flag_input) + wire = nullptr; - if (wire != NULL && wire->port_output != flag_output) - wire = NULL; + if (wire != nullptr && wire->port_output != flag_output) + wire = nullptr; - if (wire == NULL) + if (wire == nullptr) log_cmd_error("Found incompatible object with same name in module %s!\n", module->name.c_str()); log("Module %s already has such an object.\n", module->name.c_str()); @@ -53,7 +52,6 @@ static void add_wire(RTLIL::Design *design, RTLIL::Module *module, std::string n wire->port_output = flag_output; if (flag_input || flag_output) { - wire->port_id = module->wires_.size(); module->fixup_ports(); } @@ -63,21 +61,20 @@ static void add_wire(RTLIL::Design *design, RTLIL::Module *module, std::string n if (!flag_global) return; - for (auto &it : module->cells_) + for (auto cell : module->cells()) { - if (design->modules_.count(it.second->type) == 0) + RTLIL::Module *mod = design->module(cell->type); + if (mod == nullptr) continue; - - RTLIL::Module *mod = design->modules_.at(it.second->type); if (!design->selected_whole_module(mod->name)) continue; if (mod->get_blackbox_attribute()) continue; - if (it.second->hasPort(name)) + if (cell->hasPort(name)) continue; - it.second->setPort(name, wire); - log("Added connection %s to cell %s.%s (%s).\n", name.c_str(), module->name.c_str(), it.first.c_str(), it.second->type.c_str()); + cell->setPort(name, wire); + log("Added connection %s to cell %s.%s (%s).\n", name.c_str(), module->name.c_str(), cell->name.c_str(), cell->type.c_str()); } } @@ -155,9 +152,9 @@ struct AddPass : public Pass { extra_args(args, argidx, design); - for (auto &mod : design->modules_) + for (auto module : design->modules()) { - RTLIL::Module *module = mod.second; + log_assert(module != nullptr); if (!design->selected_whole_module(module->name)) continue; if (module->get_bool_attribute("\\blackbox")) diff --git a/passes/techmap/deminout.cc b/passes/techmap/deminout.cc index b976b401b..35d43b106 100644 --- a/passes/techmap/deminout.cc +++ b/passes/techmap/deminout.cc @@ -121,8 +121,7 @@ struct DeminoutPass : public Pass { goto tribuf_bit; } else { tribuf_bit: - if (bits_used.count(bit)) - new_input = true; + new_input = true; } } diff --git a/tests/simple/partsel.v b/tests/simple/partsel.v index 7461358ad..83493fcb0 100644 --- a/tests/simple/partsel.v +++ b/tests/simple/partsel.v @@ -60,3 +60,7 @@ always @(posedge clk) begin end endmodule + +module partsel_test003(input [2:0] a, b, input [31:0] din, output [3:0] dout); +assign dout = din[a*b +: 2]; +endmodule diff --git a/tests/various/deminout_unused.ys b/tests/various/deminout_unused.ys new file mode 100644 index 000000000..5ed00509d --- /dev/null +++ b/tests/various/deminout_unused.ys @@ -0,0 +1,14 @@ +read_verilog <<EOT +module top(input clk, inout [7:0] x); + +reg [3:0] ctr; +always @(posedge clk) ctr <= ctr + 1'b1; + +assign x[7:4] = ctr; +endmodule +EOT +proc +tribuf +deminout +select -assert-count 1 i:x o:x %i + |