diff options
| -rw-r--r-- | CHANGELOG | 7 | ||||
| -rw-r--r-- | Makefile | 4 | ||||
| -rw-r--r-- | frontends/verific/verific.cc | 85 | ||||
| -rw-r--r-- | frontends/verific/verific.h | 1 |
4 files changed, 89 insertions, 8 deletions
@@ -2,11 +2,14 @@ List of major changes and improvements between releases ======================================================= -Yosys 0.25 .. Yosys 0.25-dev +Yosys 0.26 .. Yosys 0.26-dev +-------------------------- + +Yosys 0.25 .. Yosys 0.26 -------------------------- * New commands and options - Added "bwmuxmap" pass to replace $bwmux cells with equivalent logic. - - Added "xprop" pass for formal x propagation. + - Added "xprop" experimental pass for formal x propagation. - Added "splitcells" pass to split up multi-bit cells. - Added "viz" pass to visualize data flow graph. - Added option "-make_cover" to "miter" pass. @@ -141,7 +141,7 @@ LDLIBS += -lrt endif endif -YOSYS_VER := 0.25+102 +YOSYS_VER := 0.26+1 # Note: We arrange for .gitcommit to contain the (short) commit hash in # tarballs generated with git-archive(1) using .gitattributes. The git repo @@ -157,7 +157,7 @@ endif OBJS = kernel/version_$(GIT_REV).o bumpversion: - sed -i "/^YOSYS_VER := / s/+[0-9][0-9]*$$/+`git log --oneline e02b7f6.. | wc -l`/;" Makefile + sed -i "/^YOSYS_VER := / s/+[0-9][0-9]*$$/+`git log --oneline 7e58866.. | wc -l`/;" Makefile # set 'ABCREV = default' to use abc/ as it is # diff --git a/frontends/verific/verific.cc b/frontends/verific/verific.cc index 8898c4597..c1e9fc7d0 100644 --- a/frontends/verific/verific.cc +++ b/frontends/verific/verific.cc @@ -361,10 +361,16 @@ RTLIL::SigSpec VerificImporter::operatorInport(Instance *inst, const char *portn for (unsigned i = 0; i < portbus->Size(); i++) { Net *net = inst->GetNet(portbus->ElementAtIndex(i)); if (net) { - if (net->IsGnd()) - sig.append(RTLIL::State::S0); - else if (net->IsPwr()) - sig.append(RTLIL::State::S1); + if (net->IsConstant()) { + if (net->IsGnd()) + sig.append(RTLIL::State::S0); + else if (net->IsPwr()) + sig.append(RTLIL::State::S1); + else if (net->IsX()) + sig.append(RTLIL::State::Sx); + else + sig.append(RTLIL::State::Sz); + } else sig.append(net_map_at(net)); } else @@ -379,6 +385,36 @@ RTLIL::SigSpec VerificImporter::operatorInport(Instance *inst, const char *portn } } +RTLIL::SigSpec VerificImporter::operatorInportCase(Instance *inst, const char *portname) +{ + PortBus *portbus = inst->View()->GetPortBus(portname); + if (portbus) { + RTLIL::SigSpec sig; + for (unsigned i = 0; i < portbus->Size(); i++) { + Net *net = inst->GetNet(portbus->ElementAtIndex(i)); + if (net) { + if (net->IsConstant()) { + if (net->IsGnd()) + sig.append(RTLIL::State::S0); + else if (net->IsPwr()) + sig.append(RTLIL::State::S1); + else + sig.append(RTLIL::State::Sa); + } + else + sig.append(net_map_at(net)); + } else + sig.append(RTLIL::State::Sa); + } + return sig; + } else { + Port *port = inst->View()->GetPort(portname); + log_assert(port != NULL); + Net *net = inst->GetNet(port); + return net_map_at(net); + } +} + RTLIL::SigSpec VerificImporter::operatorOutput(Instance *inst, const pool<Net*, hash_ptr_ops> *any_all_nets) { RTLIL::SigSpec sig; @@ -989,6 +1025,47 @@ bool VerificImporter::import_netlist_instance_cells(Instance *inst, RTLIL::IdStr return true; } + if (inst->Type() == OPER_WIDE_CASE_SELECT_BOX) + { + RTLIL::SigSpec sig_out_val = operatorInport(inst, "out_value"); + RTLIL::SigSpec sig_select = operatorInport(inst, "select"); + RTLIL::SigSpec sig_select_values = operatorInportCase(inst, "select_values"); + RTLIL::SigSpec sig_data_values = operatorInport(inst, "data_values"); + RTLIL::SigSpec sig_data_default = operatorInport(inst, "default_value"); + + RTLIL::Process *proc = module->addProcess(new_verific_id(inst)); + import_attributes(proc->attributes, inst); + + RTLIL::CaseRule *current_case = &proc->root_case; + current_case = &proc->root_case; + + RTLIL::SwitchRule *sw = new RTLIL::SwitchRule; + sw->signal = sig_select; + current_case->switches.push_back(sw); + + int select_width = inst->InputSize(); + int data_width = inst->OutputSize(); + int select_num = inst->Input1Size() / inst->InputSize(); + + int offset_select = 0; + int offset_data = 0; + + for (int i = 0; i < select_num; i++) { + RTLIL::CaseRule *cs = new RTLIL::CaseRule; + cs->compare.push_back(sig_select_values.extract(offset_select, select_width)); + cs->actions.push_back(SigSig(sig_out_val, sig_data_values.extract(offset_data, data_width))); + sw->cases.push_back(cs); + + offset_select += select_width; + offset_data += data_width; + } + RTLIL::CaseRule *cs_default = new RTLIL::CaseRule; + cs_default->actions.push_back(SigSig(sig_out_val, sig_data_default)); + sw->cases.push_back(cs_default); + + return true; + } + #undef IN #undef IN1 #undef IN2 diff --git a/frontends/verific/verific.h b/frontends/verific/verific.h index d9f0077db..44485751c 100644 --- a/frontends/verific/verific.h +++ b/frontends/verific/verific.h @@ -87,6 +87,7 @@ struct VerificImporter RTLIL::SigSpec operatorInput1(Verific::Instance *inst); RTLIL::SigSpec operatorInput2(Verific::Instance *inst); RTLIL::SigSpec operatorInport(Verific::Instance *inst, const char *portname); + RTLIL::SigSpec operatorInportCase(Verific::Instance *inst, const char *portname); RTLIL::SigSpec operatorOutput(Verific::Instance *inst, const pool<Verific::Net*, hash_ptr_ops> *any_all_nets = nullptr); bool import_netlist_instance_gates(Verific::Instance *inst, RTLIL::IdString inst_name); |